VIRTUAL PRECISION TIME PROTOCOL CLOCK GENERATOR FOR VIRTUAL NODES

Abstract

A device comprising: a storage medium for storing a plurality of information items; a supervisor for providing a plurality of virtual nodes; and a controller separate from the supervisor to provide a plurality of virtual precision time protocol clock devices, wherein: each virtual precision time protocol clock device of the plurality of virtual precision time protocol clock devices corresponds to an information element of the plurality of information elements; the controller uses the information element corresponding to a given virtual precision time protocol clock device of the plurality of virtual precision time protocol clock devices to provide a precision time protocol-based time for the given virtual precision time protocol clock device; and the controller providing the precision time protocol-based time comprises communicating a sequence of precision time protocol-based messages using the given virtual precision time protocol clock device and with a given virtual node of the plurality of virtual nodes to synchronize a clock of the given virtual node with the precision time protocol-based time.

Description

BACKGROUND

[0001] A bare-metal computing platform may maintain a system time relative to a system clock of the computing platform. The computing platform may use the system clock to timestamp various events, operations, and transactions of the computing platform (e.g., by assigning times via tags that represent the times). For example, the bare-metal computing platform may set a timestamp when a record (e.g., a file) is created or modified, a timestamp for logged events, a timestamp for financial transactions, a timestamp for the receipt or sending of emails, a timestamp for security alerts, and so on. The computing platform may have one or more virtual machines, which may maintain their own system clocks to timestamp events, operations, and transactions associated with the virtual machines.US 2016 / 0112 182 A1 describes methods for network time synchronization for virtual machine (VM) host systems, which enable synchronization of master / slave clocks within VM host hardware systems. It is an object of the invention to propose a device, a non-transitory, machine-readable storage medium, and a method for synchronizing virtual node clocks with a time based on precision time protocols of virtual precision time protocol clock devices. This object is achieved by an inventive device according to claim 1, an inventive, non-transitory, machine-readable storage medium according to claim 16, and an inventive method according to claim 19. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Fig. is a block diagram of a computing platform including a platform controller that provides virtual Precision Time Protocol (PTP) clock devices for virtual machines of the computing platform, according to an example implementation.

[0003] Fig. is a block diagram of the platform control of Fig. according to an example implementation.

[0004] Fig. is a block diagram of a memory address space associated with the virtual PTP clocks according to example implementations.

[0005] Fig. is a block diagram of a device having a controller that provides virtual PTP clocks to virtual nodes of the device according to an example implementation.

[0006] Fig. is an illustration of a non-transitory, machine-readable storage medium storing machine-executable embodiments that, when executed, cause a machine to execute virtual nodes that access virtual PTP clock devices according to an example implementation.

[0007] Fig. is a flowchart showing a process for provisioning virtual PTP clocks to virtual nodes according to an example implementation. DETAILED DESCRIPTION

[0008] A computing platform may provide one or more instances of computing environments. For example, the computing platform may be part of a cloud computing system. The cloud computing system may include a central management subsystem that orchestrates software-defined logical infrastructure and services (e.g., software-defined compute services (SDC), software-defined storage services (SDS), and software-defined network services (SDN)) hosted on computing platforms of the cloud computing system. As part of providing the logical infrastructure and services, the computing platforms may provide instances of the computing environment.

[0009] Among the types of computing environments, a bare-metal computing environment is connected to actual hardware and software resources. A virtual computing environment, also referred to here as a "virtual node," is an abstraction or virtualization of actual hardware and software resources. The computing platform containing the actual hardware and software resources serves as the host for the virtual node.

[0010] A virtual machine (which may also be referred to as a "guest virtual machine," "virtual machine," "VM instance," "guest VM," or "VM") is an example of a virtual node. A VM is a machine-level abstraction that has its own virtualized resources (such as CPU(s), system memory, network interface(s), and storage) of the host computing platform. A VM may also have its own guest operating system. A VM supervisor, also known as a virtual machine monitor (VMM) or hypervisor, performs deployment actions on the VM instances. In general, the hypervisor can manage the lifecycles of VM instances running on the host computing platform, maintain isolation between the VM instances, and provide virtualization services to the VM instances.

[0011] A "container" (also called an "instantiated container," "container instance," or "software container") is another example of a virtual node. A container is generally a virtual runtime environment for one or more applications and / or application modules, and this virtual runtime environment is built to interface with an operating system kernel. For example, a container for a particular application might contain the executable code for the application and its dependencies, such as system tools, libraries, configuration files, executable files, and binaries for the application. The container contains an interface for incorporating the operating system kernel, but no operating system kernel. For example, a particular computing platform might contain multiple containers that share an operating system kernel of the host computing platform through corresponding operating system kernel mount interfaces.Docker containers and rkt containers are examples of containers. A container supervisor, also known as a container engine daemon, performs actions to deploy the containers. Generally, the container engine daemon can perform actions to create and run the containers.

[0012] A particular entity (e.g., a virtual node instance or a bare-metal instance) running on a computing platform can timestamp various events, operations, and transactions associated with the entities. The entity may maintain a system clock to track the current time while an operating system associated with the entity is running. As used herein, the term "clock" refers to a virtual or actual physical component or device that provides a value representing a time (e.g., a time of day).

[0013] The entity can update the system clock time depending on the ticks of the host's central processing unit (CPU). Because the memory associated with an operating system is erased when the operating system boots, the operating system associated with the entity may not initially know the current time. During boot, the operating system can either take action to determine the current time or it can be informed of the time. Because CPU clock ticks are relatively imprecise (e.g., the CPU oscillator may have a fluctuation of 50 parts per million (ppm), resulting in a deviation of about 4.25 seconds per day), the system clock can be periodically refreshed (e.g., by periodically resynchronizing with a time represented by another clock) while the operating system is running.

[0014] The operating system can obtain the current time (both for the initial value after boot and for subsequent updates) from a platform-internal or platform-external time source. For example, a VM instance can obtain its time from a hypervisor located within the computing platform. A battery-backed real-time clock (RTC) is another example of an internal time source. Another platform-internal time source can be a hardware-based Precision Time Protocol (PTP) clock device. External clock sources to the computing platform can include Network Time Protocol (NTP) servers and PTP servers.

[0015] Clock sources can vary in their accuracy and associated implementation costs. For example, a battery-backed RTC may be relatively inexpensive to implement, but less accurate than the host CPU's ticks. A PTP clock source may be relatively more accurate than a battery-backed RTC or NTP clock source, but may be relatively more expensive to implement.

[0016] NTP and PTP are examples of time synchronization protocols. In general, a unit of a computing platform can use a time synchronization protocol to synchronize the unit's clock with a reference clock (e.g., to obtain an initial clock value representing the time of day and periodically update the clock value thereafter). The accuracy of time synchronization protocols varies. For example, PTP can have an accuracy of 200 nanoseconds (ns) (i.e., a given clock can be synchronized to within 200 ns of the reference clock using PTP), while NTP has a relatively lower accuracy of 200 microseconds (µs).

[0017] Although potentially more expensive to implement, there may be several reasons for using a relatively precise time synchronization protocol such as PTP. For example, industry standards and / or government regulations may require precise time specifications for certain computer-related events, operations, and transactions, such as financial transactions, healthcare transactions, recording of events and disturbances in electrical transmission infrastructure, recording of seismic events, etc. In addition, there have been a number of security breaches, computer system failures, and other computer-related problems resulting from time synchronization errors and / or time inaccuracies (e.g., leap second errors, security attacks, software bugs, certificate validation errors, etc.).

[0018] PTP is connected to a hierarchy (or "clock hierarchy") of nodes. The PTP clock hierarchy can form a tree structure. At the root, or top, of the tree structure, the clock hierarchy contains a master or primary node, referred to here as the "primary PTP leader." The primary PTP leader maintains the primary reference clock, and the clocks of the other nodes in the PTP clock hierarchy are synchronized with the clock of the primary PTP leader. A particular node among the remaining nodes in the PTP clock hierarchy can be either a PTP follower or both a PTP follower and a PTP leader. In general, a PTP leader (be it the primary PTP leader or another PTP leader) communicates a specific sequence of messages with a PTP follower to synchronize the PTP follower's clock with the PTP leader's clock.A node that is both a PTP follower and a PTP leader is considered a boundary node, a node that is only a PTP follower (i.e., a leaf node of the PTP clock hierarchy tree) is considered a client node.

[0019] For example, the clock of the primary PTP leader may be synchronized with an atomic clock (e.g., the clock of the primary PTP leader may be synchronized with the US atomic clock in Boulder, CO, via radio frequency communication). As another example, the clock of the primary PTP leader may be synchronized with a Global Navigation Satellite System (GNSS) clock. As a more specific example, a computing platform may include a hardware component such as a timing card (e.g., a Peripheral Component Interconnect Express (PCIe) card) that serves as the primary PTP leader to which the clocks of other PTP followers are synchronized. Another example is a computing platform with PTP followers that synchronize their clocks with a PTP leader external to the platform, such as a network switch.

[0020] A physical hardware PTP clock device (e.g., a PTP clock device consisting of dedicated hardware components such as a gate array, an application-specific integrated circuit (ASIC), and / or a microcontroller or processing core) can be relatively expensive. The cost can increase further if a computing platform has multiple (e.g., dozens to hundreds) VM instances running on the computing platform, and PTP clocks are provided for the respective VM instances.

[0021] One approach to providing a PTP clock source for a VM instance (instead of a dedicated physical hardware PTP clock device) is for a computing platform hypervisor to emulate the hardware PTP clock device for the VM instance. This allows the hypervisor to have an emulation layer to emulate hardware PTP clocks for multiple VM instances, so that the hypervisor provides a virtual PTP clock for each VM instance as a result of this emulation. However, this approach may have performance and / or security drawbacks. Hypervisor-based emulation of PTP clock devices can introduce latency variations because other executable entities wait while the hypervisor executes the PTP clock emulation code. For example, NTP clients can apply mathematical filters to the times they receive from NTP servers to mitigate the impact of erroneous time values.Implementing mathematical filters may require the use of some mathematical functions (e.g., mathematical functions for adding the last n values ​​and dividing by n), which consume some CPU cycles. Furthermore, using the hypervisor to emulate PTP clock devices may pose a security vulnerability to the computing platform. To allow guest operating systems to make hypervisor system calls, a separate driver can be provided for each guest operating system. Such paravirtualization can present a highly sensitive attack surface for hypervisor penetration.

[0022] According to the example implementations described here, a controller of a computing platform emulates physical hardware PTP clocks (here referred to as "PTP clocks") to provide corresponding virtual PTP clocks for corresponding virtual node instances. Controller-provided emulation of PTP clocks can be beneficial to the security of the computing platform for reasons such as reducing the attack surface. Furthermore, controller-provided PTP clock emulation can free up computing platform processing resources (e.g., processing resources, such as freeing CPU resources otherwise used to emulate PTP clocks as part of a hypervisor's emulation layer).

[0023] According to some implementations, the controller may be a "platform controller," which refers to a controller that performs specific tasks in a computing platform. In some examples, the platform controller is a bus device on a bus, such as a Peripheral Component Interconnect (PCI) bus or a PCIe bus. In other examples, the platform controller may be a bus device connected to another type of bus in a computing platform. A "bus" refers to a communications link over which multiple devices can communicate with each other.

[0024] The platform controller may be separate from the main processor(s) of the computing platform. The main processor(s) may execute various machine-readable instructions of the system, such as virtual node instances (e.g., container instances and / or VM instances), operating system instances, application instances, firmware (e.g., boot code, hardware initialization code, etc.), etc. The platform controller may be dedicated to performing certain tasks for the computing platform, including emulating PTP clock devices as well as other tasks (e.g., power management tasks, thermal management tasks, system monitoring tasks, etc.). In some examples, the platform controller may be a separate system-on-chip connected to the main processor(s).In more specific examples, the platform controller may consist of an intelligent network interface controller (NIC) or be part of a baseboard management controller (BMC). The platform controller may have its own processing circuitry (separate from the main processor(s) running the operating system and / or other program code of a computer system) and run its own firmware. A BMC is a specialized service processor capable of monitoring the physical state of the computer platform using sensors. The BMC may communicate with a management system (e.g., a remote management server) via an independent out-of-band connection.

[0025] The BMC can also communicate with applications running at the operating system level through an IOCTL (input / output controller) interface driver, a REST application program interface (API), or another system software proxy that enables communication between the BMC and the applications. The BMC can access the hardware components of the computing platform at the hardware level. The BMC can be capable of directly modifying the hardware components. The BMC can operate independently of the operating system of the computing platform in which the BMC is located. The BMC can be located on the motherboard or main circuit board of the computing platform to be monitored.The fact that a BMC is mounted on a motherboard of the computer platform being monitored, or otherwise connected or attached to the computer platform being monitored, does not prevent the BMC from being considered separate from a processing resource running the operating system. A BMC provides management capabilities for managing components of the computer platform. Examples of BMC management capabilities may include one or a combination of the following: power control, thermal monitoring and control, fan control, system health monitoring, remote access to the computer system, remote reboot of the computer system, system setup, operating system image deployment and recovery, system security, etc.

[0026] In some examples, a BMC may provide so-called "lights-out" functionality for a computing platform. The "lights-out" functionality may allow a user, such as a system administrator, to perform management operations on the computing platform even if an operating system is not installed or is not functioning on the computing platform. Furthermore, in some examples, the BMC may be powered by auxiliary power (such as battery power or an auxiliary power rail). As a result, the computing platform does not need to be turned on for the BMC to perform its tasks. The services provided by the BMC may be considered "out-of-band" services because the operating system may not be running. In some cases, the BMC may provide out-of-band services through a management channel when the rest of the computing platform is fully or partially turned off or not functioning properly (for example,if the computer platform experiences a malfunction or hardware failure).

[0027] A platform controller can be part of an entity other than a bus device or a BMC. For example, the platform controller can be a chassis management controller. Regardless of its particular form, according to the example implementations, the platform controller provides a separate physical processor (separate from the main processor(s) of the computing platform) in which PTP clock device emulation can be securely deployed. For example, according to the example implementations, the platform controller is protected against attacks that could compromise the operation of the main processor(s), such as malware infecting a computing platform and running on the main processor(s).

[0028] By offloading the emulation of PTP clocks to the platform controller, the main processor overhead that might otherwise be incurred for generating virtual PTP clocks is reduced. According to example implementations, a portion of PCI memory is allocated to contain information elements individually associated with corresponding virtual node instances (e.g., VM instances or container instances). According to example implementations, the information element can be a register or a set of registers. Each register set contains registers that can be accessed for the purpose of passing messages related to synchronizing the clocks of the virtual node instances with the respective virtual PTP clock devices.The platform controller can detect accesses to the registers in the PCI memory portion, which allows the platform controller to generate appropriate responses to emulate PTP clock devices.

[0029] As in Fig. As a more specific example, a computer system 99 may, in accordance with some implementations, include one or more computer platforms 100. According to some embodiments, the computer platform 100 may be part of a computer network. In further embodiments, the computer platform 100 may be a standalone platform. In the Fig. In the example implementation illustrated, the computer system 99 is a cloud computing system, and one or more computer platforms 100 form corresponding domain nodes of the cloud computing system. In accordance with example implementations, the computer platform 100 may be one of a plurality of cloud resources 188 connected to each other and to one or more clients 186 (i.e., clients associated with cloud tenants) via the network structure 180.

[0030] In general, the network fabric 180 may be connected to one or more types of communication networks, such as (as examples) Fibre Channel networks, Gen-Z fabrics, dedicated management networks, local area networks (LANs), wide area networks (WANs), global networks (e.g., the Internet), wireless networks, or any combination thereof.

[0031] The term "computing platform" refers herein to a modular unit comprising a frame or enclosure. Furthermore, this modular unit may include hardware mounted on the chassis capable of executing machine-executable instructions. A blade server is an example of a computing platform 100 according to one example implementation. However, according to further implementations, the computing platform 100 may be any platform other than a blade server, such as a rack-mounted server, a client, a desktop, a smartphone, a laptop, a tablet computer, a modular switch, a compute node, a storage array, a cluster node, a wearable computer, etc.

[0032] Computing platform 100 includes N virtual node instances, where "N" is an integer greater than or equal to one, in accordance with example implementations. According to one example, the virtual node instance may be a VM instance. Fig. Specifically, it shows VM instance 101-1 through VM instance 101-N. Note that, although the following discussion describes example implementations in which the virtual node instances are VM instances, in accordance with other implementations, the virtual node instances may be other types of virtual computing environments, such as container instances. In accordance with other example implementations, a computing platform may run various types of virtual node instances, such as VM instances and container instances.Regardless of the specific implementation of the virtual node or the types of virtual node instances executing on a computing platform, the computing platform includes one or more supervisors that provide one or more virtual node instances; and the computing platform includes a controller other than the supervisor(s) that provides one or more emulated PTP clock devices for the respective virtual node instance(s). Fig. In the example implementation shown, the supervisor is a hypervisor 106. According to another example implementation, the virtual node instances are container instances, and the supervisor may be a container engine daemon. According to other example implementations, the virtual node instances may be VM instances and container instances, each having a container engine daemon and a hypervisor-based supervisor.

[0033] In dem in Fig. In the illustrated implementation example, the VM instances 101 may be started upon request by a user or other entity. The computing platform 100 may begin with zero VM instances 101, and additional VM instance(s) 101 may be started upon request. Each VM instance 101 includes a corresponding guest operating system instance 102 (or "guest operating system"), according to example implementations. The guest operating system instance 102 may correspond to a LINUX operating system, a WINDOWS operating system, and / or another type of operating system. The various guest operating system instances 102 may be of the same type or of different types. Each VM instance 101 may also include one or more application program instances 104 (or "application programs 104") executing in the VM instance 101.Note that before creating a VM instance 101, there is no guest operating system instance 102 and no application program instance 104.

[0034] Computing platform 100 includes a hypervisor 106 in accordance with example implementations. Hypervisor 106 may generally provision VM instances 101. Thus, hypervisor 106 may create VM instances 101 and manage the execution of VM instances 101. Hypervisor 106 may emulate physical resources of computing platform 100 that may be accessible to VM instances 101. Furthermore, hypervisor 106 may provide isolation between VM instances 101 and perform various virtualization tasks for VM instances 101.

[0035] According to example implementations, instead of emulating a PTP clock device using hypervisor 106, the emulation of the PTP clock device is offloaded to a platform controller 108 of computing platform 100. According to example implementations, platform controller 108 is a bus device on a bus 110 of computing platform 100. Bus 110 may be, for example, a PCIe bus. According to further example implementations, bus 110 may be a bus type other than a PCIe bus. Furthermore, according to further implementations, platform controller 108 may be connected to a communication fabric other than a bus.

[0036] The platform controller 108 may be implemented with any type of hardware processing circuitry, including, as examples, hardware processing circuitry that includes one or more microcontrollers, one or more programmable integrated circuits (e.g., one or more ASICs, one or more programmable gate arrays, one or more microprocessor processing cores, etc.).

[0037] In some examples, the platform controller 108 is separate and distinct from the one or more main processors 112 of the computing platform 100. The main processor 112 may include one or more microprocessors, one or more cores of a multi-core microprocessor, one or more microcontrollers, one or more programmable integrated circuits, one or more programmable gate arrays, one or more digital signal processors, one or more other hardware processing circuits, etc.

[0038] In general, the platform controller 108 can take one of many different architectures, depending on the particular implementation. For example, the platform controller 108 can be part of an intelligent network interface card (Smart NIC), an intelligent input / output (I / O) peripheral, a BMC, a chassis management controller, etc. Regardless of the particular implementation, the platform controller 108 is separate from the main processor(s) 112 and performs specific tasks within the computing platform 100.

[0039] The main processor(s) 112 is (are) connected to the bus 110 either directly or through another device, such as a bridge device. According to example implementations, the main processor(s) 112 execute machine-readable instructions of the computing platform 100, including instructions to form the hypervisor 106, instructions to form the VM instances 101, instructions to form a host operating system (if present), and other instructions associated with other software programs and / or firmware programs.

[0040] As in Fig. As shown, the main processor(s) 112 may be coupled to a system memory 113 in accordance with example implementations. The system memory 113 is a non-transitory storage medium and may include one or more storage devices to store data and machine-readable instructions. A storage device may be a volatile storage device, such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and so forth. Alternatively, a storage device may be a non-volatile storage device. Although not shown, the system memory 113 may include a memory controller, or alternatively, a memory controller may be coupled to the memory device(s) to control access to the data in the memory device(s).

[0041] Devices of computing platform 100 other than main processor(s) 112 and platform controller 108 may be connected to bus 110, according to example implementations. For example, according to some implementations, one or more network interface controllers (NICs) 129 and persistent memory 132 may be connected to bus 110. According to example implementations, components of computing platform 100, including VM instances 101, use NIC 129 to communicate with devices of computing system 99 located external to computing platform 100. According to some implementations, components of computing platform 100, including VM instances 101, may communicate with devices of computing system 99 through one or more NICs 130 of platform controller 108 using pass-through communication.

[0042] Persistent storage 132 may store data that is retained even when power is removed from computing platform 100 or persistent storage 132. Persistent storage 132 may be implemented with one or more non-volatile storage devices. A non-volatile storage device may be a flash memory device, a disk-based storage device, etc.

[0043] In accordance with example implementations, the platform controller 108 performs PTP clock emulation with PCI functions 114. In Fig. N PCI functions 114 are shown (PCI function 114-1 to 114-N in Fig. ), and in accordance with example implementations, the hypervisor 106 may assign one PCI function 114 to each VM instance 101. In accordance with example implementations, the hypervisor 106 may assign multiple PCI functions 114 to a particular VM instance 101. As in Fig. As shown, the PCI functions 114 contain corresponding virtual PTP clock devices (vPTPCDs) 128 (in Fig. represented as N vPTPCDs 128-1 to 128-N, each provided via PCI functions 114-1 to 114-N).

[0044] A PTP leader (e.g., a vPTPCD 128) may communicate a sequence of messages with a PTP follower (e.g., a VM instance 101) to synchronize a clock of the PTP follower with a clock of the PTP leader. According to example implementations, the message sequence includes an initial synchronization message. More specifically, according to example implementations, the PTP leader reads a value of its clock, generates a synchronization message containing the read clock value, and sends the synchronization message. The synchronization message is received by the PTP follower, and in response to receiving the synchronization message, the PTP follower records a timestamp (referred to herein as the "initial timestamp") representing the time (relative to the PTP follower's clock) at which the PTP follower received the synchronization message.

[0045] There is a time difference between the time the PTP leader reads its clock value and the time the PTP follower receives the synchronization message. This time difference consists of two components, and the PTP follower uses the information derived from the message sequence to determine these components to determine an adjustment to the clock value sent via the synchronization message.

[0046] A first component of the time difference is the propagation delay of the communication path between the PTP leader and the PTP follower. A second component of the time difference is the time elapsed from the time the PTP leader reads the clock value to the time the PTP leader sends the synchronization message to the communication path.

[0047] To enable the PTP follower to derive the second component of the time difference, the message sequence may include a second message, referred to as a "follow-up message." The PTP leader sends the follow-up message. The follow-up message contains data representing a timestamp (referred to here as the "second timestamp") indicating the actual time (relative to the PTP leader's clock) at which the PTP leader transmitted the synchronization message to the communication path. The PTP follower may determine the second component of the time difference based on the first timestamp (indicating the time the synchronization message was received by the PTP follower) and the second timestamp (indicating the time the PTP leader sent the synchronization message).

[0048] To provide the PTP follower with information to determine the first component (i.e., the propagation delay) of the time difference, the message sequence may include two additional messages sent after the synchronization message. Specifically, after receiving the follower message, the PTP follower may send a delay request message to the PTP leader and record a timestamp (hereafter referred to as the "third timestamp") representing the time (relative to the PTP follower's clock) that the delay request message was transmitted. The PTP leader receives the delay request message and records a timestamp (hereafter referred to as the "fourth timestamp") indicating the time (relative to the PTP leader's clock) that the delay request message was received. The PTP leader may then send a delay response to the PTP follower.The delay response message contains data representing the fourth timestamp. The PTP follower can determine the second component (i.e., the propagation delay) of the time difference based on the third timestamp and the fourth timestamp.

[0049] If the PTP follower determines the time difference between the time the PTP leader reads its clock value and the time the PTP follower receives the synchronization message, the PTP follower can derive, based on the PTP leader's clock value and the time difference, the PTP follower's clock adjustment required to synchronize the PTP follower's clock with the PTP leader's clock.

[0050] A PTP follower and a PTP leader may, in accordance with further implementations, transmit messages other than the sequence of messages described here for the purpose of synchronizing the clock of the PTP follower with a clock of the PTP leader.

[0051] As used here, the term "synchronization" of a first clock with a second clock refers to one or more actions to coordinate the first clock with the second clock. Synchronization may or may not result in the first clock and the second clock being exactly the same, and further, the first clock and the second clock may drift apart (or continue to drift apart) after synchronization. According to example implementations, a PTP follower may regularly (e.g., periodically) synchronize its clock with the clock of a PTP leader. In this way, according to some implementations, the PTP leader may initiate a sequence of messages corresponding to synchronizing the clock at a regular time interval, where each sequence of messages begins with the PTP leader sending a synchronization message and ends with the PTP leader sending a delay-response message.

[0052] According to some implementations, the sequence of messages transmitted between a PTP leader and a PTP follower may follow a protocol described in the IEEE 1588-2019 specification, published in 2020. In other implementations, the sequence of messages transmitted between a PTP leader and a PTP follower may follow a protocol that conforms to a different version of the IEEE 1588 specification than the IEEE 1588-2019 specification. According to other implementations, the sequence of messages transmitted between a PTP leader and a PTP follower may also follow a protocol other than one based on the IEEE 1588 specification.

[0053] In accordance with example implementations, computer system 99 may include an actual or physical PTP leader clock device 184. According to some implementations, PTP leader clock device 184 may be the primary PTP leader for a corresponding PTP clock hierarchy. For example, in some implementations, PTP leader clock device 184 may include a GNSS radio to receive a GNSS signal indicating a time of day, and PTP clock device 184 sets its clock, the primary clock, to that time. As another example, PTP leader clock device 184 may include an RF radio that receives a signal (e.g., a frequency modulation (FM) signal corresponding to a dedicated FM channel) to synchronize the primary clock of PTP leader clock device 184 with an atomic clock. In accordance with some implementations, the PTP leader clock device 184 may be a network component, such as a network switch (e.g.,a top-of-the-rack (ToR) switch) that may be part of the network fabric 180. In accordance with further example implementations, the PTP leader clock device 184 may be a boundary node of the clock hierarchy that synchronizes its clock with another PTP leader. Furthermore, in accordance with further implementations, the PTP leader clock device 184 may be a device (e.g., a bus device, such as a PCIe bus device) of the computing platform 100.

[0054] In accordance with example implementations, the vPTPCD 128 acts as a boundary node of the PTP clock hierarchy. Thus, in accordance with example implementations, the vPTPCD 128 serves as a PTP follower that communicates messages with the PTP leader clock device 184 for the purpose of synchronizing a clock of the vPTPCD 128 with a clock of the PTP leader clock device 184. Furthermore, the vPTPCD 128 acts as a PTP leader to communicate messages with a particular VM instance 101 so that the VM instance 101 can synchronize its clock with the clock of the vPTPCD 128.

[0055] In Fig. Further details of the platform controller 108 according to embodiments are shown. According to Fig. combined with Fig. According to embodiments, the PCI functions 114 are implemented as virtual functions (VFs) 150 (or “virtual function instances”). In Fig. N virtual functions 150-1 through 150-N are shown. According to example implementations, the VFs 150 conform to PCIe Single Root I / O Virtualization (SR-IOV) as defined by a PCI Special Interest Group (SIG), a community that defines standards (including the SR-IOV specification) related to PCIe.

[0056] According to example implementations, each VF 150 includes a corresponding vPTPCD 128. Furthermore, according to example implementations, each VF 150 can be assigned to a respective single VM instance 101. For example, vPTPCD 128-1 emulates a PTP heartbeat device for VM 101-1, and vPTPCD 128-N emulates a PTP heartbeat device for VM 101-N. According to further example implementations, a particular VF 150 can be assigned to multiple VM instances 101.

[0057] In accordance with further example implementations, one or more PCI functions 114 may be implemented as functions (e.g., physical PCI functions) rather than as virtual functions.

[0058] SR-IOV enables a PCIe device (such as vPTPCD 128 implemented by the platform controller 108) to present itself to a host (e.g., the computing platform 100) as multiple distinct virtual devices. The PCIe device (e.g., the platform controller 108) implements a PCIe Physical Function (PF) 252, which is divided into multiple VFs 150 (e.g., N VFs 150-1 through 150-N for the Fig. shown example implementation) to share the resources of the PCIe device in a virtual environment.

[0059] The PF 252 enables control over the creation and allocation of VFs 150. The PF 252 contains an SR-IOV capability structure, and the PF 252 manages the SR-IOV functionality. According to the example implementations, the PF 252 can be discovered, managed, and manipulated like any other PCIe device in the computing platform 100. According to the example implementations, the VFs 150 share the underlying platform controller hardware and the PCIe interface to the PCI bus 110.

[0060] As in Fig. As shown, the platform controller 108 includes, in accordance with example implementations, one or more processors 254 and a memory 256. The processor(s) 254 execute instructions 257 (e.g., instructions stored in memory 257) of the platform controller 108 to perform tasks of the platform controller 108. The processor(s) 254 may include, in accordance with example implementations, one or more processing cores, one or more microcontrollers, one or more ASICs, one or more programmable gate arrays, etc. The memory 256 is a non-transitory storage medium and may include one or more storage devices for storing data and machine-readable instructions.Although not shown, memory 256 may include a memory controller, or alternatively, a memory controller may be coupled to the memory device(s) to control access to the data in the memory device(s).

[0061] According to example implementations, the platform controller 108 is a PTP follower, and the platform controller 108 synchronizes its system clock 260 with the clock of a PTP leader. More specifically, according to example implementations, the processor(s) 254 execute instructions (e.g., a subset of instructions 257) to synchronize PTP messages with the PTP leader clock device 184 ( Fig. ) via a network port 258 (e.g., an Ethernet port) of the NIC 130 of the platform controller to synchronize the system clock 260 with the clock of the PTP leader clock device 184. The platform controller 108 therefore calibrates its system clock 260 at certain set times in response to the PTP message communication with the PTP leader clock device 184. According to further implementations, the hardware of the platform controller 108 may communicate PTP messages with the PTP leader clock device 184 instead of executing instructions or in combination with executing instructions. According to example implementations, the platform controller 108 reads PTP messages with the PTP leader clock device 184 in response to a VM instance 101 reading a clock register of a vPTPCD 128 (e.g.,In response to a clock register read request from a VM instance 101, the platform controller 108 determines the current value of the system clock 260, adjusts the value based on the number of platform controller clock ticks since the last adjustment time, and returns a clock value to the VM instance 101 that represents a PTP clock time. Depending on the implementation, the platform controller 108 may perform these actions by executing instructions, using platform controller 108 hardware, or through a combination of instruction execution and hardware.

[0062] According to example implementations, SR-IOV enables the activation of PTP clock devices by the VM instances 101 to bypass an emulation layer in the hypervisor 106. The VFs 150 are lightweight according to SR-IOV, so that a large number of VFs 150 can be implemented in the platform controller 108. For example, if the computing platform 100 includes a large number of VM instances 101, a correspondingly large number of VFs 150 can be implemented on the platform controller 108 to perform PTP clock emulation for the respective VM instances 101.

[0063] An SR-IOV-capable device (e.g., the platform controller 108) may be configured (e.g., by the hypervisor 106 or another entity of the computing platform 100) to appear in the PCI memory space as multiple VFs 150, where each VF 150 has its own PCI memory space. A PCI memory may refer to a portion of memory space in the computing platform 100 that contains structures that can be used by an entity (e.g., a VM instance 101 or other entity) of the computing platform 100 to interact with a corresponding PCI device, such as one of the VFs 150.

[0064] According to example implementations, each VF 150 has a class code representing a PTP clock device to perform PTP clock device emulation. According to PCI, a class code is a three-byte field in a function's configuration space header that identifies a functionality of the function. For example, a class code may contain a base class subfield (e.g., one byte in length), a subclass subfield (e.g., one byte in length), and a programming interface subfield (e.g., one byte in length). The base class subfield broadly classifies the type of functionality provided by the VF 150. The subclass subfield more precisely identifies the type of functionality provided by the VF 150. The programming interface subfield identifies the specific register-level interface (if any) of a VF 150 so that device-independent software (e.g., a VM) can interact with the VF 150.

[0065] In accordance with example implementations, instead of emulating PTP clocks at specific memory location addresses, the hypervisor 106 may assign each VM instance 101 its respective VF 150. Therefore, depending on the particular implementation, multiple VM instances 101 may share a VF 150, or each VM instance 101 may have its own VF 150.

[0066] In Fig. , a memory address space 318 of the computer platform 100 is illustrated according to an example implementation. Referring to Fig. combined with Fig. According to some implementations, based on the Base Class subfield and the Subclass subfield together, the VM instance 101 may recognize that a VF 150 provides the functionality of a PTP clock device. The Programming Interface subfield may identify a PTP clock device information element. In accordance with example implementations, an information element may be one or more registers, such as a PTP clock device register set 316. In Fig. N PTP clock device register sets 316-1 to 316-N are shown. In this way, a VM instance 101 can read a PTP clock value from a register of a PTP clock device register set 316, and the platform controller 108 synchronizes this PTP clock value with the clock of a PTP master device, such as the PTP master clock device 184 ( Fig. ), as described herein.

[0067] In accordance with example implementations, the PTP clock register set 316 is part of a corresponding vPTPCD 128. The PTP clock register set 316 in the corresponding vPTPCD 128 is mapped to the memory address space 318, specifically to the PCI memory in the memory address space 318. The memory address space 318 may be implemented with a number of memory devices in the computer platform 100, including the system memory 113 of Fig. , registers in the platform controller 108, etc. In accordance with example implementations, the PTP clock register sets 316 include memory-mapped registers that are part of the memory address space 318.

[0068] In accordance with other example implementations, such as in examples where functions 114 are PFs, PTP clock device register sets 316 may be part of an I / O address space of computing platform 100.

[0069] The memory addresses of memory address space 318 may be mapped to a memory controller and / or a PCIe controller. The memory controller is connected to a memory device (or alternatively, to multiple memory devices). A memory device may be a volatile memory device (e.g., a dynamic random access memory or DRAM device, a static random access memory or SRAM device, etc.). Alternatively, a memory device may also be a non-volatile memory device (e.g., a flash memory device, etc.). A PCIe controller is connected to a PCIe device. A PCIe device may support memory accesses, but they may not actually access memory devices such as DRAMs or SRAMs. Instead, a PCIe device may access memory-related registers that are part of memory address space 318.

[0070] In accordance with example implementations, the starting address (or base address) of the PCI memory space for each PTP clock register set 316 is based on a memory address stored in a PCI base address register (BAR) 220 ( Fig. ) located in the PCI configuration space. The PCI BAR 220 is contained in the PF 252, as shown in Fig. PCI defines multiple BARs that can be used to store different memory addresses for a PCI device or function.

[0071] In Fig. N example base addresses 360-1 to 360-N are shown for the respective PTP clock register sets 316. According to the example implementations, the base addresses 360 are determined based on the values ​​stored in the BAR 220 ( Fig. ), and the hypervisor 106 writes the memory address to the BAR 220. The memory address contained in the BAR 220 defines a portion of PCI memory space to be divided equally among the VFs 150. The defined portion of PCI memory space has a size of BARSIZE. Each VF 150 can be assigned a portion of PCI memory space of size BARSIZE / N (where "N" is the number of VFs 150). The base address 360 of the PCI memory containing a particular PTP clock register set 316 is calculated based on the VF number of the corresponding VF 150 in conjunction with the memory address contained in the BAR 220.

[0072] Referring to Fig. combined with Fig. According to example implementations, a PTP clock device driver 122 ( Fig. ) or another program residing in a VM instance 101 to access the PCI memory space of the corresponding VF 150. In accordance with example implementations, each guest operating system 102 may include a PTP clock device driver 122. According to some implementations, a guest operating system 102 in a VM instance 101 may include an application programming interface (API) that enables a PTP clock device driver 122 of the VM instance 101 to access the PCI memory space of the corresponding VF 150.

[0073] After SR-IOV is enabled in the PF 252 of the platform controller 108, the VFs 150 are available for enumeration by the configuration software running on the main processor 112 and can be addressed by bus, device, and function. The configuration software, which in some examples is the hypervisor 106, can then configure the desired number of VFs 150 from those supported by the PF 252 and allocate resources accordingly (i.e., allocate a portion of the memory space 318 for the VFs 150 by programming the BAR 220). Once completed, the PTP clock register sets 316 are addressable by the processor 112.

[0074] Referring to Fig. combined with Fig. According to example implementations, the PTP clock device driver 122 of the guest operating system 102 is capable of querying the hypervisor 106 to obtain the corresponding base address 360 of the PTP clock device register set 316 of the corresponding vPTPCD 128. This enables the PTP clock device driver 122 of the guest operating system 102 to communicate messages with a vPTPCD 128 to synchronize a clock of the VM instance 101 with a clock of the vPTPCD 128.

[0075] In cases where the guest operating system 102 is unable to automatically detect a PTP clock device (e.g., because the guest operating system 102 is unable to detect the base class / subclass / programming interface values ​​for a PTP clock device described above), the address for the PTP clock device may be provided to the guest operating system 102 by other means. An example of a guest operating system that is unable to automatically detect PCI PTP clock devices is the LINUX operating system. In accordance with example implementations, the address for a PTP clock device may be provided to the guest operating system 102 by including the address in a kernel command line used to boot the guest operating system 102. In accordance with further implementations, other methods for providing the address for a PTP clock device to the guest operating system 102 may also be used.

[0076] In accordance with example implementations, each vPTPCD 128 may include write detection logic for detecting writes to the corresponding PTP clock register set 316 and / or read detection logic for detecting reads from the corresponding PTP clock register set 316. The write detection logic is capable of detecting writes by VM instances 101 or other entities to the PTP clock register sets 316 of the respective vPTPCDs 128. Writing registers to the PTP clock register sets 316 by the VM instances 101 may be performed as part of PTP messaging. For example, the VM instances 101 may write to the registers to send PTP delay request messages to the vPTPCD 128.

[0077] Reading the registers of the PTP clock register sets 316 may also be performed as part of PTP messaging. For example, the VM instances 101 may read from the registers to receive messages sent by the vPTPCD 128, such as PTP synchronization messages, PTP follow-up messages, and PTP delay reply messages.

[0078] Referring to Fig. combined with Fig. In response to a write or read operation, the write or read detection logic in the vPTPCD 128 may signal an interrupt to the processor 254 of the platform controller 108, e.g., using a corresponding PTP clock device indicator 224 (in Fig. N PTP clock device indicators 224-1 through 224-N are shown. The PTP clock indicator 224 may indicate which register of the PTP clock register set 316 was written to or read from. The PTP clock indicator 224 may include a signal, interrupt, command, or other indication related to PTP synchronization message operations or, generally, operations related to communication with the vPTPCDs 128. The PTP clock indicator 224 may include information identifying the associated VF 150 and the register to which the read / write operation occurred.

[0079] In response to a PTP clock indication 224, machine-readable instructions (e.g., firmware) running on the processor 254 may synthesize an appropriate response for the corresponding vPTPCD 128. In accordance with further implementations, the platform controller 108 includes hardware that synthesizes the response under the control of machine-readable instructions (e.g., firmware) running on the processor 254. For example, data transmitted by the PTP clock device driver 122 may be intercepted by the vPTPCD 128 and placed directly into a circular buffer (or other storage structure) associated with the VM instance 101.

[0080] Other implementations are also conceivable that fall within the scope of the appended claims. For example, the platform controller 108, as shown in Fig. shown, in accordance with further implementations, the platform controller 108 may synchronize its system clock 260 with a clock source other than a PTP leader. As a more specific example, in accordance with some implementations, the platform controller 108 may include a GNSS receiver that receives a GNSS signal (e.g., a composite signal representing received transmissions from multiple GNSS satellites). The platform controller 108 may process the GNSS signal to synchronize the clock 260 with the satellite clock of the nearest satellite.This processing may include, for example, the platform controller 108 decoding the GNSS signal into content attributable to multiple satellites; the platform controller 108 determining a physical location of the GNSS receiver and identifying the nearest satellite based on the decoded content; the platform controller 108 determining a satellite clock value provided by the nearest satellite based on the decoded content; and the platform controller 108 compensating for a delay associated with the satellite clock value. For these example implementations, the platform controller 108 may be considered a PTP leader. In accordance with further implementations, the platform controller 108 may communicate with an NTP provider (e.g., an NTP server) to synchronize the clock 260 with the NTP provider's clock (NTP).In these example implementations, the platform controller 108 is an NTP client and the platform controller 108 is a PTP leader for the vPTPCDs 128.

[0081] As in Fig. As shown, a device 400 according to example implementations includes a storage medium 404, a supervisor 412, and a controller 416. In accordance with example implementations, the supervisor 412 may be a hypervisor, such as the hypervisor 106 of Fig. , or a container engine daemon. The controller 416 may be, for example, a platform controller, such as the platform controller 108 of the Fig. . The storage medium 404 stores a plurality of information elements 408. The information elements 408 may, for example, be corresponding registers or register sets, such as the PTPCD register sets 316 in Fig. . The supervisor 412 provides a plurality of virtual nodes. The virtual nodes can be, for example, virtual machine instances, such as the VM instances 101 of Fig. and / or container instances. The controller 416 is separate from the supervisor 412. The controller 416 provides several virtual PTP clocks, such as the vPTPCDs 128 of the Fig. . Each virtual PTP clock device corresponds to an information element 404. The controller 416 uses the information element 404 corresponding to a particular virtual PTP clock device to provide a PTP-based time for the particular virtual PTP clock device.

[0082] According to Fig. A non-transitory, machine-readable storage medium 500 stores machine-executable instructions 504. When executed by a machine, the instructions 504 cause the machine to store information specifying the address positions of register sets of multiple virtual PTP clocks. The register sets may, for example, be the PTPCD register sets of Fig. act, and the virtual PTP clock devices can use the vPTPCDs 128 of the Fig. The virtual PTP clock devices are provided by a controller and are connected to a plurality of virtual nodes. For example, the controller 416 may be a platform controller, such as the platform controller 108 of Fig. . The virtual nodes can be, for example, virtual machine instances, such as the VM instances 101 of Fig. and / or container instances. Instructions 504, when executed by the machine, further cause the machine to execute the virtual nodes to use the information to access the virtual PTP clock devices. A particular virtual machine communicates with a particular virtual PTP clock device to read a clock value provided by the particular virtual PTP clock device.

[0083] As in Fig. As shown, a process 600, according to example implementations, includes the allocation (block 604) of virtual functions to corresponding virtual nodes by a supervisor in a system including a hardware processor. The supervisor may be, for example, a container engine daemon or a hypervisor, such as the hypervisor 106 of Fig. . The processor 112 from Fig. is an example of a hardware processor. The virtual functions can be PCI virtual functions, such as virtual functions 150 in Fig. . The virtual nodes can be, for example, virtual machine instances, such as the VM instances 101 of Fig. , or container instances. The virtual functions represent corresponding PTP clock devices. The PTP clocks can, for example, be virtual clocks, such as the vPTPCD clocks 128 of the Fig. The virtual functions are provided by a controller separate from the supervisor. The process 600 further includes executing (block 608) the virtual nodes in the system to use information specifying addresses of the respective virtual functions to access the respective PTP clock devices. The information may, for example, be information provided by a register or register set, such as the register sets 316 in Fig. . A given virtual node communicates with a given respective PTP clock device to read a clock value provided by the given respective PTP clock device.

[0084] The virtual nodes can be virtual machines or containers, as shown in the example implementations. Specific benefits can include a reduction in core processing overhead and a reduction in the attack surface for security risks.

[0085] According to example implementations, the controller includes a clock. The controller communicates with a precision time protocol master clock device to synchronize the controller's clock with a clock of the precision time protocol master clock device. The controller shall provide the precision time protocol-based time based on a value of the controller's clock. Specific benefits may include a reduction in core processing overhead and a reduction in the attack surface for security measures.

[0086] According to example implementations, the Precision Time Protocol master clock device is part of a network switch. Specific benefits may include a reduction in core processing overhead and a reduction in the attack surface for security measures.

[0087] According to example implementations, the ECU synchronizes the ECU clock to adjustment times. A given virtual node shall read a register of the ECU corresponding to the given virtual precision time protocol clock and respond to the register read. In response to the read, the ECU shall adjust the value of the ECU clock based on a last adjustment time of the adjustment times to provide an adjusted clock value and provide the adjusted clock value to the given virtual node. Specific benefits may include a reduction in core processing overhead and a reduction in the security attack surface.

[0088] According to example implementations, the controller communicates messages with the precision time protocol leader. The messages include a synchronization message provided by the precision time protocol leader. The synchronization message includes data representing a clock value of the precision time protocol leader and a first timestamp associated with the clock value of the precision time protocol leader. Particular benefits may include a reduction in core processing overhead and a reduction in the attack surface for security measures.

[0089] In accordance with example implementations, the messages also include a follow-up message and a delay request message. The follow-up message is provided by the precision time protocol leader, and the follow-up message contains data representing a time at which the precision time protocol leader transmitted the synchronization message. The delay request message is provided by the control device, and the delay request message contains data representing a time at which the control device transmitted the delay request message. Specific benefits may include a reduction in core processing overhead and a reduction in the attack surface for security measures.

[0090] According to example implementations, the controller includes a Global Navigation Satellite System (GNSS) receiver for receiving a GNSS signal. The controller can provide precision time protocol time based on the GNSS signal. Specific benefits may include a reduction in core processing overhead and a reduction in the attack surface for security measures.

[0091] According to example implementations, each information element from the plurality of information elements corresponds to a register set from a plurality of register sets. The plurality of register sets are located in a memory address space of a computing platform. Specific advantages may include a reduction in core processing overhead and a reduction in the security attack surface.

[0092] According to example implementations, the information elements include base address registers. Each base address register contains a memory address for deriving an address for the corresponding virtual PTP clock device. Specific benefits may include a reduction in core processing overhead and a reduction in the security attack surface.

[0093] According to example implementations, the supervisor includes either a hypervisor or a container engine, and the controller includes a baseboard management controller. Specific benefits can include a reduction in core processing overhead and a reduction in the security attack surface.

[0094] According to implementation examples, each virtual precision time protocol clock device corresponds to a different virtual function from a plurality of virtual functions, and the control unit provides the plurality of virtual functions. Specific benefits may include a reduction in core processing overhead and a reduction in the security attack surface.

[0095] According to implementation examples, the supervisor should assign the given virtual machine to the virtual function corresponding to the given virtual PTP clock device. Specific benefits may include a reduction in core processing overhead and a reduction in the attack surface for security risks.

[0096] According to example implementations, the ECU contains a clock. The controller communicates with a Network Time Protocol (NTP) provider to synchronize the controller's clock with a clock from the NTP provider. The ECU shall provide the precision time protocol-based time based on a value from the ECU's clock. Specific benefits may include a reduction in core processing overhead and a reduction in the attack surface for security measures.

[0097] According to the example implementations, the supervisor should associate multiple virtual PTP clock devices with the given virtual node. Specific benefits may include a reduction in core processing overhead and a reduction in the security attack surface.

[0098] According to implementation examples, multiple virtual precision time protocol clock devices correspond to a virtual function, and the control device provides the one virtual function. Specific benefits may include a reduction in core processing overhead and a reduction in the attack surface for security measures.

[0099] Although the present disclosure has been described with respect to a limited number of implementations, those skilled in the art, having the benefit of this disclosure, will appreciate numerous modifications and variations thereof. The appended claims are intended to cover all such modifications and variations.

Claims

[1] A device comprising: a storage medium for storing a plurality of information items; a supervisor for providing a plurality of virtual nodes; and a controller separate from the supervisor to provide a plurality of virtual precision time protocol clock devices, wherein: each virtual precision time protocol clock device of the plurality of virtual precision time protocol clock devices corresponds to an information element of the plurality of information elements; the controller uses the information element corresponding to a given virtual precision time protocol clock device of the plurality of virtual precision time protocol clock devices to provide a precision time protocol-based time for the given virtual precision time protocol clock device; and the controller providing the precision time protocol-based time comprises communicating a sequence of precision time protocol-based messages using the given virtual precision time protocol clock device and with a given virtual node of the plurality of virtual nodes to synchronize a clock of the given virtual node with the precision time protocol-based time. [2] The apparatus of claim 1, wherein the plurality of virtual nodes comprises at least one of a plurality of virtual machines or a plurality of containers. [3] Device according to claim 1, wherein: the controller includes a clock; the controller communicates with a precision time protocol master clock to synchronize the controller's clock with a clock of the precision time protocol master clock; and the controller provides the precision time protocol-based time based on a value from the controller's clock. [4] The apparatus of claim 3, wherein the precision time protocol master clock device is part of a network switch. [5] Device according to claim 3, wherein: the controller synchronizes the controller clock to setting times; the given virtual node is to read a register of the controller corresponding to the given virtual precision time protocol clock device and responsive to the reading of the register; and the controller, in response to the reading, adjusts the value of the controller's clock based on a last adjustment time of the adjustment times to provide an adjusted clock value, and provide the adjusted clock value to the given virtual node. [6] The apparatus of claim 3, wherein the controller communicates messages with the precision time log keeping device, the messages comprise a synchronization message provided by the precision time log keeping device, and the synchronization message comprises data representing a clock value of the precision time log keeping device and a first timestamp associated with the clock value of the precision time log keeping device. [7] The apparatus of claim 6, wherein the messages further comprise: a follow-up message provided by the precision time protocol managing device, the follow-up message comprising data representing a time at which the given precision time protocol managing device transmitted the synchronization message; and a delay request message provided by the controller, the delay request message comprising data representing a time at which the controller transmitted the delay request message. [8] Device according to claim 1, wherein: the controller comprises a GNSS (Global Navigation Satellite System) receiver for receiving a GNSS signal; and the controller provides the precision time protocol time based on the GNSS signal. [9] The apparatus of claim 1, wherein each information element of the plurality of information elements corresponds to a register set of a plurality of register sets, and the plurality of register sets are located in a memory address space of a computer platform. [10] The apparatus of claim 1, wherein the plurality of information elements comprises a plurality of base address registers, each base address register of the plurality of base registers containing a memory address for deriving an address for the corresponding virtual precision time protocol clock device. [11] The apparatus of claim 1, wherein the supervisor comprises either a hypervisor or a container engine and the controller comprises a baseboard management controller. [12] The apparatus of claim 1, wherein each virtual precision time protocol clock device of the plurality of virtual precision time protocol clock devices corresponds to a different virtual function of a plurality of virtual functions, and the controller provides the plurality of virtual functions. [13] Device according to claim 1, wherein: the controller includes a clock; the controller communicates with a Network Time Protocol (NTP) provider to synchronize the controller's clock with a clock of the NTP provider; and the controller provides the precision time protocol-based time based on a value from the controller's clock. [14] The apparatus of claim 1, wherein the supervisor is to allocate a plurality of virtual precision protocol clocks to the given virtual node. [15] The apparatus of claim 1, wherein a plurality of virtual precision time protocol clocks of the plurality of virtual precision time protocol clocks correspond to a virtual function, and the controller provides the one virtual function. [16] A non-transitory, machine-readable storage medium that stores machine-executable instructions that, when executed by a machine, cause the machine to: to store information indicating address locations of register sets of a plurality of virtual precision time protocol clock devices, the virtual precision time protocol clock devices being provided by a controller and associated with a plurality of virtual nodes; and the plurality of virtual nodes to execute the information to use the information to access the plurality of virtual precision time protocol clocks, wherein a given virtual node of the plurality of virtual nodes communicates a sequence of precision time protocol-based messages with a given virtual precision time protocol clock of the virtual precision time protocol clocks to synchronize a clock of the given virtual node with a precision time protocol-based time. [17] The storage medium of claim 16, wherein the information comprises memory addresses of the register sets. [18] The storage medium of claim 16, wherein the plurality of virtual precision time protocol clock devices comprise a plurality of virtual machines or a plurality of containers. [19] A procedure comprising: Assigning virtual functions to respective virtual nodes of a plurality of virtual nodes by a supervisor in a system comprising a hardware processor, wherein the virtual functions represent respective precision time protocol clock devices and the virtual functions are provided by a controller separate from the supervisor, and Executing the plurality of virtual nodes in the system to use information indicative of addresses of the respective precision time protocol clocks to access the respective precision time protocol clocks, wherein a given virtual node of the plurality of virtual nodes communicates a sequence of precision time protocol-based messages with a given respective precision time protocol clock of the precision time protocol clocks to synchronize a clock of the given virtual node to a precision time protocol-based time. [20] The method of claim 19, wherein the plurality of virtual nodes comprises at least a plurality of virtual machines or a plurality of containers.

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