Semiconductor light emission component, light emission device and distance measuring device

Abstract

Semiconductor light emission device (500) with a structure in which a substrate (301), a first reflector (302), a resonator cavity (303) with an active layer, a second reflector (504) and a tunnel transition layer (542) are stacked in this sequence, the semiconductor light emission device (500) comprising: an insulating layer (561); a transparent conductive layer (562) arranged on the insulating layer (561); a first current constriction section, which is provided with an oxidation constriction layer (306) in the second reflector (504); and a second current constriction section, which is provided with the insulating layer (561) formed on an upper side of the tunnel transition layer (542) and having an opening, and a contact section between the transparent conductive layer (562) and a semiconductor layer with which the transparent conductive layer (562) is in contact, where a width d6 of the second stream constriction section is smaller than a width d5 ​​of the first stream constriction section, the tunnel transition position (542) is located on an uppermost section of the second reflector (504), and the insulating layer (561) and the transparent conductive layer (562) are arranged on the tunnel transition layer (542), and the transparent conductive layer (562) is in contact with the second reflector (504) via the tunnel transition layer (542).

Description

BACKGROUND OF THE INVENTION Technical field

[0001] The present invention relates to a semiconductor light emission device, a light emission device and a distance measuring device. State of the art

[0002] A vertical cavity surface-emitting laser (VCSEL) attracts attention as a light source for light detection and distance measurement (LIDAR) of a time-of-flight type (ToF type).

[0003] Higher power is required for light sources to improve distance measurement accuracy and increase the measurable distance.

[0004] One possible method for achieving high power output in a VCSEL is to increase the emission diameter. However, simply increasing the emission diameter reduces the current density in the central region of the emission diameter and increases the current density in the peripheral region. In other words, merely increasing the emission diameter causes problems with far-field beam control and durability.

[0005] Document WO 2019 / 107 273 A1 discloses a substrate-back-emitting VCSEL, wherein a current constriction structure, distinct from oxidation constriction, is arranged on the front side of a substrate. This configuration allows the current density to be increased not only in a circumferential section but also in the section around the center of the light emission diameter, while simultaneously increasing the light emission diameter itself. However, in the case of a substrate-back-emitting VCSEL, light is absorbed by the substrate, so such a conversion may not be possible depending on the wavelength, or high power cannot be achieved.

[0006] Publication JP 2006-114915A discloses a substrate-front-emitting VCSEL in which the current constriction structure, which is distinct from the oxidation constriction, is arranged on the front of the device, which is the light-emitting side, by diffusion or ion implantation. By increasing the light emission diameter using this configuration, the current density can be increased not only in the circumferential section but also in the section around the center of the light emission diameter.

[0007] Publication JP 2006-114915A discloses a method for forming a current constriction structure in which a current flows only through the central section by implanting ions into the circumferential section on the substrate front face to increase the resistance of the circumferential section. With reference to Fig.13 below describes a problem that arises when the current constriction structure is formed in this way.

[0008] A VCSEL according to Fig.13 comprises an electrode layer 701, an n-GaAs substrate 702, an n-DBR layer 704, an active region 706, an insulating layer (e.g., an oxide) 707, a p-DBR layer 708, a p-GaAs layer 710, and an upper electrode 714. In such a VCSEL, a high-resistance region 712 is formed by implanting ions into a circumferential section of the p-GaAs layer 710, and a current path from the second electrode 714 to a current injection region 720 is left in the upper section of the p-GaAs layer 710. Furthermore, a current path is formed from the current injection region 720 to an opening 716 in the p-DBR 708. Consequently, the thickness of the p-GaAs layer 710 must be on the order of µm. If the distance of the current injection region 720 in the vertical direction of the substrate becomes thick or large (on the order of µm), the resistance increases, and as a result, the voltage of the entire semiconductor light-emitting device increases.

[0009] Furthermore, document CN 209 516 312 U discloses a laser structure with vertical surface emission, document JP 2018 049 862 A discloses a light-emitting nitride semiconductor device with a nitride semiconductor having a wurtzite structure, document DE 10 2019 106 644 A1 discloses a vertical resonator surface emission laser device with an integrated tunnel contact, and document US 2005 / 0 111 507 A1 discloses a surface-emitting semiconductor laser used as a light source in optical information processing and high-speed optical communication, and a method for its manufacture. INVENTION SUMMARY

[0010] Taking into account the foregoing, it is an object of the present invention to provide a semiconductor light emission device that easily controls rays in a far field with high power, while limiting an increase in voltage throughout the device.

[0011] The object of the invention is achieved by a semiconductor light emission device according to claims 1 and 2, a light emission device according to claim 10, and a distance measuring device according to claim 11. Further features and advantageous embodiments are shown in the dependent claims.

[0012] According to the present invention, a semiconductor light-emitting device can be provided that easily controls beams in a far field with high power, while limiting the voltage increase across the entire device. By using this semiconductor light-emitting device, a distance measuring device can be provided that improves distance measurement accuracy and the measurable distance.

[0013] Further features of the present invention can be seen from the following description of exemplary embodiments with reference to the accompanying drawing. BRIEF DESCRIPTION OF THE DRAWING Fig. Figure 1 shows a representation illustrating an embodiment of the present invention; Fig. 2A and Fig.Figure 2B shows graphs illustrating a distribution and change of a current density according to an embodiment of the present invention; Fig. Figure 3 shows a representation illustrating Example 1; Fig. Figure 4 shows a representation illustrating Example 2; Fig. Figure 5 shows a representation illustrating Example 3; Fig. 6A and Fig. Figure 6B shows graphs illustrating a distribution and change in current density according to Example 3; Fig. Figure 7 shows a representation illustrating Example 4; Fig. Figure 8 shows a representation illustrating Example 5; Fig. Figure 9 shows a representation illustrating Example 6; Fig. Figure 10 shows a representation illustrating example 7; Fig.Figure 11 shows a representation illustrating Example 8; Fig. Figure 12 shows a representation illustrating Example 9; and Fig. Figure 13 shows a representation illustrating a comparative example. DESCRIPTION OF THE EXAMPLES OF EXECUTION

[0014] Exemplary embodiments of the present invention are described below. The present invention is not limited to the exemplary embodiments described below and includes modifications and adaptations that can be carried out on the basis of the knowledge of a person skilled in the art without departing from the spirit and scope of the present invention.

[0015] A semiconductor light emission device 100 according to an embodiment of the present invention is described below with reference to Fig.1 described. The semiconductor light emission device 100 comprises a substrate 101, a first distributed Bragg reflector (DBR) 102, a semiconductor resonator cavity 103 and a second DBR 104. The first DBR 102 and the second DBR 104 correspond respectively to the first reflector and the second reflector of the present invention.

[0016] A multitude of quantum well layers 140 are arranged in the resonator cavity 103. An AlGaAs layer, whose Al content is higher than that of the other layers, is contained within part of the second DBR 104. An oxidation constriction layer 106, whose perimeter is insulated, is formed by carrying out a vapor oxidation on the AlGaAs layer. The oxidation constriction layer 106 corresponds to the first current constriction section. Fig.1 only indicates the isolated section by the reference numeral 106, however, the non-oxidized central section of the semiconductor layer also corresponds to the oxidation constriction layer 106.

[0017] In this case, the second DBR 104 is formed by a semiconductor. In a further embodiment of the present invention, a third DBR, which is different from the second DBR, can also be arranged on the second DBR, and its details are described below in Example 5.

[0018] The resonator cavity 103 and the second DBR 104 are machined to be tubular (or round) and mesa-shaped, and are covered with an insulating layer 161. A transparent conductive layer 162 is formed on the insulating layer 161.

[0019] An upper electrode 150 is in electrical contact with part of the transparent conductive layer 162. A lower electrode 151 is in ohmic contact with the back of the substrate 101.

[0020] According to Fig.1. The insulating layer 161, the central section of which has been partially removed, is formed on the upper side of the second DBR 104, which has been machined to be tubular and mesa-shaped. The section where the insulating layer 161 has been removed is referred to below as the "insulating opening." In the insulating opening, the transparent conductive layer 162 is in contact with the upper side of the second DBR 104. This insulating opening provides a contact section between the transparent conductive layer 162 and the upper side of the second DBR 104. The shape of the insulating section can be a circle, an ellipse, a polygon, or a similar shape. If the shape of the insulating opening includes an acute-angled section, current tends to concentrate at this section, which is undesirable with regard to the current profile and durability.The shape of the insulating opening is preferably close to a circle. Charge carriers supplied from the upper electrode 150 flow into the second DBR 104 only through the contact section of the insulating opening. In other words, the second current constriction section is formed by: the insulating layer 161, which has the insulating opening; and the contact section between the second DBR 104 and the transparent conductive layer 162. If the shape of the second current constriction section is, for example, a circle, its diameter is d2.

[0021] In the case that the cross-sectional shape of the insulation layer 161 tapers to be thinner closer to the central section, according to Fig. 1. The size of the second current constriction structure is defined by the distance d2 at the peak section. In other words, d2 is the essential quantity by which the current is constricted by the second constriction structure.

[0022] According to Fig. 1. The mesa form extends from the second DBR 104 to the resonator cavity 103; however, it is necessary that the tubular mesa form is formed at a depth lower than the oxidation constriction layer 106. This means that the mesa form can be formed at a depth in the middle of the resonator cavity 103, or at a depth in the middle of the first DBR 102.

[0023] The present embodiment describes a structure in which the light-emitting element is processed in the tubular mesa form, but the present invention is not limited to this. For example, instead of uniformly processing the circumference into a tubular form, the oxidation constriction layer 106 can be formed by removing a portion of the section by etching, extending to a target depth, and subsequently isolating the circumference by vapor oxidation.

[0024] Furthermore, there is in Fig. 1. A layer of the transparent conductive layer 162, however, one or more transparent insulating layers (for example, SiOx, SiNx, TiOx) can be stacked on top of it if required. In this case, part of the insulating layer under the upper electrode 150 is removed such that the upper electrode 150 and the transparent conductive layer 162 are electrically connected.

[0025] If a high refractive index layer and a low refractive index layer, each with an optical layer thickness of λc / 4, form a pair, the first DBR 102 is formed with a plurality of these pairs stacked together. λc is a mean wavelength of the high-refractive-index band of the first DBR 102.

[0026] The quantum pot layer 140 has a configuration in which a pot layer is embedded by two barrier layers and is an active layer of the resonator cavity 103.

[0027] If a high refractive index layer and a low refractive index layer, each with an optical thickness of λc / 4, form a pair, the second DBR 104 is configured with a plurality of these pairs stacked together. However, a portion of the high refractive index layer on the top layer is replaced with a contact layer whose charge carrier density is higher than that of the other layers in order to improve the electrical contact properties with the transparent conductive layer 162. Furthermore, in the second DBR 104, a portion of the high refractive index layer closest to the quantum well layer (active layer 140) is replaced by an AlGaAs layer whose aluminum content is higher than that of the other layers.After the mesa of the VCSEL 100 is formed, this AlGaAs layer the size of the pot of the mesa is oxidized by vapor oxidation a predetermined length from the side wall of the mesa, whereby the oxidation constriction layer 106 with insulating properties is formed on its circumference.

[0028] The width d2 of the second current constriction, i.e., the insulation opening section where the insulating layer 161 is removed, is shorter than the width d1 of the semiconductor section on the inner side of the oxidation constriction layer 106, which is the first current constriction (this semiconductor section is a section where current can flow and is referred to below as the "non-oxidized section"). That is, d1 and d2 satisfy the following formula (1). d2 <d1

[0029] The following describes the case where the formulas of the non-oxidized section (semiconductor section on the inner side of the oxidation constriction layer 106) and the second current constriction are circles; however, the shape is not limited to a circle but can be an ellipse, a polygon, or a similar shape. In this case, each width d1 and d2, when cut at a specific cross-section, satisfies formula (1).

[0030] The effect of the above configuration is described below based on the calculation result, which is shown in Fig. 2A is specified. The component configuration used for this calculation model is based on the configuration of Example 1, which is described later below.

[0031] Fig.Figure 2 indicates a current density distribution flowing into quantum well position 140 if the diameter d2 of the isolation opening changes from 5 µm to 29 µm, provided the oxidation constriction diameter d1 is 30 µm. The abscissa according to Fig. 2A indicates a position in the radius direction, with the center of the mesa (i.e., the center of the non-oxidized section) being at position 0.

[0032] The solid line according to Fig. 2B indicates the state of a change if the current density at the central section is Jc, and the minimum value of the current density in the circumferential section (10-µm section from the circumferential edge of d1 in the direction of the central section) is Je.

[0033] A far-field image can be controlled by increasing the current density distribution of a current flowing into the quantum well position in the central section compared to the peripheral section. In other words, Jc>Je is preferred.

[0034] Furthermore, Jc>2×Je even more preferred.

[0035] According to the Fig. 2A and Fig. 2B The current density distribution, whose central section is prominent, can be formed in a region where the diameter d2 of the insulation opening section is less than 25 µm, i.e., in a region where formula (2) is satisfied. Furthermore, the current density profile in the central section is even more prominent in a region where d2 is less than 15 µm, i.e., in a region where formula (3) is satisfied.

[0036] If the current density, which is concentrated in the circumferential section of the oxidation constriction diameter, is extended towards the central section, the generation of non-light emission recoupling (or non-light emission feedback) and similar phenomena propagating from the circumferential section is limited, thereby improving the device's durability. The dashed line in Fig. 2B indicates the state of change of Jmax / Jmin in the current density in the non-oxidized section where Jmax is the maximum value and Jmin is the minimum value. In the region where d2 is less than 20 µm, Jmax / Jmin (dashed line) is approximately the same as Jc / Je (solid line).

[0037] With regard to durability, it is preferred that the following equation is satisfied. Jmax < 3.3 × Jmin

[0038] Durability is generally inversely proportional to the square of the current density, so that by satisfying the condition of formula (4) the scatter in the plane of local durability in the non-oxidized section can be limited to within one spot.

[0039] If the focus is placed on the far-field profile instead of durability, the following can be considered: Jmax < 10 × Jmin can be used. By fulfilling the conditions of formula (5), the variation in local durability in the non-oxidized section can be limited to within two locations.

[0040] The three components of the preferred device configuration, the non-oxidation constriction diameter d1 and the diameter d2 of the isolation opening, influence each other and are determined in accordance with the applications or requirements. In the event that the device configuration is determined according to Fig.For example, if the component has a 30 µm non-oxidation constriction diameter d1, as specified in Example 1 mentioned later, a preferred value for the diameter d2 of the isolation aperture is 12 to 18 µm, for example, if durability is a priority. The value of the diameter d2 can be 12 µm or less for applications where the focus is on the far-field profile rather than durability.

[0041] If the device configuration changes, the suitable ranges of d1 and d2 also change accordingly, so that preferred ranges of these are selected in accordance with the application.

[0042] In the present invention, the transparent conductive layer 162 is arranged on the second DBR 104 to form the second current constriction structure. The transparent conductive layer 162, which can be thinner than the p-GaAs layer used in the prior art ( Fig.13) can reduce the resistance of the second constriction structure. Compared to the case of using the ion implantation method, the voltage rise in the second current constriction structure section can consequently be reduced to approximately one decimal place with respect to the entire VCSEL 100. By using this device as a light source, a distance measuring device can therefore be provided that not only improves distance measurement accuracy and measurable distance, but also achieves a smaller size and lighter weight.

[0043] Examples of the present invention are described in detail below with reference to a specific layer configuration and the like of the light emission component. Example 1

[0044] A VCSEL 300 according to Example 1 is described below with reference to Fig. 3 described. Fig.Figure 3 shows a sectional view of the VCSEL 300 from Example 1. The VCSEL 300 is configured with a GaAs substrate 301, a first DBR 302, a semiconductor resonator cavity 303, and a second DBR 304, stacked in that order. Fig. 3. These components are in direct contact with each other, however another component may be positioned between them. The foregoing description serves to describe the structure and is not intended to limit the sequence of manufacturing each component.

[0045] Three quantum well layers 340 are arranged in the resonator cavity 303. An Al 0,98 GaAs is oxidized in part of the second DBR 304 by vapor oxidation, forming an oxidation constriction layer 306 which has insulating properties.

[0046] The resonator cavity 303 and the second DBR 304 are machined to be tubular and mesa-shaped, and are covered with an insulating layer 361. Furthermore, an indium tin oxide (ITO) layer 362 is formed on the insulating layer 361.

[0047] According to Fig.In the second DBR 304, the insulating layer 361, the middle section of which has been partially removed, is formed on the upper side of the second DBR 304, which has been machined to be mesa-shaped. In this removed section, the ITO layer 362 is in contact with the upper side of the second DBR 304. The section where the insulating layer 361 has been removed is referred to below as the "insulating opening." This means that the ITO layer 362 is in contact with the upper side of the second DBR 304 in the insulating opening section. The shape of the insulating opening is a circle in Example 1. An upper ring electrode 350 is in electrical contact with a portion of the ITO layer 362. A lower common electrode 351 is in ohmic contact with the back side of the GaAs substrate 301.

[0048] If an Al 0,1 GaAs layer and an Al 0,9By forming a pair of GaAs layers, each with an optical thickness of λc / 4, the first DBR 302 is configured with 35 stacked pairs. λc is a mean wavelength of the high-reflectivity band of the first DBR 302 and is 940 nm in Example 1.

[0049] The quantum well layer 340 has a configuration in which an 8 nm thick In 0,1 GaAs layer through 10 nm thick Al 0,1 GaAs barrier layers are embedded. In Example 1, three quantum well layers are arranged in the resonator cavity 303.

[0050] If an Al 0,1 GaAs layer and an Al 0,9 The second DBR 304, consisting of GaAs layers with an optical thickness of λc / 4, forms a pair. It is equipped with 20 stacked pairs. Part of the Al 0,1 However, the GaAs layer on the upper layer is replaced by a GaAs contact layer with a thickness of 50 nm and a charge carrier density of 1 × 10 19 cm -3This is to improve the electrical contact properties to the transparent conductive layer (ITO layer) 362. Furthermore, part of the Al 0,1 GaAs layer, which is closest to the quantum well layer 340 of the second DBR 304, with an Al 0,98 A GaAs layer, 30 nm thick, is replaced. After the mesa of the VCSEL 300 is formed, the Al 0,98 The GaAs layer is oxidized from the side wall of the mesa by a predetermined length from the edge of the mesa by vapor oxidation, whereby the oxidation constriction layer 306 with insulating properties is formed on its circumference.

[0051] The optical layer thickness of ITO layer 362 is assumed to be λc / 2.

[0052] The diameter d2 of the isolation opening section, where the isolation layer 361 is removed, is 10 µm, and the diameter d1 of the semiconductor section (i.e., a section through which a current can flow, i.e., the non-oxidized section) on the inner side of the oxidation constriction layer 306 is 30 µm. Since the non-oxidized section is a section of the resonator cavity 103 through which a current can flow, the diameter of the non-oxidized section is the light emission diameter of the VCSEL. This embodiment of Example 1 is the same as in Example 2 and in subsequent examples.

[0053] As in the Fig. 2A and Fig.As specified in 2B, in Example 1 the current density distribution profile of the current flowing into quantum well position 340 can be configured such that it is prominent in the central section, thereby controlling the far-field image. In the configuration of Example 1, the values ​​of Jc / Je and Jmax / Jmin are 4.2. In Example 1, a value greater than 3.3 is chosen for Jmax / Jmin because short-term use is assumed. Conversely, if the focus is on the lifetime factor, d2 can be set to, for example, 15 µm. In this case, the values ​​of Jc / Je and Jmax / Jmin are 2.4.

[0054] Furthermore, the second constriction structure is formed by the formation of a thin, transparent conductive layer 362 (approximately 300 nm thick) on the second DBR 304. Therefore, the voltage rise in the second constriction structure with respect to the entire VSCEL 300 can be reduced by approximately one order of magnitude compared to the ion implantation method. By using the light-emitting device of Example 1 as a light source, a distance measuring device can be provided that not only improves the distance measurement accuracy and the measurable distance, but also achieves a smaller size and lower weight. Example 2

[0055] A VCSEL 400 as an example is described below with reference to Fig.4 described. In Example 2, the current constriction function on the upper side of the second DBR is implemented by restricting the contact area similarly to Example 1, without forming the insulating opening.

[0056] Fig. Figure 4 shows a sectional view of the VCSEL 400 from Example 2. The configuration of the section from the lower common electrode 351 to the second DBR 304 according to Fig. 4 is the same as in Example 1, so that the assembling components are each designated with the same reference symbols as in Example 1, and a description of these is omitted.

[0057] A tunnel transition level 442 is arranged on the second DBR 304. According to Fig.4 The tunnel transition layer 442 is arranged on the outermost surface of the second DBR 304 only in the section with diameter d4 from the center of the mesa. The diameter d4 is smaller than the diameter d1 of the non-oxidized section of the oxidation constriction layer 106. Outside the upper side of the tunnel transition layer 442 and the upper side of the second DBR 304, an ITO layer 462 is formed on the section where the tunnel transition layer 442 is not located. The optical thickness of the ITO layer 462 can be an integer multiple of λc / 2; however, λc / 2 is preferred if the conductivity in the horizontal direction of the substrate is not a problem, since the ITO layer also absorbs light to a degree. An upper ring electrode 450 is arranged on the ITO layer 462.

[0058] The tunnel transition layer 442 consists of at least two layers, i.e., a p-GaAs layer 440, which has a charge carrier density of 5 × 10 19 cm -3was doped, and an n-GaAs layer 441, which has a charge carrier density of 1 × 10 19 cm -3 The doping was arranged in this sequence from the substrate side. The total optical thickness of these two layers is set to an integer multiple of λc / 2. For example, the actual thickness of the n-GaAs layer 441 is set to 190 nm.

[0059] In cases where absorption in a highly doped p-GaAs layer is problematic, the p-GaAs layer 440 can be configured with a variety of layers. For example, a two-layer configuration can be used, with one layer on the substrate side designed for a charge carrier density of 1 × 10 18 cm -3 is doped; and a layer on it (layer in contact with the n-GaAs layer 441), which is a thin layer (e.g. 20 nm thick) with a charge carrier density of 1 × 10 19 cm -3 is endowed.

[0060] If an etch stop layer is necessary in the structuring of the tunnel transition layer 442, the etch stop layer can be formed between the second DBR 304 and the tunnel transition layer 442. The optical layer thickness of the etch stop layer is set to an integer multiple of λc / 2.

[0061] The tunnel transition layer, where the p-layer and the n-layer are connected in this way, each with a charge carrier density of 1 × 10 18 cm -3If the voltage exceeds the specified value, it acts as a tunnel diode, and thus, due to the tunneling effect, a current also flows in the opposite direction via a thin depletion layer generated on the pn junction interface. Therefore, if a voltage is applied between the upper ring electrode 450 and the lower electrode 151, causing the upper ring electrode 450 to become positive, a current flows from the upper ring electrode 450 to the second DBR 304 via the ITO layer 462 and the tunnel junction layer 442. The current flowing into the second DBR 304 diffuses within the second DBR 304, just as in the configuration shown in [reference missing]. Fig. 3 in Example 1, and the current density distribution of the current injected into the active layer becomes the current density distribution whose center is high and protrudes.

[0062] As described above, the far-field image can also be controlled using the configuration of Example 2 in exactly the same way as in Example 1. By spreading the current density, which is concentrated on the circumferential section of the oxidation constriction diameter, to the central section, the generation of non-light emission feedback or the like, which propagates from the circumferential section, is limited, thereby improving the durability of the device.

[0063] Furthermore, the second constriction structure is formed by arranging the thin transparent conductive layer 462 and the tunnel transition layer 442 on the second DBR 304. The tunnel transition layer 442 exhibits low resistance because both the p-layer and the n-layer are highly doped layers with a charge carrier density on the order of 10 19Therefore, the stress increase in the second constriction structure can be reduced by approximately one order of magnitude with respect to the entire VCSEL 400 compared to the ion implantation method. By using the light-emitting device from Example 2 as a light source, a distance measuring device can be provided that not only improves distance measurement accuracy and the measurable distance, but also achieves a smaller size and lower weight. Example 3

[0064] A VCSEL 500 according to Example 3 is described below with reference to Fig. 5. One aspect shared with Example 1 is the arrangement of the isolation opening, and one shared with Example 2 is the arrangement of the tunnel transition. The main differences between Examples 1 and 2 are described below.

[0065] Fig.Figure 5 shows a sectional view of the VCSEL 500 in Example 3. The VCSEL 500 is set up by the GaAs substrate 301, the first DBR 302, the semiconductor resonator cavity 303, a second DBR 504 and a tunnel junction layer 542, which are stacked in this sequence.

[0066] The resonator cavity 303, the second DBR 504, and the tunnel transition layer 542 are machined to be tubular and mesa-shaped, and are covered with an insulating layer 561. An ITO layer 562 is formed on the insulating layer 561.

[0067] According to Fig.In Example 3, the insulating layer 561, whose central section has been partially removed, is formed on the upper side of the second DBR 504, which has been machined to be mesa-shaped. Within this insulating opening, the ITO layer 562 is in contact with the upper side of the tunnel transition layer 542. The shape of the insulating opening is circular. An upper ring electrode 550 is in electrical contact with a portion of the ITO layer 562. A common electrode 351 is in ohmic contact with the back side of the GaAs substrate 301.

[0068] The tunnel transition layer 542 is lined with a p-GaAs layer 540, which has a charge carrier density of 5 × 10 19 cm -3 was doped, and an n-GaAs layer 541 was established, which has a charge carrier density of 1 × 10 19 cm -3 was doped. The tunnel transition layer, in which the p-layer and the n-layer are connected in this way, whose charge carrier densities are each 1 × 10 18 cm-3 The junction exceeding the limit is a tunnel diode. Thus, due to the tunneling effect, a current also flows in the opposite direction across a thin depletion layer, which is generated on the pn junction interface by the tunneling effect just as in the case of tunnel junction layer 442 from Example 2.

[0069] In Example 3, the configuration in which an opening is present in part of the insulation layer in the upper section of the mesa is the same as in Example 1; however, the preferred diameter d6 of the insulation opening and diameter d5 of the non-oxidation section differ from those in Example 1 because of the tunnel transition layer 542 present in Example 3. The effect of this configuration is described below.

[0070] In Example 3, the diameter d6 of the insulation opening section, where the insulation layer 561 is removed, is 20 µm, and the diameter d5 of the non-oxidation section on the inner side of the oxidation constriction layer 306 is 70 µm.

[0071] The effect of this configuration is described below based on the calculation result, which is shown in Fig. 6A is specified. Fig. 6A denotes the abscissa as a position in the non-oxidized section in the radius direction, and the ordinate indicates a current density, and values ​​in the graph indicate each value of the diameter d6 of the insulation opening section. Fig. 6A specifies a current density distribution if d6 is set to 70 µm and d6 is changed in the range from 10 µm to 69 µm. As in Fig.Given that 6A is specified, the current density distribution maintains the profile, the center of which protrudes, if d6 is up to 30 µm. In this case, a current can be injected into the boundary between the oxidized and non-oxidized sections, i.e., at the 35 µm position on the abscissa of Fig. 6A.

[0072] The solid line in Fig. 6B specifies the ratio of Jc / Je in the case where d5 is set to 70 µm and d6 is changed. As in Fig. If 6B is specified, then formula (3) is satisfied if d6 is less than approximately 35 µm.

[0073] For comparison, the dashed line indicates the case of Example 1. The case of Example 1 is the case where d1 is 70 µm in the structure of Example 1. Jmax / Jmin is approximately the same as Jc / Je if d2 or d6 is 30 µm or more, and therefore this is not specified here.

[0074] The same calculation can be used to determine a value for d2 or d6 that simultaneously satisfies formula (3) and formula (5), provided that d1 or d5 is any value. Table 1 gives the value of d2 or d6 that simultaneously satisfies formula (3) and formula (5) if d1 to d5 are 30, 50, 70, and 100 µm, respectively. [Table 1] Diameter of the first constriction section d1 or d5 (µm) Example 1: Diameter of the second constriction section d2 (µm) Example 3 Diameter of the second constriction section d6 (µm) 30 13-17 None 50 30-36 10-19 70 40-52 25-35 100 -(not charged) 50-59

[0075] As Table 1 indicates, in the case of Example 1, the minimum value of the preferred range of d2 is 4 µm if d1 is 30 to 70 µm, and the allowable range of d2 is the maximum (6 µm) if d1 is 50 µm. On the other hand, in Example 3, the preferred range of d6 is at least 9 µm if d5 is at least in the range of 50 to 100 µm.

[0076] According to the above description, in Example 3 the tunnel transition layer 542 is arranged on the highest section of the mesa, and the charge carriers propagate in the direction parallel to the substrate, in particular through the n-GaAs layer 541 in the tunnel transition layer 542. Therefore, in comparison to Example 1, a desired current density distribution can be achieved even if the light emission area is increased.

[0077] According to Example 3, the diameter of the non-oxidized section can be set larger compared to Example 1, and thus a light emission component with higher power can be implemented.

[0078] In the description of Example 3, the tunnel transition layer 542 is located on the upper side of the second DBR 504; however, the tunnel transition layer can instead be located on the high refractive index layer, which is the uppermost layer of the second DBR 504. In this case, the layer thickness is adjusted such that the optical layer thickness of the tunnel transition layer becomes an odd multiple of λc / 4. In the case of Example 3, charge carriers diffuse horizontally in the n-GaAs layer 541, and thus this layer must be relatively thick. For example, this layer thickness is set to 190 nm, and the optical layer thickness of the tunnel transition layer is set to 3λc / 4.

[0079] Furthermore, in Example 3, the tunnel transition layer 542 is formed on the entire upper surface of the second DBR 304; however, the tunnel transition layer 542 need not be located in the circumferential section of the mesa structure. For example, the tunnel transition layer 542 can be configured such that it has a diameter encompassing the center of the mesa and is longer than d5 in order to encompass the entire non-oxidized section of the oxidation constriction layer 306 in a top view. Example 4

[0080] A VCSEL 700 according to Example 4 is described below with reference to Fig. 7 described. In example 4, the absorption of light by the ITO layer is reduced by reducing the thickness of the ITO layer.

[0081] Example 4 is described below based on Example 1 above. Components that are the same as in Example 1 are identified by the same reference numerals as in Example 1, and a description of these is omitted. Fig. Figure 7 only illustrates the configuration above the first DBR 302.

[0082] If absorption through the ITO layer is high, and this affects the oscillation and output of the VCSEL in Example 1, the thickness of the ITO layer can be reduced to less than λc / 2, and the transparent insulation layer or a plurality of layers or layers can be placed on top of it as in Example 4.

[0083] In the VCSEL 700 described in Example 4, the insulating layer 361, the central section of which is partially removed, is formed on the upper side of the second DBR 304, which has been machined to be mesa-shaped. An ITO layer 762 is in contact with the upper side of the second DBR 304 within this insulating opening. The thickness of the ITO layer 762 is assumed to be 100 nm. Subsequently, a transparent insulating layer 763 (e.g., SiOx) is formed on top of this, such that the total optical thickness of the ITO layer 762 and the transparent insulating layer 763 becomes an integer multiple of λc / 2. An upper ring electrode 750 is electrically connected to a portion of the ITO layer 762 at the section where the transparent insulating layer 763 is partially removed.

[0084] In the event that a deviation of the optical layer thickness of the ITO layer 762 from λc / 2 causes a drop in reflectance at the insulating aperture, and this drop becomes problematic, a plurality of transparent insulating layer layers can be formed on the transparent insulating layer 763. The reflectance at the insulating aperture can be improved by increasing the thickness of the transparent insulating layer in contact with the ITO layer 762 to λc / 2 (if added to the thickness of the ITO layer 762), and subsequently by alternating stacking of two types of layers with mutually different refractive indices, so that the optical layer thickness becomes λc / 4.

[0085] In the case of the formation of an additional transparent insulating layer on the transparent insulating layer layer 763, an opening, which is the same as that of the transparent insulating layer layer 763, is also formed on these transparent insulating layer layers, so that the upper ring electrode 750 and the ITO layer 762 are electrically connected.

[0086] According to Example 4, in addition to the effect of Example 1, absorption by the ITO layer can be reduced, thus further improving light emission efficiency. Furthermore, the risk of oscillation stalling due to a decrease in reflectance can be reduced.

[0087] Example 4 is based on Example 1, however the present invention is not limited to it and may be applicable to configurations of other examples and embodiments.

[0088] In Example 4, the thickness of the ITO layer is 762 100 nm; however, the thickness of the ITO layer can be thinner as long as the increase in resistance from the upper ring electrode to the tunnel junction, caused by electrical conductivity, does not become problematic. However, considering the probability of a connection failure that may be caused by the step difference of the insulation opening, the thickness of the ITO layer is preferably 10 nm or more. Example 5

[0089] A VCSEL 800 according to Example 5 is described below with reference to Fig. 8 described. One difference from Example 1 is that the VCSEL 800 further comprises a third DBR 801 on the ITO layer 362. The third DBR 801 is equipped with a multilayer dielectric layer such as SiOx, SiNx and TiOx.

[0090] In Example 1, the size of d2 is either 10 µm or 15 µm. 15 µm is a design value if durability is a priority. In some cases, it may be difficult to set d2 to 15 µm or less due to process constraints or similar factors. To increase the values ​​of Jc / Je and Jmax / Jmin in such a case, in Example 5, the thickness of a second DBR 804 is set to be thinner than the thickness specified in Example 1, and the resulting reduction in reflectivity is compensated for by the addition of a third DBR 801.

[0091] If, in particular, the thickness of the second DBR 804 3 / 5 of Example 1 is, then 4.4 can be obtained as the setting value of both Jc / Je and Jmax / Jmin, even if d2 is 15 µm.

[0092] The size of the third DBR 801 in the horizontal direction of the paper surface of Fig. 8 must be optically large enough to act as a resonator above the active position. Fig.In 8, the size of the third DBR 801 is smaller than the inner diameter of the upper ring electrode 350 and larger than d1; however, the present invention is not limited to this. The size of the third DBR 801 can be approximately the same as or larger than the inner diameter of the upper ring electrode 350, as long as a current can be supplied to the upper ring electrode 350 in this configuration.

[0093] In Example 5, the thickness of the second DBR 804 is set to be thinner than that set in Example 1; however, the thickness of the second DBR 804 can be set to be thicker than that of Example 1 to achieve a preferred current density distribution. In this case, one layer or a plurality of layers of the second DBR can, for example, be set to 3 / 4 λc. Example 6

[0094] A VCSEL 900 according to Example 6 of the present invention is described below with reference to Fig. 9 described. One difference between VCSEL 900 and Example 1 is that λc is 850 nm. Therefore, in the first DBR 502 and the second DBR 504, the optical layer thickness of each layer is changed to λc / 4 (= 212.5 nm). The composition and optical layer thickness of the quantum well layer 540 and the resonator cavity 503 are similarly adapted.

[0095] In particular, the quantum well layer 540 is arranged such that an 8 nm thick GaAs layer is sandwiched between 8 nm thick Al layers. 0,3 GaAs barrier layers are embedded. In Example 6, three quantum well layers are arranged in the resonator section 503.

[0096] Even for a band wavelength of 850 nm, whose absorption rate in the substrate is high and with which achieving high power via backside emission is difficult, a high-power semiconductor light emission device can be provided, whereby the influence of absorption by the substrate is limited.

[0097] Example 6 has a configuration of Example 1 in which one oscillation wavelength is changed, but it can be applied to any of Example 2 to Example 5 of the present invention. Example 7

[0098] A VCSEL 330 according to Example 7 is described below with reference to Fig. 10 described. Fig.Figure 10 shows a sectional view of the VCSEL 3300 from Example 7. Unlike the VCSEL 300 from Example 1, a thick layer contact layer 3400 is arranged between the second DBR 304 and the ITO layer 362 in Example 7. In Example 7, the thick layer contact layer 3400 is a p-GaAs layer with an optical thickness of λc / 2.

[0099] The VCSEL 3300 is configured by the GaAs substrate 301, the first DBR 302, the semiconductor resonator cavity 303, the second DBR 304, and the thick layer contact layer 3400, stacked in this sequence. Fig. 10. These components are in direct contact with each other, however another component may be positioned between them. The foregoing description serves to describe the structure and is not intended to limit the sequence of manufacturing each component.

[0100] Three quantum well layers 340 are arranged in the resonator cavity 303. An Al 0,98GaAs is oxidized in part of the second DBR 304 by vapor oxidation, whereby an oxidation constriction layer 306 with insulating properties is formed on its circumference.

[0101] The resonator cavity 303, the second DBR 304, and the thick layer contact layer 3400 are machined to be tubular and mesa-shaped, and are covered with the insulating layer 361. Furthermore, the indium tin oxide layer (ITO layer) 362 is formed on the insulating layer 361.

[0102] According to Fig.In 10, the insulating layer 361, the central section of which has been partially removed, is formed on the upper side of the thick layer contact layer 3400, which has been machined to be mesa-shaped. In this removed section, the ITO layer 362 is in contact with the upper side of the thick layer contact layer 3400. The section where the insulating layer 361 has been removed is referred to as the "insulating opening" in this description. The ITO layer 362 is in contact with the upper side of the thick layer contact layer 3400 in the insulating opening section. In other words, a contact section is provided between the ITO layer 362 and the semiconductor layer, which is in contact with the ITO layer 362. The shape of the insulating opening is a circle in Example 7. The upper ring electrode 350 is in electrical contact with a portion of the ITO layer 362. The lower common electrode 351 is in ohmic contact with the back of the GaAs substrate 301.

[0103] The layer constituting the DBR preferably has an optical layer thickness that is an odd multiple of λc / 4 and does not act as a reflection layer for any longer, since the optical layer thickness approaches λc / 2. The thick layer contact layer 3400 of Example 7 has an optical layer thickness of λc / 2 and is therefore not a layer of the DBR. According to the foregoing description, in the VCSEL 3300 of Example 7, the section that acts as the DBR forming the VCSEL, unlike the VCSEL 300 of Example 1, is not in direct contact with the ITO layer. Nevertheless, in Example 7, just as in Example 1, the current distribution flowing into the quantum well layer can be controlled to a desired profile. This is because it is the two current-constriction layers and the semiconductor layer arranged between them that control the current distribution flowing into the quantum well layer to a desired profile.In Example 7, the current constriction structure provided by the insulating opening, which is formed in the oxidation constriction layer 306, and the insulating layer 361 comprise two current constriction layers and utilize the propagation of the current in the semiconductor layer arranged between them. Therefore, the effect of the invention is implemented regardless of whether the ITO layer is in direct contact with the layer acting as the DBR.

[0104] ITO is typically an n-type semiconductor, and ITO layer 362 in Example 7 is also an n-type semiconductor. This means that the interface to the thick layer contact layer 3400, which is a p-type semiconductor layer, is the pn junction where a depletion layer is created. Therefore, the thickness of the layer on the side of the p-type semiconductor layer containing holes is reduced by the width of the depletion layer. Due to the level of defects present at the interface with ITO layer 362, the number of holes decreases further in an area near the interface.

[0105] Therefore, in the case of contact using the ITO layer, a contact layer with a greater thickness than a common contact using a p-contact electrode may be required, depending on the charge carrier density of the ITO layer or similar conditions. In such a case, the configuration of Example 7 offers advantages, as the thickness of the contact layer can be increased to an integer multiple of the optical layer thickness λc / 2 without changing the reflectivity of the upper section of the VCSEL.

[0106] As described in Example 7, the propagation of charge carriers in the present invention is controlled using the two current constriction structures and the semiconductor layer arranged between them. Therefore, the total thickness of the semiconductor layer between the two current constriction structures is also an important parameter. If, for example, the layer thickness is set for a suitable number of pairs from the perspective of ensuring the reflectivity of the DBR, the layer thickness required for ideal charge carrier propagation may become inefficient. In this case, a suitable layer thickness can be designed by placing a semiconductor layer, whose optical layer thickness is an integer multiple of λc / 2, between the ITO layer and the DBR. This allows both ensuring the reflectivity of the DBR and controlling the propagation of charge carriers to be achieved.

[0107] In the configuration of Example 7, the thick layer contact layer 3400 is arranged in the VCSEL of Example 1; however, the thick layer contact layer 3400 can be arranged in any VCSEL of Examples 2 to 6. In each of these cases, both ensuring the reflectivity of the DBR and controlling the propagation of charge carriers can be implemented. Example 8

[0108] The VCSEL arrangement 1000 according to Example 8 of the present invention is described below with reference to Fig. 11 described. In Examples 1 to 7 there is one VCSEL light emission section, however the present invention is not limited thereto, and a plurality of VCSEL light emission sections can be arranged.

[0109] According to Fig.In the VCSEL arrangement 1000 of Example 8, a plurality of VCSEL 300 described in Example 1 are arranged in an arrangement. A circle 910 indicates an inner diameter of the upper ring electrode. A dashed line 911 indicates a light emission area whose inner diameter is d1. A section indicated by the dashed line is a pad area 920 of the upper electrode.

[0110] According to Fig. In this configuration, a multitude of light emission points are connected to the same electrode, and these multiple points emit light simultaneously. Using this configuration allows the light emission device to achieve even higher output power.

[0111] In Example 8, 16 light emission points are arranged in a triangular 4 × 4 grid; however, the present invention is not limited to this, and the number and arrangement of the light emission points can be modified to suit an application. In this example, the entire plurality of light emission points is controlled simultaneously; however, depending on the application, the light emission points and the corresponding upper electrodes can be divided into a plurality of groups and controlled individually, or controlled individually to emit light at different times.

[0112] Example 8 specifies a configuration where the VCSEL from Example 1 is arranged in an array; however, any VCSEL from Examples 2 to 7 can be arranged in an array. If the VCSEL is arranged according to Example 3, a larger diameter of the non-oxidation section can be used than in the case of using the VCSEL according to Example 1 or 2, so that this array can achieve higher performance with a smaller area. Example 9

[0113] Fig. 12 specifies a distance measuring device 2000 according to Example 9. Fig. Figure 12 shows a laser light detection and distance measurement device (LIDAR device) in which a VCSEL of the above examples is used as a light source unit.

[0114] As in Fig.As indicated in 12, the distance measuring device 2000 is equipped with a general control unit 1010, a VCSEL control 1020, a VCSEL 1030, a light emission side optics system 1040, a light receiving side optics system 1060, a light receiving image sensor 1070 and a distance data processing unit 1080.

[0115] In Example 9, the VCSEL 1030 used is the VCSEL described in Example 1, however, the present invention is not limited to this, and any VCSEL or VCSEL arrangement described in Examples 1 to 8 can be used.

[0116] The VCSEL 1030 has a configuration in which a VCSEL as described in the preceding examples is mounted in a housing. Each of the light-emission side optics system 1040 and the light-receiving side optics system 1060 can be a convex lens element or can be configured with a lens group in which a plurality of lenses are combined. The light-receiving image sensor 1070 is an image sensor in which a single-photon avalanche diode photosensor (SPAD photosensor) is arranged in a two-dimensional configuration.

[0117] An overview of the operation of the 2000 distance measuring device is described below. First, a control signal is output from the general control unit 1010 to the VCSEL control unit 1020. The VCSEL control unit 1020, which has received the control signal, injects a predetermined current value into the VCSEL 1030 to oscillate it.

[0118] The laser light generated in the VCSEL 1030 contacts a measurement target 1200 via the light emission side optics system 1040, and the light reflected by the measurement target 1200 enters the light receiving image sensor 1070 via the light receiving side optics system 1060. In this way, the reflected light of the light emitted by the VCSEL 1030 is detected by each image element of the light receiving image sensor 1070. It is irrelevant whether the distance data processing unit 1080 and the light receiving image sensor 1070 are arranged in the same housing or in different housings and electrically connected by a circuit board, as long as the distance data processing unit 1080 is electrically connected to the light receiving image sensor 1070.

[0119] An electrical signal pulse, output by each pixel of the light-receiving image sensor 1070, is input to the distance data processing unit 1080. The distance data processing unit 1080 calculates the distance information in the direction of light propagation based on the time (capture time) of the electrical signal pulse output by each pixel of the light-receiving side optics system 1060, and generates and outputs its three-dimensional information.

[0120] In this way, the distance measuring device 2000 can obtain and output the three-dimensional information.

[0121] The Distance Measuring Device 2000 can be applied to a control system for preventing collisions with other vehicles and to a control system for autonomous driving that follows another vehicle, or similar applications in the automotive sector. Furthermore, the Distance Measuring Device 2000 can be used for a moving body (moving device) of a ship, aircraft, industrial robot, or similar device, and for a moving body detection system. In addition, the Distance Measuring Device 2000 can be applied to various devices that detect an object in three dimensions, including distance information.

[0122] The application of three-dimensional information is not limited to the above. For example, distance information can be used for image processing. If a virtual object is superimposed and displayed on a captured image of a real space, the virtual object can, of course, be displayed on the real-world image by using the three-dimensional information of the real space. Furthermore, by acquiring three-dimensional information simultaneously with image acquisition, blurring can be corrected based on the three-dimensional information after the image has been captured. Further examples of implementation

[0123] While preferred embodiments have been described above, the present invention is not limited to these embodiments, but can be modified and altered in various ways within the scope of its spirit.

[0124] Although the present invention is described with reference to exemplary embodiments, the invention must not be understood as limited to the disclosed exemplary embodiments. The scope of the following claims must be interpreted in the broadest possible way to encompass all such modifications and equivalent structures and effects.

[0125] A semiconductor light emission device with a structure in which a substrate, a first reflector, a resonator cavity with an active layer, a second reflector and a transparent conductive layer are stacked in this sequence, wherein the semiconductor light emission device comprises: a first current constriction section configured with an oxidation constriction layer, and a second current constriction section configured with an insulating layer formed on an upper side of the second reflector and having an opening, and a contact section between the transparent conductive layer and a semiconductor layer with which the transparent conductive layer is in contact, wherein a width d2 of the second current constriction section is smaller than a width d1 of the first current constriction section.

Claims

[1] Semiconductor light emission device (500) with a structure in which a substrate (301), a first reflector (302), a resonator cavity (303) with an active layer, a second reflector (504) and a tunnel transition layer (542) are stacked in this sequence, the semiconductor light emission device (500) comprising: an insulating layer (561); a transparent conductive layer (562) arranged on the insulating layer (561); a first current constriction section, which is provided with an oxidation constriction layer (306) in the second reflector (504); and a second current constriction section, which is provided with the insulating layer (561) formed on an upper side of the tunnel transition layer (542) and having an opening, and a contact section between the transparent conductive layer (562) and a semiconductor layer with which the transparent conductive layer (562) is in contact, where a width d6 of the second stream constriction section is smaller than a width d5 ​​of the first stream constriction section, the tunnel transition position (542) is located on an uppermost section of the second reflector (504), and the insulating layer (561) and the transparent conductive layer (562) are arranged on the tunnel transition layer (542), and the transparent conductive layer (562) is in contact with the second reflector (504) via the tunnel transition layer (542). [2] Semiconductor light emission device (400) with a structure in which a substrate (301), a first reflector (302), a resonator cavity (303) with an active layer, a second reflector (304) and a tunnel transition layer (442) are stacked in this sequence, the semiconductor light emission device (400) comprising: an insulating layer (461) with an opening; a transparent conductive layer (462) arranged on the insulating layer (461); a first current constriction section, which is equipped with an oxidation constriction layer (306) in the second reflector (304); and a second current constriction section, which is provided with the tunnel transition layer (442) formed on an upper side of the second reflector (304), wherein the second current constriction section is located in the opening of the insulating layer (461), where a width d4 of the second stream constriction section is smaller than a width d1 of the first stream constriction section, the width d4 of the second current constriction section is smaller than a diameter of the opening of the insulating layer (461), the tunnel transition layer (442) is arranged on the uppermost section of the second reflector (304) to include at least one non-oxidized section within the oxidation constriction layer (306) in the first stream constriction section in a plan view, and the transparent conductive layer (462) is in electrical contact with the second reflector (304) at least via the tunnel transition layer (442). [3] Semiconductor light emission device (500) according to claim 1, wherein the opening of the insulating layer (561) in the second current constriction section is included in a non-oxidized section within the oxidation constriction layer (306) in the first current constriction section in a top view. [4] Semiconductor light emission device (500) according to claim 1 or 3, wherein the width d5 ​​of the first current constriction section satisfies 30 µm ≤ d5 ≤ 70 µm. [5] Semiconductor light emission device (500) according to claim 1 or 3, wherein the width d5 ​​of the first current constriction section satisfies 50 µm ≤ d5 ≤ 100 µm. [6] Semiconductor light emission device (400, 500) according to one of claims 1 to 5, wherein a transparent insulating layer (763) is arranged on the transparent conductive layer (462, 562). [7] Semiconductor light emission device (400, 500) according to one of claims 1 to 6, wherein a third reflector (801) formed from a dielectric substance is further arranged on the second reflector (304, 504). [8] Semiconductor light emission device (400, 500) according to any one of claims 1 to 7, wherein the transparent conductive layer (462, 562) is an indium tin oxide, ITO, layer. [9] Semiconductor light emission device (400, 500) according to any one of claims 1 to 8, wherein the resonator cavity (303) and the second reflector (304, 504) are mesa-shaped and are covered with the insulating layer (461, 561) which has an opening. [10] Light emission device, comprising a plurality of semiconductor light emission devices (400, 500) according to any one of claims 1 to 9 arranged side by side. [11] Distance measuring device (2000), with: a light source comprising the semiconductor light emission device (400, 500) according to any one of claims 1 to 9; a sensor (1070) that detects reflected light from the light produced by the light source; and a processing unit (1080) that obtains distance information based on a time of acquisition to capture the reflected light.

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