Thin film transistor, manufacturing method thereof and display panel

Abstract

This invention provides a thin-film transistor (TFT), its fabrication method, and a display panel. The method for fabricating the TFT includes: sequentially forming a gate, a gate insulating layer, a semiconductor layer, a doped semiconductor layer, and a metal layer on one side of a substrate; forming a photoresist layer on the surface of the metal layer, the photoresist layer including a first photoresist layer; sequentially performing a first wet etching, photoresist ashing, dry etching, and a second wet etching through the first photoresist layer to obtain a source, a drain, an ohmic contact layer, and an active layer. At least one of the first and second wet etching processes uses a composite etching solution, which includes molten metal and fluoride ions. The composite etching solution can etch the metal layer, the doped semiconductor layer, and part of the semiconductor layer. This fabrication process can save process steps, reduce parasitic capacitance and light leakage current, thereby effectively improving reliability defects such as water ripples and crosstalk in display panels, and also facilitating the achievement of extremely narrow bezels.

Description

Technical Field

[0001] This invention relates to the field of display technology, specifically to thin-film transistors, their fabrication methods, and display panels. Background Technology

[0002] Currently, referring to Figure 1 In 4mask products, thin-film transistors are typically fabricated using a 2W2D process, consisting of two wet etching passes and two dry etching passes. This process creates a tail (a-Si tail) at the edges of the source and drain electrodes (6) and a tail (n-Si tail) at the active layer (6). + The a-Si tail is too large (the spacing s1 between the edge of the source / drain electrode 6 and the edge of the active layer 4 is large, and the spacing s2 between the edge of the source / drain electrode 6 and the edge of the ohmic contact layer 5 is large). Figure 1 The substrate 1, gate 2, gate insulating layer 3 and photoresist 7 are still missing, which makes the parasitic capacitance of the product larger and the leakage current under light greater, ultimately leading to abnormal product reliability, such as water ripples, crosstalk and other defects.

[0003] Therefore, further research is needed on the fabrication of thin-film transistors. Summary of the Invention

[0004] This invention aims to at least partially address one of the technical problems in the related art. Therefore, one object of this invention is to provide a method for fabricating thin-film transistors, which produces thin-film transistors with superior reliability.

[0005] In one aspect of the invention, a method for fabricating a thin-film transistor is provided. According to an embodiment of the invention, the method for fabricating a thin-film transistor includes: sequentially forming a gate, a gate insulating layer, a semiconductor layer, a doped semiconductor layer, and a metal layer on one side of a substrate; forming a photoresist layer on the surface of the metal layer, the photoresist layer including a first photoresist layer; sequentially performing a first wet etching, photoresist ashing, dry etching, and a second wet etching through the first photoresist layer to obtain a source, a drain, an ohmic contact layer, and an active layer, wherein the etching solution used in at least one of the first wet etching and the second wet etching is a composite etching solution, the composite etching solution including molten metal and fluoride ions, the composite etching solution being capable of etching the metal layer, the doped semiconductor layer, and a portion of the semiconductor layer. Therefore, by using a composite etching solution, not only the metal layer is etched during etching, but also the ohmic contact layer and a portion of the semiconductor layer are etched, thus reducing the process complexity compared to other methods. Figure 1The proposed solution eliminates the second dry etching process, saving process steps and reducing the distance between the source / drain edges and the active layer edges (i.e., reducing the tail length of the active layer at the source / drain edges) and the distance between the source / drain edges and the ohmic contact layer edges (i.e., reducing the tail length of the ohmic contact layer at the source / drain edges). Furthermore, performing photoresist ashing before dry etching weakens the photoresist layer's protection of the doped semiconductor layer and the semiconductor layer, further enhancing the protection of the doped semiconductor layer and the semiconductor layer. The etching degree of the conductor layer further reduces the trailing length of the active layer and ohmic contact layer at the source and drain edges. The significant reduction in the trailing length of the active layer can reduce parasitic capacitance and light leakage current, thereby effectively improving the reliability defects of the display panel such as water ripples and crosstalk. Without the trailing length of the ohmic contact layer, the channel length design value of the TFT can be reduced while ensuring the charging rate remains unchanged, realizing the miniaturization design of TFT devices. At the same time, the width of the GOA area can also be reduced, which further reduces the size of the display panel bezel and is conducive to achieving an ultra-narrow bezel.

[0006] According to an embodiment of the present invention, the photoresist layer further includes a second photoresist layer, through which the first wet etching, the photoresist ashing, the dry etching, and the second wet etching are performed sequentially to obtain a data signal line.

[0007] According to an embodiment of the present invention, a sub-metal layer is obtained after the first wet etching. The first photoresist layer includes a thickened photoresist region and a thinned photoresist region. The second photoresist layer is a thickened photoresist layer. By photoresist ashing, the thinned photoresist region is removed, and the thickened photoresist region and the second photoresist layer are thinned into a sub-photoresist layer. The orthographic projection of the sub-photoresist layer on the substrate is located inside the orthographic projection of the sub-metal layer on the substrate.

[0008] According to an embodiment of the present invention, the doped semiconductor layer and the semiconductor layer not covered by the sub-metal layer are removed by the dry etching to obtain a sub-doped semiconductor layer and a sub-semiconductor layer. The orthogonal projection of the sub-metal layer on the substrate covers the orthogonal projection of the sub-doped semiconductor layer on the substrate and also covers the orthogonal projection of the sub-semiconductor layer on the substrate.

[0009] According to an embodiment of the present invention, the etching solution for the first wet etching is a metal etching solution, and the etching solution for the second wet etching is the composite etching solution. The method includes: etching the metal layer by the first wet etching to obtain the sub-metal layer and expose the doped semiconductor layer; ashing the photoresist layer by photoresist ashing; etching the doped semiconductor layer and the semiconductor layer not covered by the sub-metal layer by dry etching to obtain the sub-doped semiconductor layer and the sub-semiconductor layer; and etching the sub-metal layer, the sub-doped semiconductor layer and the sub-semiconductor layer corresponding to the channel region by the second wet etching to remove the sub-metal layer, the sub-doped semiconductor layer and a portion of the thickness of the sub-semiconductor layer corresponding to the channel region, thereby obtaining the source, the drain, the ohmic contact layer and the active layer.

[0010] According to an embodiment of the present invention, the etching solution for the first wet etching and the etching solution for the second wet etching are both the composite etching solution. The method includes: etching the metal layer, the doped semiconductor layer, and a portion of the semiconductor layer by the first wet etching to obtain the sub-metal layer, the sub-doped semiconductor layer, and the thinned semiconductor layer, and exposing the thinned semiconductor layer; ashing the photoresist layer by photoresist ashing; etching the thinned semiconductor layer by dry etching to obtain the sub-semiconductor layer; and etching the sub-metal layer, the sub-doped semiconductor layer, and the sub-semiconductor layer corresponding to the channel region by the second wet etching to remove the sub-metal layer, the sub-doped semiconductor layer, and the sub-semiconductor layer corresponding to the channel region, thereby obtaining the source, the drain, the ohmic contact layer, and the active layer.

[0011] According to an embodiment of the present invention, the ashing gas for photoresist ashing includes oxygen and fluorine-containing gas.

[0012] According to an embodiment of the present invention, the ashing gas is NF3 / O2, CF4 / O2, SF6 / O2, or CHF3 / O2.

[0013] According to an embodiment of the present invention, the etching gas for dry etching includes an inert gas and a fluorine-containing gas, but does not contain chlorine gas, and the etching gas can etch the doped semiconductor layer and the semiconductor layer.

[0014] According to an embodiment of the present invention, the etching gas is NF3 / He, CF4 / He, CHF3 / He, or SF6 / He.

[0015] According to embodiments of the present invention, based on the total mass of the composite etching solution, the fluoride ion content is 0.1% to 0.4% by mass percentage; when the metal layer comprises aluminum, the etching solution comprises nitric acid and phosphoric acid, wherein, based on the total mass of the composite etching solution, the nitric acid content is 2.8% to 3.2%, and the phosphoric acid content is 63% to 70%; when the metal layer comprises copper, the etching solution comprises hydrogen peroxide, wherein, based on the total mass of the composite etching solution, the hydrogen peroxide content is 15% to 25%.

[0016] According to an embodiment of the present invention, after obtaining the source, drain, ohmic contact layer and active layer, the method further includes: removing the sub-photoresist layer by photoresist ashing.

[0017] In another aspect, the present invention provides a thin-film transistor. According to an embodiment of the present invention, the thin-film transistor is fabricated using the method described above. Therefore, the thin-film transistor exhibits superior reliability, lower parasitic capacitance and light leakage current, effectively improving reliability defects such as water ripples and crosstalk in display panels; the TFT channel length is smaller, which is beneficial for miniaturization design of TFT devices; simultaneously, the width of the GOA region can be reduced, further reducing the size of the display panel bezel and facilitating the achievement of extremely narrow bezels.

[0018] According to an embodiment of the present invention, the tail length of the active layer at the edge of the source and drain is less than or equal to 1.4 micrometers, and the tail length of the ohmic contact layer at the edge of the source and drain is less than or equal to 0.5 micrometers.

[0019] According to an embodiment of the present invention, the thickness of the active layer is

[0020] In another aspect, the present invention provides a display panel that, according to an embodiment of the invention, includes the thin-film transistors described above. Thus, the display panel has high reliability and a narrow bezel. Those skilled in the art will understand that the display panel possesses all the features and advantages of the thin-film transistors described above, and will not be elaborated further here. Attached Figure Description

[0021] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0022] Figure 1 This is a flowchart of the fabrication process of thin-film transistors in existing technology;

[0023] Figure 2 This is a flowchart illustrating the fabrication process of a thin-film transistor in one embodiment of the present invention;

[0024] Figure 3 This is a flowchart illustrating the fabrication process of a thin-film transistor in another embodiment of the present invention;

[0025] Figure 4 This is a flowchart illustrating the fabrication process of a thin-film transistor in another embodiment of the present invention;

[0026] Figure 5 These are scanning electron microscope (SEM) comparison images of thin-film transistors fabricated using 2W2D and 2W1D processes.

[0027] Figure 6 This is the effect of the active layer trailing length on the water ripple pattern of the display panel. Detailed Implementation

[0028] The present invention will be explained below with reference to embodiments. Those skilled in the art will understand that the following embodiments are for illustrative purposes only and should not be considered as limiting the scope of the invention. Where specific techniques or conditions are not specified in the embodiments, they are performed according to the techniques or conditions described in the literature in the field or according to the product instructions. Reagents or instruments whose manufacturers are not specified are all conventional products that can be obtained commercially.

[0029] The present invention will now be described with reference to specific embodiments. It should be noted that these embodiments are merely descriptive and do not limit the present invention in any way.

[0030] In one aspect of the invention, a method for fabricating a thin-film transistor is provided. According to an embodiment of the invention, referring to... Figure 2 The fabrication methods of thin-film transistors include:

[0031] S100: A gate 110, a gate insulating layer 120, a semiconductor layer 130, a doped semiconductor layer 140 and a metal layer 150 are sequentially formed on one side of the substrate 100.

[0032] According to embodiments of the present invention, the gate material can be a metallic material, such as conductive metallic materials like molybdenum-aluminum-molybdenum (Mo / AL / Mo), molybdenum-copper (Mo / Cu), molybdenum-niobium-copper (MoNb / Cu), and molybdenum-niobium-copper-molybdenum-titanium (MoNb / Cu / MoTi); the gate insulating layer is formed by materials including but not limited to insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride; the semiconductor layer 130 is used to form the active layer 132, and its material can be polycrystalline silicon (a-Si) or IGZO; the doped semiconductor layer 140 is used to form the ohmic contact layer 142, and its material can be polycrystalline silicon (a-Si) or IGZO, the purpose of which is to reduce the potential barrier between the active layer and the source and drain; the metal layer is used to form the source and drain, and its material can be conductive materials such as molybdenum-aluminum-molybdenum (Mo / AL / Mo), molybdenum-copper (Mo / Cu), molybdenum-niobium-copper (MoNb / Cu), and molybdenum-niobium-copper-molybdenum-titanium (MoNb / Cu / MoTi).

[0033] S200: A photoresist layer is formed on the surface of the metal layer 150, the photoresist layer including a first photoresist layer 161, such as... Figure 2 As shown.

[0034] According to an embodiment of the present invention, referring to Figure 3 and Figure 4 In subsequent steps, the photoresist layer also includes a second photoresist layer 162. The second photoresist layer 162 is used to sequentially perform a first wet etching, photoresist ashing, dry etching, and a second wet etching to obtain the data signal line 154. That is, the data signal line 154, source 153, and drain 152 are obtained through the same steps.

[0035] According to an embodiment of the present invention, referring to Figure 3 and Figure 4After the first wet etching, a sub-metal layer 151 is obtained. The first photoresist layer 161 includes a thickened photoresist region 1611 and a thinned photoresist region 1612 (i.e., the thickness of the thickened photoresist region 1611 is greater than the thickness of the thinned photoresist region 1612). The second photoresist layer 162 is a thickened photoresist layer (which is formed in the same step as the thickened photoresist region 1611, and the thicknesses of the two are the same). Through the subsequent photoresist ashing step, the thinned photoresist region 1612 is removed, and the thickened photoresist region 1611 and the second photoresist layer 162 are thinned into a sub-photoresist layer 1600. The orthographic projection of the sub-photoresist layer 1600 on the substrate 100 is located inside the orthographic projection of the sub-metal layer 151 on the substrate 100. This allows the thinned photoresist region 1612 to correspond to the channel region of the TFT. After removing the thinned photoresist region 1612, the sub-metal layer 151 corresponding to the channel region is exposed, so that the sub-metal layer can be etched by the second wet etching process. The orthogonal projection of the sub-photoresist layer 1600 on the substrate 100 is located inside the orthogonal projection of the sub-metal layer 151 on the substrate 100. Therefore, in the subsequent dry etching process, the protection of the photoresist layer on the doped semiconductor layer 140 and the semiconductor layer 130 can be weakened, so that the etching gas can better etch the doped semiconductor layer 140 and the semiconductor layer 130. This results in the sub-doped semiconductor layer 141 and the sub-semiconductor layer 131 being covered by the sub-metal layer 151, which helps to reduce the tail length of the active layer and the ohmic contact layer, and may even make the tail of the subsequently obtained ohmic contact layer zero.

[0036] S300: The first photoresist layer 161 is sequentially subjected to a first wet etching, photoresist ashing, dry etching, and a second wet etching to obtain the source, drain, ohmic contact layer, and active layer. At least one of the first and second wet etching processes uses a composite etching solution, which includes molten metal and fluoride ions. This composite etching solution can etch the metal layer, the doped semiconductor layer, and a portion of the semiconductor layer. In other words, it can completely etch away the metal layer and the doped semiconductor layer in the area to be etched, but can only partially etch away the semiconductor layer, reducing its thickness but not completely removing it. Of course, those skilled in the art will understand that if the photoresist layer includes a second photoresist layer 162, the second photoresist layer 162 will also be sequentially subjected to a first wet etching, photoresist ashing, dry etching, and a second wet etching to obtain the data signal line 154.

[0037] According to an embodiment of the present invention, in the above steps, the doped semiconductor layer 140 and semiconductor layer 130 not covered by the sub-metal layer 151 are removed by dry etching to obtain the sub-doped semiconductor layer 141 and sub-semiconductor layer 131, as shown below. Figure 3 and Figure 4As shown, the orthogonal projection of the sub-metal layer 151 on the substrate 100 covers the orthogonal projection of the sub-doped semiconductor layer 141 on the substrate, and also covers the orthogonal projection of the sub-semiconductor layer 131 on the substrate 100. Therefore, after photoresist ashing, the aforementioned dry etching results in smaller sub-doped semiconductor layers 141 and 131, which are covered by the sub-metal layer. This helps reduce the tail length of the active layer and the ohmic contact layer, and may even result in zero tail length for the subsequently obtained ohmic contact layer.

[0038] According to some specific embodiments of the present invention, the etching solution for the first wet etching is a metal etching solution, and the etching solution for the second wet etching is a composite etching solution, as shown in the reference. Figure 3 Methods for fabricating thin-film transistors include:

[0039] S11: The metal layer 150 is etched by the first wet etching to obtain the sub-metal layer 151 and expose the doped semiconductor layer 140.

[0040] The etching solution used in the first wet etching is a metal etching solution, which is a commonly used etching solution in current technology. In the first wet etching, only the metal etching solution etches the metal layer and does not affect the doped semiconductor layer or the semiconductor layer.

[0041] S12: The photoresist layer is ashed by photoresist ashing to obtain sub-photoresist layer 1600.

[0042] According to an embodiment of the present invention, referring to Figure 3 The photoresist layer also includes a second photoresist layer 162. The metal layer portion corresponding to the second photoresist layer 162 is used to fabricate the data signal line 154. That is, the data signal line 154, source 153, and drain 152 are obtained through the same step.

[0043] According to an embodiment of the present invention, referring to Figure 3The first photoresist layer 161 includes a thickened photoresist region 1611 and a thinned photoresist region 1612 (i.e., the thickness of the thickened photoresist region 1611 is greater than the thickness of the thinned photoresist region 1612). The second photoresist layer 162 is a thickened photoresist layer (which is formed in the same step as the thickened photoresist region 1611, and the thicknesses of the two are the same). Through the subsequent photoresist ashing step, the thinned photoresist region 1612 is removed, and the thickened photoresist region 1611 and the second photoresist layer 162 are thinned into a sub-photoresist layer 1600. The orthographic projection of the sub-photoresist layer 1600 on the substrate 100 is located inside the orthographic projection of the sub-metal layer 151 on the substrate 100. This allows the thinned photoresist region 1612 to correspond to the channel region of the TFT. After removing the thinned photoresist region 1612, the sub-metal layer 151 corresponding to the channel region is exposed, so that the sub-metal layer can be etched by the second wet etching process. The orthogonal projection of the sub-photoresist layer 1600 on the substrate 100 is located inside the orthogonal projection of the sub-metal layer 151 on the substrate 100. Therefore, in the subsequent dry etching process, the protection of the photoresist layer on the doped semiconductor layer 140 and the semiconductor layer 130 can be weakened, so that the etching gas can better etch the doped semiconductor layer 140 and the semiconductor layer 130. This results in the sub-doped semiconductor layer 141 and the sub-semiconductor layer 131 being covered by the sub-metal layer 151, which helps to reduce the tail length of the active layer and the ohmic contact layer, and may even make the tail of the subsequently obtained ohmic contact layer zero.

[0044] S13: The doped semiconductor layer 140 and semiconductor layer 130 not covered by the sub-metal layer 151 are etched by dry etching to obtain the sub-doped semiconductor layer 141 and sub-semiconductor layer 131.

[0045] In the above steps, dry etching is used to remove the doped semiconductor layer 140 and semiconductor layer 130 that are not covered by the sub-metal layer 151, resulting in the sub-doped semiconductor layer 141 and sub-semiconductor layer 131, as shown. Figure 3 As shown, the orthogonal projection of the sub-metal layer 151 onto the substrate 100 covers the orthogonal projection of the sub-doped semiconductor layer 141 onto the substrate, and also covers the orthogonal projection of the sub-semiconductor layer 131 onto the substrate 100. Therefore, after photoresist ashing and performing the aforementioned dry etching, the resulting sub-doped semiconductor layer 141 and sub-semiconductor layer 131 are smaller in size and covered by the sub-metal layer, thereby helping to reduce active layer tailing (…). Figure 3 The length of the ohmic contact layer tail (S1) and the tail of the ohmic contact layer can even make the tail of the subsequently obtained ohmic contact layer zero (e.g., Figure 3 (As shown).

[0046] S14: A second wet etching process is performed on the sub-metal layer 151, sub-doped semiconductor layer 141, and sub-semiconductor layer 131 corresponding to the channel region. This removes the sub-metal layer 151, sub-doped semiconductor layer 141, and a portion of the thickness of the sub-semiconductor layer 131 corresponding to the channel region, resulting in the source 153, drain 152, ohmic contact layer 142, and active layer 132. Consequently, the tail S1 of the active layer at the edge of the drain 152 or source 153 (only the drain 152 is used as an example in the figure) is relatively small. In some instances, this tail S1 is less than or equal to 1.4 micrometers. At the same time, the tail of the ohmic contact layer at the edge of the drain 152 or source 153 (only the drain 152 is used as an example in the figure) is also relatively small, for example, less than or equal to 0.5 micrometers, or even 0.

[0047] According to some specific embodiments of the present invention, the etching solution for the first wet etching and the etching solution for the second wet etching are both the composite etching solution, as shown in the reference. Figure 4 Methods for fabricating thin-film transistors include:

[0048] S21: The metal layer 150, the doped semiconductor layer 140 and the partial thickness of the semiconductor layer 130 are etched by the first wet etching to obtain the sub-metal layer 151, the sub-doped semiconductor layer 141 and the thinned semiconductor layer 133, and expose the thinned semiconductor layer.

[0049] In the above steps, the etching solution used for the first wet etching is a composite etching solution, which can completely etch away the metal layer and the doped semiconductor layer 140 in the etched area, and partially etch away the semiconductor layer 130 to thin it out.

[0050] S22: The photoresist layer is ashed by photoresist ashing to obtain sub-photoresist layer 1600.

[0051] According to an embodiment of the present invention, referring to Figure 4 The photoresist layer also includes a second photoresist layer 162. The metal layer portion corresponding to the second photoresist layer 162 is used to fabricate the data signal line 154. That is, the data signal line 154, source 153, and drain 152 are obtained through the same step.

[0052] According to an embodiment of the present invention, referring to Figure 4The first photoresist layer 161 includes a thickened photoresist region 1611 and a thinned photoresist region 1612 (i.e., the thickness of the thickened photoresist region 1611 is greater than the thickness of the thinned photoresist region 1612). The second photoresist layer 162 is a thickened photoresist layer (which is formed in the same step as the thickened photoresist region 1611, and the thicknesses of the two are the same). Through the subsequent photoresist ashing step, the thinned photoresist region 1612 is removed, and the thickened photoresist region 1611 and the second photoresist layer 162 are thinned into a sub-photoresist layer 1600. The orthographic projection of the sub-photoresist layer 1600 on the substrate 100 is located inside the orthographic projection of the sub-metal layer 151 on the substrate 100. This allows the thinned photoresist region 1612 to correspond to the channel region of the TFT. After removing the thinned photoresist region 1612, the sub-metal layer 151 corresponding to the channel region is exposed, so that the sub-metal layer can be etched by the second wet etching process. The orthogonal projection of the sub-photoresist layer 1600 on the substrate 100 is located inside the orthogonal projection of the sub-metal layer 151 on the substrate 100. Therefore, in the subsequent dry etching process, the protection of the photoresist layer on the doped semiconductor layer 140 and the semiconductor layer 130 can be weakened, so that the etching gas can better etch the doped semiconductor layer 140 and the semiconductor layer 130. This results in the sub-doped semiconductor layer 141 and the sub-semiconductor layer 131 being covered by the sub-metal layer 151, which helps to reduce the tail length of the active layer and the ohmic contact layer, and may even make the tail of the subsequently obtained ohmic contact layer zero.

[0053] S23: The thinned semiconductor layer 133 is etched by dry etching to obtain the sub-semiconductor layer 131 and the sub-doped semiconductor layer 141.

[0054] In the above steps, the sub-doped semiconductor layer 141 not covered by the sub-metal layer 151 and the thinned semiconductor layer 133 are removed by dry etching to obtain the sub-semiconductor layer 131, as shown. Figure 4 As shown, the orthogonal projection of the sub-metal layer 151 onto the substrate 100 covers the orthogonal projection of the sub-doped semiconductor layer 141 onto the substrate, and also covers the orthogonal projection of the sub-semiconductor layer 131 onto the substrate 100. Therefore, after photoresist ashing and performing the aforementioned dry etching, the resulting sub-doped semiconductor layer 141 and sub-semiconductor layer 131 are smaller in size and covered by the sub-metal layer, thereby helping to reduce active layer tailing (…). Figure 4 The length of the ohmic contact layer tail (S1) and the tail of the ohmic contact layer can even make the tail of the subsequently obtained ohmic contact layer zero (e.g., Figure 4 (As shown).

[0055] In particular, since the doped semiconductor layer and part of the semiconductor layer in the etched area have been removed in the first wet etching, compared to Figure 3 The dry etching method used in the fabrication process can significantly reduce the etching time.

[0056] S24: A second wet etching process is performed on the sub-metal layer 151, sub-doped semiconductor layer 141, and sub-semiconductor layer 131 corresponding to the channel region. This removes the sub-metal layer 151, sub-doped semiconductor layer 141, and a portion of the thickness of the sub-semiconductor layer 131 corresponding to the channel region, resulting in the source 153, drain 152, ohmic contact layer 142, and active layer 132. Consequently, the tail S1 of the active layer at the edge of the drain 152 or source 153 (only the drain 152 is used as an example in the figure) is relatively small. In some instances, the tail S1 is less than or equal to 1.4 micrometers. At the same time, the tail of the ohmic contact layer at the edge of the drain 152 or source 153 (only the drain 152 is used as an example in the figure) is also relatively small, for example, less than or equal to 0.5 micrometers, or even 0.

[0057] According to an embodiment of the present invention, referring to Figure 3 and Figure 4 It can also reduce the trailing S2 of the active layer at the edge of the data signal line (e.g., Figure 3 and Figure 4 The length of S2 in the data signal line is increased, thereby reducing the impact of parasitic capacitance on the data signal line and improving the performance of the data signal line.

[0058] According to embodiments of the present invention, as can be seen from the above-described TFT fabrication steps, the active layer is formed through wet etching. Compared to dry etching, wet etching offers higher uniformity, which can improve TFT production capacity, reduce dry etching waste gas emissions, and comply with national low-carbon and environmental protection policies. Furthermore, it can effectively achieve mass production of the active layer wet etching process. Moreover, due to the higher uniformity of wet etching, the thickness of the active layer can be reduced during fabrication, potentially to a smaller thickness. (If dry etching is used to fabricate the active layer, the active layer will be relatively thick, approximately...) This reduces production costs.

[0059] Moreover, compared to the traditional 2W2D process ( Figure 1The 2W1D process of this invention can significantly improve product yield, mainly because the ohmic contact layer and active layer etched in the back channel are wet-etched. The etching solution can etch the ohmic contact layer and active layer, but will not etch the gate insulating layer. That is, the loss of the gate insulating layer reduces the short-circuit failure at the overlap between the gate metal and the source or drain, thereby improving product yield. In some embodiments, when the product model is 75 0+5120Hz, 75 0+4120Hz or 75 0+460Hz as shown in Table 1, the yield of the 2W2D process is 92.49% before repair and 97.86% after repair; the yield of the 2W1D process is 94.44% before repair and 98.88% after repair. For product models 65 4K-C60Hz, 65 4K-C144Hz, 65 4K-C240Hz, 65 0+4 60Hz, or 65 1+5 60Hz 8K as listed in Table 1, the yield rate before repair for the 2W2D process is 94.25%, and after repair it is 98.20%; for the 2W1D process, the yield rate before repair is 96.19%, and after repair it is 98.97%. For product models 32 single-cut 0+4 60Hz as listed in Table 1, the yield rate before repair for the 2W2D process is 99.13%, and after repair it is 99.72%; for the 2W1D process, the yield rate before repair is 99.10%, and after repair it is 99.73%. Here, "before repair" refers to the yield rate of a batch of products produced, and "after repair" refers to the total yield rate of a batch of products, including the defective products that were repaired and then passed, and the products that were originally qualified.

[0060] According to embodiments of the present invention, the ashing gas for photoresist ashing includes oxygen and a fluorine-containing gas. Thus, the fluorine-containing gas can ionize to produce fluoride ions, which promote the dissociation of oxygen and dilute the distribution of oxygen ions, thereby improving the ashing rate and uniformity of the photoresist. Further, the ashing gas is NF3 / O2, CF4 / O2, SF6 / O2, or CHF3 / O2. Among these gases, the fluorine-containing gas can effectively ionize to produce fluoride ions and mixes relatively uniformly with oxygen.

[0061] In the photoresist ashing process, the flow rate of fluorine-containing gas can be 500–3000 sccm, the flow rate of oxygen gas can be 2000–15000 sccm, the source power in the ashing power is 5–15 kW, the bias power in the ashing power is 5–15 kW, the ashing gas pressure is 20–70 mT, and the ashing time is 40–80 s. Under these conditions, the photoresist layer can be ashed quickly and uniformly.

[0062] According to embodiments of the present invention, the etching gas for dry etching includes an inert gas and a fluorine-containing gas, but does not contain chlorine. The etching gas can etch the doped semiconductor layer and the semiconductor layer. The aforementioned gas can perform etching quickly and uniformly, resulting in a film structure with superior performance. Furthermore, the absence of chlorine in the etching gas avoids corrosion of the channel metal layer by chlorine (chlorine is a highly corrosive gas that reacts with metals, generating metal chlorides that are difficult to remove in subsequent processes, easily leading to defects), and reduces safety management risks and waste gas emissions, achieving chlorine-free production. Further, the etching gas is NF3 / He, CF4 / He, CHF3 / He, or SF6 / He. The above-mentioned etching gases have high etching efficiency and good etching uniformity.

[0063] In the dry etching process, the flow rate of the fluorine-containing gas can be 2000–6000 sccm, the flow rate of the inert gas can be 2000–6000 sccm, the source power and bias power in the dry etching power are 5–15 kW, and the ashing gas pressure is 20–70 mT. Under these conditions, the doped semiconductor layer and the semiconductor layer can be etched rapidly and uniformly.

[0064] According to embodiments of the present invention, based on the total mass of the composite etching solution, the fluoride ion content is 0.1% to 0.4% by mass, which can effectively etch semiconductor layers and doped semiconductor layers. When the metal layer includes aluminum, the etching solution includes nitric acid and phosphoric acid, wherein, based on the total mass of the composite etching solution, the nitric acid content is 2.8% to 3.2% and the phosphoric acid content is 63% to 70%, thus effectively etching aluminum-containing metal layers. When the metal layer includes copper, the etching solution includes hydrogen peroxide, wherein, based on the total mass of the composite etching solution, the hydrogen peroxide content is 15% to 25%, thus effectively etching copper-containing metal layers. Therefore, the above-mentioned composite etching solution possesses the ability to etch metal layers as well as the ability to etch ohmic contact layers and active layers.

[0065] According to an embodiment of the present invention, referring to Figure 3 and Figure 4 After obtaining the source, drain, ohmic contact layer, and active layer, the process also includes removing the sub-photoresist layer 1600 using a photoresist ashing process. Using a dry stripping method for the sub-photoresist layer avoids contamination of the TFT channel by the stripping solution, reducing back channel leakage current. Simultaneously, the active layer tails S1 and S2 at the edges of the signal lines, source, and drain metals are oxidized during the sub-photoresist stripping process, reducing the photosensitive nature of the active layer tails and decreasing photo-induced leakage current, thereby improving the characteristics of the TFT device.

[0066] According to embodiments of the present invention, by employing a composite etching solution, not only the metal layer is etched during etching, but also the ohmic contact layer and part of the semiconductor layer are etched, thus achieving relatively efficient etching in the process. Figure 1 The proposed solution eliminates the second dry etching process, saving process steps and reducing the distance between the source / drain edges and the active layer edges (i.e., reducing the tail length of the active layer at the source / drain edges) and the distance between the source / drain edges and the ohmic contact layer edges (i.e., reducing the tail length of the ohmic contact layer at the source / drain edges). Furthermore, performing photoresist ashing before dry etching weakens the photoresist layer's protection of the doped semiconductor layer and the semiconductor layer, further enhancing the protection of the doped semiconductor layer and the semiconductor layer. The etching degree of the conductor layer further reduces the trailing length of the active layer and ohmic contact layer at the source and drain edges. The significant reduction in the trailing length of the active layer can reduce parasitic capacitance and light leakage current, thereby effectively improving the reliability defects of the display panel such as water ripples and crosstalk. Without the trailing length of the ohmic contact layer, the channel length design value of the TFT can be reduced while ensuring the charging rate remains unchanged, realizing the miniaturization design of TFT devices. At the same time, the width of the GOA area can also be reduced, which further reduces the size of the display panel bezel and is conducive to achieving an ultra-narrow bezel.

[0067] In some specific embodiments of the present invention, reference is made to... Figure 5 ,use Figure 3 The fabrication steps for thin-film transistors resulted in an active tail (S1) length of 1.15 micrometers at the source and drain edges, while the ohmic contact layer showed zero tail, indicating no significant step characteristics between the ohmic contact layer and the active layer. Figure 1 The 2W2D process used to fabricate thin-film transistors resulted in an active tail (d1) length of 1.8 micrometers at the source and drain edges of the active layer. The ohmic contact layer also had a tail of a certain length, and there was a clear step characteristic between the ohmic contact layer and the active layer.

[0068] The impact of the active tail on the display panel's display effect can be found in the following reference. Figure 6 (The vertical axis represents the water ripple effect level, with higher levels indicating greater severity; the horizontal axis represents the length of the active layer tail S1.) When the LCD screen is placed under PWM (Pulse Width Modulation) modulated backlight, the larger the active layer tail, the more severe the water ripple defect. Currently, the quality control standard is that waterfall defects ≤ L2 (i.e., water ripple effect level less than or equal to 2 is acceptable), meaning the active layer tail of the product is less than or equal to 1.4 micrometers.

[0069] As shown in Table 1, the test data indicates that compared to Figure 1 Compared with the traditional 2W2D process, the 2W1D process of this invention can significantly improve the ion mobility (Ion) and tail-end (leakage current at P_Ioff-20V) of thin film transistors. This is mainly because the wet etching of the ohmic contact layer and active layer of the back channel can reduce the damage to the semiconductor (such as semiconductor a-Si), thereby reducing the defect state of the film and optimizing the product characteristics. At the same time, it can reduce the thickness of the active layer, which increases the production capacity and reduces the production cost.

[0070] Table 1

[0071]

[0072]

[0073] In another aspect, the present invention provides a thin-film transistor. According to an embodiment of the present invention, the thin-film transistor is fabricated using the method described above. Therefore, the thin-film transistor exhibits superior reliability, lower parasitic capacitance and light leakage current, effectively improving reliability defects such as water ripples and crosstalk in display panels; the TFT channel length is smaller, which is beneficial for miniaturization design of TFT devices; simultaneously, the width of the GOA region can be reduced, further reducing the size of the display panel bezel and facilitating the achievement of extremely narrow bezels.

[0074] According to an embodiment of the present invention, the tail length S1 of the active layer at the edges of the source and drain is less than or equal to 1.4 micrometers (i.e., the distance between the edge of the active layer in the thin-film transistor and the edge of the source and drain is less than or equal to 1.4 micrometers), such as 1.4 micrometers, 1.3 micrometers, 1.2 micrometers, 1.1 micrometers, 1.0 micrometers, 0.9 micrometers, 0.8 micrometers, 0.7 micrometers, 0.6 micrometers, etc.; the tail length of the ohmic contact layer at the edges of the source and drain is less than or equal to 0.5 micrometers (i.e., the distance between the edge of the source and drain and the edge of the ohmic contact layer is less than or equal to 0.5 micrometers), such as 0.5 micrometers, 0.4 micrometers, 0.3 micrometers, 0.2 micrometers, 0.1 micrometers, or 0. Therefore, the thin-film transistor has better reliability, lower parasitic capacitance and light leakage current, which can effectively improve the defects of poor reliability such as water ripple and crosstalk in the display panel; the channel length of the TFT is smaller, which is conducive to the miniaturization design of TFT devices; at the same time, the width of the GOA area can also be reduced, which further reduces the size of the display panel bezel and is conducive to achieving an ultra-narrow bezel.

[0075] According to an embodiment of the present invention, the thickness of the active layer is This reduces the manufacturing cost of the active layer, thereby reducing the overall manufacturing cost of the ground transistor.

[0076] In another aspect, the present invention provides a display panel that, according to an embodiment of the invention, includes the thin-film transistors described above. Thus, the display panel has high reliability and a narrow bezel. Those skilled in the art will understand that the display panel possesses all the features and advantages of the thin-film transistors described above, and will not be elaborated further here.

[0077] The terms "first" and "second" used in this document are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature marked "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0078] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0079] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for fabricating a thin-film transistor, characterized in that, include: A gate, a gate insulating layer, a semiconductor layer, a doped semiconductor layer, and a metal layer are sequentially formed on one side of the substrate; A photoresist layer is formed on the surface of the metal layer, the photoresist layer including a first photoresist layer; By sequentially performing a first wet etching, photoresist ashing, dry etching, and a second wet etching on the first photoresist layer, the source, drain, ohmic contact layer, and active layer are obtained. Wherein, the etching solution used in at least one of the first wet etching and the second wet etching is a composite etching solution, the composite etching solution includes etching metal liquid and fluoride ions, and the composite etching solution can etch the metal layer, the doped semiconductor layer and part of the semiconductor layer; The photoresist layer further includes a second photoresist layer, through which the first wet etching, the photoresist ashing, the dry etching, and the second wet etching are performed sequentially to obtain the data signal line; After the first wet etching, a sub-metal layer is obtained. The first photoresist layer includes a thickened photoresist region and a thinned photoresist region. The second photoresist layer is a thickened photoresist layer. By ashing the photoresist, the thinned photoresist region is removed, and the thickened photoresist region and the second photoresist layer are thinned into a sub-photoresist layer. The orthographic projection of the sub-photoresist layer on the substrate is located inside the orthographic projection of the sub-metal layer on the substrate. The dry etching process removes the doped semiconductor layer and the semiconductor layer that are not covered by the sub-metal layer, resulting in a sub-doped semiconductor layer and a sub-semiconductor layer. The orthogonal projection of the sub-metal layer on the substrate covers the orthogonal projection of the sub-doped semiconductor layer on the substrate, and also covers the orthogonal projection of the sub-semiconductor layer on the substrate. The etching solution used in the first wet etching and the etching solution used in the second wet etching are both the composite etching solution, and the method includes: The first wet etching process etches the metal layer, the doped semiconductor layer, and a portion of the semiconductor layer to obtain the sub-metal layer, the sub-doped semiconductor layer, and the thinned semiconductor layer, thereby exposing the thinned semiconductor layer. The photoresist layer is ashed by the aforementioned photoresist ashing process; The thinned semiconductor layer is etched by the dry etching process to obtain the sub-semiconductor layer; The second wet etching process is used to etch the sub-metal layer, the sub-doped semiconductor layer, and the sub-semiconductor layer corresponding to the channel region, thereby removing the sub-metal layer, the sub-doped semiconductor layer, and the sub-semiconductor layer corresponding to the channel region, and obtaining the source, the drain, the ohmic contact layer, and the active layer.

2. The method according to claim 1, characterized in that, The ashing gas used for photoresist ashing includes oxygen and fluorine-containing gases.

3. The method according to claim 2, characterized in that, The ashing gas is NF3 / O2, CF4 / O2, SF6 / O2, or CHF3 / O2.

4. The method according to claim 1, characterized in that, The etching gas used in the dry etching process includes inert gas and fluorine-containing gas, but does not contain chlorine. The etching gas can etch the doped semiconductor layer and the semiconductor layer.

5. The method according to claim 4, characterized in that, The etching gases are NF3 / He, CF4 / He, CHF3 / He, and SF6 / He.

6. The method according to claim 1, characterized in that, Based on the total mass of the composite etching solution, the fluoride ion content is 0.1%~0.4% by mass percentage; When the metal layer comprises aluminum, the etching solution comprises nitric acid and phosphoric acid, wherein, based on the total mass of the composite etching solution, the content of nitric acid is 2.8%~3.2%, and the content of phosphoric acid is 63%~70%. When the metal layer comprises copper, the etching solution comprises hydrogen peroxide, wherein the hydrogen peroxide content is 15% to 25% based on the total mass of the composite etching solution.

7. The method according to claim 1, characterized in that, After obtaining the source, the drain, the ohmic contact layer and the active layer, the method further includes: removing the sub-photoresist layer by photoresist ashing.

8. A thin-film transistor, characterized in that, It is produced using the method described in any one of claims 1 to 7.

9. The thin-film transistor according to claim 8, characterized in that, The tail length of the active layer at the edge of the source and drain is less than or equal to 1.4 micrometers, and the tail length of the ohmic contact layer at the edge of the source and drain is less than or equal to 0.5 micrometers.

10. The thin-film transistor according to claim 9, characterized in that, The thickness of the active layer is 600 Å to 1100 Å.

11. A display panel, characterized in that, The thin-film transistor includes any one of claims 8 to 10.

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