METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES

Abstract

Method for manufacturing a semiconductor device, comprising the method: Forming a fin structure (20) by structuring a semiconductor layer (10); Forming an insulating layer (30) such that an upper section of the fin structure (20) protrudes from the insulating layer (30); Formation of a gate dielectric layer (120) by a deposition process; After the gate dielectric layer (120) has been formed, nitrogen is introduced into the gate dielectric layer (120); and Forming a gate electrode layer (40) over the gate dielectric layer (120), wherein the gate dielectric layer (120), as it is formed, is silicon oxide, where: the introduction of nitrogen involves a plasma nitriding process using an N2 gas and an NH3 gas and a flow ratio NH3 / (N2 + NH3) in a range of 0.1 to 0.3, wherein a part of the gate dielectric layer (120) formed on a side wall of the upper section of the fin structure (20) contains no nitrogen or contains nitrogen in an amount less than 3 atomic %.

Description

BACKGROUND

[0001] As the semiconductor industry has evolved to nanometer-scale processing nodes in the pursuit of higher device density, higher performance, and lower costs, challenges have arisen in both manufacturing and design for three-dimensional designs, such as multi-gate field-effect transistors (FETs) containing a fin FET (FinFET) and a gate-all-around FET (GAA-FET). With transistor dimensions constantly being developed to technology nodes smaller than 10-15 nm, further improvements to the FinFET are needed, for example, precise control of the critical dimension (CD) and defect-free fin formation processes.

[0002] Document US 2013 / 0001707A1 describes a method for fabricating a MOS transistor, in which a gate dielectric layer of a fin field-effect transistor is formed on a substrate. A nitriding process using nitrogen plasma and helium gas is performed to nitride the gate dielectric layer.

[0003] Document US 2008 / 0254588A1 describes a method for forming a semiconductor structure, which includes the formation of a gate dielectric layer over a substrate. One top surface of the gate dielectric layer is treated to partially nitride it. The treated gate dielectric layer is then thermally treated with an oxygen-containing precursor, resulting in a nitrogen concentration between 0.5 atomic percent and 20 atomic percent.

[0004] Document US 2006 / 0148179A1 describes a process for producing a nitrogen-containing gate dielectric layer. First, a gate dielectric layer is formed on a substrate by a wet oxidation process. Then, a nitration process is carried out to introduce nitrogen into the gate dielectric layer. Finally, a reoxidation process is performed.

[0005] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure is best understood with reference to the following detailed description in conjunction with the accompanying drawings. It is emphasized that, in accordance with industry practice, various features are not shown to scale and are for illustrative purposes only. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. 1A, Fig. 1B, Fig. 1C and Fig. Figure 1D shows cross-sectional views of different stages of a sequential process for manufacturing a FinFET device according to an embodiment of the present disclosure. Fig. 2A, Fig. 2B, Fig. 2C and Fig. Figure 2D shows cross-sectional views of different stages of a sequential process for manufacturing a FinFET device according to an embodiment of the present disclosure. Fig. 3A, Fig. 3B, Fig. 3C and Fig. 3D shows cross-sectional views of various stages of a sequential process for manufacturing a FinFET device according to an embodiment of the present disclosure. Fig. 4A, Fig. 4B, Fig. 4C, Fig. 4D, Fig. 4E and Fig. Figure 4F shows cross-sectional views of various stages of a sequential process for manufacturing a FinFET device according to an embodiment of the present disclosure. Fig. Figure 5 shows a flowchart of a sequential manufacturing process of a FinFET device according to an embodiment of the present disclosure. Fig. 6A is a perspective view after a gate electrode layer has been formed, and Fig. Figure 6B shows a cross-sectional view of the gate dielectric layer and the fin structures according to an embodiment of the present disclosure. Fig. 7A, Fig. 7B and Fig. Figure 7C shows cross-sectional views of the gate dielectric layer and the fin structures according to various embodiments of the present disclosure. Fig. Figure 8 shows nitrogen concentrations along the vertical direction of the nitrided gate dielectric layer according to various embodiments of the present disclosure. Fig. 9A shows a plasma processing device according to an embodiment of the present disclosure and Fig. Figure 9B shows a pulsed bias plasma process according to an embodiment of the present disclosure. Fig. Figure 10A shows a schematic view of a directed plasma processing device according to an embodiment of the present disclosure. Fig. 10B, Fig. 10C and Fig. Figure 10D shows schematic views of a directed plasma process according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0007] It is clear that the following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or disclosed values, but may depend on process conditions and / or desired properties of the device.Furthermore, the formation of a first structural element above or on top of a second structural element in the following description can include embodiments in which the first and second structural elements are formed in direct contact, and can also include embodiments in which additional structural elements can be formed between the first and second structural elements, so that the first and second structural elements might not be in direct contact. For the sake of simplicity and clarity, different structural elements can be drawn at different scales.

[0008] Furthermore, spatially relative terms such as "underlying," "below," "under," "superior," "above," and the like may be used herein to facilitate description and to describe the relationship of one element or structural element to another element(s) or structural element(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Additionally, the term "made of" may mean either "comprising" or "consisting of."In the present disclosure, the phrase "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C) and does not mean one element of A, one element of B, and one element of C, unless otherwise specified. Throughout the disclosure, a Source and a Drain are used interchangeably, and a Source / Drain refers to one or both of the Source and the Drain. In the following embodiments, materials, configurations, dimensions, processes, and / or operations as described with respect to one embodiment (e.g., one or more figures) may be used in the other embodiments, and a detailed description thereof may be omitted.

[0009] In the fabrication process of a semiconductor device incorporating FinFETs, the quality of the gate dielectric layer is a primary concern. In particular, when silicon oxide is used as the gate dielectric layer, it is essential that the gate dielectric layer exhibits high reliability in electrical properties (e.g., high time-dependent dielectric breakdown (TDDB)) and high physical properties (e.g., high etch resistance). This disclosure provides a novel process for improving the quality of the silicon oxide gate dielectric layer by introducing nitrogen into the silicon oxide layer.

[0010] Fig. 1A-4F show views of different levels and Fig. Figure 5 shows a flowchart of a sequential manufacturing process of a FinFET device according to an embodiment of the present disclosure. It is clear that additional operations before, during, and after the processes described in Figure 5 are required. Fig. 1A-4F and Fig. Figure 5 shows that some of the operations described below can be provided, and some of the operations can be replaced or eliminated for additional embodiments of the method. The sequence of operations / processes can be interchangeable.

[0011] In S101 of Fig. 5. A hard mask structure is formed to create fin structures. In some embodiments, such as in Fig. As shown in Figure 1A, a hard mask layer 15 is formed over a substrate 10. In one embodiment, the substrate 10 has a single-crystalline semiconductor layer on at least its surface portion. The substrate 10 can contain a single-crystalline semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In one embodiment, the substrate 10 is made of Si. The substrate 10 can have various regions that have been suitably doped with impurities (e.g., p- or n-type conductivity). The dopants are, for example, boron (BF₂) for an n-type FinFET and phosphorus or arsenic for a p-type FinFET.

[0012] In some embodiments, the mask layer 15 comprises a first mask layer 15A and a second mask layer 15B. In some embodiments, the first mask layer 15A comprises a silicon nitride layer and the second mask layer 15B comprises a silicon oxide layer. The first and second mask layers 15A and 15B are formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), including sputtering, atomic layer deposition (ALD), or another suitable film formation process. In some embodiments, a pad oxide layer 12, made of a silicon oxide that can be formed by thermal oxidation, is formed before the first mask layer 15A is formed.

[0013] In some embodiments, fin structures are formed using one or more photolithography processes, comprising dual or multiple structuring processes. Generally, dual or multiple structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, smaller divisions than would otherwise be obtainable using a single, direct photolithography process. For example, as in Fig. As shown in Figure 1B, a sacrificial layer is formed over a substrate and structured using one or more photolithography and etching processes to form spindle structures (sacrificial structures) 16. Then a cover layer 18 is formed, as shown in Figure 1B. Fig. 1C shown, and anisotropic etching performed to form sidewall spacers 18 along the spindle structures using a self-aligning process, as shown in Fig. 1D shown. Then the spindle structures 16 are removed and the remaining spacers 18 are used as a mask structure 18, as shown in Fig. 2A shown. In some embodiments, one or more additional sidewall formation processes are carried out to form mask structures that have even smaller divisions.

[0014] As in Fig. As shown in Figure 2A, the mask structure 18 has several conduction structures corresponding to one or more fin structures in a p-region and one or more fin structures in an n-region. In some embodiments, the division of the mask structure 18 in the p-region is larger than the division of the mask structure 18 in the n-region.

[0015] Further, as in Fig. As shown in Figure 2B, in some embodiments a cover layer 19 is formed further over the mask structure 18. In some embodiments, the cover layer 19 is made of one or more silicon oxides, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a dielectric low-k material. In some embodiments, the cover layer 19 is formed by ALD. In some embodiments, the thickness of the cover layer 19 ranges from about 0.5 nm to about 5 nm.

[0016] Then the mask layer 15 and the pad oxide layer 12 are structured using one or more etching processes, as shown in Fig. 2C shown. In some embodiments, the mask structures 18 are cut into short pieces using one or more lithography and etching processes before the mask layer 15 and the pad oxide layer 12 are structured, in order to form structures corresponding to individual fin structures. In some embodiments, one or more unnecessary structures (e.g., dummy structures) are also removed by etching.

[0017] Further information is provided in S102 by Fig. 5. The substrate 10 is structured using the structured mask layer as an etching mask, thereby forming fin structures 20N and 20P (collectively fin structures 20) extending in the Y direction. In some embodiments, the fin structures 20N are for an n-FET and the fin structures 20P are for a p-FET. Fig. In 2D, two fin structures 20P are arranged in the X-direction in the p-region, and four fin structures 20N are arranged in the X-direction in the n-region. However, the number of fin structures is not limited to two or four and can be one, three, or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structures 20 to improve structural accuracy in the structuring processes.

[0018] After the fin structures 20 were formed, in S103 of Fig. 5. One or more cleaning processes are performed. In some embodiments, a meniscus reconfiguration cleaning using heated isopropyl alcohol is employed as the cleaning process.

[0019] In some embodiments, after the wet cleaning process in S104, Fig. 5. A first tempering process is carried out to remove damage caused to the sidewalls of the fin structures. In some embodiments, the tempering process comprises rapid thermal tempering at a temperature in the range of about 900 °C to about 1100 °C for about 1 to 20 seconds. In other embodiments, the temperature is in the range of about 950 °C to 1050 °C. In other embodiments, the duration is in the range of about 5 to 15 seconds. In some embodiments, the tempering process is carried out in a surrounding inert gas (Ar, He, and / or N₂). In other embodiments, the tempering process is carried out under a pressure in the range of 1.3 × 10⁻⁶ -5 Pa up to 6.7 × 10 -4 Pa (1 × 10 -7 Torr up to 5 × 10 -6The tempering process is carried out using Torr). This process causes hydrogen and fluorine atoms to diffuse out of the fin structures and recrystallize the damaged areas. If the temperature is lower than the specified ranges, hydrogen and fluorine cannot be effectively removed from the damaged areas of the fin structures. If the temperature is higher than the specified ranges, the fin structure may bend and become damaged. Similarly, if the process time is shorter than the specified ranges, hydrogen and fluorine cannot be effectively removed from the damaged areas of the fin structures. If the process time is longer than the specified ranges, previously formed diffusion areas may be damaged.

[0020] Then, in S105, from Fig. 5 one or more insulating material layers 30L formed for an insulating layer over the fin structures, as in Fig. Figure 3A shows that in some embodiments, the insulating material layer 30L is formed over the substrate such that the fin structures 20 are completely embedded in the insulating layer 30L. The insulating material for the insulating layer can contain silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a dielectric low-k material formed by LPCVD (low-pressure chemical vapor deposition), plasma CVD, or flowable CVD. An annealing process can be carried out after the insulating layer has been formed.

[0021] Then, as in Fig. As shown in Figure 3B, a first planarization process, such as a chemical-mechanical polishing (CMP) process and / or a back-etching process, is performed so that the upper surfaces of the second mask layer 15B are exposed from the insulating material layer 30L. Then, a second planarization process is performed to remove the second mask layer 15B and the first mask layer 15A and expose the upper surfaces of the fin structures 20, as shown in Figure 3B. Fig. Figure 3C shows that in some embodiments, the first and second planarization processes are combined.

[0022] Then, as in Fig. As shown in 3D, the insulating material layer 30L is recessed to form an insulating layer 30, exposing the upper sections (channel regions 22) of the fin structures 20. This process electrically isolates the fin structures 20 from each other through the insulating layer 30, also known as trench insulation (STI).

[0023] In some embodiments, before the insulating layer 30 is formed, one or more insulating lining layers are formed over the fin structures 20. The insulating lining layer contains silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, or another suitable material. The insulating lining layer formed on the channel areas 22 of the fin structures is removed when the insulating layer 30 is recessed, and the lower part of the fin structures is covered by the insulating lining layer within the insulating layer 30.

[0024] In some embodiments, before the insulating layer 30 is formed and before the lining layer is formed, one or more lining semiconductor layers are formed over the fin structures. In some embodiments, the lining semiconductor layers include a first lining semiconductor layer containing silicon, SiGe, or Ge. In certain embodiments, silicon is used. The first lining semiconductor layer is formed over the fin structures to prevent fin bending. In some embodiments, the thickness of the first lining semiconductor layer is in the range of about 0.2 nm to about 4 nm, and in other embodiments, it is in the range of about 0.5 nm to about 2 nm, depending on device and / or process requirements.In some embodiments, the first liner semiconductor layer is epitaxially grown by an LPCVD process, molecular beam epitaxy, atomic layer deposition, or another suitable method. The LPCVD process is carried out at a temperature of about 400 °C to 850 °C, which is lower than the annealing temperature, and under a pressure of about 133 Pa to 2.7 × 10⁻⁶. 4 Pa (1 Torr to 200 Torr) is carried out using a silicon source gas such as SiH4, Si2H6, or Si3H8. If SiGe or Ge is formed, the source gas contains one or more of GeH4 or Si2H6. In some embodiments, the first lining semiconductor layer is undoped, and in other embodiments, the first lining semiconductor layer 100 is appropriately doped for the n-fin structures 20N and p-fin structures 20P.

[0025] After the first liner semiconductor layer has been formed, one or more wet cleaning processes are carried out in some embodiments. In some embodiments, a wet cleaning solution contains aqueous solutions of ammonia (NH3) and hydrogen peroxide (H2O2) and / or aqueous solutions of hydrochloric acid (HCl) and hydrogen peroxide (H2O2). During the wet cleaning process, the first liner semiconductor layer (and in some embodiments the fin structures 20) is slightly etched.

[0026] In some embodiments, a second liner semiconductor layer is formed over the fin structures. In some embodiments, the second liner semiconductor layer contains silicon, SiGe, or Ge. In certain embodiments, silicon is used. The second liner semiconductor layer is formed over the fin structures to adapt the dimensions (width) of the fin structures. In some embodiments, the thickness of the second liner semiconductor layer is in the range of approximately 0.2 nm to approximately 4 nm, and in the range of approximately 0.5 nm to approximately 2 nm, depending on device and / or process requirements. In some embodiments, the second liner semiconductor is grown epitaxially, similar to the first liner semiconductor layer.In some embodiments, the second lining semiconductor layer is not doped, and in other embodiments, the second lining semiconductor layer is doped appropriately for the n-fin structures 20N and p-fin structures 20P.

[0027] Subsequently, after the insulating layer 30 has been formed, in S106 of Fig. 5, as in Fig. Figure 4A shows a gate dielectric layer 120 formed over the channel regions 22 of the fin structures 20 and the upper surface of the insulating layer 30. In some embodiments, the gate dielectric layer 120 is silicon oxide formed by CVD, including low-pressure CVD and plasma-enhanced CVD, ALD including plasma-enhanced ALD, or another suitable film formation process. In some embodiments, the thickness of the gate dielectric layer 120 is in the range of about 0.5 nm to about 10 nm, and in other embodiments, it is in the range of about 1 nm to about 6 nm, depending on the design and / or process requirements.

[0028] Then in S107 from Fig. 5, as in Fig. Figure 4B shows a nitriding process 100 being carried out on the gate dielectric layer 120 to nitride the surface section of the gate dielectric layer 120.

[0029] In some embodiments, the nitriding process is carried out using plasma with a source gas of N2 and NH3. In some embodiments, the flow ratio of NH3 is... 3 / (N2+NH3) in a range of approximately 0.4 to 1.0. In some embodiments, the flow rate of NH3 is greater than the flow rate of N2. In some embodiments, the flow ratio is in a range of approximately 0.4 to 0.6. In other embodiments, the flow ratio is in a range of approximately 0.8 to 0.95. In certain embodiments, the flow ratio is in a range of approximately 0.6 to 0.8. As the amount of NH3 increases, the uniformity of the nitration increases.

[0030] In some embodiments, the nitriding process is carried out at a substrate temperature in the range of approximately 50 °C to approximately 450 °C and at a pressure in the range of approximately 1.3 Pa to 20.0 Pa (10 mTorr to approximately 150 mTorr). In some embodiments, the plasma RF power is in the range of approximately 300 W to approximately 2000 W. The RF power is applied in pulses with a duty cycle of approximately 5% to approximately 70% in some embodiments. The nitriding time is in the range of approximately 20 seconds to approximately 150 seconds, depending on the design and / or process requirements.

[0031] After the nitriding process, the gate dielectric layer 120N has a composition SiO₂. 2-x N xin some embodiments, where x is approximately 0.01 to approximately 0.2 and in other embodiments, x is approximately 0.05 to 0.1. In some embodiments, the gate dielectric layer 120N has a region of lower nitrogen concentration, where x is approximately 0.01 to approximately 0.05, and a region of higher nitrogen concentration, where x is approximately 0.1 to approximately 0.2.

[0032] After the nitration process, S108 is treated by Fig. 5, as in Fig. 4C and Fig. Figure 4D shows a gate electrode layer 40 formed over the channel regions 22 of the fin structures. In some embodiments, the gate electrode layer 40 comprises silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the gate electrode layer 40 is in some embodiments in the range of about 100 nm to about 200 nm. The gate electrode layer 40 is deposited using CVD, including LPCVD and PECVD, PVD, ALD, or another suitable process, and is patterned using, for example, a hard mask layer comprising one or more layers of silicon nitride and silicon.

[0033] In the embodiment of Fig. In embodiment 4C-4D, a gate electrode layer 40 is deposited over two fin structures 20P in the p-region, and a gate electrode layer 40 is deposited over four fin structures 20N in the n-region. However, the number of fin structures per gate electrode layer is not limited and can be one, two, three, or more than four. In other embodiments, a gate electrode layer 40 is formed over one or more n-fin structures 20N and one or more p-fin structures 20P.

[0034] After the gate electrode layer 40 has been formed, S109 is Fig. 5 a gate sidewall spacer 45 formed, as in Fig. Figure 4E shows a cover layer of insulating material for sidewall spacers that is conformally formed using CVD or other suitable methods. The cover layer is conformally deposited such that it has substantially the same thickness on vertical surfaces, such as the sidewalls, horizontal surfaces, and the top of the sacrificial gate structure. In some embodiments, the cover layer is deposited to a thickness in the range of about 2 nm to about 10 nm. In one embodiment, the insulating material of the cover layer is a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN, and combinations thereof. The sidewall spacers are formed on opposite sidewalls of the gate electrode layer 40.

[0035] Then, in S110, Fig. 5 a source / drain epitaxial layer is formed. In some embodiments, the fin structures of source / drain regions are recessed below the upper surface of the insulating layer 30 using dry etching and / or wet etching, and then one or more semiconductor layers are epitaxially formed over the recessed fin structures. In other embodiments, one or more semiconductor layers are epitaxially formed over the source / drain region of the non-recessed fin structure. The source / drain epitaxial layer for an n-FET comprises one or more layers of SiC, SiP, and SiCP, and the source / drain epitaxial layer for a p-FET comprises one or more layers of SiGe and SiGeSn, which may be doped with B. In at least one embodiment, the epitaxial layers are epitaxially grown by an LPCVD process, molecular beam epitaxy, atomic layer deposition, or another suitable method.The LPCVD process is carried out at a temperature of approximately 400 °C to approximately 850 °C and under a pressure of approximately 133 Pa to 2.7 × 10. 4 Pa (1 Torr to about 200 Torr), using a silicon source gas such as SiH4, Si2H6, or Si3H8; a germanium source gas such as GeH4 or G2H6; a carbon source gas such as CH4 or SiH3CH3; a phosphorus source gas such as PH3; and / or a boron source gas such as B2H6. In some embodiments, two or more layers with different compositions (e.g., different P, C, Ge, and / or B concentrations) are formed as the source / drain epitaxy layers.

[0036] Then, in S111, Fig. 5 a first dielectric intermediate layer (ILD layer) 50 is formed over the source / drain epitaxy layers and the gate electrode layer 40, as in Fig. 4F shown. The materials for the first ILD layer 50 contain compounds comprising Si, O, C and / or H, such as silicon dioxide, SiCOH and SiOC. Organic materials, such as polymers, can be used for the first ILD layer 50.

[0037] Fig. 6A is a perspective view after formation of the gate electrode layer 40 and Fig. Figure 6B shows a cross-sectional view of the gate dielectric layer 120N and the fin structure 20 along the X direction.

[0038] In some embodiments, the height H1 of the channel region 22 of the fin structure 20 above the upper surface of the insulating layer 30 is in a range of approximately 15 nm to approximately 85 nm, depending on the design and / or process requirements. In some embodiments, the width W1 of the channel region 22 at its base is in a range of approximately 4 nm to approximately 30 nm, and the space S1 between adjacent channel regions 22 is in a range of approximately 6 nm to approximately 30 nm, depending on the design and / or process requirements.

[0039] In some embodiments, the thickness T1 of the gate dielectric layer at the top of the channel region 22 is in a range of approximately 0.5 nm to approximately 6 nm, depending on the design and / or process requirements. In some embodiments, the thickness of the nitrided section T2 (SiON) is approximately 20% to approximately 80% of T1 or approximately 30% to 50% of T1. In some embodiments, the interface between the nitrided section (SiON) and a non-nitrided section (silicon oxide) is located at a position where the nitrogen concertation is 1 / e (e: Euler's number) of the nitrogen concentration at the surface of the nitrided section, or at a position where the nitrogen concertation is below the detection limit of secondary ion mass spectrometry (SIMS). In some embodiments, the thickness T3 of the gate dielectric layer on the side wall of the channel region 22 is in a range of about 0.5 nm to about 6 nm, depending on the design and / or process requirements.In some embodiments, T1 > T3.

[0040] In some embodiments, such as in Fig. As shown in Figure 7A, the nitrogen atoms are introduced substantially uniformly into the silicon oxide gate dielectric layer. In some embodiments, the uniformity of the nitrogen concentration in the nitrided section of the gate dielectric layer (e.g., at the surface of the gate dielectric layer) is in a range of about 5% to 50% with respect to an average nitrogen concentration in the nitrided section, and in other embodiments in a range of about 10% to 25%.

[0041] In some embodiments, the nitrided gate dielectric layer 120N has a lower region with a height Hb = 5% of H1 and an upper region with a height Ht = 5% of H1, and the nitrogen concentration Cb of the lower region and the nitrogen concentration Ct of the upper region correspond to Cb / Ct of approximately 0.8 to approximately 1.0. In some embodiments, Cb / Ct is approximately 0.85 to approximately 0.95. In some embodiments, the lower end of the lower region is 5 nm from the upper surface of the insulating layer, and the upper end of the upper region corresponds to the top of the channel region 22. In some embodiments, the depth T4 of the nitrided section of the gate dielectric layer 120N formed on the side wall of the channel region 22 is about 20% to about 80% of the total thickness T3 of the gate dielectric layer 120N formed on the side wall of the channel region 22, or about 30% to about 50% of T3.

[0042] Furthermore, along the depth direction of the gate dielectric layer 120N, the nitrogen concentration gradually (e.g., monotonically) decreases from the surface to the interface between the gate dielectric layer 120N and the channel region 22. In some embodiments, the nitrogen concentration at the interface between the gate dielectric layer 120N and the channel region 22 is less than approximately 3 atomic percent and more than 0 atomic percent. The nitrided gate dielectric layer 120N is a single layer made entirely of silicon oxynitride (SiON), in which the nitrogen concentration changes gradually, and therefore differs from Bi layers made of SiN / SiO2, SiN / SiON, or SiON / SiO2, in which the nitrogen concentration changes stepwise.

[0043] In some embodiments, such as in Fig. As shown in Figure 7B, the nitrogen concentration in the nitrided gate dielectric layer 120N is higher in the upper region than in the lower region. In some embodiments, the gate dielectric layer formed on the side wall of the channel region 22 is only partially nitrided. In some embodiments, the height H2 of the nitrided portion of the gate dielectric layer formed on the side wall of the channel region 22 is approximately 15% to approximately 70% of the channel height H1 or approximately 20% to approximately 50% of the channel height H1 from the top of the channel region 22. In some embodiments, the nitrogen concentration at the interface between the gate dielectric layer 120N and the channel region 22 is less than approximately 3 atomic percent and more than 0 atomic percent.

[0044] In some embodiments, the nitrided gate dielectric layer 120N comprises a lower region with a height Hb = 5% of H1, a middle region with a height Hm = 5% of H1, and an upper region with a height Ht = 5% of H1, and the nitrogen concentration Cm of the middle region and the nitrogen concentration Ct of the upper region have a Cm / Ct ratio of approximately 0.2 to approximately 0.4. In some embodiments, Cb / Ct is approximately 0.01 to approximately 0.05. The middle region has an area of ​​±0.05 H1 above a height of 0.5 H1. In some embodiments, the nitrogen concentration in the middle region and / or the lower region of the gate dielectric layer 120N is less than approximately 3 atomic percent (and more than 0 atomic percent).

[0045] In some embodiments, the angle θ1 formed by the sidewall plane of the gate dielectric layer formed on the sidewall of the channel region 22 and the interface plane between the nitrided section and the remaining (non-nitrided) section of the gate silicon oxide layer is equal to or less than 5 degrees. In some embodiments, the angle is equal to or greater than 1 degree.

[0046] If the top surface of the silicon oxide gate dielectric layer is more heavily nitrided, this can reduce damage to the gate dielectric layer covering the upper sections of the fin structure (source / drain regions) exposed by the gate electrode etching process.

[0047] In some embodiments, such as in Fig. As shown in 7C, the nitrogen concentration of the nitrated gate dielectric layer 120N, which is formed on the side wall of the channel region 22, is essentially uniform, similar to Fig. 7A, and the nitrogen concentration of the nitrided gate dielectric layer 120B, which is formed in the upper region, is higher than in the side and lower regions. In some embodiments,

[0048] The nitrogen concentration Cb of the lower region and the nitrogen concentration Cm of the middle region meet the Cb / Cm ratio of approximately 0.8 to approximately 1.0. In some embodiments, Cb / Cm is approximately 0.85 to approximately 0.95. In some embodiments, the nitrogen concentration Cm of the middle region and the nitrogen concentration Ct of the upper region meet the Cm / Ct ratio of approximately 0.4 to approximately 0.8. In some embodiments, Cm / Ct is approximately 0.5 to approximately 0.6.

[0049] As in Fig. As shown in Figures 7A-7C, the gate dielectric layer formed on the insulating layer 30 is also nitrided. In some embodiments, the nitrogen concentration Ci of the gate dielectric layer formed on the insulating layer 30 differs from the nitrogen concentration Cm, Cb of the middle and / or lower region. In some embodiments, the nitrogen concentration Ci is about 70% to 95% of the nitrogen concentration Cm and / or Cb, and in other embodiments, the nitrogen concentration Ci is about 105% to 130% of the nitrogen concentration Cm and / or Cb. In some embodiments, the nitrogen concentration Ci is less than the nitrogen concentration Ct of the upper region. In some embodiments, the nitrogen concentration Ci is about 0.7% to 0.95% of the nitrogen concentration Ct.In some embodiments, the nitrogen concentration Ci of the gate dielectric layer formed on the insulating layer 30 increases with increasing distance from the fin structure.

[0050] As explained above, the uniformity of the nitrogen concentration in the nitrated gate dielectric layer 120N, particularly in the side section formed at the side wall of the channel region 22, can be controlled by controlling at least the gas flow ratio of N2 and NH3. In some embodiments, the radicals generated by NH3 plasma are anisotropic and the radicals generated by N2 plasma are isotropic. As the flow rate of N2 increases, the upper region of the gate dielectric layer becomes more nitrated than the lower region. Fig. Figure 8 shows nitrogen concentrations along the vertical direction (along the side wall of channel region 22) of the nitrided gate dielectric layer with different flow ratios of NH3 / (N2+NH3). Fig. 8 corresponds to embodiment 1 in the case where the flow ratio of NH 3 / (N2+NH3) 0.8-1.0, embodiment 2 corresponds to the case where the flow ratio of NH 3 / (N2+NH3) 0.4-0.6, and embodiment 3 corresponds to the case where the flow ratio of NH 3 / (N2+NH3) is approximately 0.3.

[0051] In some embodiments, the flow ratio of NH 3 / (N2+NH3) is changed during the nitriding process of the gate dielectric layer. In some embodiments, a first nitriding process is carried out with a high flow ratio of NH. 3 / (N2+NH3) is carried out similarly to embodiment 1 or 2, and then a second nitration process is carried out with a lower flow ratio similarly to embodiment 2 or 3, or vice versa. In some embodiments, the flow ratio of NH 3 / (N2+NH3) gradually changed during the nitration process.

[0052] In some embodiments, the nitriding process of the gate dielectric layer comprises a plasma process using a plasma processing unit 1000, which is located in Fig. 9A is shown. Fig. Figure 9B shows a pulsed bias plasma process according to embodiments of the present disclosure. In some embodiments, the substrate 10, on which the fin structures, the insulating layer, and the gate dielectric layers are formed, is placed on a wafer platform 1100 of a vacuum chamber, and the substrate 10 and / or the wafer platform 1100 are biased, for example, with a DC voltage. RF power (transformer-coupled plasma power (TCP power)) is applied to a counter electrode 1200, which is a coil that, in some embodiments, is arranged above or around the vacuum chamber.

[0053] During a plasma nitriding process, a DC bias voltage is applied to a wafer platform 1100 and RF power is applied to a TCP electrode. In a TCP plasma, a coil electrode 1200 is placed above or around a plasma nitriding chamber and RF power is applied to the coil electrode 1200. In a pulsed bias process, the bias voltage is applied as a pulse, as in Fig. 9B is shown, while the RF voltage power is constant.

[0054] In some embodiments, the high (or ON) value of the pulsed DC bias (V1) is in a range of approximately 100 V to approximately 900 V, and in other embodiments, it is in a range of approximately 200 V to approximately 400 V. In some embodiments, the low value of the DC bias is zero (OFF). In some embodiments, the RF voltage power is in a range of approximately 400 W to approximately 1200 W, and in other embodiments, it is in a range of approximately 600 W to 1000 W.

[0055] In some embodiments, the frequency (1 / (one cycle)) of the pulsed bias is in a range of about 200 Hz to about 8000 Hz, and in other embodiments it is in a range of about 1000 Hz to about 4000 Hz.

[0056] The pulse ratio (on / off cycle ratio) varies between approximately 10% and 80% in some embodiments, and between approximately 20% and 60% in others. The pulse ratio can be any two values ​​between 10%, 20%, 30%, 40%, 50%, 60%, 70%, and 80%.

[0057] As explained above, the process gas NH3 and / or N2 is introduced from the gas supply and the nitration process is carried out accordingly.

[0058] Fig. Figure 10A shows a schematic view of a directed plasma processing device according to an embodiment of the present disclosure. Fig. 10B, Fig. 10C and Fig. Figure 10D shows schematic views of directed plasma processes according to embodiments of the present disclosure.

[0059] As in Fig. As shown in Figure 10A, the directed plasma processing device, for example a directed nitriding device 2000, comprises a main chamber 2010 in which a wafer platform 2030 for a wafer to be processed is arranged, and a plasma generation chamber 2020 for generating plasma. In some embodiments, the plasma is RF (radio frequency) generated plasma, using a radio frequency power supply at 13.56 MHz and / or 2.45 GHz. Other frequency ranges may be used. A partition plate 2026 is arranged between the main chamber 2010 and the plasma chamber 2020. The partition plate 2026 has a slot 2022 from which plasma jets 2100 are introduced into the main chamber. In some embodiments, an adjustable meniscus 2024 is provided above the slot 2022 on the plasma chamber side.One or more vacuum systems 2040, which may include a turbomolecular pump, are coupled to the main chamber and the plasma chamber (not shown) to maintain reduced pressure conditions in the chambers. In some embodiments, the pressure in the main chamber is lower than the pressure in the plasma chamber during the nitration process.

[0060] In some embodiments, the separating plate 2026 and the wafer platform 2030 are each biased by DC voltage to extract and control the plasma jets 2100, respectively. Furthermore, the wafer platform 2030 is movable relative to the plasma jets 2100 by a movement mechanism 2035 to scan the wafer.

[0061] In some embodiments, at least one of the RF and DC bias voltages is tuned to achieve an electric field that causes radicals (N-radicals) to flow substantially horizontally along a direction in the plane (for example, in the X-direction) relative to a surface above the substrate, or to provide a large angle of incidence. In some embodiments, the radicals are tuned to exhibit a momentum profile of the energy species such that the momentum of the radicals or energy species along a front line are not the same, i.e., the momentum of radicals on the upper path differs from the momentum of radicals on the lower path.In some embodiments, the momentum of radicals on the upper path differs from the momentum of radicals in the middle path above the lower path, and the momentum of radicals on the upper path is the same as, or differs from, the momentum of radicals on the lower path. All combinations can be achieved by adjusting the electromagnetic control to match the energies of the radicals.

[0062] In some embodiments, such as in Fig. 10B and Fig. As shown in Figure 10C, the position of the meniscus 2024 is adjusted to change the angle of incidence θi of the plasma beams 2100. As shown in Fig. As shown in Figure 10D, a notch pattern can be formed by scanning the wafer along the X direction without significantly widening the notch in the Y direction.

[0063] In some embodiments, the ratio of the degree of nitriding in the X-direction to the degree of nitriding in the Y-direction is approximately 2 or more, and in other embodiments, it is approximately 5 or more. In certain embodiments, the ratio is approximately 10 or more. Ideally, the ratio is as high as possible, but in some embodiments, it can be as high as approximately 100, and in others, as low as approximately 50. Furthermore, the degree of nitriding along the Z-direction (vertical direction) is less than the degree of nitriding in the X-direction. In some embodiments, the ratio of the degree of nitriding in the X-direction to the degree of nitriding in the Z-direction is approximately 2 or more, and in other embodiments, it is approximately 5 or more. In certain embodiments, the ratio is approximately 10 or more.Ideally, the ratio is as high as possible, but in some embodiments it can be up to about 100 and in other embodiments up to about 50.

[0064] As described above, the process gas NH3 and / or N2 is introduced from the gas supply and the nitration process is carried out accordingly. In some embodiments, the directed plasma jet 2100 is applied to the top and side walls of the channel region of the fin structures (e.g., along the X-direction of Fig. 4B applied). By setting or dynamically changing the angle θi of the plasma jets 2100 during the nitration process, different nitration profiles can be achieved, as in Fig. 7A-7C shows how to obtain the following. For example, a large angle θi forms a nitriding profile similar to... Fig. 7B and a small angle θi form the nitriding profile similarly Fig. 7A.

[0065] The various embodiments or examples described herein offer several advantages over the prior art. In the embodiments of the present disclosure, it is possible to control the nitrogen profile in the nitrided silicon oxide gate dielectric layer by adjusting the gas flow ratio of N₂ and NH₃. Compared with thermal nitriding, the plasma process of the present embodiments can form relatively shallow nitrided sections and can prevent problems with nitrogen accumulation at the interface between the gate dielectric layer and the channel region, which would otherwise cause threshold voltage variations. Additionally, by introducing nitrogen to the top surface of the gate dielectric layer, it is possible to improve etch resistance in the gate electrode etching process, which in turn can prevent problems of damage to the fin top surface.

[0066] It is clear that not all advantages have necessarily been discussed here, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer other advantages.

[0067] According to one aspect of the present disclosure, in a method for manufacturing a semiconductor device, a fin structure is formed by structuring a semiconductor layer, an insulating layer is formed such that an upper portion of the fin structure projects from the insulating layer, a gate dielectric layer is formed by a deposition process, a nitriding process is carried out on the gate dielectric layer, and a gate electrode layer is formed over the gate dielectric layer. The gate dielectric layer, as formed, contains silicon oxide, and the nitriding process comprises a plasma nitriding process using N₂ gas and NH₃ gas. In one or more of the preceding and following embodiments, the flow ratio NH₃ / (N₂ + NH₃) is in the range of 0.1 to 0.3.In one or more of the preceding and following embodiments, a portion of the gate dielectric layer formed on a sidewall of the upper section of the fin structure contains no nitrogen or contains nitrogen in an amount of less than 3 atomic percent. In one or more of the preceding and following embodiments, an upper portion of the gate dielectric layer formed on a top surface of the upper section of the fin structure and an upper side surface of the gate dielectric layer continuously from the upper portion to a distance below the top surface of the upper section of the fin structure contain nitrogen in an amount of 20 to 40 atomic percent, the distance being 15% of the height of the upper section of the fin structure from an upper surface of the insulating layer.In one or more of the preceding and following embodiments, the angle between an interface between a nitrided portion of the gate dielectric layer and a non-nitrided portion of the gate dielectric layer and a side wall of the gate dielectric layer is 1 to 5 degrees. In one or more of the preceding and following embodiments, the nitrogen concentration at an interface between the gate dielectric layer and the upper portion of the fin structure after the nitriding process is less than 3 atomic percent. In one or more of the preceding and following embodiments, a portion of the gate dielectric layer formed on the insulating layer is also nitrided. In one or more of the preceding and following embodiments, the process temperature of the nitriding process is in the range of 50 °C to 450 °C.In one or more of the preceding and following embodiments, the nitriding process duration is in the range of 20 sec to 150 sec.

[0068] According to another aspect of the present disclosure, in a method for manufacturing a semiconductor device, a fin structure is formed by structuring a semiconductor layer, an insulating layer is formed such that an upper portion of the fin structure projects from the insulating layer, a gate dielectric layer is formed by a deposition process, a nitriding process is carried out on the gate dielectric layer, and a gate electrode layer is formed over the gate dielectric layer. The gate dielectric layer, as formed, contains silicon oxide, the nitriding process comprises a plasma nitriding process using one or more N₂ gases and an NH₃ gases, and the flow ratio NH₃ / (N₂ + NH₃) is in the range of 0.4 to 1.0. In one or more of the preceding and following embodiments, the flow ratio is in the range of 0.8 to 0.95.In one or more of the preceding and following embodiments, an entire surface of the gate dielectric layer is nitrided. In one or more of the preceding and following embodiments, the nitrogen concentration of the gate dielectric layer after the nitriding process is greater in an upper region of the gate dielectric layer than in a lower region of the gate dielectric layer. In one or more of the preceding and following embodiments, the nitrogen concentration at an interface between the gate dielectric layer and the upper portion of the fin structure after the nitriding process is less than 3 atomic percent.In one or more of the preceding and following embodiments, the depth of a nitrided section of the gate dielectric layer formed on a sidewall of the upper section of the fin structure is 20% to 80% of the thickness of the gate dielectric layer formed on the sidewall of the upper section of the fin structure. In one or more of the preceding and following embodiments, the gate dielectric layer after the nitriding process is a single layer in which a nitrogen concentration varies along a thickness direction.

[0069] According to another aspect of the present disclosure, in a method for manufacturing a semiconductor device, a fin structure is formed by structuring a semiconductor layer, an insulating layer is formed such that an upper portion of the fin structure projects from the insulating layer, a gate dielectric layer is formed by a deposition process, a nitriding process is carried out on the gate dielectric layer, and a gate electrode layer is formed over the gate dielectric layer. The nitriding process comprises a plasma nitriding process using one or more N₂ gases and an NH₃ gases, and the flow ratio NH₃ / (N₂ + NH₃) varies during the nitriding process. In one or more of the preceding and following embodiments, the flow ratio varies gradually.In one or more of the preceding and following embodiments, the flow ratio varies stepwise by two or more steps. In one or more of the preceding and following embodiments, the nitriding process includes directed plasma nitriding.

[0070] According to another aspect of the present disclosure, a semiconductor device comprises a semiconductor fin structure arranged over a substrate and having a channel region, an insulating layer from which the channel region projects, a gate dielectric layer arranged over the channel region, and a gate electrode arranged over the gate dielectric layer. The gate dielectric layer contains silicon oxide that is only partially nitrided. In one or more of the preceding and following embodiments, a portion of the gate dielectric layer formed on a side wall of the channel region contains no nitrogen or contains nitrogen in an amount of less than 3 atomic percent.In one or more of the preceding and following embodiments, an upper portion of the gate dielectric layer formed on a top surface of the channel region and an upper side portion of the gate dielectric layer continuously contain nitrogen in an amount of 20 to 40 atomic percent from the upper portion to a distance below the top surface of the channel region, wherein the distance is 15 percent of the height of the channel region from a top surface of the insulating layer. In one or more of the preceding and following embodiments, the angle between an interface between a nitrided portion of the gate dielectric layer and a non-nitrided portion of the gate dielectric layer and a side wall of the gate dielectric layer is 1 to 5 degrees.In one or more of the preceding and following embodiments, the nitrogen concentration at a middle side portion below the upper side portion of the gate dielectric layer, which is located on the side wall of the channel region, is lower than that of the upper side portion. In one or more of the preceding and following embodiments, the nitrogen concentration of the middle side portion is less than 3 atomic percent. In one or more of the preceding and following embodiments, the nitrogen concentration at an interface between the gate dielectric layer and the channel region is less than 3 atomic percent. In one or more of the preceding and following embodiments, a horizontal portion of the gate dielectric layer formed on the insulating layer contains nitrogen.In one or more of the preceding and following embodiments, the amount of nitrogen in the horizontal part is less than the amount of nitrogen in an upper part of the gate dielectric layer formed on a top side of the channel region.

[0071] According to another aspect of the present disclosure, a semiconductor device comprises a semiconductor fin structure arranged over a substrate and having a channel region, an insulating layer from which the channel region projects, a gate dielectric layer arranged over the channel region, and a gate electrode arranged over the gate dielectric layer. The gate dielectric layer has a nitrided silicon oxide section and a silicon oxide section arranged between the nitrided silicon oxide section and the channel region, and the nitrogen concentration in the nitrided silicon oxide section is uniform between 10% and 25% with respect to an average nitrogen concentration in the nitrided silicon oxide section.In one or more of the preceding and following embodiments, the nitrogen concentration of the gate dielectric layer in an upper region of the gate dielectric layer is greater than the nitrogen concentration in a lower region of the gate dielectric layer. In one or more of the preceding and following embodiments, the depth of a nitrided silicon oxide section located on a side wall of the channel region is 20% to 80% of the thickness of the gate dielectric layer located on the side wall of the channel region. In one or more of the preceding and following embodiments, the nitrogen concentration in the nitrided silicon oxide section gradually decreases from a surface to the silicon oxide section.In one or more of the preceding and following embodiments, the nitrogen concentration in the nitrated silicon oxide section of the gate dielectric layer, which is arranged on a side wall of the channel region, gradually decreases from a top side of the gate dielectric layer to a bottom side of the gate dielectric layer.

[0072] According to another aspect of the present disclosure, a semiconductor device comprises a semiconductor fin structure arranged over a substrate and having a channel region, an insulating layer from which the channel region projects, a gate dielectric layer arranged over the channel region, a gate electrode arranged over the gate dielectric layer, and a gate sidewall spacer arranged on a sidewall of the gate electrode. The gate dielectric layer has the composition SiO₂. 2-x N x, where x is 0.01 to 0.2. In one or more of the preceding and following embodiments, the gate dielectric layer has an upper section located on a top surface of the channel region and a side section located on a side wall of the channel region, and the nitrogen concentration of the upper section differs from that of the side section. In one or more of the preceding and following embodiments, the side section has an upper side section, a middle side section below the upper side section, and a lower side section below the middle side section, and the nitrogen concentration of the upper side section differs from that of at least one of the nitrogen concentrations of the middle side section or the lower side section.In one or more of the preceding and following embodiments, the nitrogen concentration of the middle side section differs from the nitrogen concentration of the lower side section. In one or more of the preceding and following embodiments, the nitrogen concentration of the lower side section is 0.85 to 0.95 times the nitrogen concentration of the upper side section. In one or more of the preceding and following embodiments, the nitrogen concentration at an interface between the gate dielectric layer and the channel region is less than 3 atomic percent.

Claims

[1] Method for manufacturing a semiconductor device comprising the method: Forming a fin structure (20) by structuring a semiconductor layer (10); Forming an insulating layer (30) such that an upper section of the fin structure (20) protrudes from the insulating layer (30); Formation of a gate dielectric layer (120) by a deposition process; After the gate dielectric layer (120) has been formed, nitrogen is introduced into the gate dielectric layer (120); and Forming a gate electrode layer (40) over the gate dielectric layer (120), wherein the gate dielectric layer (120), as it is formed, is silicon oxide, where: the introduction of nitrogen involves a plasma nitriding process using an N2 gas and an NH3 gas and a flow ratio NH3 / (N2 + NH3) in a range of 0.1 to 0.3, wherein a part of the gate dielectric layer (120) formed on a side wall of the upper section of the fin structure (20) contains no nitrogen or contains nitrogen in an amount less than 3 atomic %. [2] Method according to claim 1, wherein an upper part of the gate dielectric layer (120) formed on a top surface of the upper section of the fin structure (20) and a side part of the gate dielectric layer (120) continuously contain nitrogen in an amount of 20 to 40 atomic % from the upper part to a distance below the top surface of the upper section of the fin structure (20), wherein the distance is 15 % of a height of the upper section of the fin structure (20) from an upper surface of the insulating insulating layer (30). [3] Method according to claim 2, wherein an angle between an interface between a nitrided section of the gate dielectric layer (120) and a non-nitrided section of the gate dielectric layer (120) and a side wall of the gate dielectric layer (120) is 1 degree to 5 degrees. [4] Method according to any one of the preceding claims 1 to 3, wherein a nitrogen concentration at an interface between the gate dielectric layer (120) and the upper part of the fin structure (20) after the nitration process is less than 3 atomic %. [5] Method according to any one of the preceding claims 1 to 4, wherein a part of the gate dielectric layer (120) formed on the insulating insulating layer (30) is also nitrided. [6] Method according to any one of the preceding claims 1 to 5, wherein the process temperature of the nitration process is in a range of 50 °C to 450 °C. [7] Method according to claim 6, wherein the process duration of the nitriding process is in the range of 20 sec to 150 sec. [8] Method for manufacturing a semiconductor device comprising the method: Forming a fin structure (20) by structuring a semiconductor layer (10); Forming an insulating layer (30) such that an upper section of the fin structure (20) protrudes from the insulating layer (30); Formation of a gate dielectric layer (120) over the fin structure (20) by a deposition process; Performing a nitriding process on the gate dielectric layer (120); and Forming a gate electrode layer (40) over the gate dielectric layer (120), wherein: the gate dielectric layer (120), as it is formed, contains silicon oxide, the nitration process comprises a plasma nitration process using one or more of N2 gas and NH3 gas and a flow ratio NH3 / (N2 + NH3) in a range of 0.4 to 1.0, wherein a nitrogen concentration at an interface between the gate dielectric layer (120) and the upper section of the fin structure (20) after the nitration process is less than 3 atomic %. [9] Method according to claim 8, wherein the flow ratio is in a range of 0.8 to 0.

95. [10] Method according to claim 8 or 9, wherein an entire outer surface of the gate dielectric layer (120) is nitrided. [11] Method according to any one of the preceding claims 8 to 10, wherein a nitrogen concentration of the gate dielectric layer (120) after the nitration process is greater in an upper region of the gate dielectric layer (120) than a nitrogen concentration in a lower region of the gate dielectric layer (120). [12] Method according to any one of claims 8 to 11 above, wherein the depth of a nitrided section of the gate dielectric layer (120) formed on a side wall of the upper section of the fin structure (20) is 20% to 80% of the thickness of the gate dielectric layer (120) formed on the side wall of the upper section of the fin structure (20). [13] Method according to any one of claims 8 to 12 above, wherein the gate dielectric layer (120) after the nitriding process is a single layer in which a nitrogen concentration varies along a thickness direction. [14] Semiconductor device comprising: a semiconductor fin structure (20) arranged over a substrate (10) and containing a channel region; an insulating insulating layer (30) from which the canal area protrudes; a gate dielectric layer (120) arranged over the channel region; and a gate electrode (40) arranged above the gate dielectric layer (120), wherein: the gate dielectric layer (120) contains silicon oxide that is only partially nitrided, wherein a part of the gate dielectric layer (120) formed on a side wall of the channel region contains no nitrogen or contains nitrogen in an amount less than 3 atomic %. [15] Semiconductor device according to claim 14, wherein an upper part of the gate dielectric layer (120) formed on a top surface of the channel region and an upper side part of the gate dielectric layer (120) continuously contain nitrogen in an amount of 20 to 40 atomic percent from the upper part to a distance below the top surface of the channel region, wherein the distance is 15 percent of a height of the channel region from an upper surface of the insulating insulating layer (30). [16] Semiconductor device according to claim 15 , wherein an angle between an interface between a nitrided section of the gate dielectric layer (120) and a non-nitrided section of the gate dielectric layer (120) and a side wall of the gate dielectric layer (120) is 1 degree to 5 degrees.

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