Circuit arrangement for the galvanically isolated transmission of electrical energy to two outputs

Abstract

Circuit arrangement for the galvanically isolated transmission of electrical energy from a primary side to a secondary side, - wherein a number of secondary circuits (3) are arranged on the secondary side, - wherein the secondary circuits (3) each comprise a secondary winding (12) of a transformer (1) which is connected to a first and a second output (14, 15) of the respective secondary circuit (3) at which, with reference to a respective secondary-side ground (13), a first and a second output voltage (U1, U2) are provided, - wherein a first diode (16) is arranged between the respective secondary winding (12) and the respective first output (14) and a second diode (17) is arranged between the respective secondary winding (12) and the respective second output (15), - wherein on the primary side a respective control input of a first and a second semiconductor switch (8, 10) is connected to a control device (11) by which the first and the second semiconductor switch (8, 10) are switched at a common operating frequency (f), such that during a period (T) corresponding to the operating frequency (f) the first semiconductor switch (8) is switched on for a first period (T1) and the second semiconductor switch (10) is switched on for a second period (T2), - wherein on the primary side a series connection of a primary winding (4) of the transformer (1) coupled to the secondary windings (12) of the secondary circuits (3) and a capacitor (5) is connected on one side to a primary-side ground (6) and on the other side to a primary-side node (7), - wherein the node (7) is connected on the one hand via the first semiconductor switch (8) to a voltage source (9) providing a primary-side supply voltage (U0) and on the other hand via the second semiconductor switch (10) to the primary-side ground (6), characterized in that - the primary winding (4) is connected to the primary-side node (7) and the capacitor (5) is connected to the primary-side ground (6), - that a capacitor voltage (UC) is tapped and supplied to the control unit (11) and - that the control device (11) is designed in such a way that it takes into account the tapped capacitor voltage (UC) when determining the ratio (α) of the first period (T1) to the second period (T2).

Description

[0001] The present invention relates to a circuit arrangement for the galvanically isolated transmission of electrical energy from a primary side to a secondary side, - wherein a number of secondary circuits are arranged on the secondary side, - wherein the secondary circuits each comprise a secondary winding of a transformer connected to a first and a second output of the respective secondary circuit, at which, with respect to a respective secondary-side ground, a first and a second output voltage are provided, - wherein a first diode is arranged between the respective secondary winding and the respective first output, and a second diode is arranged between the respective secondary winding and the respective second output, - wherein on the primary side a respective control input of a first and a second semiconductor switch is connected to a control device by which the first and the second semiconductor switches are switched at a common operating frequency, such that during a period corresponding to the operating frequency the first semiconductor switch is switched on for a first period and the second semiconductor switch is switched on for a second period - wherein on the primary side a series connection of a primary winding of the transformer coupled to the secondary windings of the secondary circuits and a capacitor is connected on the one hand to a primary-side ground and on the other hand to a primary-side node, - wherein the node is connected on the one hand to a voltage source providing a primary-side supply voltage via the first semiconductor switch and on the other hand to the primary-side ground via the second semiconductor switch.

[0002] The number of secondary circuits can vary depending on requirements. A minimum of one secondary circuit is present. However, multiple secondary circuits are often present.

[0003] Such a circuit arrangement is known, for example, from DE 10 2005 001 322 A1.

[0004] From DE 10 2010 001 322 A1, a circuit arrangement for the galvanically isolated transmission of electrical energy from a primary side to a secondary side is known, in which a primary-side voltage supply is connected to a center tap of the primary winding on the primary side, such that the primary winding is divided by the center tap into a first winding section and a second winding section. The ends of the primary winding are connected to a primary-side ground via the first and second semiconductor switches. The ratio of the two output voltages is determined by the ratio of the two winding sections. Furthermore, the two semiconductor switches must also be controlled in this ratio.

[0005] The solution known from DE 10 2010 001 322 A1 is rigid. Changing the desired ratio of the two output voltages necessitates altering the primary winding's configuration, which ultimately requires replacing or at least modifying the primary winding. Furthermore, the leakage inductance of each winding section of the primary winding forms a resonant circuit with the parasitic capacitance of the respective semiconductor switch, resulting in uncontrolled oscillations in the now high-impedance inductor after each switching operation. These oscillations complicate compliance with emission standards, which are required for electromagnetic compatibility. Additionally, the primary winding's configuration, necessitated by the center tap, incurs further costs.

[0006] In the circuit known from DE 10 2005 001 322 A1, these problems are solved in principle. However, it is not easily possible to guarantee that the desired output voltages are actually set.

[0007] The object of the present invention is to create possibilities by means of which the disadvantages of the prior art can be avoided.

[0008] The problem is solved by a circuit arrangement having the features of claim 1. Advantageous embodiments of the circuit arrangement are the subject of dependent claims 2 to 10.

[0009] According to the invention, a circuit arrangement of the type mentioned above is designed by: - that the primary winding is connected to the primary-side node and the capacitor is connected to the primary-side ground, - that a capacitor voltage is tapped and supplied to the control unit and - that the control device is designed in such a way that it takes the tapped capacitor voltage into account when determining the ratio of the first period to the second period.

[0010] This results in several advantages.

[0011] Due to the first characteristic, the sequence consists of nodes. - Primary winding - capacitor - primary ground. This is more advantageous than a sequence node - capacitor. - Primary winding - primary-side ground. This reduces the remaining alternating fields radiated by the circuit arrangement. Furthermore, tapping the capacitor voltage is simplified. The tapped voltage is already referenced to ground and can therefore be used directly without the need for a differential amplifier or other galvanically isolated measurement. By considering the tapped capacitor voltage, any switching times of the semiconductor switches, which could (slightly) distort the ratio of the two output voltages, can be taken into account when controlling the semiconductor switches (i.e., when determining the first and second time periods). Alternatively, it can be ensured that one of the two output voltages is regulated (add: exactly) to its target value.

[0012] Because only a single, unified primary winding is required—that is, a primary winding without a center tap and therefore without division into winding sections—the circuit arrangement according to the invention can be operated flexibly. To change the ratio of the two output voltages to each other, only the ratio of the two time periods during which the first and second semiconductor switches are on needs to be adjusted. Furthermore, when a semiconductor switch is turned off, the inductance of the primary winding causes a corresponding recharging of the parasitic capacitance of that switch. This recharging occurs (almost) without loss. Since the other semiconductor switch is usually turned on immediately after the first one is turned off, oscillations are also avoided, thus facilitating and simplifying compliance with emission standards.

[0013] Preferably, the control unit sets a ratio of the first period to the second period depending on a ratio of a setpoint for the first output voltage to a setpoint for the second output voltage, or depending on a ratio of a setpoint for the first output voltage to a setpoint for the supply voltage. The control unit can be provided with the setpoints of the two output voltages, their ratio, the ratio of the first period to the second period directly, or the setpoint of one of the two output voltages and the setpoint of the supply voltage, as required.

[0014] In the simplest case, the ratio of the first period to the second period corresponds directly to the ratio of the setpoints of the two output voltages, or to the ratio of the setpoint of one of the two output voltages to the setpoint of the supply voltage, scaled by the transformer's turns ratio. However, even better results are achieved with a design in which the current flowing in the primary winding is measured using a measuring device, and the corresponding measured value is supplied to the control unit. For this to work, the control unit must take the measured current value into account when determining the ratio of the first period to the second period.In particular, the control unit can determine the voltage losses occurring, taking into account the operating frequency and the stray inductance of the transformer, and compensate for them by appropriately adjusting the control of the two semiconductor switches.

[0015] When the two output voltages have the same polarity, their sum is determined by the supply voltage and the transformer's turns ratio; when they have different polarities, their difference is determined by the supply voltage. Preferably, the control unit adjusts the primary-side supply voltage by appropriately controlling the voltage source, based on the sum of the magnitudes of a setpoint for the first output voltage and the magnitudes of a setpoint for the second output voltage. This ensures that, depending on the sign of the two output voltages, the sum or difference of the two output voltages has the desired value. In conjunction with setting the desired ratio between the two output voltages, the absolute values ​​of both output voltages can also be adjusted.As a result, by appropriately adjusting the supply voltage on the one hand and the ratio of the first period to the second period, both the first output voltage and the second output voltage can be individually adjusted to their respective target values.

[0016] Preferably, the supply voltage is also tapped and fed to the control unit. In this case, the control unit takes the tapped supply voltage into account when determining the control signal for the voltage source. This avoids any errors caused by a faulty or inaccurate supply voltage. Suitable controllable voltage sources are generally known to experts. A boost converter and a buck converter can be mentioned as examples.

[0017] As mentioned earlier, multiple secondary circuits are often present. This means that several secondary windings are coupled to the same primary winding, each providing a first and a second output voltage. As a result, when the control unit is switched on, all involved secondary circuits often initially exhibit a relatively high energy demand. Simultaneous rapid charging of, for example, buffer capacitors in all involved secondary circuits can therefore lead to an overload of the primary side. To avoid such an overload, the control unit can alternately switch the two semiconductor switches immediately after being switched on, during a first and second period, and these two periods already have the correct ratio, but with relatively low initial values ​​in absolute terms.At a later point, when the secondary circuits are fully or at least partially charged, the control unit can increase the absolute values ​​of both time periods to larger final values ​​while maintaining the desired ratio between them. The ratio of the first period to the second period is thus kept constant during the transition from the initial to the final values ​​of the two time periods. The increase in the time periods can be abrupt. Preferably, it occurs gradually.

[0018] To reliably prevent a short circuit between the supply voltage and the primary-side ground, the first and second time periods must always be separated by dead times during which neither the first nor the second semiconductor switch is closed. The control unit can reduce at least one of these dead times to increase the first time period from its initial value to its final value and the second time period from its initial value to its final value. Usually, the dead times are reduced to their minimum possible or permissible values. Alternatively, the control unit can reduce the operating frequency to increase the first time period from its initial value to its final value and the second time period from its initial value to its final value. Combinations of these two measures are also possible.

[0019] Often, the respective output voltages, relative to their respective secondary-side grounds, should have different polarities. This can be easily achieved by... - one end of each secondary winding is directly connected to the respective secondary-side ground, and the other end of each secondary winding is connected via the respective first diode to the respective first output and via the respective second diode to the respective second output and - the respective first diode and the respective second diode are connected antiparallel to each other.

[0020] However, it is also possible that the respective output voltages, relative to their respective secondary-side grounds, have the same polarity. This can be easily achieved by... - one end of the respective secondary winding is connected via the respective first diode to the respective first output and via a respective third diode to the respective secondary-side ground, - the other end of the respective secondary winding is connected via the respective second diode to the respective second output and via a respective fourth diode to the respective secondary-side ground and - the respective first, second, third and fourth diodes are all polarized in the same switching direction.

[0021] Further advantages and details will become apparent from the following description of exemplary embodiments in conjunction with the drawings. These show, in schematic principle representation: Fig. 1 a block diagram of a circuit arrangement, Fig. 2 a time diagram, Fig. 3 a primary circuit, Fig. 4 a time diagram, Fig. 5 another time diagram, Fig. 6 another time diagram, Fig. 7 a secondary circuit and Fig. 8 another secondary circuit.

[0022] The in Fig. The circuit arrangement shown in Figure 1 serves for the galvanically isolated transmission of electrical energy from a primary side to a secondary side. For this purpose, a transformer 1 is provided, which effects the galvanic isolation. The transformer 1 divides the circuit arrangement into a primary circuit 2 located on the primary side and a secondary circuit 3 located on the secondary side.

[0023] The primary circuit 2 comprises a primary winding 4 of the transformer 1 and a capacitor 5. The primary winding 4 and the capacitor 5 are connected in series. The series connection of the primary winding 4 and the capacitor 5 is connected on one side to a primary-side ground 6 and on the other side to a primary-side junction 7. The connections are as shown in the diagram. Fig. 1 the primary winding 4 is connected to the primary-side node 7 and the capacitor 5 to the primary-side ground 6.

[0024] Junction 7 is connected to a voltage source 9 via a first semiconductor switch 8 (e.g., a MOSFET). Voltage source 9 provides a primary-side supply voltage U0, referenced to primary-side ground 6. The supply voltage U0 is a DC voltage. Junction 7 is also connected to primary-side ground 6 via a second semiconductor switch 10 (e.g., also a MOSFET). Both semiconductor switches 8 and 10 have a control input. The two control inputs are connected to a control device 11.

[0025] The control device 11 can, for example, be configured as a software-programmable control device 11. In this case, the operation or configuration of the control device 11 is determined by a control program (not shown) with which the control device 11 is programmed.

[0026] Regardless of the specific method of implementation of the control unit 11 (e.g., hardwired or software-programmed), the control unit 11 switches according to the representation in Fig. 2. The two semiconductor switches 8, 10 as a function of time t. The control device 11 switches the two semiconductor switches 8, 10 with a common operating frequency f, such that the state of the two semiconductor switches 8, 10 changes with a corresponding period T = 1 / f. In particular, the control device 11 switches the first semiconductor switch 8 such that it is switched on during the respective period T for a first period T1. Likewise, the control device 11 switches the second semiconductor switch 10 such that it is switched on during the respective period T for a second period T2. However, at any given time, at most one of the two semiconductor switches 8, 10 is switched on. Thus, there is no time at which both semiconductor switches 8, 10 are switched on simultaneously. Specifically, the periods T1, T2 are separated in particular by (usually relatively small) dead times T3, T4.During the dead times T3, T4, neither of the two semiconductor switches 8, 10 is switched on.

[0027] The secondary circuit 3 comprises a secondary winding 12 of the transformer 1. The secondary winding 12 is coupled to the primary winding 4. The secondary winding 12 is connected on one side to a secondary-side ground 13. On the other side, the secondary winding 12 is connected to a first and a second output 14, 15 of the secondary circuit 3. A first and a second output voltage U1, U2 are provided at the outputs 14, 15. The two output voltages U1, U2 are referenced to the secondary-side ground 13. A first diode 16 is arranged between the secondary winding 12 and the first output 14. Likewise, a second diode 17 is arranged between the secondary winding 12 and the second output 15.

[0028] In the design according to Fig. One end of the secondary winding 12 is directly connected to the secondary ground 13, while the other end of the secondary winding 12 is connected via the first diode 16 to the first output 14 and via the second diode 17 to the second output 15. Furthermore, the two diodes 16 and 17 are connected antiparallel to each other. As a result, the two output voltages U1 and U2 have opposite polarities relative to the secondary ground 13. Specifically, due to the polarity of the two diodes 16 and 17, the first output voltage U1 is greater than zero, while the second output voltage U2 is less than zero. Capacitors 18 and 19 are usually also present. These capacitors serve to smooth and stabilize the output voltages U1 and U2.

[0029] The two output voltages U1 and U2 are determined (neglecting losses) by the supply voltage U0, the turns ratio k of transformer 1, and the two time intervals T1 and T2. Specifically, the following relationships apply: |U1|+|U2|=kU0 and |U1T2|−|U2T1|=0.

[0030] The supply voltage U0 is generally fixed or at least known to the control unit 11. The control unit 11 can therefore set a ratio α of the first period T1 to the second period T2, for example, depending on a ratio of a setpoint U1* for the first output voltage U1 to a setpoint U2* for the second output voltage U2. It is almost equivalent if the control unit 1 sets the ratio α of the first period T1 to the second period T2 depending on a ratio of the setpoint U1* for the first output voltage U1 to a setpoint U0* for the supply voltage U0. The setpoint U0* for the supply voltage U0 results from the setpoints U1*, U2* for the first and second output voltages U1, U2 and the turns ratio k of the transformer 1: |U1*|+|U2*|=kU0*.

[0031] The circuit arrangement described above represents a minimal configuration. This minimal configuration can be designed in various ways. For example, several secondary circuits 3 can be arranged on the secondary side. However, the secondary circuits 3 are identical to each other. Fig. Figure 1 therefore shows only a single secondary circuit 3. The following explanations also refer to the configuration in which only a single secondary circuit 3 is present. If several secondary circuits 3 are present, this does not result in any fundamental changes. Furthermore, the primary circuit 2 can be configured in various ways. Possible configurations of the primary circuit 2 are explained below in conjunction with the other figures.

[0032] Fig. 3 shows a design in contrast to that of Fig. 1. Modified primary circuit. 2. The secondary circuit 3 is unchanged. It is therefore only shown schematically. Furthermore, it shows Fig. Three advantageous configurations can be combined. However, the advantageous configurations can be implemented independently of each other.

[0033] According to Fig. 3. A capacitor voltage UC is tapped, which drops across capacitor 5. For example, a tap point 20 can be arranged between the primary winding 4 and capacitor 5 to tap the capacitor voltage UC. The tapped capacitor voltage UC is supplied to the control unit 11. The control unit 11 can therefore take the tapped capacitor voltage UC into account when determining the ratio α of the first period T1 to the second period T2. For example, the control unit 11 can use this ratio for the period T1 to the second period T2. Fig. 3 Primary circuit 2 shown based on the relationship UC*=(1−β)U0* Determine a target value for the capacitor voltage UC. β is the ratio of the first period T1 to the sum of the two periods T1 and T2. The ratio β, i.e., the ratio of the first period T1 to the sum of the two periods T1 and T2, is conceptually equivalent to the ratio α, i.e., the ratio of the first period T1 to the second period T2. In particular, the two ratios α and β can be determined using the relationship α=β / (1−β) They can be converted into one another. However, the ratio β was chosen above because it is also defined for the two limiting cases (T1 = 0 and T2 = 0). If the measured capacitor voltage UC deviates from its target value UC*, the ratio α can be adjusted, for example by adjusting the first period T1, by adjusting the second period T2, or by making opposing adjustments to the two periods T1 and T2.

[0034] Furthermore, it is possible for the control unit 11 to adjust the supply voltage U0 by appropriately controlling the voltage source 9, depending on a difference between the setpoints U1*, U2* of the two output voltages U1, U2. In particular, equation (3) provides the setpoint U0* for the supply voltage U0.

[0035] In addition to setting the supply voltage U0, the supply voltage U0 can be tapped. For example, a further tap point 21 can be arranged between the voltage source 9 and the first semiconductor switch 8 to tap the supply voltage U0. The tapped supply voltage U0 is supplied to the control unit 11. The control unit 11 can therefore take the tapped supply voltage U0 into account when determining the control signal for the voltage source 9.

[0036] Alternatively or additionally, the current I flowing in the primary winding 4 can be measured using a measuring device 22. In this case, the corresponding measured value is supplied to the control unit 11. This allows the control unit 11 to take the measured value for the current I into account when determining the ratio α and, if necessary, also when determining the control signal for the voltage source 9. This approach can be particularly useful if the leakage inductance of the transformer 1 is known to the control unit 11, so that the control unit 11 can compensate for the losses by appropriately adjusting the control signal for the semiconductor switches 8, 10 and, if necessary, also for the voltage source 9.

[0037] The following are related to the Fig. Four to six further advantageous configurations are explained. These configurations are comparable to the configurations of Fig. 3 can be combined.

[0038] As already mentioned, several secondary circuits 3 are often present. Particularly in this case – but also in principle with only a single secondary circuit 3 – it is possible that high loads occur immediately after the control unit 11 is switched on – i.e., when the control of the semiconductor switches 8, 10 begins. To reduce such excessive loads, the control unit 11 sets, according to Fig. 4. The control unit 11 initially sets the first period T1 to a first initial value T1A immediately after switching on. It then maintains this value for the time period T1. At a later time, however, the control unit 11 increases the first period T1 to a first final value T1E. This is preferably done as shown in the diagram. Fig. 4. A gradual increase. However, at every point in time, the ratio α of the first period T1 to the second period T2 remains constant. Thus, the increase of the first period T1 is accompanied by an equivalent increase in the second period T2.

[0039] To increase the time periods T1, T2, the control unit 11 can, for example, be configured as shown in Fig. 5. The operating frequency f is maintained, but initially, larger dead times T3 and T4 are used, which are later reduced. For example, immediately after switching on the control unit 11, the dead times T3 and T4 can each be 45% of period T, so that only 10% of period T is available for periods T1 and T2. Later, the control unit 11 can then gradually reduce the dead times T3 and T4 to their minimum values ​​of, for example, 1% of period T each, so that 98% of period T is available for periods T1 and T2. The numerical values ​​mentioned are, of course, purely illustrative.

[0040] Alternatively, the control unit 11 can be configured as shown in Fig. Although the control unit 11 operates with relatively small dead times T3 and T4 from the outset, it initially operates at a high operating frequency f (value fA), which it later reduces to a lower value fE. For example, the operating frequency f immediately after switching on the control unit 11 might be 1 MHz, resulting in a period T of only 1 µs. Later, the control unit 11 could gradually reduce the operating frequency f to, for example, 100 kHz, so that the period T is now 10 µs. The numerical values ​​mentioned are, of course, purely illustrative.

[0041] Furthermore, both measures can also be combined.

[0042] As already mentioned, in the secondary circuit 3 of Fig. 1. One end of the secondary winding 12 is directly connected to the secondary-side ground, while the other end of the secondary winding 12 is connected via the two diodes 16 and 17 to the two outputs 14 and 15, so that the two output voltages U1, U2, with respect to the secondary-side ground 13, have opposite polarities. However, it is also possible to configure the secondary circuit 3 in which the two output voltages U1, U2, with respect to the secondary-side ground 13, have the same polarity. The following are described in conjunction with Fig. 7 and Fig. Eight such configurations of a secondary circuit 3 are explained. These secondary circuits 3 can be – just like the secondary circuit 3 according to Fig. 1 - as required in conjunction with the primary circuit 2 of Fig. 1 or in conjunction with the primary circuit 2 of Fig. 3 can be used.

[0043] According to the Fig. 7 and Fig. 8 is one end of the secondary winding 12 connected to the first output 14 via the first diode 16.

[0044] The other end of the secondary winding 12 is connected to the second output 15 via the second diode 17. Additionally, a third diode 23 and a fourth diode 24 are present. One end of the secondary winding 12 is connected to the secondary-side ground 13 via the third diode 23, and the other end of the secondary winding 12 is connected via the fourth diode 24. All four diodes 16, 17, 23, 24 of the respective secondary circuit 3 are polarized in the same switching direction.

[0045] The difference between the secondary circuits 3 of the Fig. 7 and Fig. 8 consists of the switching direction of diodes 16, 17, 23, 24 and, correspondingly, the polarity of the two output voltages U1, U2. In the secondary circuit 3 according to Fig. 7 are (relative to the secondary-side ground 13) both output voltages U1, U2 are positive, in the secondary circuit 3 according to Fig. 8 negative.

[0046] The present invention has many advantages. In particular, it results in a simple, cost-effective design of the primary side, which is also very flexible in its operation.

[0047] The above description serves solely to explain the present invention. The scope of protection of the present invention, however, shall be determined exclusively by the accompanying claims. Reference symbol list 1 transformer 2 Primary circuit 3 Secondary circuit 4 Primary winding 5, 18, 19 capacitors 6 primary-side mass 7 Junction 8, 10 semiconductor switches 9 Voltage source 11 Control unit 12 Secondary winding 13 secondary-side mass 14, 15 exits 16, 17, 23, 24 diodes 20, 21 sampling points 22 Measuring device f Operating frequency fA, T1A Initial values fE, T1E final value k translation ratio I current T period T1, T2 periods T3, T4 dead times t time U0 Supply voltage U1, U2 output voltages U0*, U1*, U2*, UC* Setpoints UC capacitor voltage α, β ratios

Claims

[1] Circuit arrangement for the galvanically isolated transmission of electrical energy from a primary side to a secondary side, - wherein a number of secondary circuits (3) are arranged on the secondary side, - wherein the secondary circuits (3) each comprise a secondary winding (12) of a transformer (1) which is connected to a first and a second output (14, 15) of the respective secondary circuit (3) at which, with reference to a respective secondary-side ground (13), a first and a second output voltage (U1, U2) are provided, - wherein a first diode (16) is arranged between the respective secondary winding (12) and the respective first output (14) and a second diode (17) is arranged between the respective secondary winding (12) and the respective second output (15), - wherein on the primary side a respective control input of a first and a second semiconductor switch (8, 10) is connected to a control device (11) by which the first and the second semiconductor switch (8, 10) are switched at a common operating frequency (f), such that during a period (T) corresponding to the operating frequency (f) the first semiconductor switch (8) is switched on for a first period (T1) and the second semiconductor switch (10) is switched on for a second period (T2), - wherein on the primary side a series connection of a primary winding (4) of the transformer (1) coupled to the secondary windings (12) of the secondary circuits (3) and a capacitor (5) is connected on one side to a primary-side ground (6) and on the other side to a primary-side node (7), - wherein the node (7) is connected on the one hand via the first semiconductor switch (8) to a voltage source (9) providing a primary-side supply voltage (U0) and on the other hand via the second semiconductor switch (10) to the primary-side ground (6), characterized by , - the primary winding (4) is connected to the primary-side node (7) and the capacitor (5) is connected to the primary-side ground (6), - that a capacitor voltage (UC) is tapped and supplied to the control unit (11) and - that the control device (11) is designed in such a way that it takes into account the tapped capacitor voltage (UC) when determining the ratio (α) of the first period (T1) to the second period (T2). [2] Circuit arrangement according to claim 1, characterized by, that the control device (11) is designed such that it sets a ratio (α) of the first period (T1) to the second period (T2) depending on a ratio of a setpoint (U1*) for the first output voltage (U1) to a setpoint (U2*) for the second output voltage (U2) or depending on a ratio of a setpoint (U1*) for the first output voltage (U1) to a setpoint (U0*) for the supply voltage (U0). [3] Circuit arrangement according to claim 2, characterized by , that the control device (11) is designed such that it sets the primary-side supply voltage (U0) as a function of the sum of the magnitude of the setpoint (U1*) for the first output voltage (U1) and the magnitude of the setpoint (U2*) for the second output voltage (U2) by appropriately controlling the voltage source (9). [4] Circuit arrangement according to claim 1, characterized by, that the control device (11) is designed such that it sets the primary-side supply voltage (U0) as a function of a sum of the magnitude of a setpoint (U1*) for the first output voltage (U1) and the magnitude of a setpoint (U2*) for the second output voltage (U2) by appropriately controlling the voltage source (9). [5] Circuit arrangement according to claim 3 or 4, characterized by , that the supply voltage (U0) is tapped and supplied to the control unit (11) and that the control unit (11) is designed in such a way that it takes the tapped supply voltage (U0) into account when determining the control of the voltage source (9). [6] Circuit arrangement according to one of the above claims, characterized by, that the current (I) flowing in the primary winding (4) is detected by means of a measuring device (22) and a corresponding measured value is supplied to the control device (11) and that the control device (11) is designed in such a way that it takes into account the measured value for the current (I) when determining the ratio (α) of the first period (T1) to the second period (T2). [7] Circuit arrangement according to one of the above claims, characterized by, that the control device (11) is designed such that immediately after the control device (11) is switched on, it sets the first period (T1) to a first initial value (T1A) and the second period (T2) to a second initial value, and at a later time increases the first period (T1) to a first final value (T1E) and the second period (T2) to a second final value, and that the ratio (α) of the first period (T1) to the second period (T2) is kept constant during the transition of the two periods (T1, T2) from their initial values ​​(T1A) to their final values ​​(T1E). [8] Circuit arrangement according to claim 7, characterized by, that the first period (T1) and the second period (T2) are separated by dead times (T3, T4) during which neither the first nor the second semiconductor switch (8, 10) is switched on, and that the control device (11) is designed such that, in order to increase the first period (T1) from the first initial value (T1A) to the first final value (T1E) and the second period (T2) from the second initial value to the second final value, it reduces at least one of the dead times (T3, T4). [9] Circuit arrangement according to claim 7 or 8, characterized by , that the control device (11) is designed such that it reduces the operating frequency (f) in order to increase the first period (T1) from the first initial value (T1A) to the first final value (T1E) and the second period (T2) from the second initial value to the second final value. [10] Circuit arrangement according to any one of claims 1 to 9, characterized by , - that one end of the respective secondary winding (12) is directly connected to the respective secondary-side ground (13) and the other end of the respective secondary winding (12) is connected via the respective first diode (16) to the respective first output (14) and via the respective second diode (17) to the respective second output (15) and - that the respective first diode (16) and the respective second diode (17) are connected antiparallel to each other, so that the respective first and the respective second output voltage (U1, U2), with respect to the respective secondary-side ground (13), have different polarities. [11] Circuit arrangement according to any one of claims 1 to 9, characterized by , - that one end of the respective secondary winding (12) is connected via the respective first diode (16) to the respective first output (14) and via a respective third diode (23) to the respective secondary-side ground (13), - that the other end of the respective secondary winding (12) is connected via the respective second diode (17) to the respective second output (15) and via a respective fourth diode (24) to the respective secondary-side ground (13) and - that the respective first, second, third and fourth diodes (16, 17, 23, 24) are all polarized in the same switching direction, so that the respective first and the respective second output voltages (U1, U2), with respect to the respective secondary-side ground (13), have the same polarity.

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