Integrated circuit packages and methods for their manufacture

Abstract

Procedure with the following steps: Producing a first crack-stopping layer (106-A) of a first crack-stopping structure (106) over a first integrated circuit die (50A) and along side walls of the first integrated circuit die (50A); Forming a dielectric film (106-B) over the first crack-stopping layer (106-A); Forming a second crack-stopping layer (106-C) of the first crack-stopping structure (106) over the dielectric film (106-B); and Deposition of a first gap-filling dielectric (108) around the first crack-stopping structure (106) and the first integrated circuit die (50A).

Description

BACKGROUND

[0001] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density is largely attributable to repeated reductions in the smallest feature size, allowing more components to be integrated into a given area. As the demand for miniaturized electronic devices has intensified, a need has arisen for methods to achieve smaller and more innovative packaging for semiconductor dies.

[0002] US Patent 2012 / 0217641A1 describes a device with an upper metal layer, an overlying UTM conductor of a first thickness, and an overlying passivation layer of a second thickness. The ratio of the second to the first thickness is less than approximately 0.33.

[0003] US patent 2019 / 0139851A1 discloses a semiconductor package with an organic interposer comprising: a first and a second semiconductor chip, each with active surfaces on which connection pads are arranged; the organic interposer, which is arranged on the active surfaces of the first and second semiconductor chips and has a wiring layer that is electrically connected to the connection pads; barrier layers arranged on the side faces of the first and second semiconductor chips; and an encapsulation material that encloses at least parts of the first and second semiconductor chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a sectional view of an integrated circuit die. The Fig. Figures 2-6, 7A, 8A, 9A, and 11-23 are sectional views of intermediate stages in the manufacture of integrated circuit packages according to some embodiments. The Fig. 7B, Fig. 8B, Fig. 8C and Fig. Figure 9B shows gradient diagrams of elements corresponding to different configurations of integrated circuit packages according to some embodiments. The Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 10E, Fig. 10F and Fig. 10G are flowcharts of a process for manufacturing a crack stopper structure according to various embodiments. Fig. Figure 23 is a sectional view of an integrated circuit package according to some other embodiments. Fig. Figure 24 shows a sectional view of an intermediate stage in the manufacture of integrated circuit packages according to some embodiments. The Fig. 25A, Fig. 25B, Fig. 25°C and Fig. Figure 25D shows sectional views of an integrated circuit package according to some other embodiments. The Fig. Figures 26-28 are sectional views of intermediate stages in the manufacture of integrated circuit packages according to some embodiments. Fig. Figure 29 is a sectional view of an integrated circuit package according to some other embodiments. DETAILED DESCRIPTION

[0005] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0007] For system-on-integrated-chip (SoIC) devices, integrated circuit devices (which can also be called dies or chips) are mounted together in a single system device package. Gap-filling materials, such as oxide materials, can be used to fill the areas around the mounted dies. The SOIC devices can then be used in further packages, for example, in an integrated fan-out package (InFO package), a chip-on-wafer-on-substrate (CoWoS) package, or another 3D package. Gap-filling materials can be brittle and prone to cracking, especially when used in volume-filling applications such as gap filling. Cracks can occur, for example, during thermal stresses from heating and / or cooling cycles associated with subsequent processes, or during mechanical stresses caused by sawing dies.Cracks can damage functional dies or trigger process disruptions. For example, a crack can propagate into a die and impair its function or performance, or a crack can provide access for contamination from residues or for the penetration of liquids such as solder, oils, cleaning agents, etc.

[0008] According to various embodiments, after an integrated circuit die has been placed, a crack stop structure is provided to enclose the integrated circuit die before the majority of the gap filler material is deposited. As described in more detail below, the crack stop structure can have a single-layer or multi-layer structure that provides a stress relief point where cracks stop, thus preventing damage to the attached die. The resulting stress relief can prevent cracks from forming in the first place, and if cracks do form, the crack stop structure reduces the length of the cracks and prevents or reduces damage to the attached die.Although the crack-stopping structure is referred to as such, it is understood that the various crack-stopping structures have different layers of different dielectric materials with specific thicknesses to limit crack propagation. It is therefore understood that the "crack-stopping structure," as it is called here, is synonymous with an arrangement of dielectric layers.

[0009] Fig. Figure 1 is a sectional view of an integrated circuit die 50. The integrated circuit die 50 will be capped in a later operation to create an integrated circuit device. The integrated circuit die 50 can be a logic die (e.g., a main processor (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory die (DRAM die)). dynamic random access memory), a static random access memory die (SRAM die) (SRAM: static random access memory), etc.), a power management die (e.g., a PMIC die (PMIC: power management integrated circuit), a high frequency die (HF die), a sensor die, a MEMS die (MEMS: micro-electro-mechanical system), a signal processing die (e.g., a DSP die (DSP: digital signal processing)), a front-end die (e.g., an AFE die (AFE: analog front-end)), the like, or a combination thereof.

[0010] The integrated circuit die 50 can be fabricated on a wafer, which may have various fixture areas that are separated in subsequent steps to produce a plurality of integrated circuit dies. The integrated circuit die 50 can be processed according to the applicable fabrication processes to produce integrated circuits. For example, the integrated circuit die 50 comprises a semiconductor substrate 52, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may consist of other semiconductor materials, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.Other substrates, such as multilayer or gradient substrates, can also be used. The semiconductor substrate 52 has an active surface (e.g., the surface that is in ). Fig. 1 facing upwards), which is occasionally referred to as a front face, and an inactive surface (e.g., the surface that is in Fig. 1 pointing downwards), which is occasionally referred to as a reverse side.

[0011] Devices 54 (represented by a transistor) are arranged on the active surface of the semiconductor substrate 52. The devices 54 can be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. For example, the devices 54 can be transistors, which may have gate structures and source / drain regions, wherein the gate structures are on channel regions, and the source / drain regions are adjacent to the channel regions. The channel regions can be structured regions of the semiconductor substrate 52. The channel regions can be, for example, regions of semiconductor fins, semiconductor nanolayers, semiconductor nanowires, or the like, structured into the semiconductor substrate 52. If the devices 54 are transistors, they can be nanostructure field-effect transistors (nanostructure FETs), fin field-effect transistors (FinFETs), planar transistors, or the like.

[0012] An interlayer dielectric 56 is arranged over the active surface of the semiconductor substrate 52. The interlayer dielectric 56 can enclose and cover the devices 54. The interlayer dielectric 56 can have one or more dielectric layers made of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like, and which can be produced by a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. Contacts 58 extend through the interlayer dielectric 56 to electrically and physically connect the devices 54. For example, if the devices 54 are transistors, the contacts 58 can connect the gates and the source / drain regions of the transistors.The contacts 58 can be made from a suitable conductive material, such as tungsten, cobalt, nickel, copper, silver, gold, aluminium, the like or combinations thereof, which can be produced by a deposition process such as physical vapor deposition (PVD) or CVD, a plating process such as electrolytic or electroless plating, or the like.

[0013] An interconnect structure 60 is arranged above the interlayer dielectric 56 and the contacts 58. The interconnect structure 60 connects the devices 54 to form an integrated circuit. The interconnect structure 60 can, for example, be fabricated from metallization structures 62 in dielectric layers 64. The dielectric layers 64 can, for example, be low-k dielectric layers. The metallization structures 62 feature metal conductors and vias that can be fabricated in the dielectric layers 64 using a Damascene process, such as a single-Damascene process, a dual-Damascene process, or the like. The metallization structures 62 can be fabricated from a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, a combination thereof, or the like.The metallization structures 62 are electrically connected to the devices 54 via the contacts 58.

[0014] The conductive vias 66 extend into the interconnect structure 60 and / or the semiconductor substrate 52. The conductive vias 66 are electrically connected to the metallization structures 62 of the interconnect structure 60. The conductive vias 66 can be substrate vias, such as silicon vias. The conductive vias 66 can be produced, for example, by creating recesses in the interconnect structure 60 and / or the semiconductor substrate 52, for example, by etching, milling, laser techniques, a combination thereof, or the like. A thin barrier layer can be conformally deposited in the recesses, for example, by CVD, ALD, PVD, thermal oxidation, a combination thereof, or the like. The barrier layer can be made of an oxide, a nitride, a carbide, a combination thereof, or the like.A conductive material can be deposited over the junction and in the recesses. The conductive material can be produced by an electrochemical plating process, CVD, ALD, PVD, a combination thereof, or the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, a combination thereof, or the like. Excess conductive material and excess junction are removed from a surface of the interconnect structure 60 or the semiconductor substrate 52, for example, by chemical-mechanical polishing (CMP). The remaining portions of the junction and the conductive material in the recesses form the conductive vias 66.

[0015] In this embodiment, the conductive vias 66 are fabricated using a via-middle process, such that the conductive vias 66 extend through a portion of the interconnect structure 60 (e.g., a subset of the dielectric layers 64) and into the semiconductor substrate 52. The conductive vias 66 fabricated using a via-middle process are connected to a middle metallization structure 62 of the interconnect structure 60. In another embodiment, the conductive vias 66 are fabricated using a via-first process, such that the conductive vias 66 extend into the semiconductor substrate 52 but not into the interconnect structure 60. The conductive vias 66 fabricated using a via-first process are connected to a lower metallization structure 62 of the interconnect structure 60.In yet another embodiment, the conductive vias 66 are fabricated using a via-last process, such that the conductive vias 66 extend through an entirety of the interconnect structure 60 (e.g., each of the dielectric layers 64) and into the semiconductor substrate 52. The conductive vias 66, fabricated using a via-last process, are connected to an upper metallization structure 62 of the interconnect structure 60.

[0016] One or more passivation layers 68 are arranged on the interconnect structure 60. The one or more passivation layers 68 can be made of one or more suitable dielectric materials, such as silicon nitride, silicon nitride, low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, a polymer such as polyimide, solder resist, polybenzoxazole (PBO), a benzocyclobutene-based polymer (BCB-based polymer), molding compound, the like, or a combination thereof. The one or more passivation layers 68 can be produced by chemical vapor deposition (CVD), spin coating, lamination, the like, or a combination thereof. In some embodiments, the one or more passivation layers 68 comprise a silicon nitride layer or a silicon nitride layer.

[0017] A dielectric layer 72 is arranged on one or more passivation layers 68. The dielectric layer 72 can be made of an oxide, such as silicon dioxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), a tetraethyl orthosilicate-based (TEOS-based) oxide, or the like; a nitride, such as silicon nitride, or the like; a polymer, such as PBO, polyimide, a BCB-based polymer, or the like; a combination thereof; or the like. The dielectric layer 72 can be produced, for example, by chemical vapor deposition (CVD), spin coating, lamination, or the like. In some embodiments, the dielectric layer 72 is made of TEOS-based silicon dioxide.

[0018] The die interconnects 74 extend through the dielectric layer 72 and the one or more passivation layers 68. The die interconnects 74 may have conductive pillars, pads, or the like to which external connections can be made. In some embodiments, the die interconnects 74 have bond pads on the front surface of the integrated circuit die 50, and they have bond pad vias that connect the bond pads to the upper metallization structure 62 of the interconnect structure 60. In these embodiments, the die interconnects 74 (with the bond pads and the bond pad vias) may be fabricated by a Damascene process, such as a single Damascene process, a dual Damascene process, or the like.The die connecting elements 74 can be made from a conductive material, such as a metal, such as copper, aluminium or the like, which can be produced, for example, by plating or the like.

[0019] Optionally, solder pads (not shown separately) can be placed on the die connectors 74 during the fabrication of the integrated circuit die 50. These solder pads can be used to perform a chip probe test (CP test) on the integrated circuit die 50. The solder pads can be, for example, solder balls, solder contact bumps, or the like, used to attach a chip probe to the die connectors 74. The chip probe test can be performed on an integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Thus, only integrated circuit dies 50 that are KGDs are further processed and capped, and dies that fail the CP test are not capped. After testing, the solder pads can be removed in subsequent processing steps.

[0020] In some embodiments, the integrated circuit die 50 is a stacked device comprising multiple semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device comprising multiple memory dies, such as a hybrid memory cube device (HMC), a high-bandwidth memory device (HBM), or the like. In these embodiments, the integrated circuit die 50 comprises multiple semiconductor substrates 52 interconnected by substrate through-substrate vias (TSVs), such as silicon vias. Each of the semiconductor substrates 52 may have a separate interconnect structure 60 (or may not have a separate interconnect structure 60).

[0021] The Fig. Figures 2, 3, and 11-23 are sectional views of intermediate stages in the fabrication of integrated circuit packages 100 according to some embodiments. The integrated circuit packages 100 are produced, in particular, by capping several integrated circuit dies 50 in respective package areas 102P. The package areas 102P are separated by scoring groove areas 102S. During subsequent machining, the package areas 102P are separated along the scoring groove areas 102S to produce the integrated circuit packages 100. The machining of two package areas 102P is shown, but it is understood that any number of package areas 102P can be machined simultaneously to produce any number of integrated circuit packages 100. The integrated circuit packages 100 can be system-on-integrated-chips (SoIC) devices, although other types of packages can also be manufactured.

[0022] In Fig. 2. A support substrate 102 is provided. The support substrate 102 can be a glass support substrate, a ceramic support substrate, or the like. The support substrate 102 can be a wafer, so that multiple packages can be fabricated simultaneously on the support substrate 102.

[0023] The first integrated circuit dies 50 (e.g., integrated circuit dies 50A) are attached to the carrier substrate 102 with their front faces down, so that the front faces of the integrated circuit dies 50 are attached to the carrier substrate 102. One integrated circuit die 50A is placed in each package area 102P. The integrated circuit dies 50A can be placed, for example, using a pick-and-place process. The integrated circuit dies 50A can be logic devices, such as CPUs, GPUs, SoCs, microcontrollers, or the like.

[0024] The integrated circuit dies 50A can be attached to the support substrate 102 by bonding them to the support substrate 102 with a bonding layer 104. The bonding layer 104 is located on the front faces of the integrated circuit dies 50A and on a surface of the support substrate 102. In some embodiments, the bonding layer 104 is a release layer, such as an epoxy-based thermal release material that loses its adhesive properties when heated, such as an LTHC release layer (LTHC: light-to-heat conversion); an ultraviolet adhesive (UV adhesive) that loses its adhesive properties when exposed to UV light; or the like. In some embodiments, the bonding layer 104 is an adhesive, such as a suitable epoxy, a die attach film (DAF) or the like.In some embodiments, the bonding layer 104 is an oxide layer, such as a layer of silicon oxide. The bonding layer 104 can have any desired amount of release layers and / or adhesive layers. In some embodiments, the bonding layer 104 comprises a first bonding layer 104A, which is applied to the front faces of the integrated circuit dies 50, and / or a second bonding layer 104B, which is applied over the surface of the support substrate 102. For example, the first bonding layer 104A can be applied to the back faces of the integrated circuit dies 50 before the integrated circuit dies 50 are singulated for separation.

[0025] At this stage of processing, the integrated circuit dies 50A can have the dielectric layer 72 or the die connecting elements 74 (foreword for Fig. (described in 1) may not yet have this. Consequently, the upper passivation layers 68A of the respective integrated circuit dies 50A can be attached to the support substrate 102. In these embodiments, the die connecting elements for the integrated circuit dies 50A are manufactured later, after other integrated circuit dies have been attached to the integrated circuit dies 50A.

[0026] In Fig. 3. The semiconductor substrates 52A of the integrated circuit dies 50A are optionally thinned, which can help reduce the overall thickness of the integrated circuit packages 100. The thinning process can be, for example, a chemical-mechanical polishing (CMP) process, a grinding process, a back-etching process, or the like, performed on the back side of the integrated circuit dies 50A. The thinning process reduces the thickness of the semiconductor substrate 52A. After this thinning step, the conductive vias 66A of the integrated circuit dies 50A may be further embedded by the respective semiconductor substrates 52A. Thinning the semiconductor substrates 52A in this processing step can help reduce the cost of exposing the conductive vias 66A in subsequent processing steps.

[0027] Furthermore, in Fig. 3. A crack-stopping structure 106 is fabricated over each of the integrated circuit dies 50A along the sides of the integrated circuit dies 50A and along the top surfaces of the bond layer 104B (if present) or the support substrate 102 (if the bond layer 104B is not present). The fabrication of the crack-stopping structure 106 is described below with reference to the Fig. 4 to 10 described.

[0028] After fabrication of the crack-stopping structure, a gap-filling dielectric 108 is applied to the crack-stopping structure 106 between and over the integrated circuit dies 50A, burying or encapsulating them laterally and vertically, so that the top surface of the gap-filling dielectric 108 is above the top surfaces of the integrated circuit dies 50A. The gap-filling dielectric 108 is positioned over portions of the support substrate 102 between the integrated circuit dies 50A and contacts of the top surface of the crack-stopping structure 106 between the integrated circuit dies 50A. The gaps between the integrated circuit dies 50A are filled (and can be overfilled) with the gap-filling dielectric 108.The gap-filling dielectric 108 can be made from a dielectric material, such as an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), a tetraethyl orthosilicate-based (TEOS-based) oxide or the like, which can be produced by a suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or the like.

[0029] The total thickness of the crack-stopping structure 106 and the gap-filling dielectric 108 depends on the thickness of the integrated circuit die 50A. In some embodiments, the total thickness can range from approximately 20 µm to 30 µm. In some embodiments, the thickness of the crack-stopping structure 106 can range from approximately 0.4 µm to approximately 15 µm, depending on the variations in the crack-stopping structure 106 as described below.

[0030] Parts of the crack-stopping structure 106 and the gap-filling dielectric 108 are arranged in the groove regions 102S. The crack-stopping structure 106 will provide protection against cracks that may result from the singulation of the packages 100 by the groove regions 102S.

[0031] The Fig. 4, Fig. 5, Fig. 6, Fig. 7A, Fig. 7B, Fig. 8A, Fig. 8B, Fig. 8C, Fig. 9A and Fig. Figure 9B shows close-up views of variations in the manufacture of the crack-stopping structure 106. Fig. Figures 4 to 9B are close-up views of the box marked with dashed lines. Fig. 3, which is labelled F4-10, according to some embodiments. For each of the Fig. For the sake of clarity, details of the integrated circuit die 50 / 50A and the carrier substrate 102 with the bond layer 104B (if used) have been omitted from sections 4 to 9B. Fig. Figures 4 to 9B show the fabrication of the crack-stopping structure 106 and the gap-filling dielectric 108. Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 10E, Fig. 10F and Fig. 10G provides flowcharts for the various configurations that are in the Fig. Figures 4 to 9B are shown. The fabrication of the crack-stopping structure 106 is described in each specific configuration. The fabrication of the gap-filling dielectric 108 is described above with reference to Fig. 3 described.

[0032] There will be brief reference to Fig. 10A taken. A process 10 comprises attaching a die to a support in step 12, as above with reference to the integrated circuit die 50A in Fig. 2 as described. Then, in step 14, a crack-stopping structure (e.g., crack-stopping structure 106) is fabricated over the die and over the support. Afterwards, a gap-filling dielectric (e.g., gap-filling dielectric 108) is fabricated over the crack-stopping structure. Fig. 10B, Fig. 10C, Fig. 10D, Fig. 10E, Fig. 10F and Fig. 10G provides details for step 14 of the crack-stopper structure fabrication, which are described in more detail below. Similar reference designations are used to identify similar elements.

[0033] In the Fig. 4 and Fig. In 10B, the crack-stopping structure 106 is a single-layer crack stopper with a first crack-stopping layer 106-A according to some embodiments. The first crack-stopping layer 106-A is produced on the support substrate 102 and along sidewalls and a top surface of the integrated circuit die 50A (or more generally, any similar integrated circuit die 50). The material of the first crack-stopping layer 106-A has a mechanical strength (e.g., tensile strength or hardness) that is higher than that of the gap-filling dielectric 108. Silicon nitride, for example, has a higher tensile strength than silicon oxide, with the ratio of the tensile strength of silicon nitride to that of silicon oxide being approximately 1.5:1. A first crack-stopping layer 106-A with a material tensile strength between approximately 1.2 and 3 times that of the gap-filling dielectric 108 can be used. A similar relationship applies to the hardness.In some embodiments, the first crack-stopping layer 106-A can be made of silicon nitride, silicon carbonitride, silicon oxide nitride, silicon oxide carbonitride, silicon carbide or the like, which is added in step 18 of . Fig. 10B can be produced using a suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), or the like. If a single crack-stopping layer 106-A is used, as in the Fig. 4 and Fig. As shown in Figure 10B, in some embodiments the first crack-stopping layer 106-A can be deposited with a thickness between approximately 3000 and 5000 angstroms, such as approximately 4000 angstroms, thus providing more significant support than a coating layer. In some embodiments, the first crack-stopping layer 106-A can be deposited with a thickness between approximately 1800 and 3000 angstroms, such as approximately 2000 angstroms.

[0034] According to some embodiments, in the Fig. 5, Fig. 6, Fig. 10C and Fig. 10D the crack-stopping structure 106 is therefore a multilayer structure, with a sandwich structure comprising two or more crack-stopping layers and a dielectric film arranged between successive sets of crack-stopping layers. A two-layer crack-stopping structure 106 is in Fig. 5 shown and a three-layer crack-stopping structure 106 is in Fig. 6 shown, however, it is understood that the same processes occur in the corresponding Fig. 10C and Fig. 10D can be used to create a four-layer crack stopper structure, a five-layer crack stopper structure, etc.

[0035] In the Fig. 5 and Fig. In some embodiments, the crack-stopping structure 10C comprises a first crack-stopping layer 106-A and a second crack-stopping layer 106-C, separated from each other by an interposed first dielectric film 106-B. The first crack-stopping layer 106-A can be produced in step 18 using materials and processes similar to those used to produce the first crack-stopping layer 106-A described above with reference to the Fig. 4 and Fig. 10B have been described. After the production of the first crack-stopping layer 106-A in step 18 of Fig. In step 20, the first dielectric film 106-B is deposited. The first dielectric film 106-B can be deposited using materials and processes similar to those used for depositing the gap-filling dielectric 108, which are described with reference to Fig. 3 have been described. In fact, in some embodiments, the material of the first dielectric film 106-B can be the same material that is subsequently used to produce the gap-filling dielectric 108, while in other embodiments, the material of the first dielectric film 106-B can be different from the material used to produce the gap-filling dielectric 108. After the production of the first dielectric film 106-B, the second crack-stopper layer 106-C is deposited onto the first dielectric film 106-B in step 22. The second crack-stopper layer 106-C can be deposited using materials and processes similar to those used to produce the first crack-stopper layer 106-A. The first crack-stopper layer 106-A and the second crack-stopper layer 106-C can be produced from the same materials or from different materials. As described in Fig. As shown in Figure 5, after the production of the second crack-stopping layer 106-C, the gap-filling dielectric 108 is produced.

[0036] In the Fig. 6 and Fig. In some embodiments, the crack-stopping structure 10D comprises a first crack-stopping layer 106-A and a second crack-stopping layer 106-C, separated from each other by an interposed first dielectric film 106-B, and a third crack-stopping layer 106-E, separated from the second crack-stopping layer 106-C by an interposed second dielectric film 106-D. (With cross-reference to...) Fig. 5, shows Fig. 6, that prior to the deposition of the gap-filling dielectric 108 in step 16, a second dielectric film 106-D is deposited on the second crack-stopping layer 106-C in step 24. The second dielectric film 106-D can be produced using processes and materials similar to those used to produce the first dielectric film 106-B. The material of the second dielectric film 106-D can be the same material as that used to produce the first dielectric film 106-B, or it can be a different material. Similarly, the material of the second dielectric film 106-D can be the same material subsequently used to produce the gap-filling dielectric 108, or it can be a different material.Additional dielectric films arranged between the layers (if used) may be made of the same or different materials as other dielectric films arranged between the layers. The function of the crack-stopping structure 106 is to stop cracking or to reduce the number or severity of cracks, for example by reducing their propagation, as indicated by cracks 107A, 107B, and 107C, which are discussed below with reference to the singulation process.

[0037] After the fabrication of the second dielectric film 106-D in step 24, the third crack-stopping layer 106-E is deposited onto the second dielectric film 106-D in step 26. The third crack-stopping layer 106-E can be fabricated using processes and materials similar to those used to fabricate the first crack-stopping layer 106-A and / or the second crack-stopping layer 106-C. In some embodiments, the first crack-stopping layer 106-A, the second crack-stopping layer 106-C, and the third crack-stopping layer 106-E can each be fabricated from the same materials; however, in other embodiments, one or more of the first crack-stopping layer 106-A, the second crack-stopping layer 106-C, and the third crack-stopping layer 106-E can also be fabricated from different materials.

[0038] As in the Fig. 6, Fig. 10A and Fig. As shown in Figure 10D, after the production of the third crack-stopper layer 106-E in step 16, the gap-filling dielectric 108 is produced. It is understood, however, that the process of deposition of dielectric films (such as the first dielectric film 106-B or the second dielectric film 106-D) and crack-stopper layers (such as the second crack-stopper layer 106-C or the third crack-stopper layer 106-E) can be repeated as many times as desired (as indicated by the box marked with dashed lines) to obtain a specific number of sandwich layers of the crack-stopper structure 106.

[0039] In the Fig. 5 and Fig. 6. Each of the crack-stopping layers (e.g., 106-A, 106-C, and 106-E) can be deposited with a thickness between approximately 500 and 5000 angstroms, such as between approximately 1000 and 4000 angstroms. The first crack-stopping layer, 106-A, can be deposited with a greater minimum thickness, such that its thickness is between approximately 1000 and approximately 5000 angstroms. In some embodiments, each of the crack-stopping layers can have approximately the same thickness. For example, the first crack-stopping layer, 106-A, the second crack-stopping layer, 106-C, the third crack-stopping layer, 106-E (if used), and / or each subsequent layer (if used) can each have the same thickness, between approximately 500 and approximately 2500 angstroms. In some embodiments, the first crack-stopping layer 106-A can be 2 to 3 times larger than one or more of the other crack-stopping layers.For example, the first crack-stopping layer 106-A can be 1.5 to 3 times thicker than the second crack-stopping layer 106-C and / or the third crack-stopping layer 106-E (if used) and / or any subsequent layer (if used). As an example of... Fig. 6. The first crack-stopping layer 106-A can be approximately 1500 to approximately 5000 angstroms, and the second crack-stopping layer 106-C and / or the third crack-stopping layer 106-E can each be approximately 500 to approximately 2500 angstroms.

[0040] In the Fig. 5, Fig. 6, Fig. 10C and Fig. In 10D, the first dielectric film 106-B and the second dielectric film 106-D (if used) and any further dielectric film arranged between the layers (if used) can each be deposited such that they have a thickness between about 1 µm and about 5 µm. The dielectric films arranged between the layers can each be deposited such that they have the same thickness or that one or more of the dielectric films arranged between the layers have different thicknesses.

[0041] The Fig. 7A and Fig. Figure 10E shows the production of a crack-stopping structure 106, which has a first crack-stopping layer 106-A with a first sub-layer 106-A1 and a second sub-layer 106-A2. Fig. 7A is therefore similar Fig. 4, except that the first crack-stopping layer comprises the first sublayer 106-A1 and the second sublayer 106-A2. The first sublayer 106-A1 can be produced in step 18 using processes and materials similar to those used to produce the first crack-stopping layer 106-A, as described above with reference to Fig. 4 has been discussed. The second sublayer 106-A2 can be described in step 19 as a buffer layer between the first sublayer 106-A1 and the gap-filling dielectric 108 (which was described in step 16 of Fig. 10E is produced). The function of the second sublayer 106-A2 as a buffer layer is to provide a tensile strength that lies between the tensile strength of the first sublayer 106-A1 and the gap-filling dielectric 108, thus providing a smoother transition from the hardness of the first sublayer 106-A1 to the lower hardness of the gap-filling dielectric 108.

[0042] The second sublayer 106-A2 also serves as an adhesive layer to provide better adhesion between the first crack-stopping layer 106-A and the gap-filling dielectric 108, creating a hard transition from, for example, silicon nitride to silicon oxide. As an adhesive layer, the second sublayer 106-A2 can exhibit an overlap of elements in the first sublayer 106-A1 and elements in the gap-filling dielectric 108. For example, if the gap-filling dielectric 108 is silicon oxide and the first sublayer 106-A1 is silicon nitride, then the second sublayer 106-A2 can exhibit an overlap of elements in the first sublayer 106-A1 and elements in the gap-filling dielectric 108, which could include silicon, nitrogen, and oxygen. In this example, the second sublayer 106-A2 could be silicon oxide nitride, silicon oxide carbonitride, and so on, so that the second sublayer 106-A2 contains at least silicon, nitrogen, and oxygen.Other elements may be present, such as carbon, hydrogen, chlorine, and so on. In another example, if the gap-filling dielectric 108 is silicon oxide and the first sublayer 106-A1 is silicon carbide, then the second sublayer 106-A2 may have an overlap of elements in the first sublayer 106-A1 and elements in the gap-filling dielectric 108, which could include silicon, carbon, and oxygen. In this example, the second sublayer 106-A2 could be silicon oxide carbide, silicon oxide carbonitride, and so on, so that the second sublayer 106-A2 contains at least silicon, carbon, and oxygen. Other elements, such as nitrogen, hydrogen, chlorine, and so on, may be present. Accordingly, the second sublayer 106-A2 serves to provide adhesion and buffer the transition from the material (e.g., silicon nitride) of the first sublayer 106-A1 to the material (e.g., silicon oxide carbonitride) of the second sublayer 106-A2.to provide silicon dioxide) of the gap-filling dielectric 108.

[0043] In some embodiments, Option 19A allows the second sublayer 106-A2 to be produced by direct deposition of the second sublayer material, such as by PEALD, ALD, or PECVD. In other embodiments, Option 19B allows the second sublayer 106-A2 to be produced by providing a treatment process for the first sublayer 106-A1. For example, the treatment process can be an oxygen plasma process by which an upper portion of the first sublayer 106-A1 is converted into the second sublayer 106-A2 by incorporating oxygen radicals and oxygen ions into the first sublayer 106-A1 with the oxygen plasma. The high energy state of the oxygen radicals breaks the bonds of the material of the first sublayer 106-A1 and causes at least a portion of the first sublayer 106-A1 to be converted into the second sublayer 106-A2.

[0044] In other embodiments, Option 19C allows the second sublayer 106-A2 to be produced by incorporating a pre-deposition treatment process during the production of the gap-filling dielectric 108. For example, during the initial stages of the deposition of the gap-filling dielectric 108, an oxygen-rich gas ratio can be used to cause the upper portion of the first sublayer 106-A1 to oxidize, forming a thin SiON layer. The gas ratio can then be changed to reduce the available oxygen in order to produce the remaining gap-filling dielectric 108.

[0045] The thickness of the first sublayer 106-A1 can be between approximately 1000 and 4000 angstroms, such as approximately 2000 angstroms. The thickness of the second sublayer 106-A2 can be between approximately 50 and 1000 angstroms. Consequently, in embodiments where a two-layer first crack-stopping layer 106-A is used, the total thickness of the first crack-stopping layer 106-A can be between approximately 1000 and 5000 angstroms.

[0046] Fig. Figure 7B shows a diagram representing the concentration of a first element E1 (e.g., nitrogen and / or carbon) and a second element E2 (e.g., oxygen) in the various layers of the first crack-stopping layer 106-A and the gap-filling dielectric 108. The y-axis indicates the concentration percentage, and the x-axis indicates the distance (for example, in the thickness of the layers in the direction indicated by arrow F7d). It should be understood that the lines are only examples and serve to illustrate the relationships between the layers discussed above. In particular, the distance between the first interface I1 and the second interface I2 can be stretched or compressed according to the thickness of the second sublayer 106-A2. In addition to the adhesion and buffering properties of the second sublayer 106-A2, the diagram in Figure 7B shows the following: Fig. 7B, that the second sublayer 106-A2 also serves as a gradient layer. The first element E1 and the second element E2 can be paired with the same base element to form a dielectric material. For example, if the first element E1 is nitrogen and the second element E2 is oxygen, then they can both be paired with silicon to form silicon nitride and silicon oxide, respectively. The first sublayer 106-A1 has a high concentration of the first element E1 and only near the interface I1 between the first sublayer 106-A1 and the second sublayer 106-A2 is there a significant concentration of the second element E2. The gap-filling dielectric 108 has a high concentration of the second element E2 and only near the interface I2 between the second sublayer 106-A2 and the gap-filling dielectric 108 is there a significant concentration of the first element E1.The second sublayer 106-A2 has a significant concentration of both the first element E1 and the second element E2, but a lower percentage concentration of each than the first sublayer 106-A1 or the gap-filling dielectric 108. A gradient is formed at each of the interfaces between the layers, causing the concentrations of the first element E1 and the second element E2 to transition from one layer to the next. At interface I1, for example, element E1 has a negative gradient into the second sublayer 106-A2 as a result of the addition of element E1 to the second sublayer 106-A2 by diffusion. The percentage concentration can then remain constant for a portion of the thickness of the second sublayer 106-A2.At interface I1, element E2 has a positive gradient into the second sublayer 106-A2, due to the addition of element E2 to the first sublayer 106-A1 by diffusion from the second sublayer 106-A2. At interface I2, element E1 has a negative gradient into the gap-filling dielectric 108, due to the addition of element E1 to the gap-filling dielectric 108 from the second sublayer 106-A2 by diffusion. At interface I2, element E2 has a positive gradient into the gap-filling dielectric 108, due to the addition of element E2 to the second sublayer 106-A2 by diffusion from the gap-filling dielectric 108.

[0047] The Fig. 8A, Fig. 8B, Fig. 8C and Fig. Figure 10F shows the fabrication of a crack-stopping structure 106 comprising: a first crack-stopping layer 106-A, which has a first sublayer 106-A1 and a second sublayer 106-A2, a dielectric film 106-B arranged between the layers, and a second crack-stopping layer 106-C, which has a first sublayer 106-C1 and a second sublayer 106-C2. According to some embodiments, in Fig. 8A The crack-stopping structure 106 is therefore a multilayer structure, with a sandwich structure comprising two or more crack-stopping layers and a dielectric film arranged between successive sets of crack-stopping layers. The two-layer crack-stopping structure 106, which is described in Fig. The one shown in 8A is similar to the one shown in Fig. Figure 5 shows, except that the first crack-stopping layer 106-A and the second crack-stopping layer 106-C each have a first sublayer and a second sublayer, as described in more detail below. Although in Fig. Figure 8A shows a two-layer crack-stopping structure 106; it is understood that the same processes can be used to create a three-layer crack-stopping structure (as shown in Figure 106). Fig. 6 is shown), to produce a four-layer crack stopper structure, a five-layer crack stopper structure, etc.

[0048] According to some embodiments, the crack-stopper structure comprises 106 in Fig. 8A a first crack-stopping layer 106-A and a second crack-stopping layer 106-C, separated from each other by an interposed first dielectric film 106-B. The first crack-stopping layer 106-A can comprise a first sublayer 106-A1 and a second sublayer 106-A2, which are separated in steps 18 and 19 of Fig. 10F can be manufactured using materials and processes similar to those used to manufacture the respective sublayers of the first crack-stopping layer 106-A, which are described above with reference to Fig. 7A. After the production of the first crack-stopping layer 106-A, the first dielectric film 106-B is deposited in step 20. The first dielectric film 106-B can be deposited using materials and processes similar to those used for depositing the gap-filling dielectric 108, which is described with reference to Fig. 3 is described. In some embodiments, the material of the first dielectric film 106-B can be the same material that is later used to produce the gap-filling dielectric 108, while in other embodiments, the material of the first dielectric film 106-B can be different from the material that is later used to produce the gap-filling dielectric 108. After the production of the first dielectric film 106-B, the second crack-stopping layer 106-C is produced in steps 22 and 23 of Fig. 10F is produced on the first dielectric film 106-B. The second crack-stopping layer 106-C can have a first sublayer 106-C1, produced in step 22, and a second sublayer 106-C2, produced in step 23, each of which can be deposited using materials and processes similar to those used to produce the first sublayer 106-A1 and the second sublayer 106-A2 of the first crack-stopping layer 106-A, respectively. The first crack-stopping layer 106-A and the second crack-stopping layer 106-C can be produced from the same materials or from different materials.

[0049] The Fig. 8B and Fig. Figure 8C shows diagrams representing the concentration of a first element E1 (e.g., nitrogen) and a second element E2 (e.g., oxygen) in the layers of the first crack-stopping layer 106-A, the first dielectric film 106-B, the second crack-stopping layer 106-C, and the gap-filling dielectric 108. The diagrams of Fig. 8B and Fig. 8C also shows that the second sublayer 106-A2 and 106-C2 serve as gradient layers. Fig. 8B and Fig. 8C exhibits a similar structure to those described in relation to Fig. 7B, and similar reference numerals refer to similar elements described above with reference to Fig. 7B have been described. In particular, it resembles Fig. 8B of the Fig. 7B, except that the first dielectric film 106-B takes the place of the one in Fig. 7B uses gap-filling dielectric 108. Fig. 8B also applies to the structures that are in the Fig. 9A are shown.

[0050] In Fig. 8C are the interactions of the first element E1 and the second element E2 around the first interface I1 and the second interface I2 similar to those described with reference to Fig. 7B above. A third interface I3 is shown between the first dielectric film 106-B and the first sublayer 106-C1. As described in Fig. As can be seen in Figure 8C, the dielectric film 106-B has a high concentration of the second element E2, and the first sublayer 106-C1 has a high concentration of the first element E1. The diffusion of the first element E1 into the first sublayer 106-C1 causes a steep negative gradient of the first element E1 at the third interface I3. Similarly, the diffusion of the second element E2 into the first dielectric film 106-B causes a steep positive gradient of the second element E2 at the third interface I3.

[0051] In some embodiments, option 19A / 23A of Fig. 10F (which includes option 19A from Fig. (10E concerns) the second sublayer 106-A2 and / or the second sublayer 106-C2 are produced by direct deposition of the material of the second sublayer, such as with PEALD, ALD, PECVD. In other embodiments, options 19B / 23B of Fig. 10F the second sublayer 106-A2 and / or the second sublayer 106-C2 are produced by providing a treatment process on the first sublayer 106-A1, such as an oxygen plasma process, by which an upper part of the first sublayer 106-A1 / 106-C1 is converted into the second sublayer 106-A2 / 106-C2 by embedding oxygen radicals and oxygen ions into the first sublayer 106-A1 / 106-C1 with the oxygen plasma. In other embodiments, Option 19C / 23C of Fig. 10F the second sublayer 106-A2 / 106-C2 is produced by providing a pre-deposition treatment process on the first dielectric film 106-B or the gap-filling dielectric 108, in which, for example, an oxygen-rich gas ratio is provided during the initial phases of the deposition of the first dielectric film 106-B and / or the gap-filling dielectric 108.

[0052] In embodiments with a first dielectric layer arranged between the layers, the thickness of the first sublayer 106-A1 of the first crack-stopping layer 106-A can be between approximately 1000 and 4000 angstroms, such as approximately 2000 angstroms. The thickness of the second sublayer 106-A2 can be between approximately 50 and 1000 angstroms. In embodiments with a two-layer first crack-stopping layer 106-A, the total thickness of the first crack-stopping layer 106-A can therefore be between approximately 1000 and 5000 angstroms. In some embodiments, the second crack-stopping layer 106-C can be produced with the same thickness as the first crack-stopping layer 106-A. In other embodiments, the thickness of the first sublayer 106-A1 can be between 1.5 and 3 times greater than the thickness of the first sublayer 106-C1, similar to what was described above with reference to the Fig. 5 and Fig. As explained in section 6. In these embodiments, for example, the first sublayer 106-C1 can have a thickness between approximately 500 and 2500 angstroms. The second sublayer 106-C2 can have the same thickness as, or a different thickness than, the second sublayer 106-A2, each having a thickness between approximately 50 and 1000 angstroms. In some embodiments, the total thickness of the first crack-stopping layer 106-A can be between one and three times the total thickness of the second crack-stopping layer 106-C.

[0053] As in Fig. As shown in Figure 10F, after the fabrication of the second sublayer 106-C2, the steps of depositing a dielectric film (similar to the dielectric film 106-B) and depositing a crack-stopping layer 106-C can be repeated as many times as desired to produce a structure with three, four, five, etc. crack-stopping layers in the crack-stopping structure 106.

[0054] The Fig. 9A, Fig. 9B and Fig. Figure 10G shows the fabrication of a crack-stopping structure 106 comprising: a first crack-stopping layer 106-A, having a first sublayer 106-A1 and a second sublayer 106-A2, a dielectric film 106-B arranged between the layers, and a second crack-stopping layer 106-C, having a first sublayer 106-C1, a second sublayer 106-C2, and a third sublayer 106-C3. According to some embodiments, the crack-stopping structure 106 is in Fig. 9A therefore has a multilayer structure, similar to that found in Fig. Figure 8A, and described above with reference to this figure, comprises a sandwich structure with two or more crack-stopping layers and a dielectric film arranged between successive sets of crack-stopping layers. Fig. 9A comprises the crack-stopping structure 106, a first crack-stopping layer 106-A and a second crack-stopping layer 106-C, which are separated from each other by an intermediate first dielectric film 106-B according to some embodiments. Although Fig. Figure 9A shows a two-layer crack-stopping structure 106; it is understood that the same processes can be used to create a three-layer crack-stopping structure (as in Figure 106). Fig. 6), to produce a four-layer crack-stopping structure, a five-layer crack-stopping structure, etc. The function of the crack-stopping structure 106 is to stop cracks or to reduce the number or severity of cracks, for example by reducing their propagation, as indicated by cracks 107C and 107D, which are discussed below with reference to the singulation process.

[0055] The first crack-stopping layer 106-A can have a first sub-layer 106-A1 and a second sub-layer 106-A2, which are formed in steps 18 and 19 of Fig. 10G are manufactured using materials and processes similar to those used to manufacture the respective sublayers of the first crack-stopping layer 106-A, which are described above with reference to the Fig. 7A and Fig. 10E. After the production of the first crack-stopping layer 106-A, the first dielectric film 106-B is deposited in step 20. The first dielectric film 106-B can be deposited using processes and materials similar to those used to deposit the gap-filling dielectric 108, which is described with reference to Fig. 3 has been described. In fact, in some embodiments, the material of the first dielectric film 106-B can be the same material that is later used to produce the gap-filling dielectric 108, but in other embodiments, the material of the first dielectric film 106-B can be different from the material used to produce the gap-filling dielectric 108.

[0056] After the production of the first dielectric film 106-B, the second crack-stopping layer 106-C is added in steps 21, 22 and 23 of Fig. 10G is produced on the first dielectric film 106-B. The second crack-stopping layer 106-C can comprise a first sublayer 106-C1 and a second sublayer 106-C2, which are similar to the first sublayer 106-A1 and the second sublayer 106-A2 of the first crack-stopping layer 106-A, but the second crack-stopping layer 106-C can also comprise a third sublayer 106-C3, which is arranged between the first sublayer 106-A1 and the first dielectric film 106-B. The third sublayer 106-C3 is therefore produced in step 21 after the first dielectric film 106-B has been produced, the first sublayer 106-C1 is produced in step 22 after the third sublayer 106-C3 has been produced, and the second sublayer 106-C2 is then produced after the first sublayer 106-C1 has been produced. The first sublayer 106-C1 and the second sublayer 106-C2 are similar to those described above with reference to Fig. 8A have been discussed. The third sublayer 106-C3 can have a similar function to the second sublayer 106-C2 and the second sublayer 106-A2. The third sublayer 106-C3 can buffer the transition from the first dielectric film 106-B to the second crack-stopping layer 106-C, as well as provide better adhesion and smoother material gradients.

[0057] Fig. Figure 9B shows a diagram illustrating the concentration of a first element E1 (e.g., nitrogen) and a second element E2 (e.g., oxygen) in the layers of the first crack-stopping layer 106-A, the first dielectric film 106-B, the second crack-stopping layer 106-C, and the gap-filling dielectric 108. The diagram of Fig. Figure 9B also shows that the second sublayer 106-C2 and the third sublayer 106-C3 serve as gradient layers. In Fig. 9B Similar reference marks refer to similar elements referred to above by reference to Fig. 7B have been used. Fig. 9B is similar Fig. 8C, except that the third sublayer 106-C3 is present to provide a buffer and a gradient between the first dielectric film 106-B and the first sublayer 106-C1. In Fig. 9B The interactions of the first element E1 and the second element E2 around the first interface I1 and the second interface I2 are similar to those described above with reference to Fig. 7B have been described. A third interface I3 is shown between the third sublayer 106-C3 and the first sublayer 106-C1, and a fourth interface 14 is shown between the third sublayer 106-C3 and the first dielectric film 106-B. As in Fig. As can be seen in Figure 8C, the dielectric film 106-B and the gap-filling dielectric 108 have a high concentration of the second element E2, and the first sublayer 106-C1 has a high concentration of the first element E1. The second sublayer 106-C2 and the third sublayer 106-C3 exhibit a significant percentage of both the first element E1 and the second element E2. The third interface I3 is essentially a mirror image of the first interface I1, and the fourth interface I4 is essentially a mirror image of the second interface I2. In contrast to the third interface I3, which in Fig. As shown in Figure 8C, the gradients of the first element E1 and the second element E2 are in Fig. 9B is less steep because the third sublayer 106-C3 serves as an additional buffer and gradient layer.

[0058] In some embodiments, options 19A, 19B, 19C, 23A, 23B and 23C of Fig. 10G the second sublayer 106-A2 and / or the second sublayer 106-C2 are manufactured using various processes described above with reference to Fig. 10F have been discussed. For the production of the third sublayer 106-C3, in option 21A the third sublayer 106-C3 can be produced by direct deposition of the material of the second sublayer, such as with PEALD, ALD, PECVD.

[0059] In other embodiments, option 21B of Fig. The third sublayer 106-C3 can be produced by applying a post-deposition treatment process to the first dielectric film 106-B, for example, by providing a nitrogen treatment process to convert an upper part of the first dielectric film 106-B into the third sublayer 106-C3. The treatment process can, for example, be a nitrogen plasma process, in which an upper part of the first dielectric film 106-B is converted into the third sublayer 106-C3 by embedding nitrogen radicals and nitrogen ions into the first dielectric film 106-B with the nitrogen plasma. The high energy state of the nitrogen radicals disrupts the bonds of the material (e.g., silicon oxide) of the first dielectric film 106-B and causes at least a portion of the first dielectric film 106-B to be converted into the third sublayer 106-C3.

[0060] In other embodiments, option 21C of Fig. The third sublayer 10G, 106-C3, can be produced by providing a post-deposition treatment process after an initial deposition of the third sublayer 106-C3. For example, an oxygen treatment process can be provided after the deposition of the third sublayer 106-C3 to convert the deposited material into the final material of the third sublayer 106-C3. The oxygen treatment process can be a plasma process in which a plasma of oxygen is generated, thereby producing oxygen ions and oxygen radicals that can effect the conversion of the third sublayer 106-C3 based on the initial deposition.

[0061] In other embodiments, option 21D of Fig. The third sublayer 106-C3 can be produced by providing a pre-deposition treatment process for the deposition of the first sublayer 106-C1. This is achieved, for example, by supplying an oxygen gas during the deposition of the first sublayer 106-C1 while another gas is ignited, creating a plasma. Plasma radicals can interact with the oxygen gas, causing the oxygen to combine with the other materials of the first sublayer 106-C1, such as silicon nitride, as an initial component (the third sublayer 106-C3). After the third sublayer 106-C3 has been produced, the oxygen gas can be stopped for the remaining deposition of the first sublayer 106-C1.

[0062] In embodiments with a first dielectric layer arranged between the layers, the thickness of the first sublayer 106-A1 of the first crack-stopping layer 106-A can be between approximately 1000 and 5000 angstroms, such as approximately 2000 angstroms. The thickness of the second sublayer 106-A2 can be between approximately 50 and 1000 angstroms. In embodiments using a two-layer first crack-stopping layer 106-A, the total thickness of the first crack-stopping layer 106-A can therefore be between approximately 1000 and 5000 angstroms. In some embodiments, the second crack-stopping layer 106-C can be manufactured with the same thickness as the first crack-stopping layer 106-A. In other embodiments, the thickness of the first sublayer 106-A1 can be between 2 and 3 times greater than the thickness of the first sublayer 106-C1, similar to the above with reference to the Fig. 5 and Fig. 6 has been discussed. In these embodiments, for example, the first sublayer 106-C1 can have a thickness between approximately 700 and 1200 angstroms. The second sublayer 106-C2 can have the same thickness as, or a different thickness than, the second sublayer 106-A2, each having a thickness between approximately 600 and 5000 angstroms. The third sublayer 106-C3 can have the same thickness as, or a different thickness than, the second sublayer 106-C2. In some embodiments, the total thickness of the first crack-stopping layer 106-A can be between 0.5 and 3 times the total thickness of the second crack-stopping layer 106-C. In some embodiments, the total thickness of the second crack-stopping layer 106-C can be between approximately 1900 and 14000 angstroms.

[0063] As in Fig. As specified in 10G, after the fabrication of the second sublayer 106-C2, the steps of depositing a dielectric film (similar to the dielectric film 106-B) and depositing a crack-stopping layer 106-C can be repeated as many times as desired to fabricate a structure with three, four, five, etc., crack-stopping layers in the crack-stopping structure 106. Furthermore, it is understood that the various configurations described above with respect to the crack-stopping layers of the crack-stopping structures 106 can be combined to provide other variations not specifically discussed, such as combining the second crack-stopping layer 106-C of Fig. 9A with the crack-stopper structure 106 from Fig. 6, and so on.

[0064] In Fig. 11. A removal process is performed to bring the surfaces of the gap-filling dielectric 108 to the same level as the back surfaces of the integrated circuit dies 50A. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. After the planarization process, the surfaces of the gap-filling dielectric 108, the crack-stopping structure 106, and the integrated circuit dies 50A (with the semiconductor substrates 52A) are substantially coplanar (within the process variations). After the removal process, the conductive vias 66A may be further buried by the semiconductor substrates 52A.

[0065] In Fig. 12. The semiconductor substrates 52A are thinned to expose the conductive vias 66A. Parts of the gap-filling dielectric 108 and parts of the crack-stopping structure 106 can also be removed by the thinning process. The thinning process can be, for example, a chemical-mechanical polishing (CMP), grinding, etching, or the like, performed on the back side of the integrated circuit dies 50A.

[0066] In Fig. Optionally, bond layers 112 are fabricated around the conductive vias 66A of each integrated circuit die 50A. The bond layers 112 can help to electrically isolate the conductive vias 66A from each other, thus preventing short circuits, and they can also be used in a subsequent bonding process. The bond layers 112 can be fabricated, for example, by recessing the semiconductor substrates 52A to expose portions of the sidewalls of the conductive vias 66A. The recessing can be performed by an etching process, such as dry etching, wet etching, or a combination thereof. A dielectric material can then be fabricated in the recesses.The dielectric material can be an oxide, such as silicon oxides, phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), a tetraethyl orthosilicate-based oxide (TEOS-based oxide), or the like, which can be produced by a suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. Other suitable dielectrics, such as a low-temperature polyimide material, PBO, an encapsulation material, combinations thereof, or the like, can also be used. A planarization process, such as CMP, grinding, or back-etching, can be performed to bring the dielectric material to the same level above the conductive vias 66A. In some embodiments, as shown in [reference], [further details may be added]. Fig. As shown in Figure 13, excess parts of the dielectric material above the conductive vias 66A are removed, whereas in other embodiments, some of the dielectric material may remain above the conductive vias 66A. The remaining parts of the dielectric material in the recesses form the bond layers 112. The bond layers 112 laterally enclose parts of the sidewalls of the respective conductive vias 66A.

[0067] In Fig. Optionally, bond pads 114 are fabricated over the conductive vias 66A of each integrated circuit die 50A. The bond pads 114 can be used to bond another integrated circuit die 50A to the back side of the integrated circuit die 50A. The bond pads 114 can be fabricated, for example, by creating openings in the bond layers 112, thereby exposing the conductive vias 66A, and fabricating the bond pads 114 in the openings on the conductive vias 66A. The openings in the bond layers 112 can be created by an etching process, such as dry etching, wet etching, or a combination thereof. A conductive material can then be fabricated in the openings.In some embodiments, a conductive coating or barrier layer can first be produced, and then the conductive material can be deposited in the remaining openings. The bond pads 114 can be made from a suitable conductive material, such as tungsten, cobalt, nickel, copper, silver, gold, aluminum, the like, or combinations thereof, which can be produced by a deposition process, such as physical vapor deposition (PVD) or continuous vapor deposition (CVD), by a plating process, such as electrolytic or electroless plating, or the like.

[0068] In Fig. 15. Second integrated circuit dies 50 (e.g., integrated circuit die 50B) are attached to the integrated circuit dies 50A in a face-to-back arrangement, such that the front sides of the integrated circuit dies 50B are attached to the back sides of the integrated circuit dies 50A. In the illustrated embodiment, one integrated circuit die 50B is placed in each package area 102P, although any desired number of integrated circuit dies 50B can be attached to each integrated circuit die 50A. In the illustrated embodiment, the integrated circuit dies 50B appear to have the same footprint as the integrated circuit dies 50A; however, it is understood that the integrated circuit dies 50B can be smaller or larger than the integrated circuit dies 50A. The integrated circuit dies 50B can, for example,They can be placed using a pick-and-place process. The 50B integrated circuit dies can be memory devices such as dynamic random access memory dies (DRAM dies), static random access memory dies (SRAM dies), hybrid memory cube modules (HMC modules), high bandwidth memory modules (HBM modules), or the like.

[0069] The integrated circuit dies 50B can be attached to the integrated circuit dies 50A by bonding them together. For example, the integrated circuit dies 50B can be bonded to the integrated circuit dies 50A using hybrid bonding. The dielectric layers 72B of the integrated circuit dies 50B are bonded directly to the respective bond layers 112 of the integrated circuit dies 50A by dielectric-dielectric bonding without the use of an adhesive (e.g., a die mounting layer). The die connecting elements 74B of the integrated circuit dies 50B are bonded directly to the respective bond pads 114 (or conductive vias 66A) of the integrated circuit dies 50A by metal-to-metal bonding, without the use of eutectic material (e.g., solder). Bonding may include pre-bonding and annealing.During pre-bonding, a low pressure is applied to press the integrated circuit dies 50B against the integrated circuit dies 50A. Pre-bonding is performed at a low temperature, such as room temperature (15°C to 30°C), and after pre-bonding, the dielectric layers 72B are bonded to the bonding layers 112. The bond strength can then be improved in a subsequent annealing step, in which the bonding layers 112, the bond pads 114 (or conductive vias 66A), the dielectric layers 72B, and the die connecting elements 74B are annealed. After annealing, direct bonds, such as fusion bonds, are created to bond the bonding layers 112 to the dielectric layers 72B.For example, the bonds can be covalent bonds between the material of the bond layers 112 and the material of the dielectric layer 72B. The bond pads 114 (or conductive vias 66A) are bonded to the die connectors 74B with a one-to-one match. The bond pads 114 (or conductive vias 66A) and the die connectors 74B can be in physical contact after pre-bonding or can expand to be brought into physical contact during annealing. Furthermore, during annealing, the material of the bond pads 114 (or the conductive vias 66A) and the die connectors 74B (e.g., copper) mixes, thus also forming metal-to-metal bonds.Consequently, the resulting bonds between the integrated circuit dies 50A, 50B are hybrid bond connections, exhibiting both dielectric-dielectric bond connections and metal-metal bond connections.

[0070] When hybrid bonding is used to attach the 50B integrated circuit dies to the 50A integrated circuit dies, the 100 integrated circuit packages can be manufactured without some components. For example, hybrid bonding allows bond pads on the back faces of the 50A integrated circuit dies to be omitted. Instead, the 66A conductive vias are directly bonded to the 74B die connectors, without the need for bond pads between the 66A conductive vias and the 74B die connectors.

[0071] The integrated circuit dies 50B can have conductive vias 66 (described above for Fig. 1), which in Fig. 15, represented by the dashed outline, may or may not have. For example, if the device plane containing the integrated circuit dies 50B is to be the top level, then the integrated circuit dies 50B may not require conductive vias 66B (represented by the dashed outline) and these can therefore be omitted. In another example, however, the conductive vias 66B may be used for a device placed later above the top level of the integrated circuit dies 50B of the integrated circuit packages 100.

[0072] In Fig. 16 A crack-stopping structure 126 is fabricated over the integrated circuit die 50B and along the top surfaces of the bond layer 112. The crack-stopping structure 126 can be fabricated according to one of the configurations described above with reference to the crack-stopping structure 106 (see Fig. 4, Fig. 5, Fig. 6, Fig. 7A, Fig. 7B, Fig. 8A, Fig. 8B, Fig. 8C, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 10E, Fig. 10F and Fig. 10G). A gap-filling dielectric 128 is produced between the integrated circuit dies 50B. Initially, the gap-filling dielectric 128 can bury or cover the integrated circuit dies 50B, such that the top surface of the gap-filling dielectric 128 is above the top surfaces of the integrated circuit dies 50B. The gap-filling dielectric 128 is placed over portions of the gap-filling dielectric 108 between the integrated circuit dies 50A. The gaps between the integrated circuit dies 50B are filled (and can also be overfilled) with the gap-filling dielectric 128. The gap-filling dielectric 128 can be made of a dielectric material, such as an oxide, for example.Silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), a tetraethyl orthosilicate-based (TEOS-based) oxide, or the like, are produced by a suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. In some embodiments, the gap-filling dielectric 128 is produced from the same dielectric material as the gap-filling dielectric 108.

[0073] In Fig. 17. A removal process is performed to bring the surfaces of the gap-filling dielectric 128 to the same level as the back surfaces of the integrated circuit dies 50B. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. After the planarization process, the surfaces of the gap-filling dielectric 128, the crack-stopping structure 126, and the integrated circuit dies 50B (with the semiconductor substrates 52B) are essentially coplanar (within the process variations).

[0074] The crack-stopping structure 106 extends along the side walls of the integrated circuit die 50A, and the crack-stopping structure 126 extends along the side walls of the integrated circuit die 50B. The crack-stopping structure 106 may be a different variant than the crack-stopping structure 126, these variants having been described above in connection with the crack-stopping structure 106. The outer side walls of the crack-stopping structure 106 and the crack-stopping structure 126 may or may not be aligned with each other. More generally, the crack-stopping structure 106 and the crack-stopping structure 126 each have vertical parts and horizontal parts, the vertical parts of the crack-stopping structure 126 being aligned with corresponding vertical parts of the crack-stopping structure 106 in some embodiments.

[0075] In Fig. 17 Optionally, a bond layer 132 is produced on the planarized surfaces of the gap-filling dielectric 128, the crack-stopping structure 126, and the integrated circuit dies 50B. In some embodiments, such as when optional conductive vias 66B (shown by the outline marked with dashed lines) are present, the semiconductor substrates 52B can also be omitted, as described above with reference to the semiconductor substrates 52A of Fig. The bond layer 132 can be produced using processes and materials similar to those discussed above with reference to the bond layer 112. In embodiments where the bond layer 132 is omitted, it is understood that subsequent structures can be produced on or attached to the top surfaces of the integrated circuit dies 50B, the gap-filling dielectric 128, and the crack-stopping structures 126 instead of the described bond layer 132.

[0076] In Fig. In step 18, a support substrate 142 is attached to the bonding layer 132. The support substrate 142 can be a glass support substrate, a ceramic support substrate, or the like. The support substrate 142 can be a wafer.

[0077] The support substrate 142 can be attached to the bonding layer 132 by bonding the support substrate 142 to the bonding layer 132 with a bonding layer 144. The bonding layer 144 is located on a surface of the support substrate 142 and a surface of the bonding layer 132. In some embodiments, the bonding layer 144 is a release layer, such as an epoxy-based thermal release material that loses its adhesive properties when heated, such as an LTHC release layer (LTHC: light-to-heat conversion); an ultraviolet adhesive (UV adhesive) that loses its adhesive properties when treated with UV light; or the like. In some embodiments, the bonding layer 144 is an adhesive, such as a suitable epoxy, a die attach film (DAF), or the like. In some embodiments, the bonding layer 144 is an oxide layer, such as a silicon oxide layer.The bonding layer 144 can have any desired quantity of release layers and / or adhesive layers. The bonding layer 144 can be applied to the support substrate 142 and / or to the bonding layer 132. In some embodiments, the bonding layer 144 can be omitted, and the bonding layer 132 can be used as the bonding layer 144.

[0078] In Fig. 19. A debonding process is performed on a support substrate to separate (or “debonde”) the support substrate 102 from the integrated circuit dies 50A. According to some embodiments in which the first bonding layer 104A has a release layer, the debonding process involves projecting light, such as laser light or UV light, onto the first bonding layer 104A, so that the first bonding layer 104A dissolves under the heat of the light and the support substrate 102 can be removed. The structure is then turned over and placed on a tape (not shown separately).

[0079] In the Fig. 20 and Fig. 21. A removal process is carried out to expose the upper passivation layers 68A of the integrated circuit dies 50A. In Fig. 20. Parts of the gap-filling dielectric 108 and parts of the crack-stopping structure 106 can also be removed by the removal process, exposing the gap-filling dielectric 108. The removal process allows the surfaces of the upper passivation layers 68A to be brought to the same level as the surfaces of the gap-filling dielectric 108 and the crack-stopping structure 106. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a re-etching process, combinations thereof, or the like, is used. After the planarization process, the surfaces of the gap-filling dielectric 108, the crack-stopping structure 106, and the integrated circuit die 50A (with the upper passivation layers 68A) are essentially coplanar (within the process variations). Fig. In embodiment 21, the first bonding layer 104A was not used, so that the horizontal parts of the crack-stopping structure 106 could remain intact. In these embodiments, any residue of the second bonding layer 104B can be removed by a cleaning process, thereby exposing the upper passivation layers 68A of the integrated circuit dies 50A.

[0080] Also in the Fig. 20 and Fig. 21 An optional redistribution structure 158 is fabricated across the front faces of the integrated circuit devices 50A, across the gap-filling dielectric 108, and across (now) the top faces of the crack-stopping structure 106. The redistribution structure 158 connects the integrated circuit devices 50 (e.g., 50A and / or 50B) to subsequently fabricated front connecting elements and / or to each other. The redistribution structure 158 can, for example, be fabricated from metallization structures 154 in the dielectric layers 156. The metallization structures 154 feature metal conductors and vias that can be fabricated in the dielectric layers 156 using a damascene process, such as a single-damascene process, a dual-damascene process, or the like.The metallization structures 154 can be made from a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, a combination thereof, or the like. In some embodiments, the redistribution structure 158 extends wider than the terminal area of ​​the integrated circuit dies 50A.

[0081] A passivation layer 162 is then produced over the redistribution structure 158 and over the integrated circuit dies 50A, the crack-stopping structures 106, and the gap-filling dielectric 108. The passivation layer 162 can be produced from one or more suitable dielectric materials, such as silicon nitride, silicon nitride, low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, a polymer such as polyimide, solder resist material, polybenzoxazole (PBO), a benzocyclobutene-based (BCB-based) polymer, molding compound, the like, or a combination thereof. The passivation layer 162 can be produced by chemical vapor deposition (CVD), spin coating, lamination, the like, or a combination thereof.In some embodiments, the passivation layer 162 comprises a first passivation layer made from an oxide and a second passivation layer made from a nitride.

[0082] After the passivation layer 162 is produced, openings for die connecting elements 166 are created through the passivation layer 162. The openings can be produced using suitable photolithographic and etching techniques. In some embodiments, the openings expose portions of an upper metallization structure 154 of the redistribution structure 158. In some embodiments, the openings expose portions of an upper metallization structure 62A of the integrated circuit die 50A.

[0083] Optionally, die connectors 166 are then formed in the openings through the passivation layer 162. The die connectors 166 may have conductive pillars, pads, or the like to which external connections can be made. In some embodiments, the die connectors 166 have bond pads on the front surface of the passivation layer 162, and they have bond pad vias extending through the passivation layer 162 and connecting the bond pads to the upper metallization structure 154 of the redistribution structure 158 (or, if no redistribution structure 158 is present, to the upper metallization structure 62A of the integrated circuit die 50A). The die connecting elements 166 (with the bond pads and the bond pad vias) can be manufactured using a Damascene process, such as a single Damascene process, a dual Damascene process or the like.The die connecting elements 166 can be made from a conductive material, such as a metal, such as copper, aluminium or the like, which is produced, for example, by plating or the like.

[0084] Conductive connecting elements 168 are optionally manufactured on the die connecting elements 166. The conductive connecting elements 168 can be manufactured before or after the singulation process, which is described below with reference to Fig. 22. The conductive interconnects 168 can be BGA interconnects (BGA: Ball Grid Array), solder balls, metal pillars, C4 contact bumps (C4: Controlled Collapse Chip Interconnect), microbumps, contact bumps produced by the ENEPIG process (ENEPIG: Electroless Nickel Electroless Palladium Immersion Gold), or the like. The conductive interconnects 168 can comprise a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive interconnects 168 are produced by first creating a layer of a meltable material (e.g., solder) by vapor deposition, electroplating, printing, solder transfer, bead placement, or the like.After the solder layer has been applied to the structure, a melting process can be performed to shape the material into the desired contact bump forms. The conductive connecting elements 168 can then be used to connect the integrated circuit package 100 to another component, such as an interposer, a capping substrate, or the like.

[0085] In Fig. 22 is based on the structure of the Fig. 20 or Fig. 21 A singulation process is performed to separate the package regions 102P from one another. The singulation process may include a mechanical process, such as a sawing process, a cutting process, or the like. In some embodiments, the singulation process may include an etching process, a laser process, a mechanical process, and / or combinations thereof. The singulation is performed along the scribed groove regions 102S through the passivation layer 162, the redistribution structure 158, the gap-filling dielectrics 108, 128, the crack-stopping structures 106, 126, the bonding layer 132, the bonding layer 144, and the support substrate 142. The resulting singulated integrated circuit package 100 (see Fig. 23) is from one of the package areas 102P. After the singulation process, the singulated parts of the passivation layer 162, the bond layer 132, the bond layer 144 and the support substrate 142 are laterally identical.

[0086] Due to the crack-stopping structure 106, cracks that may form in the gap-filling dielectric 108 and / or 128 as a result of singulation are stopped at the crack-stopping structure 106 and cannot propagate into the integrated circuit dies 50 (e.g., 50A, 50B, 50C, 50D). For example, with reference to Fig. 6. A crack 107A can terminate at an outer layer (e.g., 106-E) of the crack-stopping structure, a crack 107B can extend through the outer layer of the crack-stopping structure 106 and terminate at an inner layer (e.g., 106-C) of the crack-stopping structure 106, and a crack 107C can extend through the entire crack-stopping structure 106 except for the inner layer (e.g., 106-A) of the crack-stopping structure 106. In another example, with reference to Fig. 9A, a crack 107C extends through the entire crack stop structure 106 except for the inner layer (e.g. 106-A) of the crack stop structure 106, while a crack 107D extends partially through a crack stop layer with several sublayers.

[0087] With reference to Fig. 23 The integrated circuit package 100 is a component that can subsequently be implemented in an integrated circuit device. In some embodiments, an integrated circuit device is produced by attaching the integrated circuit package 100 to another component, such as an interposer, a capping substrate, or the like. In some embodiments, an integrated circuit device is produced by encapsulating the integrated circuit package 100 and creating redistribution lines on the encapsulation material to fan out connections from the integrated circuit package 100. The integrated circuit dies 50 of the integrated circuit package 100 can be heterogeneous dies.By encapsulating the Integrated Circuit Package 100 instead of or in addition to the individual encapsulation of the dies, heterogeneous dies can be integrated with a smaller connection area.

[0088] In Fig. In Figure 24, the scoring trench areas 102S are arranged differently, and the singulation process is carried out by the scoring trench areas 102S to separate the package areas 102P from adjacent package areas 102P (not shown in this view) by singulation. The singulation process can be described above with reference to Fig. 22 has been described, will be carried out.

[0089] In the Fig. Sections 25A to 25D show integrated circuit packages 100 according to variations that can be implemented in the steps described above, using similar reference symbols for similar elements. Fig. For example, package 100 of package 25A comprises several integrated circuit dies 50 in each layer, with integrated circuit dies 50A and 50C in the first layer and integrated circuit dies 50B and 50D in the second layer. Integrated circuit dies 50C and 50D have functions corresponding to those discussed above with reference to integrated circuit dies 50. Fig. Figure 25B shows integrated circuit dies 50B and 50D, which have a smaller contact area than integrated circuit dies 50A and 50C, resulting in a gap-filling dielectric 108 at the edge of the integrated circuit package 100 that has a different lateral thickness than the gap-filling dielectric 128 at the same edge of the integrated circuit package 100. Fig. Figure 25C shows integrated circuit dies 50B and 50D, which have a larger contact area than integrated circuit dies 50A and 50C, resulting in a gap-filling dielectric 108 at the edge of the integrated circuit package 100 that has a different lateral thickness than the gap-filling dielectric 128 at the same edge of the integrated circuit package 100. Fig. In Figure 25D, the integrated circuit dies 50B span two or more integrated circuit dies 50 (e.g., 50A and 50C) in the first (or second) layer of the integrated circuit dies. The terminal area of ​​the spanning integrated circuit die 50B is shown to have smaller lateral dimensions than the outer edges of the integrated circuit dies 50A and 50C; however, it is understood that the size of the integrated circuit die 50B may be such that its outer edges are aligned with the outer edges of the integrated circuit dies 50A and 50C, or that it may have larger lateral dimensions than the outer edges of the integrated circuit dies 50A and 50C.

[0090] The Fig. Figures 26 to 28 show intermediate stages in the fabrication of an integrated fan-out package (InFO package) using the integrated circuit package 100 with the crack-stopper structures 106 and 126 (with one of the configurations discussed above in the package 100) as a chiplet device die of the InFO package. For simplicity, details of the integrated circuit packages 100 have been omitted.

[0091] In Fig. In step 26, a support substrate 202 is provided, and a release layer 204 is produced on the support substrate 202. The support substrate 202 can be transferred to the support substrate 102 from Fig. 2 may be similar, and the release layer 204 may be similar to the bonding layer 104B, and they may be manufactured using similar processes and materials.

[0092] In Fig. 26 A rear-side redistribution structure 206 can be produced on the release layer 204. In the illustrated embodiment, the rear-side redistribution structure 206 comprises a dielectric layer 208, a metallization structure 210 (occasionally referred to as redistribution layers or redistribution lines), and a dielectric layer 212. The rear-side redistribution structure 206 is optional. In some embodiments, a dielectric layer without metallization structures is produced on the release layer 204 instead of the rear-side redistribution structure 206.

[0093] The dielectric layer 208 can be produced on the release layer 204. The underside of the dielectric layer 208 can be in contact with the top side of the release layer 204. In some embodiments, the dielectric layer 208 is produced from a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 208 is produced from a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), or the like. The dielectric layer 208 can be produced by a suitable deposition process, such as spin coating, CVD, lamination, or a combination thereof.

[0094] The metallization structure 210 can be fabricated on the dielectric layer 208. The metallization structure 210 can be fabricated, for example, by fabricating a seed layer over the dielectric layer 208. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer with multiple sublayers made of different materials. In some embodiments, the seed layer has a titanium layer and a copper layer over the titanium layer. The seed layer can be fabricated, for example, using physical vapor deposition (PVD) or the like. A photoresist (not shown) is then fabricated and patterned on the seed layer. The photoresist can be fabricated by spin coating or the like and exposed to light for patterning. The structure of the photoresist corresponds to the metallization structure 210.The structuring process creates openings through the photoresist to expose the seed layer. A conductive material is then fabricated within these openings and on the exposed portions of the seed layer. This conductive material can be produced by plating, such as electroplating or electroless plating, or similar processes. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, or similar. The photoresist and any portions of the seed layer where the conductive material was not fabricated are then removed. The photoresist can be removed using a suitable stripping or removal process, such as oxygen plasma. After the photoresist has been removed, any remaining exposed portions of the seed layer are removed, for example, using a suitable etching process, such as wet or dry etching.The remaining parts of the seed layer and the conductive material form the metallization structure 210.

[0095] The dielectric layer 212 can be fabricated on the metallization structure 210 and the dielectric layer 208. In some embodiments, the dielectric layer 212 is fabricated from a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, and which can be patterned using a lithographic mask. In other embodiments, the dielectric layer 212 is fabricated from a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer 212 can be fabricated by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 212 is then patterned to form openings that expose portions of the metallization structure 210.The structuring can be achieved using a suitable process, such as exposure of the dielectric layer 212 if the dielectric layer 212 is a photosensitive material, or etching, for example using anisotropic etching. If the dielectric layer 212 is a photosensitive material, it can be developed after exposure.

[0096] In some embodiments, the rear redistribution structure 206 can have any number of dielectric layers and metallization structures. If multiple dielectric layers and metallization structures are to be produced, the steps and processes discussed above can be repeated. The metallization structures can have one or more conductive elements. The conductive elements can be produced during the fabrication of the metallization structure by forming the seed layer and the conductive material of the metallization structure over a surface of the underlying dielectric layer and in the opening of the underlying dielectric layer, thereby connecting and electrically coupling various conductive lines.A process similar to that used to produce the backside redistribution structure 206 can also be used to produce the redistribution structure 158 discussed above, and vice versa.

[0097] Vias 216 are created in the openings in the redistribution structure 206 and extend away from the topmost dielectric layer of the backside redistribution structure 206 (e.g., the dielectric layer 212). The vias 216 can be created, for example, by fabricating a seed layer (not shown) over the backside redistribution structure 206, e.g., on the dielectric layer 212 and portions of the metallization structure 210 exposed through the openings 214. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer with multiple sublayers made of different materials. In a particular embodiment, the seed layer has a titanium layer and a copper layer over the titanium layer. The seed layer can be fabricated, for example, using PVD or the like.A photoresist is fabricated and patterned on the seed layer. The photoresist can be produced by spin coating or similar processes and can be exposed to create the pattern. The pattern of the photoresist corresponds to the conductive vias. The patterning creates openings through the photoresist to expose the seed layer. A conductive material is fabricated in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be fabricated by plating, such as electroplating or electroless plating, or similar processes. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, or similar. The photoresist and portions of the seed layer where the conductive material has not been fabricated are removed.The photoresist can be removed using a suitable stripping or peeling process, such as oxygen plasma or the like. After the photoresist has been removed, exposed parts of the seed layer are removed, for example, using a suitable etching process such as wet or dry etching. The remaining parts of the seed layer and the conductive material form the vias 216.

[0098] The packages 100 are attached to the dielectric layer 212 using an adhesive 218. The packages 100 can be prepared such that the conductive connecting elements 168 are omitted and only the die connecting elements 166 are produced. The adhesive 218 is applied to the back surfaces of the packages 100 and is used to bond the packages 100 to the back-side redistribution structure 206, such as the dielectric layer 212. The adhesive 218 can be any suitable type of adhesive, epoxy, die attach film (DAF), or the like. The adhesive 218 can be applied to the back surfaces of the packages 195, can be applied over the surface of the support substrate 202 if no back-side redistribution structure 206 is used, or can be applied to a top surface of the back-side redistribution structure 206 if applicable.The adhesive 218 can, for example, be applied to the backs of the packages 195 before the package areas 102P are separated to separate the packages 100 (see e.g. . Fig. 24). Although one of the packages 100 is shown for each package component 200 (e.g. package component 200A or 200B), it is understood that several of the packages 100 can be used in any combination.

[0099] Subsequently, an encapsulation material 220 is produced on and around the various components. After production, the encapsulation material 220 encapsulates the vias 216 and the packages 100. The encapsulation material 220 can be a molding compound, an epoxy resin, or the like. The encapsulation material 220 can be applied by compression molding, heat pressing, or the like, and can be produced over the support substrate 202 such that the vias 216 and / or the packages 100 are buried or covered. The encapsulation material 220 is also produced in gaps between the packages 100. The encapsulation material 220 can be applied in liquid or semi-liquid form and then cured. The encapsulation material 220 surrounds the packages 100 laterally and has lateral extensions that are larger than the extensions of the various structural elements of the packages 100.

[0100] A planarization process is then carried out on the encapsulation material 220 to create the vias 216 and the die connecting elements 166 (see Fig. 20 and Fig. 21) to expose. The planarization process can also remove material from the vias 216, the dielectric layer 136, and / or the die connectors 166 until the die connectors 166 and the vias 216 are exposed. After the planarization process, the top surfaces of the vias 216, the die connectors 166, the dielectric layer 136, and the encapsulation material 220 are substantially coplanar within the process variations. The planarization process can be, for example, a chemical-mechanical polishing (CMP) process, a grinding process, or the like. In some embodiments, the planarization can be omitted, for example, if the vias 216 and / or the die connectors 166 are already exposed.

[0101] A front-side redistribution structure 222 is then fabricated over the encapsulation material 220, the vias 216, and the packages 195. The front-side redistribution structure 222 comprises dielectric layers 224, 228, 232, and 236; and metallization structures 226, 230, and 234. The metallization structures can also be referred to as redistribution layers or redistribution lines. The front-side redistribution structure 222 is shown as an example with three layers of metallization structures. More or fewer dielectric layers and metallization structures can be fabricated in the front-side redistribution structure 222. The front-side redistribution structure 222 can be fabricated using processes and materials similar to those discussed above with reference to the redistribution structure 206.If fewer dielectric layers and metallization structures are to be produced, the steps and processes discussed above can be omitted or repeated.

[0102] Under-bump metallizations (UMBs) 238 are fabricated for external connection to the front-side redistribution structure 222. The UBMs 238 have contact bump portions on the main surface of the dielectric layer 236 extending along it, and they have via portions extending through the dielectric layer 236 to physically and electrically connect the metallization structure 234. As a result, the UBMs 238 are electrically connected to the vias 216 and the package 195. The UBMs 238 can be fabricated from the same material as the metallization structure 226. In some embodiments, the UBMs 238 have a different size than the metallization structures 226, 230, and 234.

[0103] Conductive interconnects 250 are fabricated on the UBMs 238. The conductive interconnects 250 can be BGA interconnects (BGA: Ball Grid Array), solder balls, metal pillars, C4 contact bumps (C4: Controlled Collapse Chip Interconnect), microbumps, contact bumps fabricated by the ENEPIG process (ENEPIG: Electroless Nickel Electroless Palladium Immersion Gold), or the like. The conductive interconnects 168 can comprise a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive interconnects 168 are fabricated by first producing a layer of solder by vapor deposition, electroplating, printing, solder transfer, bead placement, or the like.After the solder layer has been applied to the structure, a melting process can be performed to shape the material into the desired contact bump forms. In another embodiment, the conductive interconnects comprise 250 metal pillars (such as a copper pillar) produced by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal capping layer is applied to the metal pillars. The metal capping layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be produced by a plating process.

[0104] The completed integrated fan-out package components 200, such as package component 200A and package component 200B, can be singulated in a subsequent process. The resulting package components 200 are integrated fan-out packages. In some embodiments, further package components can be attached to the package components 200 before or after singulation.

[0105] In Fig. 27. A debonding process is carried out on a support substrate to detach (or “debonde”) the support substrate 202 from the rear-side redistribution structure 206, e.g., the dielectric layer 208. According to some embodiments, the debonding process includes projecting light, such as laser light or UV light, onto the layer 204, so that the release layer 204 dissolves under the heat of the light and the support substrate 202 can be removed. The structure is then turned over and placed on a tape 2. 55 placed.

[0106] To attach a second package component 300 to the package components 200, conductive connecting elements 252 are first fabricated, extending through the dielectric layer 208 to contact the metallization structure 210. Alternatively, in embodiments without a redistribution structure 206, the conductive connecting elements can contact the vias 216. Second package components 300 are then connected to the package components 200. One or more of the second package components 300 are connected in each of the first package regions 400A and the second package regions 400B to form an integrated circuit device stack 400 in each region containing the package components 200. The integrated circuit device stack 400 is an integrated fan-out package on a package structure.

[0107] The second package components 300 comprise, for example, a substrate 302 and one or more stacked dies 310 (e.g., 310A and 310B) connected to the substrate 302. Although a set of stacked dies 310 (310A and 310B) is shown, in other embodiments a plurality of stacked dies 310 (each comprising one or more stacked dies) can be arranged side by side, connected to an equal surface area of ​​the substrate 302. The substrate 302 can be made of a semiconductor material, such as silicon, germanium, diamond, or the like. In some embodiments, composite materials, such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like, can also be used. Furthermore, the substrate 302 can be a silicon-on-insulator substrate (SOI substrate).In general, an SOI substrate comprises a layer of a semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium-on-insulator (SGOI), or combinations thereof. In an alternative embodiment, the substrate 302 is based on an insulating core, such as a core of glass fiber-reinforced resin. An example of a core material is a glass fiber resin, such as FR4. Alternatives for the core material include bismaleimide triazine resin (BT resin) or other printed circuit board materials or layers. Build-up layers, such as an Ajinomoto build-up layer (ABF), or other laminates can also be used for the substrate 302.

[0108] The substrate 302 can incorporate active and passive devices (not shown). A wide range of devices, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to meet the structural and functional design requirements for the second package components 300. The devices can be fabricated using any suitable method. The substrate 302 can also incorporate metallization layers (not shown) and the conductive vias 308. In some embodiments, the substrate 302 is essentially free of active and passive devices.

[0109] The substrate 302 can have bond pads 304 on a first side of the substrate 302 to connect to the stacked dies 310, and it can have bond pads 306 on a second side of the substrate 302, the second side being opposite the first side of the substrate 302 to connect to the conductive connecting elements 252. In the illustrated embodiment, the stacked dies 310 are connected to the substrate 302 by wire bond connections 312, although other connections, such as conductive contact bumps, can also be used. In one embodiment, the stacked dies 310 are stacked memory dies. The stacked dies 310 can, for example, be memory dies such as LP DDR memory modules (LP: low power; DDR: double data rate), e.g., LPDDR1, LPDDR2, LPDDR3, LPDDR4, or similar memory modules.

[0110] The stacked dies 310 and the wire bonds 312 can be encapsulated with a molding material 314. The molding material 314 can be formed onto the stacked dies 310 and the wire bonds 312, for example, using molding presses. In some embodiments, the molding material 314 is a molding compound, a polymer, an epoxy, a silicon dioxide filler, the like, or a combination thereof. A curing process can be carried out to harden the molding material 314; the curing process can be thermal curing, UV curing, the like, or a combination thereof.

[0111] After the second package components 300 have been manufactured, they are mechanically and electrically bonded to the package component 200 by means of the conductive connecting elements 252, the bond pads 306, and a metallization structure of the rear redistribution structure 206. In some embodiments, the stacked dies 310 can be connected to the packages 195 by means of the wire bond connections 312, the bond pads 304 and 306, the conductive vias 308, the conductive connecting elements 252, the rear redistribution structure 206, the vias 216, and the front redistribution structure 222.

[0112] In some embodiments, an underfill (not shown) is produced between the package components 200 and the second package components 300, which surrounds the conductive connecting elements 252. The underfill can reduce stresses and protect connection points created by the melting of the conductive connecting elements 252. The underfill can be produced by a capillary flow process after the second package components 300 have been attached, or it can be produced by a suitable deposition process before the second package components 300 are attached.

[0113] A singulation process can be carried out by cutting along groove areas, e.g., between the first package area 400A and the second package area 400B, using a suitable singulation method such as sawing, laser cutting, or the like. The cutting separates the first package area 400A from the second package area 400B. The resulting singulated integrated circuit device stack 400 consists of either the first package area 400A or the second package area 400B. In some embodiments, the singulation process is carried out after the second package components 300 have been connected to the package components 200.In other embodiments, the singulation process is carried out before the second package components 300 are connected to the package components 200, for example after the carrier substrate 202 has been unbonded and the conductive connecting elements 252 have been produced.

[0114] In Fig. Each integrated circuit device stack 400 can then be attached to a package substrate 500 using the conductive connecting elements 250 to create a 3D package 600. The package substrate 500 comprises a substrate core 502 and bond pads 504 over the substrate core 502. The substrate core 502 can be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, composite materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like can be used. Furthermore, the substrate core 502 can be a silicon-on-insulator (SOI) substrate.In general, an SOI substrate comprises a layer of a semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium-on-insulator (SGOI), or combinations thereof. The substrate core 502 can be an organic substrate. In an alternative embodiment, the substrate core 502 is based on an insulating core, such as a core made of glass fiber-reinforced resin. An example of a core material is a glass fiber resin, such as FR4. Alternatives for the core material include bismaleimide triazine resin (BT resin) or other printed circuit board materials or layers. Build-up layers, such as an Ajinomoto build-up layer (ABF), or other laminates can also be used for the substrate core 502.

[0115] The substrate core 502 can incorporate active and passive devices (not shown). A wide range of devices, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to meet the structural and functional design requirements for the device stack. The devices can be fabricated using any suitable method. The substrate core 502 can also incorporate a redistribution structure 510 with metallization layers and vias, wherein the bond pads 504 are physically and / or electrically connected to the metallization layers and vias.

[0116] In some embodiments, the conductive connecting elements 250 are melted to attach the package component 200 to the bond pads 504. The conductive connecting elements 250 electrically and / or physically connect the package substrate 500, which has metallization layers in the substrate core 502, to the package component 200. In some embodiments, a solder resist 506 is produced on the substrate core 502. The conductive connecting elements 250 can be arranged in openings in the solder resist 506 to be electrically and mechanically connected to the bond pads 504. The solder resist 506 can be used to protect areas of the substrate core 502 against external damage.

[0117] An epoxy flux (not shown) can be applied to the conductive fasteners 250 before they are melted, with at least a portion of the epoxy flux remaining after the package component 200 has been attached to the package substrate 500. This remaining epoxy portion can serve as an underfill to reduce stress and to protect joints created by the melting of the conductive fasteners 250. In some embodiments, an optional underfill 520 can be formed between the package component 200 and the package substrate 500, so that it surrounds the conductive fasteners 250.The underfill 520 can be produced using a capillary flow method after the package component 200 has been attached, or it can be produced using a suitable deposition method before the package component 200 is attached.

[0118] Fig. Figure 29 shows the packages 100 bonded to an interposer 700, which is then bonded to a substrate 500 to form a chip-on-wafer-on-substrate (CoWoS) package 600. Although only one package 100 is shown bonded to the interposer 700, it is understood that multiple packages 100 can be used in any combination. The packages 100 can be bonded to the interposer 700 by soldering the conductive interconnects 168, by direct metal-to-metal bonding of the die interconnects 166, or by any other suitable process. An optional underfill 720, similar to the underfill 520, can be fabricated to encapsulate the connection points of the die interconnects 166.

[0119] Fig.Figure 29 also shows further devices 730 bonded to the interposer 700. These further devices can be, for example, storage devices, electrical voltage regulators, antennas, logic devices, display devices, etc. In some embodiments, the interposer 700 can be used to establish electrical connections between the further devices 730 and the packages 100, enabling them to interact electrically.

[0120] The interposer 700 can be any suitable substrate and can resemble the package substrate 500, with similar reference numerals denoting similar structures. The redistribution structure 510 can have contact pads 706 for receiving the packages 100. The interposer 700 can also have a second redistribution structure 710, which is located on one side of the substrate core 502 opposite the redistribution structure 510. The second redistribution structure 710 can be manufactured using processes and materials similar to those used to manufacture the first redistribution structure 510. The substrate core 502 has vias 704 that electrically connect the first redistribution structure 510 to the second redistribution structure 710.The vias 704 can be produced by creating openings in the substrate core 502 by etching, laser drilling, or another suitable process, and then filling the openings with a conductive material. A barrier material can also be used in the openings prior to depositing the conductive material, thus enclosing it.

[0121] The interposer 700 can also have contact pads 712 connected to the second redistribution structure 710. Each of the contact pads 712 can also have a solder ball or solder contact mound 714 arranged on it to create a ball grid array (BGA) on the underside of the interposer 700. The BGA can be used for flip-chip bonding. The solder contact mounds 714 can be created by depositing a solder material onto the pads and melting the solder.

[0122] These embodiments can offer advantages. By utilizing a crack-stopping structure that encloses attached integrated circuit devices, the number and severity of cracks can be reduced, or cracks can be eliminated altogether. Cracks propagating from an outer edge of a single package can be stopped at or within the crack-stopping structure, preventing them from propagating further into the integrated circuit device. The crack-stopping structures can have multiple layers, and they can incorporate gradient layers positioned between the multiple layers to further enhance the crack-stopping properties of the structure. Consequently, the reliability of the resulting integrated circuit packages can be improved during testing and operation.

[0123] Additional elements and processes can be used. For example, test structures can be employed to support the verification testing of 3D capping or 3D IC devices. These test structures can include, for example, test pads fabricated in a redistribution layer or on a substrate, enabling the testing of 3D capping or 3D IC devices, the use of probes and / or probe cards, and the like. Verification testing can be performed on intermediate structures as well as final structures. Furthermore, the structures and procedures described here can be used in conjunction with testing methodologies that include intermediate verification of proven good dies to increase yield and reduce costs.

[0124] One embodiment is a method comprising the following steps: fabricating a first crack-stopping layer of a first crack-stopping structure over a first integrated circuit die and along sidewalls of the first integrated circuit die. The method further comprises fabricating a second crack-stopping layer of the first crack-stopping structure over the first crack-stopping layer. The method further comprises depositing a first gap-filling dielectric around the first crack-stopping structure and the first integrated circuit die. Other embodiments of this aspect include appropriate computer systems, devices, and computer programs stored on one or more computer storage devices, each configured to perform the actions of the method.

[0125] In one embodiment, the method may include: producing a dielectric film over the first crack-stopping layer before producing the second crack-stopping layer. In another embodiment, producing the second crack-stopping layer may include: depositing a first sublayer of the second crack-stopping layer over the dielectric film, and producing a second sublayer of the second crack-stopping layer over the first sublayer of the second crack-stopping layer. In another embodiment, producing the second sublayer of the second crack-stopping layer includes performing a pre-deposition treatment process on the first gap-filling dielectric or a post-deposition treatment on the first sublayer of the second crack-stopping layer.In one embodiment, the method may include the following: before producing the first sublayer of the second crack-stopper layer, producing a third sublayer of the second crack-stopper layer, which is arranged between the dielectric film and the first sublayer of the second crack-stopper layer. In one embodiment, producing the third sublayer of the second crack-stopper layer includes performing a pre-deposition treatment on the first sublayer of the second crack-stopper layer or performing a post-deposition treatment on the dielectric film.In one embodiment, the first sublayer can comprise a first dielectric material, wherein the first gap-filling dielectric can comprise a second dielectric material, and wherein the second sublayer can comprise a third dielectric material, the third dielectric material being a combination of the first dielectric material and the second dielectric material. In one embodiment, the method can include: bonding a second integrated circuit die to the first integrated circuit die, fabricating a second crack-stopping structure over and along sidewalls of the second integrated circuit die, and depositing a second gap-filling dielectric around the second crack-stopping structure and the second integrated circuit die.In one embodiment, the method may include: prior to bonding the second integrated circuit die, recessing a back surface of a substrate of the first integrated circuit die to create a recess and expose conductive vias of the first integrated circuit die, and depositing a bonding layer in the recess, the bonding layer extending laterally beyond the first integrated circuit die. In another embodiment, the method may include: attaching a support substrate to the second gap-filling dielectric and the second integrated circuit die, and separating a first package from the support substrate, the first package comprising the first integrated circuit die and the second integrated circuit die.

[0126] Another embodiment is a device comprising: a first device level, wherein the first device level comprises: a first integrated circuit die, a first dielectric structure laterally enclosing the first integrated circuit die, and a first gap-filling dielectric laterally enclosing the first dielectric structure, wherein the first dielectric structure comprises at least two dielectric material layers different from the first gap-filling dielectric.The device further comprises: a second device level, the second device level comprising: a second integrated circuit die, a second dielectric structure laterally surrounding the second integrated circuit die, and a second gap-filling dielectric laterally surrounding the second dielectric structure, the second integrated circuit die being bonded to the first integrated circuit die in a front-to-back arrangement. The device also comprises a support substrate attached to the second integrated circuit die.

[0127] In one embodiment, the first dielectric structure comprises a first layer, a second layer, and a first dielectric film arranged between the first and second layers, the first dielectric film having the same material composition as the first gap-filling dielectric. In another embodiment, the second layer comprises a first sublayer and a second sublayer, the second sublayer being arranged between the first gap-filling dielectric and the first sublayer, the first sublayer having a first hardness, the first gap-filling dielectric having a second hardness lower than the first hardness, and the second sublayer having a third hardness between the first and second hardness.In one embodiment, the second layer further comprises a third sublayer, wherein the third sublayer is arranged between the first sublayer and the first dielectric film, and the third sublayer has the same material composition as the second sublayer. In one embodiment, the first layer of the first dielectric structure has a thickness that is 2 to 3 times greater than the thickness of the second layer of the first dielectric structure. In one embodiment, a third integrated circuit die is arranged in the first plane, wherein the third integrated circuit die is adjacent to the first integrated circuit die, and the second integrated circuit die spans both the first integrated circuit die and the third integrated circuit die.In one embodiment, the first dielectric structure comprises a first dielectric layer and a second dielectric layer, wherein a material of the second dielectric layer comprises each element of the first dielectric layer and the first gap-filling dielectric.

[0128] Another embodiment is a device with a first die, wherein the first die is laterally enclosed by a first dielectric material layer. The device also has a second dielectric material layer that laterally surrounds the first dielectric material layer. The device also has a dielectric filler material that laterally surrounds the second dielectric material layer, wherein the first dielectric material layer has the same material composition as the dielectric filler material, and wherein the second dielectric material layer has a different material composition than the dielectric filler material.

[0129] In one embodiment, the second dielectric material layer comprises a first sublayer and a second sublayer, wherein the first sublayer has a first elemental composition, the first dielectric filler material has a second elemental composition, and the second sublayer comprises each element of the first elemental composition and each element of the second elemental composition in combination. In another embodiment, the second dielectric material layer comprises a third sublayer with a third elemental composition, wherein the third elemental composition comprises each element of the first elemental composition and each element of the second elemental composition in combination.

Claims

[1] Procedure with the following steps: Producing a first crack-stopping layer (106-A) of a first crack-stopping structure (106) over a first integrated circuit die (50A) and along side walls of the first integrated circuit die (50A); Forming a dielectric film (106-B) over the first crack-stopping layer (106-A); Forming a second crack-stopping layer (106-C) of the first crack-stopping structure (106) over the dielectric film (106-B); and Deposition of a first gap-filling dielectric (108) around the first crack-stopping structure (106) and the first integrated circuit die (50A). [2] The method of claim 1, wherein producing the second crack-stopping layer comprises: Deposition of a first partial layer (106-C1) of the second crack-stopping layer (106-C) over the dielectric film (106-B); and Producing a second sub-layer (106-C2) of the second crack-stopping layer (106-C) over the first sub-layer (106-C1) of the second crack-stopping layer (106-C). [3] Method according to claim 2, wherein the production of the second sublayer (106-C2) of the second crack-stopping layer (106-C) comprises performing a pre-deposition treatment process on the first gap-filling dielectric (108) or a post-deposition treatment on the first sublayer (106-C1) of the second crack-stopping layer (106-C). [4] The method of claim 2, further comprising: prior to the production of the first sublayer (106-C1) of the second crack-stopping layer (106-C), production of a third sublayer (106-C3) of the second crack-stopping layer (106-C), which is arranged between the dielectric film (106-B) and the first sublayer (106-C1) of the second crack-stopping layer (106-C). [5] Method according to claim 4, wherein producing the third sublayer (106-C3) of the second crack-stopping layer (106-C) comprises performing a pre-deposition treatment on the first sublayer (106-C1) of the second crack-stopping layer (106-C) or performing a post-deposition treatment on the dielectric film (106-B). [6] Method according to any one of claims 2 to 5, wherein the first sublayer (106-C1) comprises a first dielectric material, wherein the first gap-filling dielectric (108) comprises a second dielectric material, and wherein the second sublayer (106-C2) comprises a third dielectric material, wherein the third dielectric material is a combination of the first dielectric material and the second dielectric material. [7] A method according to any of the preceding claims, further comprising: Bonding a second integrated circuit die (50B) to the first integrated circuit die (50A); Producing a second crack-stopping structure (126) across and along side walls of the second integrated circuit die (50B); and Depositing a second gap-filling dielectric (128) around the second crack-stopping structure (126) and the second integrated circuit die (50B). [8] The method of claim 7, further comprising: prior to bonding the second integrated circuit die (50B), recessing a back side of a substrate of the first integrated circuit die (50A) to create a recess and expose conductive vias (66A) of the first integrated circuit die (50A); and Deposition of a bond layer (112) in the recess, wherein the bond layer (112) extends laterally further than the first integrated circuit die (50A). [9] The method of claim 7 or 8, further comprising: Attaching a support substrate (142) to the second gap-filling dielectric (128) and the second integrated circuit die (50B); and Isolating a first package from the support substrate (142), wherein the first package comprises the first integrated circuit die (50A) and the second integrated circuit die (50B). [10] Device with: a first device level, wherein the first device level comprises: a first integrated circuit die (50A), a first dielectric structure (106) laterally enclosing the first integrated circuit die (50A), and a first gap-filling dielectric (108) laterally enclosing the first dielectric structure (106), wherein the first dielectric structure (106) has at least two dielectric material layers (106-A, 106-B) that are different from the first gap-filling dielectric (108); a second device level, wherein the second device level comprises: a second integrated circuit die (50B), a second dielectric structure (126) laterally enclosing the second integrated circuit die (50B), and a second gap-filling dielectric (128) laterally enclosing the second dielectric structure (126), wherein the second integrated circuit die (50B) is bonded to the first integrated circuit die (50A) in a front-to-back arrangement; and a support substrate (142) that is attached to the second integrated circuit die (50B). [11] Device according to claim 10, wherein the first dielectric structure (106) comprises a first layer (106-A) and a second layer (106-C) which further comprise: a first dielectric film (106-BD) arranged between the first layer (186-A) and the second layer (106-C), wherein the first dielectric film (106-B) has the same material composition as the first gap-filling dielectric (108). [12] Device according to claim 11, wherein the second layer (106-C) comprises a first sublayer (106-C1) and a second sublayer (106-C2), the second sublayer (106-C2) is arranged between the first gap-filling dielectric (108) and the first sublayer (106-C1), the first sublayer (106-C1) has a first hardness, the first gap-filling dielectric (108) has a second hardness which is less than the first hardness, and the second sublayer (106-C2) has a third hardness between the first hardness and the second hardness. [13] Device according to claim 12, wherein the second layer (106-C) further comprises a third sublayer (106-C3), the third sublayer (106-C3) being arranged between the first sublayer (106-C1) and the first dielectric film (106-B), and the third sublayer (106-C3) having the same material composition as the second sublayer (106-C2). [14] Device according to one of claims 11 to 13, wherein the first layer (106-A) of the first dielectric structure has a thickness that is 2 to 3 times greater than the thickness of the second layer (106-C) of the first dielectric structure (106). [15] Device according to any one of claims 10 to 14, further comprising a third integrated circuit die (50C) arranged in the first device plane, wherein the third integrated circuit die (50C) is adjacent to the first integrated circuit die (50A), wherein the second integrated circuit die (50B) spans both the first integrated circuit die (50A) and the third integrated circuit die (50C). [16] Device according to one of claims 10 to 15, wherein the first dielectric structure (106) comprises a first dielectric layer (106-B) and a second dielectric layer (106-D), wherein a material of the second dielectric layer (106-D) comprises each element of the first dielectric layer (106-B) and of the first gap-filling dielectric (108). [17] Device with: a first die (50A), wherein the first die (50A) is laterally enclosed by a first dielectric material layer (106-A); a second dielectric material layer (106-C) that laterally surrounds the first dielectric material layer (106-A); and a dielectric filler material (108) that laterally surrounds the second dielectric material layer (106-C), wherein the first dielectric material layer (106-A) has the same material composition as the dielectric filler material (108), and wherein the second dielectric material layer (106-B) has a different material composition than the dielectric filler material (108). [18] Device according to claim 17, wherein the second dielectric material layer (106-C) comprises: a first sublayer (106-C1) with a first elemental composition, wherein the first dielectric filling material (108) has a second elemental composition; and a second sublayer (106-C2) which contains each element of the first elemental composition and the second elemental composition in combination. [19] Device according to claim 18, wherein the second dielectric material layer (106-C) comprises: a third sublayer (106-C3) with a third elemental composition, wherein the third elemental composition comprises each element of the first elemental composition and each element of the second elemental composition in combination.

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