Monitoring circuit and system for detecting faulty I / O signals from a chip card

Abstract

A monitoring circuit (100) is provided for detecting faulty I / O signals from a chip card (200), comprising a control module (10) and an electronic switching module (20). An I / O input (11) of the control module (10) is connectable to an I / O interface (210) of the chip card (200). The control module (10) is configured to monitor the current voltage level of an I / O signal at the I / O input and compare it with a corresponding expected reference voltage level. Based on this comparison, the control module sets a logical marker for the switching module if the current voltage level deviates from the corresponding expected reference voltage level by more than a predefined threshold.The switching module (20) is configured to electrically connect the I / O input (11) to ground potential when the logic marker is set, so that data signals sent from the chip card (200) via the I / O interface (210) are permanently pulled to ground potential, and the chip card (200) is thus detected as faulty by a reader (300) connected electrically in parallel to the monitoring circuit (100). A system consisting of a corresponding monitoring circuit (100) and a reader (200) is also provided.

Description

Field of the invention

[0001] The present invention relates to a monitoring circuit and a system for detecting faulty input / output signals (I / O signals) of a chip card. Background of the invention

[0002] Chip cards are used, for example, as payment cards or electronically readable identity documents. Such a chip card is therefore a card-shaped data storage device, which can also be designed as a dual-interface card, for example, which can be read both contact-based and contactless. Currently, the quality testing of contact-based interfaces of chip cards or dual-interface cards is carried out using a chip card reader. In this process, a chip card or its chip module is brought into contact with the chip card reader, and a reading process (or generally a communication process) is initiated. If the chip card reader cannot evaluate the communication from the chip card, the chip card is considered defective. However, this can only detect errors in the chip module that have already developed to the point where communication with the chip card is essentially no longer possible.However, especially in the case of ESD (electrostatic discharge) damage to an I / O pin on the chip card, the card may initially function well enough that the damage is not detected, even though the I / O signal is already faulty, because the previously described tests do not check the quality of the I / O signal itself. However, the damage may then develop later, causing the chip card to cease functioning at a certain point. Description

[0003] Accordingly, one object of the present invention is to detect damage, in particular ESD damage, of chip cards at an early stage.

[0004] This object is achieved by the subject matter of the independent claim. Exemplary embodiments emerge from the dependent claims and the following description.

[0005] According to a first aspect, a monitoring circuit for detecting faulty I / O signals of a chip card (or generally a chip module) is provided. The monitoring circuit comprises a control module and an electronic switching module. An I / O input of the monitoring circuit is connectable to an I / O interface of the chip card (or chip module). The electronic switching module is configured to selectively connect the I / O input to a ground potential. The control module is connected to the I / O input and is configured to monitor a current voltage level of an I / O signal at the I / O input and compare it with a corresponding expected reference voltage level, and, based on the comparison, to set a logical marker for the switching module if the current voltage level deviates from a corresponding expected reference voltage level by more than a predefined threshold.The electronic switching module is configured to electrically connect the I / O input to a ground potential when the logical marker is set, so that data signals sent by the chip card via the I / O interface are permanently pulled to the ground potential and the chip card is thus detected as faulty by a reading device electrically connected in parallel to the monitoring circuit.

[0006] A chip card has an I / O interface (I / O pin) that is used to transmit a data signal to a reader. The chip card's I / O interface, along with a GND pin and a clock pin, is connected to corresponding interfaces of a reader to enable communication between the reader and the chip card. The chip card switches an electrical signal output via the I / O interface between a logical one (high level) and a logical zero (low level) to encode data signals that are sent to the reader (the reader also sends data signals to the chip card in the same way).

[0007] The communication between the reading device and the chip card can, for example, take place via a standardized switch-on sequence (e.g. according to ISO 7816-3).

[0008] In particular, in the case of ESD damage to the I / O interface (i.e. the corresponding pin of the chip card), the chip card may initially still function because, for example, the voltage levels at high level (e.g. 5 V or any other voltage level (such as voltage classes A, B and C according to ISO-7816-3 described below) and low level (e.g. 0 V) ​​deviate from the intended reference voltage levels, but the deviations are only slight and still lie within valid threshold values. Such damage can, however, intensify over time, so that the chip card will no longer function at some point because no signals recognizable by the reading device can be transmitted to the reading device.

[0009] The disclosed monitoring circuit detects such errors early on or enables the reading device to detect such errors early on. The monitoring circuit is configured to be connected to the chip card in parallel with such a reading device via all connections / lines. The same electrical potential is therefore always present at the I / O input of the monitoring circuit as at the I / O interface of the chip card (or generally of the chip module) and at a corresponding I / O interface of the reading device. Furthermore, during operation, the monitoring circuit is connected to the reading device via a common ground potential, which is also present at the chip card during a readout process via a GND pin (ground pin, i.e., a contact pin that is at ground potential).The I / O input of the monitoring circuit is also connected to the control module of the monitoring circuit, which measures the voltage level (specifically, the differential potential difference with respect to ground potential) and compares it with the corresponding expected reference voltage levels (e.g., 5 V for high and 0 V for low). The measurement preferably begins when a reset signal changes from logic zero to logic one (or after a predetermined period of time after the chip card first sends a response via the I / O interface), which also initiates communication between the reader and the chip card. Alternatively, the measurement begins when the applied voltage (Vcc) is re-established.

[0010] If the control module detects a deviation above a predetermined threshold at a logical one or a logical zero (for example, if the voltage level during a high signal is below 4.8 V (with a reference voltage level of 5 V), or if the voltage level during a low signal is 0.2 volts or more (these thresholds are only examples, and other thresholds, as described below, are also conceivable)), the control module sets a logical marker of the electronic switching module. When the logical marker is set, the electronic switching module connects the I / O input of the monitoring circuit directly to ground potential (for example, via a transistor or other electronic switch).Since the I / O input of the monitoring circuit is connected in parallel with the I / O interface of the chip card, the voltage level of the I / O interface of the chip card is also pulled to ground potential. This means that, regardless of the electrical signal output by the chip card via the I / O interface, the reading device (which, as described above, is also electrically connected in parallel with the monitoring circuit) always measures a zero voltage relative to ground potential. The reading device can therefore no longer receive data from the chip card and recognizes the chip card as faulty. The logical marker then preferably remains active until a communication connection with the chip card is terminated (for example, when a reset signal (RST) changes from logical one to logical zero).

[0011] The electronic switching module can, for example, comprise an RS flip-flop and an electronic switch connected to a logical output Q of the RS flip-flop. When the logical marker is set, the control module can then apply a control voltage to the set input S of the RS flip-flop, setting the Q output of the flip-flop to logical one. This turns on the electronic switch and electrically connects the I / O input of the monitoring circuit to ground potential. When the reset signal (RST) changes from logical one to logical zero, the control module can apply a control voltage to the reset input of the flip-flop, thus erasing the state stored in the flip-flop. However, any other electronic switching module that fulfills the corresponding functionality is also conceivable.

[0012] According to one embodiment, the control module is further configured to periodically compare the current voltage level in accordance with the occurrence of edges of a clock signal with a corresponding expected reference voltage level after the corresponding edge.

[0013] For example, the control module can take a measurement at each occurrence of an edge of the clock signal or after each cycle of the clock signal (within a predetermined time unit) and compare the voltage level with the expected reference voltage level. This checks the expected voltage level for deviations from the reference voltage level in each clock cycle, and sets or de-sets the logical marker depending on whether the reference voltage level lies within the respective threshold values. This checks both the voltage level of the logical one and the logical zero in the I / O signal. The logical marker is then set as soon as a deviation from the expected reference voltage level above the set threshold occurs for the first time and remains set until the communication connection between the reader and the chip card is terminated (as described above).

[0014] The clock signal (as well as the control voltage for the high level) can be provided by the reader. This automatically synchronizes the monitoring circuit, the reader, and the chip card. However, a common clock signal can also be provided externally.

[0015] According to a further embodiment, the clock signal is provided externally to the monitoring circuit or is generated by the monitoring circuit itself.

[0016] According to a further embodiment, the expected reference voltage level after a rising edge of the I / O signal corresponds to a voltage level associated with a logical one, and the expected reference voltage level after a falling edge of the I / O signal corresponds to a voltage level associated with a logical zero.

[0017] The voltage level assigned to the logical one can, for example, be higher than the voltage level of the logical zero. However, it is also conceivable that the logical one is assigned a low voltage level and the logical zero a high voltage level. In particular, the expected reference voltage level of the logical one can be defined by a control voltage (Vcc), which is output, for example, by the reading device or supplied externally to the entire system. The reference voltage level of the logical zero can, for example, correspond to ground potential. However, these are only examples, and in principle any other technically reasonable reference voltage levels can be used. According to ISO-7816-3, for example, three voltage classes (classes A, B, and C) are defined.Class A corresponds to a control voltage (Vcc) of 5 V, Class B corresponds to a control voltage (Vcc) of 3.3 V, and Class C corresponds to a control voltage (Vcc) of 1.8 V, with the respective voltage level corresponding to the high level. However, voltage values ​​deviating from these voltage levels are also possible.

[0018] According to a further embodiment, the expected reference voltage level associated with a logical one corresponds to 5 V, and the expected reference voltage level associated with a logical zero corresponds to 0 V. However, it is also conceivable in principle that the reference voltage levels of the logical one and the logical zero are swapped.

[0019] According to a further embodiment, the control module is configured to begin monitoring and comparing the voltage level at the I / O input when a reset signal provided to the chip card and the monitoring circuit is active. The reset signal can, for example, be output by the reading device when communication with the chip card is initiated. However, it is also conceivable for the monitoring and comparing to be initiated manually. This makes it possible, for example, to detect whether the chip card is faulty but currently still functioning, i.e., the extent of (ESD) damage can be estimated.

[0020] According to another embodiment, the logical marker remains set after being set until the reset signal is deactivated, after which it is reset. For example, as described above, the control module can apply a control voltage to the reset input of an RS flip-flop. This makes the monitoring circuit functional again after communication with the current data carrier / chip card has been completed and returns to its initial state without a set logical marker.

[0021] Alternatively (instead of or in addition to deactivating the reset signal), Vcc can also be switched off. This deactivates the monitoring circuit. The marker is only set as long as Vcc is active and a detection has occurred.

[0022] According to a further embodiment, the electronic switching element comprises a flip-flop and an electronic switch controlled via an output of the flip-flop. However, any other suitable electronic switching element is possible.

[0023] According to another embodiment, the electronic switch is a transistor. This can be, for example, an IGBT, a MOSFET, or any other suitable type of transistor. However, in principle, any other electronic switch capable of electrically connecting the I / O input of the monitoring circuit to ground potential is also possible.

[0024] According to a second aspect, a system is provided. The system comprises a monitoring circuit according to one of the embodiments described above and a reading device. The monitoring circuit is connected in electrically parallel circuitry to the reading device. The reading device is configured to be communicatively connected to a chip module of a chip card. If the logical marker for the switching module is set, the reading device cannot read a response from the chip card due to the parallel connection and thus detects the chip card as defective.

[0025] The monitoring circuit can be either a standalone circuit connected to the reading device or an integral component of the reading device itself. In the latter case, the system would then represent a reading device with a monitoring circuit integrated as an integral component, as described herein, which thus enables early detection of damage (such as ESD damage) without the need for additional devices / equipment. Short description of the characters Fig. 1 shows an example signal curve for a not yet well developed ESD damage, which can be detected with the monitoring circuit of the Fig. 2 can be recognized. Fig. 2 shows a schematic diagram of a monitoring circuit for detecting faulty I / O signals of a chip card, which is connected in parallel to a reading device that is in communication with the chip card. Fig. Figure 3 shows the time course of a control voltage (Vcc), a clock signal (Clk), a reset signal (RST) and an I / O signal from a fault-free chip card, which is used in the circuit of the Fig. 2 occur. Detailed description of an exemplary embodiment

[0026] The representations in the figures are schematic and not to scale. Where the same reference symbols are used in different figures in the following description, they refer to identical or similar elements. Identical or similar elements may also be designated by different reference symbols.

[0027] Fig. 1 shows a section of a measured signal curve of an I / O signal 1 that comes from an I / O interface 210 of a faulty chip card 200 (see Fig. 2) to a reading device 300 (cf. Fig. 2) is output. The signal exhibits transitions between logical ones 2 and logical zeros 3. It is clearly visible that signal errors 4 occur for some of the logical ones 2, which in this example manifest themselves as too low a voltage level. Such signal errors 4 can occur, for example, in the event of ESD damage (Electro Static Discharge, ESD; damage caused by electrostatic discharge) to the chip card 200. In the example shown, however, the signal errors 4 are not yet severe, so that the chip card can still be read by the reading device 300. However, ESD damage tends to progress over time, so that the chip card 200 can fail at a later point in time (for example, with a customer at a POS (Point of Sale)), even though the chip card was still readable during regular quality control (for example, at the manufacturer). Fig. The monitoring circuit 100 shown in Figure 2 enables early detection of such fault patterns.

[0028] Fig. 2 shows a system 400 comprising a monitoring circuit 100 according to the disclosure and a reading device 300. The reading device 300 is connected to a chip card 200, for example, by inserting the chip card 200 into the reading device 300 and contacting a chip module of the chip card by a reading head (not shown) of the reading device 300. The reading device has an I / O interface I / O, an interface for a control voltage Vcc, a clock interface for a clock signal Clk, and a ground connection for a ground potential GND. The interfaces I / O, Vcc, Clk, RST, and GND of the reading device 300 are each connected to corresponding interfaces of the chip card 200, for example, by pins of the reading head of the reading device 300 contacting the chip of the chip card 200.

[0029] The monitoring circuit 100 is connected in parallel to the reading device 300, i.e., the interfaces I / O, Vcc, Clk, RST, and GND of the reading device 300 are connected to corresponding interfaces of the monitoring circuit 100 to form an electrically parallel circuit, so that the same voltage is applied to the corresponding interfaces. The monitoring circuit 100 comprises a control module 10 and an electronic switching module 20, which, in the illustrated configuration, comprises a flip-flop 21 (in particular an RS flip-flop 21) and an electronic switch 22. The electronic switch 22 can, for example, be a transistor or any other suitable electronic switch 22 and selectively connects the I / O input 11 of the monitoring circuit 100 to ground potential GND. A gate of the electronic switch 22 is controlled via a logic output Q of the flip-flop 21.When the logic output Q outputs a logic one, i.e., when a corresponding control voltage is applied to the gate of the electronic switch 22, the electronic switch 22 switches on and electrically connects the I / O input 11 to GND. The flip-flop 22, in turn, is set to logic one at the output Q when a switching signal is applied to the set input S of the flip-flop 22. When a reset signal is applied to the reset input R, the flip-flop 22 is reset, i.e., the stored state is erased.

[0030] The chip card 200 has a chip card I / O circuit 240. The chip card I / O circuit 240 can control an electronic chip card switch 230 via an I / O connection and thus output and receive logical signals. When the chip card switch 230 is open, the voltage level at the I / O interface 250 is pulled to the voltage level Vcc by the pull-up resistor 220. The voltage level Vcc can be provided, for example, by the reading device 300, by the monitoring circuit 100, or otherwise externally and defines the voltage level associated with a logical one. Vcc can be a 5 V voltage, for example. The chip card switch 230, in turn, selectively connects the I / O interface or the I / O pin 250 to the ground potential GND. Thus, when the chip card switch 230 is in an open state, the voltage Vcc and thus a logical one is present at the I / O pin 250.When the chip card switch 230 is closed, the voltage level at the I / O pin is pulled to ground potential, resulting in a logic zero. The chip card I / O circuit 240 can thus output digital signals at the I / O pin by switching the chip card switch 230.

[0031] Fig. 3 (also with reference to Fig. 2) shows a waveform of the signals Vcc, Clk, RST, and I / O from Fig. 2, when a communication connection is established between the reading device 300 and the chip card 200 (here, an error-free chip card 200). The signal waveform shown corresponds to the standardized power-on sequence according to ISO 7816-3. If the reading device 300 wants to read the chip card 200 or generally communicate with it, the control voltage Vcc is first output, and after a time t bthe RST signal is set to high (ie to logic one). In addition, after the control voltage Vcc is output, a clock generator Clk is started, which outputs a periodic clock signal (individual cycles in Fig. 3 is not visible or only indicated by hatching). When the RST signal is applied to the chip card 200, the chip card sends after a predetermined time period t c by controlling the chip card switch 230 (as described above) outputs response signals via the I / O interface 250.

[0032] Due to the parallel connection of monitoring circuit 100 to reading device 300 and chip card 200, these signals also arrive unchanged at I / O input 11 of monitoring circuit 100. The control module 100 of monitoring circuit 100 then compares the voltage level at I / O input 11 with a corresponding expected reference voltage level. The reference voltage level of logic one 2 is specified, for example, by control voltage Vcc (in particular, by the differential potential difference across GND), and the reference voltage level of logic zero 3 is specified by GND. If the voltage level at the I / O input 11 is higher than a predefined threshold value (for example, in the case of a high level, this would be a value which is still above the lower valid value according to ISO-7816-3, but below the maximum value (for example, from 90% to 98% of the maximum value of Vcc (e.g.5V in Class A or the corresponding value in other classes)); in the case of a low level, this would be a value which is still below the upper permissible value according to ISO-7816-3, but above ground potential (for example, from 5% to 10% of the maximum value of Vcc (e.g. 5V in Class A or the corresponding value in other classes))) from the respective reference voltage level in the corresponding state of the I / O signal, the control module sets a logical marker by outputting a switching signal to the set input S of the flip-flop 21, which logical marker is stored in the flip-flop. The flip-flop 21 then outputs a switching signal in the form of a logical one (i.e., a control voltage) via the output Q to the gate of the electronic switch 22, so that the switch 22 switches on and thus pulls the voltage level at the I / O input 11 of the monitoring circuit 100 to GND.If the voltage level at the I / O input 11 shows no deviation or only a deviation within predetermined tolerances / threshold values, the logical marker is not set. Due to the parallel connection to the reading device 300, the voltage level at the I / O input of the reading device 300 (when the logical marker has been set) is also pulled to GND (i.e., ideally to 0 V), regardless of which signal the chip card I / O circuit 240 is currently attempting to output. As a result, the reading device 300 can fundamentally no longer receive any data communication from the chip card 200 (since a logical zero is consistently received), and the chip card is classified as faulty, even if the chip card is still fundamentally functional but, due to the deviations in the voltage level, is already showing the first early signs of, for example, ESD damage to the I / O pin 250 or other damage with a similar error pattern.Such early signs would not be detected without the monitoring circuit 100. The logical marker then remains set until data communication is terminated by resetting the reset signal RST to low. Afterward, the logical marker is cleared by outputting a switching signal to the reset input R of flip-flop 21, so that the monitoring circuit 100 is reused for the next chip card 200.

[0033] The control module 10 detects the expected reference voltage level (i.e. whether a logic one 2 or a logic zero 3 should be present) at the I / O input 11 by detecting the edges of the Clk signal and the I / O signal. In particular, for example, the (response) I / O signal from the chip card 200 according to ISO 7816-3 always begins with a falling edge. In power-up sequences according to ISO 7816-3, a logic level of zero is therefore always checked first. Then the logic level of 1 is checked. This procedure is then repeated periodically with the clock signal. Thus, all transmitted bits are checked. As soon as an error in the voltage level is detected at any point, the chip card 200 is marked as faulty. However, it should be noted that standardized power-up sequences other than ISO 7816-3 can also be used.Since the clock signal (Clk) is also a common clock signal across the monitoring circuit 100, the reading device 300, and the chip card 200, the edges of the I / O signal always coincide with edges of the clock signal. A check can therefore be performed with each edge of the I / O signal. As soon as a first deviation in the voltage level of the I / O signal occurs that differs by more than one threshold value from the respective expected reference voltage level (i.e., from high or low), the logical marker can be set as described above. Furthermore, the corresponding length of the bit sequence can optionally be measured from the chip card 200 based on the clock signal, even in the case of longer, constant bit sequences. In this way, for example, truncated bits can also be detected, and the edge steepness can optionally also be measured.The logical marker can then be set as soon as any indicator of a faulty signal is detected. Optionally, a predefined bit pattern can also be stored in the monitoring circuit 100. The "actual signal" could then be compared with the "desired signal" via an analog comparison. The Clk signal sets the bit control (logical zero or logical one) for the correct comparison. Preferably, the analog curve could also be mapped here to account for any circuit peaks when switching the signals.

[0034] It should be noted that the disclosed monitoring circuit 100 can also be integrated directly into the reading device 300, for example, into a read head of the reading device 300, so that the reading device 300 and the monitoring circuit 100 form a common unit. The reading device 300 would then include the monitoring circuit 100 as an integral component.

[0035] The monitoring circuit 100 proposed here, or the method defined by the monitoring circuit 100, makes it possible to select chip cards from production that have ESD damage, i.e., to detect such damage at an early stage. Furthermore, only a small additional circuit is provided for this purpose, for example, in an existing chip card reader. In particular, no complex modification to an entire production facility is necessary. List of reference symbols 1, I / OI / O signal 2 Logical One, High Signal 3 Logical zero, low signal 4 signal errors 10 Control module 11 I / O input 20 electronic switching module 21 flip-flops 22 electronic switch 100 monitoring circuit 200 chip card, chip module 210 I / O interface 220, R pull-up resistor 230 electronic chip card switch 240 chip card I / O circuit 250 I / O interface, I / O pin of the chip card 300 reading device 400 System consisting of monitoring circuit and reading device RST reset signal Clk clock signal Vcc control voltage GND ground potential S Logical marker, set input of the flip-flop R Reset input of the flip-flop Q logical output of the flip-flop Q inverted logic output of the flip-flop QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited non-patent literature

[0000] ISO-7816-3 [0008, 0032]

Claims

[1] Monitoring circuit (100) for detecting faulty I / O signals of a chip card (200) or a chip module (200), comprising: a control module (10); and an electronic switching module (20); wherein an I / O input (11) of the monitoring circuit (10) is connectable to an I / O interface (210) of the chip card (200) or the chip module (200); wherein the electronic switching module (20) is configured to selectively connect the I / O input (11) to a ground potential; wherein the control module (10) is connected to the I / O input (11) and configured: to monitor a current voltage level of an I / O signal (1) at the I / O input (11) and to compare it with a corresponding expected reference voltage level; and based on the comparison, to set a logical marker (S) for the switching module (20) if the current voltage level deviates by more than a predefined threshold from a corresponding expected reference voltage level; wherein the electronic switching module (20) is configured to electrically connect the I / O input (11) to a ground potential when the logical marker (S) is set, so that data signals sent by the chip card (200) via the I / O interface (210) are permanently pulled to the ground potential and the chip card (200) is thus detected as faulty by a reading device (300) electrically connected in parallel to the monitoring circuit (100). [2] The monitoring circuit (100) of claim 1, wherein the control module (10) is further configured to periodically compare the current voltage level in accordance with the occurrence of edges of a clock signal (Clk) with a corresponding expected reference voltage level after the corresponding edge. [3] Monitoring circuit (100) according to claim 2, wherein the clock signal (Clk) is provided externally to the monitoring circuit (100) or is generated by the monitoring circuit (100) itself. [4] The monitoring circuit (100) of claim 2 or 3, wherein the expected reference voltage level after a rising edge of the I / O signal (1) corresponds to a voltage level associated with a logical one (2); and wherein the expected reference voltage level after a falling edge of the I / O signal (1) corresponds to a voltage level associated with a logical zero (3). [5] The monitoring circuit (100) of claim 4, wherein the expected reference voltage level associated with a logic one (2) corresponds to 5 V; and wherein the expected reference voltage level associated with a logic zero (3) corresponds to 0 V. [6] Monitoring circuit (100) according to one of the preceding claims, wherein the control module (10) is configured to start monitoring and comparing the voltage level at the I / O input (11) when a reset signal (RST) provided to the chip card (200) and the monitoring circuit (100) is active. [7] Monitoring circuit (100) according to claim 6, wherein the logical marker (S) remains set after setting until the reset signal (RST) is deactivated and then reset. [8] Monitoring circuit (100) according to one of the preceding claims, wherein the electronic switching element (20) comprises a flip-flop (21) and an electronic switch (22) which is controlled via an output (Q) of the flip-flop (21). [9] Monitoring circuit (100) according to claim 7, wherein the electronic switch (22) is a transistor. [10] System (400), comprising: a monitoring circuit (100) according to one of the preceding claims; and a reading device (200); wherein the monitoring circuit (100) is connected in electrical parallel circuit to the reading device (300); wherein the reading device (300) is configured to be communicatively connected to a chip module of a chip card (200); and wherein, if the logical marker (S) for the switching module (20) is set, the reading device (300) cannot read a response from the chip card (200) due to the parallel connection and thus recognizes the chip card as defective.

Images