Rate-controlled system for supplying power to an electric machine

Abstract

A slew rate controllable system for powering an electric machine. The system can include a variety of power transistors that can be operated to convert a DC input (DC) into an AC output (AC) suitable for powering the electric machine. The system can further include a gate driver system that can be operated to control a slew rate associated with switching the power transistors between the open and closed states.

Description

IntroductionThe present disclosure relates to systems configured for powering an electric machine, such as, but not necessarily limited to, a slew rate controllable system configured for managing transitions of power switches that provide electrical power to a traction motor of an electric vehicle.In a power conversion process, pulse width modulation, pulse density modulation, delta-sigma modulation, pulse frequency modulation, or other application-suitable binary (on / off) switching control signals may be used to enable switching of switches between different states for the purpose of powering an electric machine. The control signals may, for example, change the conductive state of the switches to generate electrical energy having an AC voltage waveform. Some of the more common switches used in higher power applications, such as for electric power supply to a traction motor of an electric vehicle, may be voltage and / or current controlled between states. A wide band gap (WBG), GaN, SiC, and other semiconductors such as metal oxide field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) may form a class of switches that support a variety of switching operations. The rate, speed, timing, and so forth of the switching operations, more specifically, the switching of the switches between on and off states or open and closed states, may be referred to as the rate of increase. Depending on the type of electric machine to be powered, such as when powering a traction motor to propel an electric vehicle, the ability to accurately select and control the slew rate may be advantageous to minimize second order effects such as surge voltages, electromagnetic interference (EMI), bearing current, voltage overshoot, and so forth.DESCRIPTION OF THE INVENTIONA non-limiting aspect of the present disclosure relates to a slew rate controllable system configured to be able to precisely select and control the slew rate of switches used for powering an electric machine. The slew rate controllable system may be particularly advantageous in accurately controlling the slew rate of power switches, transistors, and so forth used to facilitate powering a traction motor of the type commonly used for powering an electric vehicle. The slew rate controllable system may dynamically adjust and precisely control the slew rates according to a variety of operating and performance aspects to provide different switching speeds capable of balancing high switching slew rates relative to performance advantages and operating environment.One non-limiting aspect of the present disclosure relates to a slew rate controllable system for powering an electric machine. The system may include a plurality of power transistors operable to convert a DC input, DC, to an AC output, AC, suitable for supplying electrical power to the electric machine. The power transistors are operable to be switched between open and closed states to enable generation of the AC outputs. The system may further include a gate driver system operable to control a slew rate associated with switching the power transistors between the open and closed states. The gate driver system may include a plurality of gate driver circuits individually connected to a gate terminal of a corresponding power transistor.The gate driver system may comprise a gate driver operable to provide a control signal to the gate driver circuits suitable for optimizing the slew rate of the associated power transistor.The control signals may be operable to command the gate driver circuits to control a gate-source voltage, Vgs, between a gate terminal and a source terminal of the associated power transistor such that the Vgs controls the power transistors between the open and closed states.The control signals are operable to command gate driver circuits to control a gate current, Ig, to a gate terminal of the associated power transistor such that the Ig controls the power transistors between the open and closed states.The slew rate controllable system may include an intermediate circuit capacitor connected between the power transistors and a DC current source providing the DC input, wherein the control signals optionally optimize the discharge speed of the intermediate circuit capacitor to prevent or minimize overshoot of the voltage of the power transistors when transitioning between the open and closed states.The gate driver may be configured to generate the control signals in dependence on one or more of the following elements: a DC voltage of the DC current source, a temperature of the DC link capacitor, a current of one or more AC outputs and a junction temperature, a maximum discharge time, a drain-source voltage, Vds, and a voltage threshold, Vth, of one or more power transistors.The gate driver circuits may include an upper driver switch, an upper resistor, a lower resistor, and a lower switch, wherein the upper resistor and the lower resistor are connected in series between the upper driver switch and the lower driver switch, optionally wherein the gate terminal associated therewith is connected between a lower side of the upper resistor and an upper side of the lower resistor.The gate driver system may include an upper voltage source and a lower voltage source for each of the gate driver circuits, optionally wherein the upper voltage source is connected to the upper switch and the lower voltage source is connected to the associated lower switch.The gate driver circuits provide a gate voltage to the associated gate terminal, the gate voltage optionally being proportional to a voltage difference between the upper and lower voltage sources and the resistors of the upper and lower resistors.The control signals may be configured to selectively control the upper and lower switches between the open and closed states to adjust the gate voltages and thus the slew rate of the associated power transistor.The control signals may be pulse width modulated, PWM, signals operable between a high and a low voltage, optionally wherein the high voltage switches the upper or lower switch to the open state upon receipt and the low voltage switches the upper or lower switch to the closed state upon receipt.The gate driver may selectively vary a duty cycle for the PWM signals to control the slew rate of the power transistor associated therewith.The gate driver circuits may include an upper voltage source, a lower voltage source, an upper switch, a lower switch, and an upper resistor, optionally wherein the upper switch is connected in series with the upper voltage source and to an upper side of the upper resistor, the lower switch is connected in series with the lower voltage source and a lower side of the upper resistor, and the gate terminal associated therewith is connected to the lower side of the upper resistor.The gate driver circuits may include an upper voltage source, a lower voltage source, an upper switch, a lower switch, and a lower resistor, optionally wherein the upper switch is connected in series with the upper voltage source and to an upper side of the lower resistor, the lower switch is connected in series with the lower voltage source and a lower side of the lower resistor, and the gate terminal associated therewith is connected to the upper side of the lower resistor.One non-limiting aspect of the present disclosure relates to a slew rate controllable system for powering a traction motor of a vehicle. The system may include a plurality of power switches operable to convert a direct current (DC) input to an alternating current (AC) output to electrically power the traction motor. The power switches are operable to be switchable between open and closed states to enable the generation of the AC outputs. The system may further comprise a gate driver system operable to control a slew rate associated with switching the power switches between the open and closed states, optionally including a plurality of gate driver circuits individually connected to a gate terminal of a corresponding one of the power switches and operable to control a gate-source voltage (Vgs) between a gate terminal and a source terminal of the power switch associated therewith, the Vgs controlling the power switches between the open and closed states.The gate driver circuits may include an upper voltage source, a lower voltage source, an upper switch, an upper resistor, and a lower resistor, the upper switch being connected in series with the upper voltage source, the upper resistor, the lower resistor, and the lower voltage source, optionally wherein the associated gate terminal is connected between a lower side of the upper resistor and an upper side of the lower resistor.The gate driver system may be configured to generate control signals to control the Vgs of each gate driver circuit by controlling the upper and lower switches between open and closed states, respectively.The gate driver system may be configured to determine the control signals depending on a DC voltage of the DC input, a temperature of an DC link capacitor connected across the DC power source, a current of one or more AC outputs, and a junction temperature, a maximum discharge time, a drain-source voltage (Vds), or a voltage threshold (Vth) of one or more power switches.One non-limiting aspect of the present disclosure relates to a slew rate controllable system for powering a traction motor of a vehicle. The system may include a plurality of power switches operable to convert a direct current (DC) input to an alternating current (AC) output to electrically power the traction motor. The power switches are operable to be switchable between open and closed states to enable the generation of the AC outputs. The system may include a gate driver system operable to control a slew rate associated with switching the power switches between the open and closed states, optionally including a plurality of gate driver circuits individually connected to a gate terminal of a corresponding one of the power switches, the gate driver circuits operable to control a gate current (Ig) to a gate terminal of the power switch associated therewith, the Ig controlling the power switches between the open and closed states.The slew rate controllable system may include an intermediate circuit capacitor connected between the power switches and a DC power source operable to provide the DC input such that the gate drive system may control the slew rates of the power switches to optimize the discharge speed of the intermediate circuit capacitor to prevent or minimize voltage overshoot when transitioning between the open and closed states.These features and advantages, as well as other features and advantages of the present teachings, will be readily apparent from the following detailed description of the embodiments of the present teachings when taken in conjunction with the accompanying drawings. It should be understood that although the following figures and embodiments may be described separately, individual features thereof may be combined into additional embodiments.Brief Description of the DrawingsThe accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure. FIG. 1 shows a partial schematic view of a slew rate controllable system according to a non-limiting aspect of the present disclosure. FIG. 2 shows a partial schematic view of a gate driver circuit according to a non-limiting aspect of the present disclosure. FIG. 3 shows a controlled slew rate diagram in accordance with a non-limiting aspect of the present disclosure. FIG. 4 shows a partial schematic view of one of the gate driver circuits without the lower resistor, according to a non-limiting aspect of the present disclosure. FIG. 5 shows a partial schematic view of one of the gate driver circuits without the upper resistor, according to a non-limiting aspect of the present disclosure.DETAILED DESCRIPTIONAs needed, detailed embodiments of the present disclosure may be disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the disclosure that may be embodied in various and alternative forms. The figures are not necessarily to scale; some features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein need not be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present disclosure.FIG. 1 shows a partial schematic view of a slew rate controllable system 10 in accordance with a non-limiting aspect of the present disclosure. The system 10 may include a gate driver system 12 operable to power an electric machine 14, which for example purposes is predominantly described as an electric motor 14, typically referred to as a traction motor 14. The electric motor 14 may be of the type used in a vehicle, such as an electric vehicle, to provide a mechanical tractive force operable to propel the vehicle or may be utilized to perform other operations. As described in more detail below, the gate driver system 12 may be operable to fine select and control a slew rate for a plurality of power switches, transistors, and so forth. S1, S2,... S 6, which are used as part of a power inverter module (PIM) 16 to enable powering of the electric machine 14. The system 12 may dynamically adjust and precisely control the slew rates according to a variety of operating and performance considerations to provide different switching speeds capable of balancing high switching slew rates relative to performance advantages and operating environment. While predominantly the selective control of the rise rates for the switches S1, S2,... S 6 used in an electric vehicle would readily recognize by one of ordinary skill in the art that the capabilities of the system 12 are advantageous to enable powering other types of electric machines 14 that would similarly benefit from minimizing second order effects, such as surge voltages, electromagnetic interference (EMI), bearing current, voltage overshoot, and so forthThe vehicle may include a rechargeable energy storage system (RESS) 20 for storing and providing electrical energy to various systems onboard the vehicle. The RESS 20 may be a battery or other energy storage device capable of selectively supplying electrical energy to and receiving electrical energy from the electric machine 14 via the PIM 16. In powering the electric machine 14, the RESS 20 may be configured as a source for providing a direct current (DC) to the PIM 16. An intermediate circuit capacitor 24 may be interposed therebetween to smooth, filter, and otherwise process the DC input 22 for use with the PIM 16. The PIM 16 includes six power transistors / switches S 1, S 2,... S 6, each of which includes a gate terminal G, a drain terminal D, and a source terminal S. The gate terminal G of each switch S 1, S 2,... S 6 may each be separately and independently connected to one of a plurality of gate driver circuits 26. The switches S 1, S 2,... S6 may be implemented with a wide range of switches S1, S2,... S 6, including wide band gap semiconductors (WBG), GaN, SiC, and other similar semiconductors such as metal oxide field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs). The gate driver system 12 may include a gate controller 30 operable to individually and specifically control the gate driver circuits 26 to control the rate, speed, timing, and so forth of switching operations for the switches S 1, S 2,... S 6, that is to say to control the changeover of the switches S 1, S 2,... S6 between on and off states or open and closed states. The switching of the switches S 1, S 2,... S6 between states may be characterized as a slew rate, wherein the gate driver circuits 26 are operable to select the slew rate for each of the switches S1, S2,.... S 6 in dependence on corresponding control signals 32 provided by the gate controller 30. A non-limiting aspect of the present disclosure provides that the gate driver circuits 26 are operable to supply a gate voltage and / or a gate current to the gate terminal G associated therewith, wherein the corresponding gate voltage or the gate current is operable to supply the associated switch S 1, S 2,... S 6 to be transferred between open and closed states, that is to say to control whether the corresponding switch S 1, S 2,... S6 is active or inactive.The gate controller 30 may include a gate driver 34 configured to individually provide the control signals 32 to each of the gate driver circuits 26. The gate driver 34 can be used in this manner to switch operations for the switches S 1, S 2,... S 6, wherein the DC input 22 may be converted to an alternating current (AC) output 38. The AC output 38 may be generated in the manner illustrated to provide a polyphase output with a plurality of AC signals 40, 42, 44 operable for use in powering the electric machine 14, which for non-limiting purposes are illustrated as corresponding to a three-phase implementation in which a three-phase AC output 38 is provided to an AC bus or windings of the electric machine 14, for example via a corresponding input terminal for the associated AC input. As mentioned above, the use of the gate driver system 12 to facilitate a controllable slew rate based methodology for controlling switching operations and thus converting a DC input 22 to AC outputs 38 operable to power the electric machine 14 is illustrated for non-limiting purposes, as the present disclosure fully contemplates that the gate driver system 12 may be used in other environments and for other purposes. In the present disclosure, use of the gate driver system 12 to control slew rates for switches S 1, S 2,... S6 or other devices in addition to the application case shown, in which the switches S1, S2,... S 6 may be configured to operate as a unidirectional or bidirectional DC / AC converter.The gate controller 30 may include a non-transitory computer readable storage medium having stored thereon a plurality of non-transitory instructions that, when executed with one or more associated processors, are operable in accordance with the present disclosure to enable the generation of the control signals 32 in a manner that provides a desirable slew rate and simultaneously manages the AC outputs required for proper power supply of the electric machine 14. Although not shown in detail, a variety of sensors or other features may be used to measure or otherwise determine a DC voltage of the DC power source 20, a temperature of the DC link capacitor 24, a current of one or more of the AC outputs 38, and a junction temperature, a maximum discharge time, a drain-source voltage (Vds), a voltage threshold (Vth) of one or more of the switch / power transistors S 1, S 2,... S6. The gate controller 30 may process the sensor measurements, metrics, and so forth to provide a desired slew rate for each of the switches S 1, S 2. S 6, which may include selecting the control signals 32 to optimize the discharge speed of the DC link capacitor 24 to overshoot the voltage for the switches S 1, S 2,... S 6 are to be avoided or minimized when switching between the open and the closed state. The gate controller 30 may be used in this manner to increase the slew rates of the switches S 1, S 2,... S6 to change in real time, within and between switching actions and optionally also isolated to change the slew rates to be selected depending on operating conditions, desired power and so forth.FIG. 2 shows a partial schematic view of one of the gate driver circuits 26 in accordance with a non-limiting aspect of the present disclosure. While the connection for each switch S1, S2,... S 6 would be repeated separately, the gate driver circuit 26 is exemplarily shown as being connected to a gate terminal G of the switch S 1. The gate driver circuit 26 is thus illustrated as being connectable to the gate terminal G, as the switch S 1 is configured as a voltage and / or current controlled switch S 1, wherein a gate voltage and / or a gate current supplied to the gate terminal G may be used to switch the switch S 1 between an open and a closed state, i.e. to control switching operations. In the case that the switch S 1 uses a different configuration, the gate driver circuit 26 may be similarly adapted to supply voltage and / or current to the corresponding terminal. The gate driver circuit 26 may include an upper gate switch 46, an upper resistor 48, a lower resistor 50, and a lower gate switch 52, where the upper gate switch 46 is driven with an upper voltage source 58 and the lower gate switch 52 is driven with a lower voltage source 60. The upper gate switch 46 is connected in series to the upper voltage source 58, the upper resistor 48, the lower resistor 50, and the lower voltage source 60, the upper gate switch 46 is connected between the upper voltage source 58 and an upper surface of the upper resistor 48, the gate terminal G is connected between a lower side of the upper resistor 48 and an upper side of the lower resistor 50, the upper side of the lower resistor 50 is connected to the lower side of the upper resistor 48, and the lower gate switch 52 is connected between the lower voltage source 60 and a lower side of the lower resistor 50.The gate driver 34 may be configured to generate the control signals 32 with separate control signals 62, 64 that are operable to selectively open and close the upper and lower gate switches 46, 52 and thereby control the gate voltage and / or current supplied to the gate terminal G. The control signals 62, 64 may correspond to pulse width modulated (PWM) signals operable between a high voltage H and a low voltage L to control the upper and lower gate switches 46, 52 to a closed and an open state, respectively. The duty cycle of the control signals 32 may be varied to fine adjust the gate voltage and / or the gate current depending on the desired slew rate, for example to enable adjustment of the slew rate in real-time according to the desired operation of the electric machine 14. The PWM duty cycle control can be used to change the output current into and out of the gate G (capacitor) of the switch. The fastest gate speeds and slew rates may be preferred for delay and power consumption in switching. A method for controlling the PWM duty cycle may be based on the DC link voltage and current to ensure optimal efficiency and reliability. For example, for the 400-800 V system 12, the present disclosure may be used to adapt the PIM 16 for each bus. In the illustrated configuration, the control signals 62, 64 are operable to command the gate driver circuits 26 to control a gate-source voltage (Vgs) between the gate terminal G and the source terminal of the switch S 1, the Vgs controlling the power transistors between the open and closed states, and / or the control signals 62, 64 are operable to command the gate driver circuits 26 to control a gate current (Ig) to the gate terminal G, the Ig controlling the power transistors between the open and closed states. The Vgs and Ig supplied to the gate terminal G may be proportional to a voltage difference between the upper and lower voltage sources 58, 60 and the resistances of the upper and lower resistors 48, 50.The gate driver 34 may be configured to provide different control signals 32 to the upper and lower gate switches 46, 52, such as in the manner shown, where the control signals 32 may have different duty cycles. This ability to individually vary the duty cycle or other aspects of the control signals 32 used to transition the upper and lower gate switches 46, 52 between states may be advantageous to enable the gate controller 30 to control Vgs and / or Ig at a very fine and precise granularity, with the resulting voltage and current adjusted according to the upper and lower voltage sources 58, 60 and the resistance of the upper or lower resistors 48, 50. The gate controller 30 may optionally control the voltages provided with each of the upper and lower voltage sources 58, 60 to further improve its capabilities for fine selection of the voltage and / or current provided to the gate terminal G. In certain circumstances, the control signals 32 may be used, for example, to selectively open or deactivate one of the upper and lower gate switches 46, 52, optionally in conjunction with the change in voltages of the upper and lower voltage sources 58, 60, thereby further increasing specificity in selecting and achieving the desired slew rate.FIG. 3 shows a diagram 70 for a method of controlling the slew rate according to a non-limiting aspect of the present disclosure. The graph 70 includes a vertical axis 72 for voltage and current and a horizontal axis 74 for time. A first waveform 78 represents the voltage between the drain and source terminals (Vds), a second waveform 80 represents the current through the drain terminal (Id), a third waveform 82 represents Vgs, and a fourth waveform 84 represents Ig. The diagram 70 illustrates an example scenario in which the rate of rise of the switch S 1, i.e., dV / dt and / or dI / dt, may be selectively controlled according to the switching characteristics of the switch S 1. The time period before time T 0 may correspond to switch S 1 being off or active, whereupon gate driver circuit 26 begins powering gate terminal G at an initial slew rate at time T 0. From time T 0 to time T 1, the initial slew rate may be maintained as Id increases. At about time T 1 or shortly thereafter, as the slope of Vgs decreases and / or Vds decreases, driver circuit D may begin powering gate terminal G at an average slew rate, which may be useful to control a slope or rate at which Vds decreases accordingly. At about time T 2, or as Vds reaches or approaches its minimum, a final or greater slew rate may be implemented. The possibility of selectively controlling Vgs and / or Ig during the changeover of the switch S 1 may be advantageous in maximizing the power, in particular the rate of rise, when the switch S 1 passes through different states which are associated with the changeover from an open state to a closed state. The method can proceed in such a way that the rate of rise for the drive circuits 26 and the changeover associated therewith of the switches S 1, S 2,... S 6 may be implemented to control the DC-AC conversion required for powering the electric machine 14.FIG. 4 shows a partial schematic view of one of the gate driver circuits 26 without the lower resistor 50 according to a non-limiting aspect of the present disclosure. FIG. 5 shows a partial schematic view of one of the gate driver circuits 26 without the top resistor 48, according to a non-limiting aspect of the present disclosure. These alternative configurations for the gate driver circuits 26 may illustrate the ways of the present disclosure to minimize or reduce the number of circuit components while still maintaining the desired levels of slew rate control. Although not shown, it is also conceivable within the scope of the present disclosure to omit the upper and / or lower switches 46, 52. Each of the drive circuits 26 illustrated in FIGS. 2, 4 and / or 5 may be used simultaneously, for example, some of the switches S 1, S 2,... S6 may be connected to one type of drive circuits 26, while one or more of the other switches S1, S2,... S 6 are connected to drive circuits 26 having a different configuration. This possibility can further improve the advantageous control of the rates of rise in the manner considered here.As set forth above, the present disclosure relates to a system and method for real-time control of the slew rate (SR) of power transistors for inverters and inverters. It may include minimal amounts of hardware in the form of a voltage / current source and a low voltage pulse modulated switch for controlling the gate current to realize multiple slew rates. This allows the gate driver circuit to be converted into a charge pump for the gate capacitor, allowing advantageous control methods by variable speed gate driver circuits that allow fine tuning of switching performance to optimize loss, overshoot, EMI, and bearing current. In this way, the gate driver circuits are operable to turn the power switches on and off to convert the electrical power between DC and AC, optionally with more rapid switching, minimum switching losses, and improved maximum performance, thereby limiting the effects of electrical loading of the power switches, oscillating, conductive and radiated EMI, and overshoot of motor terminal (PDIV) voltage and bearing current. The gate driver system may have the following design features: pulse modulation control to change transistor switching speed in real time as well as between and within switching operations; applicability to voltage and current source based or hybrid gate drives; feedforward control using look-up tables (LUTs) to change switching speed depending on operating conditions, i.e., Vdc, current, Vth, and junction temperature; feedback control based on operating conditions, transistor signal sensing, and part-to-part variations and degradations; tuning the pulse modulation control at maximum junction temperature for on-transients and at minimum junction temperature for off-transients; Slew rate control for compensating transistor / switch part-to-part variations, i.e., Vth, gate resistance, leakage inductance; class D topology for the pulse modulation based gate driver system; modulation control for controlling the slew rate to realize capacitor discharge and simultaneously handle I / V overshoots; slew rate control for turning semiconductor relay (SSR) / E fuses on / off to handle I / V overshoots and protect capacitor and battery; control of the slew rate to increase losses in BEV HEAT and to decrease turn-off time in a short circuit of the switch; Control for regulating dI / dt to prevent secondary effects of a change in dV / dt; keeping the EMI frequency constant; and / or high voltage discharge by keeping one side of the switches on and connecting the other side of the switches to the PWM-based slew rate control on the side (high side or low side) to cope with voltage overshoot.The terms "consisting of", "including", and "with" are inclusive and therefore specify the presence of particular features, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, or components. The order of steps, processes, and operations may be changed as possible, and additional or alternative steps may be used. The term "or" used in this specification includes all combinations of the listed elements. The term "each of" includes any possible combination of the listed items, including "each of" the listed items. The terms "A", "an", "the", "at least one", and "one or more" are used interchangeably to indicate that at least one of the points is present. Several of these elements may also be present unless the context clearly indicates otherwise. All values of parameters (e.g., sizes or conditions), unless expressly stated or otherwise indicated in the context including the appended claims, are to be understood as being modified in all instances by the term "over", whether or not "over" actually appears before the value. A component that is "configured" to perform a particular function is capable of performing the specified function without any change, and not only has the potential to perform the specified function after further changes. In other words, when the described hardware is expressly configured to perform the specified function, it is specifically selected, created, implemented, used, programmed, and / or designed to perform the specified function.While various embodiments have been described, the description is to be considered as exemplary and not limiting, and it will be apparent to those skilled in the art that many other embodiments and implementations are possible that fall within the scope of the embodiments. Each feature of an embodiment may be used in combination with or in place of another feature or element in another embodiment, unless expressly limited. Accordingly, the embodiments are not to be limited except in view of the appended claims and their equivalents. Various modifications and changes may also be made within the scope of the appended claims. Although various ways of carrying out the many aspects of the present teachings have been described in detail, those familiar with the art to which this teachings relate will recognize various alternative aspects for carrying out the present teachings that fall within the scope of the appended claims. It is intended that all matter contained in the above description or shown in the accompanying drawings be interpreted as illustrative and exemplary of the entire range of alternative embodiments that a person of ordinary skill in the art would recognize as implicit, structural, and / or functionally equivalent, or otherwise as obvious based on the content contained, and not limited to only the expressly illustrated and / or described embodiments.

Claims

A slew rate controllable system for powering an electric machine, comprising: a plurality of power transistors operable to convert a direct current, DC, input to an alternating current, AC, output suitable for powering the electric machine, the power transistors operable between an open state and a closed state to enable generation of the AC output; and a gate driver system operable to control a slew rate associated with switching the power transistors between the open and closed states, the gate driver system comprising a plurality of gate driver circuits individually connected to a gate terminal of a corresponding one of the power transistors.The slew rate controllable system of claim 1, wherein: the gate driver system comprises a gate driver operable to provide a control signal to the gate driver circuits suitable for optimizing the slew rate and for controlling the power switches to generate the AC output.The slew rate controllable system of claim 2, wherein: the control signals are operable to command the gate driver circuits to control a gate-source voltage, Vgs, between a gate terminal and a source terminal of the power transistor associated therewith, the Vgs controlling the power transistors between the open and closed states.The slew rate controllable system of claim 2, wherein: the control signals are operable to command the gate driver circuits to control a gate current, Ig, to a gate terminal of the power transistor associated therewith, the Ig controlling the power transistors between the open and closed states.The slew rate controllable system of claim 2, further comprising: an intermediate circuit capacitor connected between the power transistors and a DC current source providing the DC input, wherein the control signals optimize the discharge speed of the intermediate circuit capacitor to prevent or minimize overshoot of the voltage of the power transistors when transitioning between the open and closed states.The slew rate controllable system of claim 5, wherein: the gate driver is configured to generate the control signals in response to one or more of a DC voltage of the DC current source, a temperature of the DC link capacitor, a current of one or more of the AC outputs, and a junction temperature, a maximum discharge time, a drain-source voltage, Vds, and a voltage threshold, Vth, of one or more power transistors.The slew rate controllable system of claim 2, wherein: the gate driver circuits comprise an upper driver switch, an upper resistor, a lower resistor, and a lower switch, the upper resistor and the lower resistor being connected in series between the upper driver switch and the lower driver switch, the gate terminal associated therewith being connected between a lower side of the upper resistor and an upper side of the lower resistor.The slew rate controllable system of claim 7, wherein: the gate driver system comprises an upper voltage source and a lower voltage source for each of the gate driver circuits, the upper voltage source being connected to the upper switch and the lower voltage source being connected to the lower switch associated therewith.The slew rate controllable system of claim 2, wherein: the gate driver circuits comprise an upper voltage source, a lower voltage source, an upper switch, a lower switch, and an upper resistor, the upper switch being connected in series with the upper voltage source and to an upper side of the upper resistor, the lower switch being connected in series with the lower voltage source and a lower side of the upper resistor, and the gate terminal associated therewith being connected to the lower side of the upper resistor.The slew rate controllable system of claim 2, wherein: the gate driver circuits comprise an upper voltage source, a lower voltage source, an upper switch, a lower switch, and a lower resistor, the upper switch being connected in series with the upper voltage source and to an upper side of the lower resistor, the lower switch being connected in series with the lower voltage source and a lower side of the lower resistor, and the gate terminal associated therewith being connected to the upper side of the lower resistor.

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