Semiconductor storage devices with flying bit conductors and methods for their manufacture

Abstract

A storage device comprises: a first storage matrix with first memory cells; a second storage matrix with second memory cells; a third storage matrix with third memory cells, the second storage matrix being arranged between the first and third storage matrices along a transverse direction; a first bit-line segment extending along the transverse direction and connected to each of the first memory cells; a second bit-line segment extending along the transverse direction and connected to each of the second memory cells; and a third bit-line segment extending along the transverse direction and connected to each of the third memory cells. The first bit-line segment is fabricated in a first metallization layer, the second bit-line segment is fabricated in a second metallization layer, and the third bit-line segment is fabricated in a third metallization layer.

Description

Cross-reference to related application

[0001] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 512,359, filed July 7, 2023, and U.S. Provisional Patent Application Serial No. 63 / 517,781, filed August 4, 2023, each of which is incorporated by reference into this application. background

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density is largely due to repeated reductions in the minimum feature size, allowing more components to be integrated into a given area. Short description of the drawings

[0003] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Rather, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 shows a block diagram of a memory device according to some embodiments. Fig. 2 shows a schematic diagram of a memory cell according to some embodiments. Fig. Figure 3 shows a schematic block diagram of an implementation of the memory device of Fig. 1 according to some embodiments. Fig. 4 shows a perspective view of a semiconductor device with multiple metallization layers fabricated over a substrate, according to some embodiments. Fig. 5 shows an exemplary sectional view of the Fig. 3 shown implementation of the memory device according to some embodiments. Fig. 6 shows another exemplary sectional view of the Fig. 3 shown implementation of the memory device according to some embodiments. Fig. Figure 7 shows a schematic block diagram of another implementation of the memory device of Fig. 1 according to some embodiments. Fig. Figure 8 shows a schematic block diagram of yet another implementation of the memory device of Fig. 1 according to some embodiments. Fig. 9 shows an exemplary plan view of the Fig. 8, according to some embodiments. Fig. 10 shows an exemplary sectional view of the Fig. 8, according to some embodiments. Fig. 11 shows an example flow diagram of a method of manufacturing a memory device according to some embodiments. Fig. 12 shows an exemplary flow diagram of another method of manufacturing a memory device according to some embodiments. Detailed description

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present disclosure, reference numbers and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structural element to one or more other elements or structural elements illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90° or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0006] A semiconductor memory device is an electronic data storage device implemented on a semiconductor-based integrated circuit. A semiconductor memory device includes various types and has faster access times than other data storage technologies. For example, a byte of data can often be written to or read from a semiconductor memory device within a few nanoseconds, while access times for circulating memories, such as hard disks, are in the range of milliseconds. For these reasons, among others, the semiconductor memory device is used as a primary storage mechanism, allowing computers to hold data they are currently processing.

[0007] A static random access memory (SRAM) is a type of semiconductor memory device that stores data in the form of bits using bistable circuits without the need for refreshing. An SRAM cell can be referred to as a bit cell because it stores one bit of information. A memory array typically contains multiple bit cells arranged in rows and columns. Each bit cell in a memory array may have connections to a supply voltage and a reference voltage. Bit lines (BLs) can be used to access a bit cell, while a word line (WL) controls connections to the BLs.A WL may be connected to a corresponding group of bit cells arranged in a row of a memory matrix, with different WLs being provided for respective rows, and a BL may be connected to a corresponding group of bit cells arranged in a column of a memory matrix, with different BLs being provided for respective columns.

[0008] A memory bank containing at least one memory matrix often has memory cells ranging in size from approximately 128 rows to approximately 512 rows. With the trend toward ever-shrinking feature sizes, a memory bank can accordingly have an increasing number of rows. However, the increased number of rows typically leads to long BLs and thus to high loads on the BLs. The high loads on the BLs can, in turn, lead to high minimum read voltages and high minimum write voltages on the BLs. Read voltages and write voltages that are lower than the high minimum read voltages and the high minimum write voltages, respectively, lead to instability when reading from and writing to the memory cells. Furthermore, the high minimum read voltages and high minimum write voltages can, in turn, result in high dynamic power consumption.

[0009] One solution to mitigate the effects of long BLs is to use smaller memory banks. For example, a large memory bank with 128 rows can be replaced by two small memory banks of 64 rows each. However, increasing the number of memory banks also increases the area occupied by the memory banks, which can increase costs. In this context, another solution has been proposed to divide the long BL into several (e.g., 2) segments, each operatively connected to a respective part of the memory bank. For example, a long BL is divided into a first BL segment and a second BL segment, with a BL control circuit (e.g., a driver) connected through the first and second BL segments to a first (near) part and a second (far) part of the memory bank, respectively.In addition, the BL control circuit uses another BL fabricated in a metallization layer higher than the first and second BL segments to connect to the second BL segment.

[0010] While the effects of high stress on a long BL can be mitigated by the individual BL segments, the spacing between adjacent BLs (e.g., across different columns) becomes smaller. As technology improves and feature sizes become smaller, neighboring BLs become even closer together. However, this close spacing leads to a significant amount of capacitive coupling. This capacitive coupling, in turn, can result in long read and write times and also lead to a deterioration of signal-to-noise margins. Thus, the existing memory device is still not entirely satisfactory in some respects.

[0011] The present disclosure provides various embodiments of a memory device comprising a plurality of BLs, each divided into a plurality of BL segments, with adjacent BLs laterally spaced at a greater pitch than in existing memory devices. Thus, at least one of the problems of high loading on a long BL or high capacitive coupling between adjacent BLs can be solved.

[0012] In one non-limiting aspect of the present disclosure, each BL of the disclosed memory device disposed in a first metallization layer may be divided into three or more BL segments, e.g., a first, a second, and a third BL segment. A BL controller of the memory device may be operatively connected to a first portion of a corresponding memory bank (sometimes referred to as a lower memory array) through the first BL segment. The BL controller may also be operatively connected to a second portion of the memory bank (sometimes referred to as a middle memory array) through the second BL segment, as well as through another (e.g., a flying) BL disposed in a second metallization layer.The term "flying BL" as used herein may refer to a BL that physically moves across a memory array (or memory portion) but is not operatively connected to that memory array (or memory portion). The BL controller may also be operatively connected to a third portion of the memory bank (sometimes referred to as an upper memory array) through the third BL segment, as well as another flying BL disposed in a third metallization layer. By using the third metallization layer (or by dividing a long BL into at least three segments), design constraints on the size of a memory array can be significantly reduced. For example, the load on each BL can be further reduced, advantageously allowing the memory array to contain a higher number of rows while protecting its BLs against high loads.

[0013] In a further non-limiting aspect of the present disclosure, each BL of the disclosed memory device arranged in a first metallization layer may be divided into two or more BL segments, e.g., a first and a second BL segment. A BL controller of the memory device may be operatively connected to a first portion of a corresponding memory bank (sometimes referred to as a lower memory matrix) through the first BL segment, wherein a complementary first BL segment is also arranged in the first metallization layer. The BL controller of the memory device may be operatively connected to a second portion of the memory bank (sometimes referred to as an upper memory matrix) through the second BL segment, wherein a complementary second BL segment is also arranged in the first metallization layer. In addition, the memory device may have a further (e.g.,Flying BLs can comprise a first (flying) BL arranged in a second metallization layer and connecting the BL controller to the second BL segment, and yet another flying BL also arranged in the second metallization layer and connecting the BL controller to the complementary second BL segment. These two flying BLs can be arranged along the same column as the first and second BL segments or along the next adjacent column. Following this principle, two corresponding flying BLs for the next adjacent column can be fabricated along the same column as the first and second BL segments or along the next adjacent column, but in a third metallization layer. Design constraints for the BL segments (and / or other metallic traces), e.g., in the first metallization layer, can be significantly reduced.Accordingly, the capacitive coupling between the adjacent BLs in the first metallization layer can be advantageously reduced.

[0014] Fig. 1 shows a block diagram of a memory device 100 according to some embodiments. As shown, the memory device 100 includes a memory controller 105 and a memory bank 120. The memory bank 120 may include a plurality of memory circuits or memory cells 125 arranged in two- or three-dimensional arrays. Each memory cell 125 may be connected to a corresponding word line WL and a corresponding bit line BL (or a pair of BLs). The memory controller 105 may write data to or read data from the memory bank 120 according to electrical signals over the word lines WL and the bit lines BL. In other embodiments, the memory device 100 includes more, fewer, or different components than those shown in Fig. 1 are shown.

[0015] Memory bank 120 is a hardware component that stores data. In one aspect, memory bank 120 is embodied as a semiconductor memory device. Memory bank 120 includes a plurality of memory circuits or memory cells 125. Memory bank 120 includes word lines WL0, WL1...WL J , each extending in a first direction (e.g., the x-direction), and bit lines BL0, BL1 ... BL K , each extending in a second direction (e.g., the y-direction). In various embodiments of the present disclosure, the word lines WL0 to WL J occasionally as lines ROW0 to ROW J and the bit lines BL0 to BL K can occasionally be used as columns COL0 to COL KThe word lines WL and the bit lines BL may each be implemented as one or more metallic or conductive traces arranged in respective metallization layers. In one configuration, each memory cell 125 is connected to a corresponding word line WL and a corresponding bit line BL, and may be operated according to voltages or currents through the corresponding word line WL and the corresponding bit line BL.

[0016] In various embodiments, each bit line BL comprises bit lines BL, BLB (which is complementary to BL) connected to a group of memory cells 125 arranged along the second direction (e.g., the y-direction) or along a corresponding one of the columns COL0 to COL Kare arranged. The bit lines BL, BLB can receive and / or provide differential signals. Each memory cell 125 can comprise a volatile memory, a non-volatile memory, or a combination thereof. In some embodiments, each memory cell 125 can be implemented as an SRAM (Static Random Access Memory) cell, a DRAM (Dynamic Random Access Memory) cell, or another type of memory cell. For example, each memory cell 125 can be implemented as an RRAM (Resistive Random Access Memory) cell, a PCRAM (Phase Change Random Access Memory) cell, or an MRAM (Magnetoresistive Random Access Memory) cell. In some embodiments, the memory bank 120 includes other lines (e.g., select lines, reference lines, reference control lines, power lines, etc.).

[0017] Memory controller 105 is a hardware component that controls operations of memory bank 120. In some embodiments, memory controller 105 includes at least a bitline controller 112 and a wordline controller 114. Bitline controller 112 and wordline controller 114 may be embodied as logic circuits, analog circuits, or a combination thereof. In one configuration, wordline controller 114 is a circuit that provides a voltage or current across one or more wordlines WL of memory bank 120, and bitline controller 112 is a circuit that provides or senses a voltage or current across one or more bitlines BL of memory bank 120. Bitline controller 112 may be connected to bitlines BL of memory bank 120, and wordline controller 114 may be connected to wordlines WL of memory bank 120.In some embodiments, memory controller 105 includes more, fewer, or different components than those shown in . Fig. 1 are shown.

[0018] For example, memory controller 105 may include a timing controller 110 configured to generate control signals for coordinating operations of bitline controller 112 and wordline controller 114. In one approach, to write data to a memory cell 125, timing controller 110 may cause wordline controller 114 to apply a voltage or current to memory cell 125 via a wordline WL connected to memory cell 125, and may cause bitline controller 112 to apply a voltage or current corresponding to the data stored in memory cell 125 via a bitline BL connected to memory cell 125.In one approach, to read data from a memory cell 125, the timing controller 110 may cause the word line controller 114 to apply a voltage or current to the memory cell 125 via a word line WL connected to the memory cell 125, and may cause the bit line controller 112 to sample a voltage or current corresponding to the data stored in the memory cell 125 via a bit line BL connected to the memory cell 125.

[0019] Fig. 2 shows a schematic diagram of memory cell 125, implemented, for example, as an SRAM cell, according to some embodiments. Hereinafter, memory cell 125 may occasionally be referred to as SRAM cell 125. In some embodiments, SRAM cell 125 includes n-type transistors N1, N2, N3, N4 and p-type transistors P1, P2. N-type transistors N1, N2, N3, N4 may be planar n-type metal-oxide-semiconductor field-effect transistors (n-MOSFETs), n-fin field-effect transistors (n-FinFETs), n-gate-all-around field-effect transistors (n-GAA-FETs), or various other n-type transistor structures. P-type transistors P1, P2 may be p-type MOSFETs, p-FinFETs, p-GAA-FETs, or various other p-type transistor structures. These components may cooperate to store a bit of data. In other embodiments, SRAM cell 125 contains more, fewer, or different components than those shown in Fig. 2 are shown.

[0020] In one configuration, the n-type transistors N3, N4 have gate electrodes connected to a word line WL. In one configuration, a drain electrode of the n-type transistor N3 is connected to a bit line BL, and a source electrode of the n-type transistor N3 is connected to a terminal Q. In one configuration, a drain electrode of the n-type transistor N4 is connected to a bit line BLB, and a source electrode of the n-type transistor N4 is connected to a terminal QB. In one aspect, the n-type transistors N3, N4 function as electrical switches. According to a voltage applied to the word line WL, the n-type transistors N3, N4 can electrically connect or disconnect the bit line BL to or from the terminal Q, and the bit line BLB can electrically connect or disconnect the bit line QB.For example, according to a power supply voltage VDD corresponding to an H state (or a logic value "1") applied to the word line WL, the n-type transistor N3 is activated to electrically connect the bit line BL to the Q terminal, and the n-type transistor N4 is activated to electrically connect the bit line BLB to the Q terminal. In another example, according to a ground voltage GND corresponding to an L state (or a logic value "0") applied to the word line WL, the n-type transistor N3 is deactivated to electrically disconnect the bit line BL from the Q terminal, and the n-type transistor N4 is deactivated to electrically disconnect the bit line BLB from the Q terminal.

[0021] In one configuration, the n-type transistor N1 has a source electrode connected to a first supply voltage bus and providing the ground voltage GND; a gate electrode connected to the QB terminal; and a drain electrode connected to the Q terminal. In one configuration, the p-type transistor P1 has a source electrode connected to a second supply voltage bus and providing the supply voltage VDD; a gate electrode connected to the QB terminal; and a drain electrode connected to the Q terminal. In one configuration, the n-type transistor N2 has a source electrode connected to the first supply voltage bus and providing the ground voltage GND; a gate electrode connected to the Q terminal; and a drain electrode connected to the QB terminal.In one configuration, the p-type transistor P2 includes a source electrode connected to the second supply voltage bus and providing the supply voltage VDD; a gate electrode connected to the Q terminal; and a drain electrode connected to the QB terminal. In this configuration, the n-type transistor N1 and the p-type transistor P1 operate as an inverter, and the n-type transistor N2 and the p-type transistor P2 also operate as an inverter, such that two inverters form cross-connected inverters. In one aspect, the cross-connected inverters can sense and amplify a voltage difference at the Q, QB terminals. When writing data, the cross-connected inverters can sense voltages at the Q, QB terminals provided via the n-type transistors N3, N4 and amplify a voltage difference on the bit lines BL, BLB.For example, the cross-connected inverters sample a voltage of 0.5 V at terminal Q and a voltage of 0.4 V at terminal QB and amplify a voltage difference at terminals Q and QB via positive feedback (or loopback) so that the voltage at terminal Q becomes the supply voltage VDD (e.g., 1 V) and the voltage at terminal QB becomes the ground voltage GND (e.g., 0 V). The amplified voltages at terminals Q and QB can be provided to bit lines BL and BLB for reading via n-type transistors N3 and N4, respectively.

[0022] Fig. 3 shows a schematic block diagram of an implementation of a portion of the memory device 100 according to some embodiments. In Fig. 3, for example, a portion of the memory bank 120 and a portion of the BL controller 112 are shown. Also shown are some of the BLs and their functionally equivalent segments (e.g., each implemented as a metallic trace disposed in a corresponding metallization layer). It is understood that the schematic block diagram of Fig. 3 is for illustrative purposes only and therefore the memory device 100 may be implemented as one of several other suitable configurations, which is also within the scope of the present disclosure.

[0023] As shown, the memory bank 120 may be functionally divided into three matrices: a lower matrix 120B, a middle matrix 120M, and an upper matrix 120T. In a non-limiting example where the memory bank 120 has 1024 rows (e.g., 1024 WLs), the lower matrix 120B may have 512 rows (e.g., 512 WLs), and the middle matrix 120M and the upper matrix 120T may each have 256 rows (e.g., 256 WLs). However, a different arrangement on the individual matrices with the respective sizes may also be envisaged, which is also within the scope of the present disclosure. According to these individual matrices, the BL controller 112 may have three sub-BL controllers, namely a lower BL controller 112B, a middle BL controller 112M, and an upper BL controller 112T.In various embodiments, each of the sub-BL controllers 112B, 112M, and 112T may include at least one multiplexer configured to activate or otherwise select one or more BLs based on a received address signal. Furthermore, each of the sub-BL controllers 112B, 112M, and 112T may be operatively connected to the memory cells 125 of the corresponding array through a respective group of BLs (e.g., by applying a voltage signal to the memory cells 125).

[0024] Functionally, the partial BL controllers 112B, 112M and 112T are each connected by a pair of BLs (BL and BLB) to the memory cells 125 of a corresponding single matrix, as shown in Fig. 1. In various embodiments, some of these functional BLs and BLBs that span one or more memory arrays may each be physically implemented as one or more lateral segments (e.g., metallic traces) and one or more vertical interconnects (e.g., via structures) that are interconnected, as will be explained in more detail later.

[0025] As in Fig. 3, the memory bank 120 is divided into three matrices along the BL direction (e.g., the y-direction) while maintaining the arrangement along the WL direction (e.g., the x-direction). It should therefore be noted that each of the sub-BL controllers 112B, 112M, and 112T remains connected to all BLs of the memory bank 120, but is only connected to different subsets of the WLs of the memory bank 120. In the following discussion, which begins with Fig. 3, examples are provided showing the arrangement between the sub-BL controllers 112B, 112M, and 112T and a representative column (e.g., COL0). The arrangements between the sub-BL controllers 112B, 112M, and 112T and other columns (e.g., COL1, COL2, COL3) are not repeated.

[0026] For example, the lower BL controller 112B may be operatively connected to the memory cells 125 of the lower array 120B (sometimes referred to as lower memory cells 125B) in COL0 through BL segments 310B and 315B. The middle BL controller 112M may be operatively connected to the memory cells 125 of the middle array 120M (sometimes referred to as middle memory cells 125M) in COL0 through BL segments 320 and 325, as well as through BL segments 330 and 335, as well as through BL segments 310M and 315M. The upper BL controller 112T may be operatively connected to the memory cells 125 of the upper array 120T (occasionally referred to as upper memory cells 125T) in COL0 through BL segments 340 and 345, as well as through BL segments 350 and 355, and through BL segments 310T and 315T. In some embodiments, the BL segments 310B and 315B may be associated with the portions of BL0 and BL0 (i.e.,, BL / BLB in COL0), each operatively connected to memory cells 125B in COL0. BL segments 320, 330, and 310M, as well as 325, 335, and 315M, may correspond to portions of BL0 and BLB0 (i.e., BL / BLB in COL0), each operatively connected to memory cells 125M in COL0. BL segments 340, 350, and 310T, as well as 355, 355, and 315T, may correspond to portions of BL0 and BLB0 (i.e., BL / BLB in COL0), each operatively connected to memory cells 125T in COL0.

[0027] In some embodiments of the present disclosure, BL segments 310B, 315B, 310M, 315M, 310T, and 315T may be disposed, embedded, or otherwise fabricated in a first of a plurality of metallization layers formed over a substrate. This first metallization layer is sometimes referred to as a "Mo layer," and the metallic traces (e.g., copper traces) formed therein are referred to as "Mo traces." BL segments 310B, 315B, 310M, 315M, 310T, and 315T may each be fabricated as a Mo trace extending along a first transverse direction (e.g., the y-direction). In addition, the BL segments 310B, 315B, 310M, 315M, 310T, and 315T are electrically and physically isolated from each other by a dielectric material (e.g., oxide-based dielectric materials or various other low-k dielectric materials) of the Mo layer.For example, BL segments 310B, 310M, and 310T are spaced apart along the y-direction. In some embodiments, BL segments 310B, 310M, and 310T may be fabricated around (e.g., above) memory arrays 120B, 120M, and 120T, respectively. Complementary BL segments 315B, 315M, and 315T may be fabricated in a similar manner, and therefore, the description will not be repeated.

[0028] Additionally, BL segments 330 and 335 may be disposed, embedded, or otherwise fabricated in a second of the metallization layers. This second metallization layer is sometimes referred to as an "M1 layer," and the metallic traces (e.g., copper traces) fabricated therein are referred to as "M1 traces." BL segments 330 and 335 may each be fabricated as an M1 trace extending along a second transverse direction (e.g., the x-direction). BL segments 320 and 325 may be disposed, embedded, or otherwise fabricated in a third of the metallization layers. This third metallization layer is sometimes referred to as an "M2 layer," and the metallic traces (e.g., copper traces) fabricated therein are referred to as "M2 traces."BL segments 320 and 325 may each be formed as an M2 trace extending along the first transverse direction (e.g., the y-direction). BL segments 350 and 355 may be disposed, embedded, or otherwise formed in a fourth of the metallization layers. This fourth metallization layer is sometimes referred to as an "M3 layer," and the metallic traces (e.g., copper traces) formed therein are referred to as "M3 traces." BL segments 350 and 355 may each be formed as an M3 trace extending along the second transverse direction (e.g., the x-direction). BL segments 340 and 345 may be disposed, embedded, or otherwise formed in a fifth of the metallization layers. This fifth metallization layer is sometimes referred to as an “M4 layer”, and the metallic conductors produced therein (e.g.Copper traces) are referred to as "M4 traces." BL segments 340 and 345 can each be manufactured as an M4 trace extending along the first transverse direction (e.g., the y-direction).

[0029] Fig. 4 shows a perspective view of a semiconductor device 400 with arrangements of the aforementioned components, e.g., the memory cells 125, the metallization layers Mo to M4, and the metallic interconnects Mo to M4 arranged therein, according to some embodiments. It is understood that the arrangements shown in Fig. 4 are merely a non-limiting implementation of the (in Fig. 3) and do not limit the scope of the present disclosure.

[0030] As shown, a plurality of memory cells 125 may be fabricated along a main surface (e.g., a front side) of a substrate 402 as a matrix, e.g., across multiple rows (extending in the x-direction) and multiple columns (extending in the y-direction). The lower matrix 120B, the middle matrix 120M, and the upper matrix 120T may each be fabricated in different lateral regions of the substrate 402. As a representative example, Fig. 4 shows a memory cell, e.g., 125B, 125M, 125T, arranged in one of the columns of each corresponding memory matrix.

[0031] A plurality of metallization layers are formed over the main surface of substrate 402. For example, a plurality of Mo conductive lines (e.g., BL segments 310B, 310M, 310T) are disposed in an immediately adjacent upper metallization layer (Mo layer). The Mo conductive lines may extend along the column direction of the memory array (e.g., along the y-direction). A plurality of M2 conductive lines (e.g., BL segment 320) are disposed above the Mo layer in the M2 layer, with the M1 layer in between. The M2 conductive lines may also extend along the column direction of the memory array (e.g., along the y-direction). The M1 layer contains one or more M1 traces (e.g., BL segment 330) that connect at least one of the M2 traces to a corresponding Mo trace. The M1 trace may extend along the row direction of the memory array (e.g., along the x-direction).Above the M2 layer, a plurality of M4 traces (e.g., BL segment 340) are arranged in the M4 layer, with the M3 layer in between. The M4 traces may also extend along the column direction of the memory array (e.g., along the y-direction). The M3 layer contains one or more M3 traces (e.g., BL segment 350) that connect at least one of the M4 traces to a corresponding M2 trace. The M3 trace may extend along the row direction of the memory array (e.g., along the x-direction).

[0032] By configuring these BL segments in this way, some of the M2 traces connected to the middle matrix 120M can overfly the lower matrix 120B, as shown in Fig. 4. Therefore, these flying M2 traces can each extend further than the (e.g., deeper) Mo traces can extend along the column direction (the y-direction). Similarly, some of the M4 traces connected to the upper matrix 120T can fly over the lower matrix 120B and the middle matrix 120M. Therefore, these flying M4 traces can each extend further than the (e.g., deeper) Mo traces can extend along the column direction (the y-direction). By dividing a memory bank into at least three parts (matrices) and connecting these parts to the BLs, which are arranged in different metallization layers, (e.g.,Front-end) loads on each of the BLs can be significantly reduced because each BL is functionally connected to a smaller number of SRAM cells while maintaining a relatively large memory bank size.

[0033] Fig. Figure 5 shows an exemplary cross-sectional view of the non-limiting implementation of the memory device 100 (which is shown in the Fig. 3 and Fig. 4). The sectional view of Fig. 5 is taken along the row direction of the lower matrix 120B (e.g., along the x-direction) to show two columns COL0 and COL1. It should be understood that the sectional view can be similarly extended to other columns, and therefore, the description will not be repeated. As shown, a Mo layer, an M2 layer, and an M4 layer are formed on the front side of the substrate 402, with one or more additional layers (e.g., a device layer including the front-end memory cells 125 and at least one middle-end interconnect layer) disposed between the Mo layer and the substrate 402.

[0034] In the Mo layer along COL0, BL segments 310B and 315B are fabricated, corresponding to BL0 and BLB0 in COL0 for the lower matrix 120B. Above the Mo layer, BL segments 320 and 325, corresponding to BL0 and BLB0 in COL0 for the middle matrix 120M, are fabricated in the M2 layer. Above the M2 layer, BL segments 340 and 345, corresponding to BL0 and BLB0 in COL0 for the upper matrix 120T, are fabricated in the M4 layer. In one aspect of the present disclosure, the BL segment 340 may be disposed directly above the BL segment 320, which may also be disposed directly above the BL segment 310B, and the BL segment 345 may be disposed directly above the BL segment 325, which may also be disposed directly above the BL segment 315B, as shown in Fig. 5. However, it should be understood that the BL segments of the BL0 / BLB0 do not necessarily have to be vertically aligned with each other, which is within the scope of the present disclosure.

[0035] Laterally adjacent to COL0 (in the y-direction), BL segments 360B and 365B, corresponding to BL1 and BLB1 in COL1 for the lower matrix 120B, are fabricated in the Mo layer. Above the Mo layer, BL segments 370 and 375, corresponding to BL1 and BLB1 in COL1 for the middle matrix 120M, are fabricated in the M2 layer. Above the M2 layer, BL segments 380 and 385, corresponding to BL1 and BLB1 in COL1 for the upper matrix 120T, are fabricated in the M4 layer. In one aspect of the present disclosure, the BL segment 380 may be disposed directly above the BL segment 370, which may also be disposed directly above the BL segment 360B, and the BL segment 385 may be disposed directly above the BL segment 375, which may also be disposed directly above the BL segment 365B, as shown in Fig. 5. However, it should be understood that the BL segments of the BL1 / BLB1 do not necessarily have to be vertically aligned with each other, which is within the scope of the present disclosure.

[0036] In the Mo, M2 and M4 layers, several metallic conductor tracks can be produced, as in Fig. 5. These metallic traces may each be configured as part of a signal line (e.g., transmitting and / or receiving a signal for one or more corresponding memory cells) or as part of an operating voltage line (e.g., providing a supply voltage for one or more corresponding memory cells).

[0037] Fig. Figure 6 shows another exemplary cross-sectional view of the non-limiting implementation of the memory device 100 (which is shown in the Fig. 3 and Fig. 4). The sectional view of Fig. 6 is essentially the Fig. 5 similar, with the exception that in Fig. 6, one or more metallic conductor tracks are formed on a backside of the substrate 402. For example, the sectional view of Fig. 6 further metallic conductor lines 602, 604, 606, and 608 arranged on the backside of the substrate 402. These metallic conductor lines 602 to 608 can each be configured as an operating voltage line for providing a supply voltage for one or more corresponding memory cells fabricated on the frontside of the substrate 402.

[0038] Fig. Figure 7 shows a schematic block diagram of another implementation of a portion of the memory device 100 according to some embodiments. For example, in Fig. 7, a portion of the memory bank 120 and a portion of the BL controller 112 are shown. Also shown are some of the BLs and their functionally equivalent segments (e.g., each implemented as a metallic trace disposed in a corresponding metallization layer). It is understood that the schematic block diagram of Fig. 7 is for illustrative purposes only and therefore the memory device 100 may be implemented as one of several other suitable configurations, which is also within the scope of the present disclosure.

[0039] As shown, the memory bank 120 can be functionally divided into four matrices, namely a lower matrix 120B, a first middle matrix 120M1, a second middle matrix 120M2, and an upper matrix 120T. In a non-limiting example where the memory bank 120 has 1024 rows (e.g., 1024 WLs), the lower matrix 120B can have 512 rows (e.g., 512 WLs), the first middle matrix 120M1 can have 256 rows (e.g., 256 WLs), and the second middle matrix 120M2 and the upper matrix 120T can each have 128 rows (e.g., 128 WLs). However, a different arrangement on the individual matrices with the respective sizes can also be envisaged, which is also within the scope of the present disclosure.Corresponding to these four individual matrices, the BL controller 112 may include four sub-BL controllers, namely a lower BL controller 112B, a first middle BL controller 112M1, a second middle BL controller 112M2, and an upper BL controller 112T, which are configured to activate or otherwise select one or more BLs associated with the matrices 120B, 120M1, 120M2, and 120T, respectively, based on a received address signal.

[0040] Functionally, the partial BL controllers 112B, 120M1, 120M2 and 112T are each connected by a pair of BLs (BL and BLB) to the memory cells 125 of a corresponding single matrix, as shown in Fig. 1. In various embodiments, some of these functional BLs and BLBs that span one or more memory matrices may each be physically implemented as one or more lateral segments (e.g., metallic traces) and one or more vertical connections (e.g., via structures) that are interconnected. For example, in Fig. 7, the partial BL controller 112B is operatively connected to the lower matrix 120B by a corresponding group of Mo traces; the partial BL controller 112M1 is operatively connected to the first middle matrix 120M2 by a corresponding group of M2 traces; the partial BL controller 112M2 is operatively connected to the second middle matrix 120M2 by a corresponding group of M4 traces; and the partial BL controller 112T is operatively connected to the upper matrix 120T by a corresponding group of M6 traces. In some embodiments, the M2 traces may each cross the matrix 120B to connect to the matrix 120M1; The M4 traces can respectively pass over the matrices 120B and 120M2 to be connected to the matrix 120M2; and the M6 ​​traces can respectively pass over the matrices 120B, 120M1, and 120M to be connected to the matrix 120T.

[0041] Fig. Figure 8 shows a schematic block diagram of yet another implementation of a portion of the memory device 100 according to some embodiments. For example, in Fig. 8, a portion of the memory bank 120 and a portion of the BL controller 112 are shown. Also shown are some of the BLs and their functionally equivalent segments (e.g., each implemented as a metallic trace disposed in a corresponding metallization layer). It is understood that the schematic block diagram of Fig. 8 is for illustrative purposes only and therefore the memory device 100 may be implemented as one of several other suitable configurations, which is also within the scope of the present disclosure.

[0042] As shown, the memory bank 120 can be functionally divided into two matrices, namely a lower matrix 120B and an upper matrix 120T. In a non-limiting example where the memory bank 120 has 1024 rows (e.g., 1024 WLs), the lower matrix 120B can have 512 rows (e.g., 512 WLs), and the upper matrix 120T can also have 512 rows (e.g., 512 WLs). However, a different arrangement on the individual matrices with the respective sizes can also be envisaged, which is also within the scope of the present disclosure. Corresponding to these two individual matrices, the BL controller 112 can have two sub-BL controllers, namely a lower BL controller 112B and an upper BL controller 112T.In various embodiments, each of the partial BL controllers 112B and 112T may include at least one multiplexer configured to activate or otherwise select one or more BLs based on a received address signal. Furthermore, each of the partial BL controllers 112B and 112T may be operatively connected to the memory cells 125 of the corresponding array through a respective group of BLs (e.g., by applying a voltage signal to the memory cells 125).

[0043] Functionally, the partial BL controllers 112B and 112T are each connected by a pair of BLs (BL and BLB) to the memory cells 125 of a corresponding single matrix, as shown in Fig. 1. In various embodiments, some of these functional BLs and BLBs that span one or more memory arrays may each be physically implemented as one or more lateral segments (e.g., metallic traces) and one or more vertical interconnects (e.g., via structures) that are interconnected, as will be explained in more detail later.

[0044] As in Fig. 8, the memory bank 120 is divided into two matrices along the BL direction (e.g., the y-direction) while maintaining the arrangement along the WL direction (e.g., the x-direction). It should therefore be noted that each of the partial BL controllers 112B and 112T remains connected to all BLs of the memory bank 120, but is only connected to different subsets of the WLs of the memory bank 120. In the following discussion, which begins with Fig. 8, examples are provided showing the arrangement between the partial BL controllers 112B and 112T and one or more representative columns (e.g., COL0, COL1). The arrangements between the partial BL controllers 112B and 112T and other columns (e.g., COL2, COL3) are not repeated.

[0045] For example, the lower BL controller 112B may be operatively connected to the memory cells 125 of the lower array 120B (sometimes referred to as lower memory cells 125B) in COL0 through BL segments 810B and 815B. The upper BL controller 112T may be operatively connected to the memory cells 125 of the upper array 120T (sometimes referred to as upper memory cells 125T) in COL0 through BL segments 820 and 825, as well as through BL segments 830 and 835, as well as through BL segments 810T and 815T. Furthermore, the lower BL controller 112B may be operatively connected to the lower memory cells 125B in COL1 through BL segments 860B and 865B. The upper BL controller 112T can be operatively connected to the upper memory cells 125T in COL1 through BL segments 840 and 845, as well as through BL segments 850 and 855, as well as through BL segments 850 and 855, as well as through BL segments 860T and 865T.

[0046] In some embodiments, BL segments 810B and 815B may correspond to portions of BL0 and BLB0 (i.e., BL / BLB in COL0) that are operatively connected to memory cells 125B in COL0, respectively. BL segments 820, 830, and 810T, and 825, 830, and 810T may correspond to portions of BL0 and BLB0 (i.e., BL / BLB in COL0), each operatively connected to memory cells 125T in COL0. BL segments 860B and 865B may correspond to portions of BL0 and BLB1 (i.e., BL / BLB in COL1), each operatively connected to memory cells 125B in COL1. The BL segments 840, 850 and 860T as well as 845, 855 and 865T may correspond to the parts of BL1 and BLB1 (ie, BL / BLB in COL1) that are each operatively connected to the memory cells 125T in COL1.

[0047] In some embodiments of the present disclosure, the BL segments 810B, 815B, 810T, and 815T may be disposed, embedded, or otherwise formed in the Mo layer. The BL segments 810B, 815B, 810T, and 815T may each be formed as a Mo conductive line extending along the first transverse direction (e.g., the y-direction). Furthermore, the BL segments 810B, 815B, 810T, and 815T are electrically and physically isolated from each other by a dielectric material (e.g., oxide-based dielectric materials or various other low-k dielectric materials) of the Mo layer. In some embodiments, the BL segments 810B and 810T may be formed around the memory array 120B and 120T, respectively. The complementary BL segments 815B and 815T can be manufactured in a similar manner, and therefore the description is not repeated.

[0048] Additionally, BL segments 830 and 835 may be disposed, embedded, or otherwise fabricated in the M1 layer. BL segments 830 and 835 may each be fabricated as an M1 trace extending along the second transverse direction (e.g., the x-direction). BL segments 820 and 825 may be disposed, embedded, or otherwise fabricated in the M2 layer. BL segments 820 and 825 may each be fabricated as an M2 trace extending along the first transverse direction (e.g., the y-direction). BL segments 850 and 855 may be disposed, embedded, or otherwise fabricated in the M3 layer. BL segments 850 and 855 may each be fabricated as an M3 conductive line extending along the second transverse direction (e.g., the x-direction). BL segments 840 and 845 may be disposed, embedded, or otherwise fabricated in the M4 layer.The BL segments 840 and 845 can each be fabricated as an M4 conductive track extending along the first transverse direction (e.g., the y-direction).

[0049] Fig. 9 shows an exemplary top view of the BL segments (M2 traces) 820 and 825 and the BL segments (M4 traces) 840 and 845 across COL0 and COL1, according to some embodiments. As shown, the portion of BL0 operatively connected to the memory cells 125T in COL0 (e.g., the BL segment 820) and the portion of BL0 operatively connected to the memory cells 125T in COL0 (e.g., the BL segment 825) are separated by a distance S1. In some embodiments, this distance may be laterally offset from a boundary of a memory cell having a cell height H. Therefore, the BL segment 820 may be arranged along COL0, and the BL segment 825 may be arranged along COL1. In other words, the respective parts of the BL and their corresponding BLB, which are operatively connected to the more distant memory cells (e.g., 125T) in a particular column, are arranged separately in different columns.

[0050] Similarly, the portion of BL1 that is operatively connected to memory cells 125T in COL0 (e.g., BL segment 840) and the portion of BLB1 that is operatively connected to memory cells 125T in COL1 (e.g., BL segment 845) are separated by a distance S2. In some embodiments, this distance may be laterally offset from the boundary of a memory cell having cell height H. Therefore, BL segment 840 may be arranged along COL0, and BL segment 845 may be arranged along COL1. In other words, the respective portions of the BL and its corresponding BLB that are operatively connected to the more distant memory cells (e.g., 125T) in a particular column are arranged separately in different columns.

[0051] By configuring these BL segments in this way, some of the M2 traces can overfly the lower matrix 120B to connect to the upper (more distant) matrix 120T, as shown in Fig. 8. Therefore, these flying M2 traces can each extend further than the (e.g., deeper) Mo traces can extend along the column direction (the y-direction). Furthermore, these M2 traces connected to the more distant matrix can be pushed away from each other along the row direction (the x-direction) with a greater distance, as shown in Fig. 9. Similarly, some of the M4 traces may overfly the lower matrix 120B to connect to the upper (more distant) matrix 120T, as shown in Fig. 8. Therefore, these flying M4 traces can each extend further than the (e.g., deeper) Mo traces can extend along the column direction (the y-direction). Furthermore, these M4 traces can be pushed apart from each other along the row direction (the x-direction) with a greater distance, as shown in Fig. 9. With this increased spacing, the capacitive coupling between adjacent metallic traces in one or more of the metallization layers can be significantly reduced.

[0052] Fig. Figure 10 shows an exemplary cross-sectional view of the non-limiting implementation of the memory device 100 (which is shown in the Fig. 8 and Fig. 9). The sectional view of Fig. 10 is taken along the row direction of the lower matrix 120B (e.g., along the x-direction) to show two columns COL0 and COL1. It should be understood that the sectional view can be similarly extended to other columns, and therefore, the description will not be repeated. As shown, a Mo layer, an M2 layer, and an M4 layer are formed on the front side of a substrate 1002, with one or more additional layers (e.g., a device layer including the front-end memory cells 125 and at least one middle-end interconnect layer) disposed between the Mo layer and the substrate 1002.

[0053] In the Mo layer, BL segments 810B and 815B, corresponding to BL0 and BLB0 in COL0 for the lower matrix 120B, and BL segments 860B and 865B, corresponding to BL1 and BLB1 in COL1 for the lower matrix 120B, are formed. Above the Mo layer, BL segments 820 and 825, corresponding to BL0 and BLB0 in COL0 for the upper matrix 120T, are formed in the M2 layer. Above the M2 layer, BL segments 840 and 845, corresponding to BL1 and BLB1 in COL1 for the upper matrix 120T, are formed in the M4 layer. In one aspect of the present disclosure, the BL segment 820 may be laterally offset from one of the BL segments 810B and 815B, and the BL segment 840 may also be laterally offset from the BL segment 820; and the BL segment 825 may be laterally offset from one of the BL segments 860B and 865B, and the BL segment 845 may also be laterally offset from the BL segment 825, as shown in Fig. 10. However, it is understood that the BL segments of BL0 / BLB0 and BL 1 / BLB1 do not necessarily have to be laterally offset from each other, which is also within the scope of the present disclosure.

[0054] In the Mo, M2 and M4 layers, several additional metallic conductor tracks can be produced, as in Fig. 10. These metallic conductive lines may each be configured as part of a signal line (e.g., transmitting and / or receiving a signal for one or more corresponding memory cells) or as part of an operating voltage line (e.g., providing a supply voltage for one or more corresponding memory cells).

[0055] Fig. 11 shows a flow diagram of an exemplary method 1100 for manufacturing a memory device according to various embodiments. For example, the method 1100 may be used to manufacture the implementation of the memory device 100 shown in Fig. 3. In some embodiments, operations of method 1100 are performed in the manner shown in Fig. 11. In some further embodiments, operations of method 1100 may be performed concurrently and / or in a different order than that shown in Fig. 11 are carried out in the order specified.

[0056] The method 1100 begins with an operation 1102 for fabricating a plurality of first memory cells, a plurality of second memory cells, and a plurality of third memory cells in first, second, and third regions of a substrate, respectively. In some embodiments, the second region is arranged between the first and third regions along a transverse direction. Furthermore, the first memory cells may correspond to a respective column of memory cells in a first memory array; the second memory cells may correspond to a respective column of memory cells in a second memory array; and the third memory cells may correspond to a respective column of memory cells in a third memory array. Therefore, the transverse direction corresponds to a column direction of the first to third memory arrays.

[0057] Let us return to the implementation of Fig. 3, in which the first, second, and third memory cells can be implemented as the lower memory cells 125B arranged along the COL0; the middle memory cells 125M arranged along the COL0; and the upper memory cells 125T arranged along the COL0, respectively.

[0058] The substrate may be a wafer, such as a silicon wafer, or a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is formed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate may include: silicon; germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0059] The first to third memory cells can each be implemented as a six-transistor SRAM cell (6T-SRAM cell) consisting of six transistors (e.g., N1, N2, N3, N4, P1, and P2), as shown in Fig. 2. However, it should be understood that the first to third memory cells may also be implemented as other types of SRAM configurations than 6T, e.g., as an eight-transistor (8T) or a ten-transistor (1oT) configuration. Alternatively or additionally, the first to third memory cells may also be implemented as other types of memory cells, such as DRAM cells (DRAM: dynamic random access memory), RRAM cells (RRAM: resistive random access memory), PCRAM cells (PCRAM: phase-change random access memory), or MRAM cells (MRAM: magnetoresistive random access memory). In various embodiments, the first to third memory cells may be formed along a main surface (e.g., a front side) of the substrate, i.e., the first to third regions in which the first to third memory cells are formed are arranged along this main surface.Accordingly, the fabrication of these first to third memory cells (and corresponding memory matrices) can sometimes be referred to as FEOL (Front End of Line) processing.

[0060] The method 1100 then proceeds to an operation 1104 of forming a first BL segment in a first of a plurality of metallization layers over the substrate, wherein the first BL segment physically extends along the transverse direction and is operatively connected to each of the plurality of first memory cells. In some embodiments, the first BL segment may correspond to the BL and BLB operatively connected to the first memory cells formed in the first region of the substrate. The first BL segment may extend along the transverse direction from a corresponding BL controller disposed immediately adjacent to a first edge of the first region along the transverse direction, through the first region, and to a second edge of the first region opposite the first edge.Additionally, the first BL segment may be formed in a first of the plurality of metallization layers disposed over the substrate.

[0061] Let us continue with the above example of Fig. 3. The first BL segment may be implemented as BL segments 310B and 315B. BL segments 310B and 315B are formed in the Mo layer with a first length extending along the transverse direction (the y-direction) above the substrate. Therefore, BL segments 310B and 315B are operatively connected to the lower memory cells 125B arranged along the COL0. The Mo layer is sometimes referred to as a bottommost of the metallization layers above the substrate. Accordingly, the formation of these metallization layers may sometimes be referred to as BEOL (Back End of Line) processing. The 310B and 315B BL segments may contain one or more metallic materials, such as tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru), or combinations thereof, and they may be manufactured using one or more damascene processes.

[0062] The method 1100 then proceeds to an operation 1106 for forming a second BL segment in a second of the metallization layers disposed over the first metallization layer, wherein the second BL segment physically extends along the transverse direction and is operatively connected to each of the plurality of second memory cells. In some embodiments, the second BL segment may correspond to the BL and the BLB operatively connected to the second memory cells fabricated in the second region of the substrate. The second BL segment may extend along the transverse direction from a corresponding BL controller, also disposed immediately adjacent to the first edge of the first region along the transverse direction, across the first region, and to an edge of the second region facing the second edge of the first region.Additionally, the second BL segment may be formed in a second of the plurality of metallization layers disposed over the first metallization layer.

[0063] Let us continue with the above example of Fig. 3. The second BL segment may be implemented as BL segments 320 and 325. The BL segments 320 and 325 are formed in the M2 layer with a second length extending along the transverse direction (the y-direction) and longer than the first length, above the Mo layer. Therefore, the BL segments 320 and 325 overfly the first region without being operatively connected to the lower memory cells 125B arranged along the COL0, but they are operatively connected to the middle memory cells 125M along the COL0. The BL segments 320 and 325 may include one or more metallic materials, such as tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru), or combinations thereof, and may be formed using one or more damascene processes.

[0064] The method 1100 then proceeds to an operation 1108 for forming a third BL segment in a third of the metallization layers disposed over the second metallization layer, wherein the third BL segment physically extends along the transverse direction and is operatively connected to each of the plurality of third memory cells. In some embodiments, the third BL segment may correspond to the BL and the BLB operatively connected to the third memory cells fabricated in the third region of the substrate. The third BL segment may extend along the transverse direction from a corresponding BL controller, also disposed immediately adjacent to the first edge of the first region along the transverse direction, across the first and second regions, and to an edge of the third region facing the other edge of the second region.Additionally, the third BL segment may be formed in a third of the plurality of metallization layers disposed above the second metallization layer.

[0065] Let us continue with the above example of Fig. 3. The third BL segment can be implemented as BL segments 340 and 345. BL segments 340 and 345 are fabricated in the M4 layer above the M2 layer with a third length extending along the transverse direction (the y-direction) and longer than the second length. Therefore, BL segments 340 and 345 traverse the first and second regions without being operatively connected to the lower memory cells 125B or the middle memory cells 125M arranged along the COL0, but they are operatively connected to the upper memory cells 125T along the COL0. The BL segments 340 and 345 may contain one or more metallic materials, such as tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru), or combinations thereof, and they may be manufactured using one or more damascene processes.

[0066] Fig. 12 shows a flow diagram of an exemplary method 1200 for manufacturing a memory device according to various embodiments. For example, the method 1200 may be used to manufacture the implementation of the memory device 100 shown in Fig. 8. In some embodiments, operations of method 1200 are performed in the manner shown in Fig. 12. In some further embodiments, operations of method 1200 may be performed concurrently and / or in a different order than that shown in Fig. 12 are carried out in the order specified.

[0067] The method 1200 begins with an operation 1202 for forming a plurality of first memory cells and a plurality of third memory cells in a first region of a substrate, and for forming a plurality of second memory cells and a plurality of fourth memory cells in a second region of the substrate. In some embodiments, the second region is arranged immediately adjacent to the first region along a transverse direction. Furthermore, the first memory cells may correspond to a respective column of memory cells in a first memory matrix, and the second memory cells may correspond to a respective column of memory cells in a second memory matrix. Therefore, the transverse direction corresponds to a column direction of the first and third memory matrixes. While the first and second memory cells are being formed, the third and fourth memory cells may also be formed simultaneously in the first and second memory matrixes, respectively.the second region. The third memory cells may correspond to a different respective column of memory cells in the first memory matrix, and the fourth memory cells may correspond to a different respective column of memory cells in the second memory matrix.

[0068] Let us return to the implementation of Fig. 8, in which the first and second memory cells may be implemented as the lower memory cells 125B arranged along COL0 and the upper memory cells 125T arranged along COL0, respectively. The third and fourth memory cells may be implemented as the lower memory cells 125B arranged along COL1 and the upper memory cells 125T arranged along COL1, respectively.

[0069] The substrate may be a wafer, such as a silicon wafer, or an SOI substrate. Generally, an SOI substrate comprises a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a BOX layer, a silicon oxide layer, or the like. The insulating layer is formed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate may include: silicon; germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0070] The first to fourth memory cells can each be implemented as a 6T SRAM cell consisting of six transistors (e.g., N1, N2, N3, N4, P1, and P2), as shown in Fig. 2. However, it should be understood that the first to fourth memory cells may also be implemented as other types of SRAM configurations than 6T, e.g., as an 8T or a 1oT configuration. Alternatively or additionally, the first to fourth memory cells may also be implemented as other types of memory cells, such as DRAM cells, RRAM cells, PCRAM cells, or MRAM cells. In various embodiments, the first to fourth memory cells may be formed along a main surface (e.g., a front side) of the substrate, i.e., the first and second regions, in which the first to fourth memory cells are formed, are arranged along this main surface. Accordingly, the formation of these first to fourth memory cells (and corresponding memory arrays) may occasionally be referred to as FEOL processing.

[0071] The method 1200 then proceeds to an operation 1204 of forming first and second BL segments in a first of a plurality of metallization layers over the substrate, wherein the first and second BL segments each physically extend along the transverse direction and are operatively connected to each of the plurality of first memory cells and each of the plurality of third memory cells, respectively. In some embodiments, the first BL segment may correspond to the BL and BLB operatively connected to the first memory cells formed in the first region of the substrate, and the second BL segment may correspond to the BL and BLB operatively connected to the third memory cells formed in the first region of the substrate.The first and second BL segments may each extend along the transverse direction from a respective BL controller located immediately adjacent to a first edge of the first region along the transverse direction, across the first region, and to a second edge of the first region opposite the first edge. Furthermore, the first and second BL segments may be formed in a first of the plurality of metallization layers disposed above the substrate.

[0072] Let us continue with the above example of Fig. 8. The first BL segment may be implemented as BL segments 810B and 815B, and the second BL segment may be implemented as BL segments 860B and 865B. BL segments 810B, 815B, 860B, and 865B are formed in the Mo layer above the substrate with a first length extending along the transverse direction (the y-direction). This operatively connects BL segments 810B and 815B to the lower memory cells 125B arranged along COL0, and BL segments 860B and 816B are operatively connected to the lower memory cells 125B arranged along COL1. The Mo layer is sometimes referred to as a bottommost of the metallization layers above the substrate. Accordingly, the production of these metallization layers can sometimes be referred to as BEOL processing.The BL segments 810B, 815B, 860B and 865B may contain one or more metallic materials, such as tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru) or combinations thereof, and they may be manufactured using one or more damascene processes.

[0073] The method 1200 then proceeds to an operation 1206 of forming a third BL segment in a second of the metallization layers over the substrate, wherein the third BL segment physically extends along the transverse direction and is operatively connected to each of the plurality of second memory cells. In some embodiments, the third BL segment may correspond to the BL and BLB operatively connected to the third memory cells formed in the second region of the substrate. The third BL segment may extend along the transverse direction from a corresponding BL controller disposed immediately adjacent to the first edge of the first region along the transverse direction, across the first region, and to an edge of the second region facing the second edge of the first region.Additionally, the third BL segment may be formed in a second of the plurality of metallization layers disposed over the first metallization layer.

[0074] Let us continue with the above example of Fig. 8. The third BL segment may be implemented as BL segments 820 and 825. BL segments 820 and 825 are formed in the M2 layer above the Mo layer with a second length extending along the transverse direction (the y-direction) and greater than the first length. Therefore, BL segments 820 and 825 traverse the first region without being operatively connected to the lower memory cells 125B arranged along COL0 or COL1, but they are operatively connected to the middle memory cells 125M along COL0. In other words, the BL segment 820 traverses the lower memory cells 125B along the COL0 to be connected to the upper memory cells 125T along the COL0, and the BL segment 825 traverses the lower memory cells 125B along the COL1 to be connected to the upper memory cells 125T along the COL0.The BL segments 820 and 825 may contain one or more metallic materials, such as tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru), or combinations thereof, and they may be manufactured using one or more damascene processes.

[0075] The method 1200 then proceeds to an operation 1208 of forming a fourth BL segment in a third of the metallization layers over the substrate, wherein the fourth BL segment physically extends along the transverse direction and is operatively connected to each of the plurality of fourth memory cells. In some embodiments, the fourth BL segment may correspond to the BL and the BLB operatively connected to the fourth memory cells formed in the second region of the substrate. The fourth BL segment may extend along the transverse direction from a corresponding BL controller disposed immediately adjacent to the first edge of the first region along the transverse direction, across the first region, and to an edge of the second region facing the second edge of the first region.Additionally, the fourth BL segment may be formed in a third of the plurality of metallization layers disposed above the second metallization layer.

[0076] Let us continue with the above example of Fig.8. The fourth BL segment can be implemented as BL segments 840 and 845. BL segments 840 and 845 are fabricated in the M4 layer above the M2 layer with a third length extending along the transverse direction (the y-direction) and greater than the first length. Therefore, BL segments 840 and 845 traverse the first region without being operatively connected to the lower memory cells 125B arranged along COL0 or COL1, but they are operatively connected to the middle memory cells 125M along COL1. In other words, the BL segment 840 traverses the lower memory cells 125B along COL0 to connect to the upper memory cells 125T along COL1, and the BL segment 845 traverses the lower memory cells 125B along COL1 to connect to the upper memory cells 125T along COL1.The BL segments 840 and 845 may contain one or more metallic materials, such as tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru), or combinations thereof, and they may be manufactured using one or more damascene processes.

[0077] In one aspect of the present disclosure, a memory device is disclosed. The memory device comprises a first memory array having a plurality of first memory cells arranged along a corresponding one of a plurality of first columns and each arranged across a plurality of first rows, wherein each of the plurality of first columns extends along a first transverse direction and each of the plurality of first rows extends along a second transverse direction. The memory device further comprises a first bit line segment extending along the first transverse direction and operatively connected to each of the plurality of first memory cells, wherein the first bit line segment is arranged in a first of a plurality of metallization layers over the plurality of first memory cells.The memory device further comprises a second bit line segment that also extends along the first transverse direction but is functionally isolated from one of the plurality of first memory cells, wherein the second bit line segment is arranged in a second of the plurality of metallization layers. The memory device further comprises a third bit line segment that also extends along the first transverse direction but is functionally isolated from one of the plurality of first memory cells, wherein the third bit line segment is arranged in a third of the plurality of metallization layers.The first bit line segment has a first length along the first transverse direction, the second bit line segment has a second length along the first transverse direction, and the third bit line segment has a third length along the first transverse direction, wherein the first length is less than the second length and the second length is less than the third length.

[0078] In another aspect of the present disclosure, a memory device is disclosed. The memory device comprises: a first memory array having a plurality of first memory cells arranged along a transverse direction; a second memory array having a plurality of second memory cells arranged along the transverse direction; a third memory array having a plurality of third memory cells arranged along the transverse direction, the second memory array being arranged between the first and third memory arrays along the transverse direction; a first bit line segment extending along the transverse direction and operatively connected to each of the plurality of first memory cells; a second bit line segment extending along the transverse direction and operatively connected to each of the plurality of second memory cells;and a third bit line segment extending along the transverse direction and operatively connected to each of the plurality of third memory cells. The first bit line segment is formed in a first metallization layer, the second bit line segment is formed in a second metallization layer over the first metallization layer, and the third bit line segment is formed in a third metallization layer over the second metallization layer.

[0079] In yet another aspect of the present disclosure, a method of fabricating a memory device is disclosed. The method comprises fabricating a plurality of first memory cells, a plurality of second memory cells, and a plurality of third memory cells in a first region, a second region, and a third region of a substrate, respectively, wherein the second region is disposed between the first and third regions along a transverse direction. The method further comprises fabricating a first bitline segment in a first of a plurality of metallization layers over a first surface of the substrate, wherein the first bitline segment physically extends along the transverse direction and is operatively connected to each of the plurality of first memory cells.The method further comprises forming a second bitline segment in a second of the plurality of metallization layers disposed over the first metallization layer, wherein the second bitline segment physically extends along the transverse direction and is operatively connected to each of the plurality of second memory cells. The method further comprises forming a third bitline segment in a third of the plurality of metallization layers disposed over the second metallization layer, wherein the third bitline segment physically extends along the transverse direction and is operatively connected to each of the plurality of third memory cells.

[0080] As used herein, the terms "about" and "approximately" generally indicate the value of a given quantity, which may vary based on a particular technology node associated with the semiconductor device of the invention. Depending on the particular technology node, the term "about" may indicate a value of a given quantity that varies within a range of, for example, 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0081] Features of several embodiments have been described above to help those skilled in the art better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent interpretations do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 512,359

[0001] US 63 / 517,781

[0001]

Claims

[1] Storage device with: a first memory array having a plurality of first memory cells arranged along a corresponding one of a plurality of first columns and each across a plurality of first rows, each of the plurality of first columns extending along a first transverse direction and each of the plurality of first rows extending along a second transverse direction; a first bit line segment extending along the first transverse direction and operatively connected to each of the plurality of first memory cells, the first bit line segment disposed in a first of a plurality of metallization layers over the plurality of first memory cells; a second bit line segment that also extends along the first transverse direction, but that is functionally isolated from each of the plurality of first memory cells, wherein the second bit line segment is arranged in a second of the plurality of metallization layers; and a third bit line segment which also extends along the first transverse direction, but which is functionally isolated from each of the plurality of first memory cells, wherein the third bit line segment is arranged in a third of the plurality of metallization layers, wherein the first bit line segment has a first length along the first transverse direction, the second bit line segment has a second length along the first transverse direction, and the third bit line segment has a third length along the first transverse direction, wherein the first length is less than the second length and the second length is less than the third length. [2] The memory device of claim 1, further comprising: a second memory array having a plurality of second memory cells arranged along a corresponding one of a plurality of second columns and each across a plurality of second rows, each of the plurality of second columns extending along the first transverse direction and each of the plurality of second rows extending along the second transverse direction; and a third memory array having a plurality of third memory cells arranged along a corresponding one of a plurality of third columns and each across a plurality of third rows, each of the plurality of third columns extending along the first transverse direction and each of the plurality of third rows extending along the second transverse direction. [3] The storage device according to claim 2, wherein; the second bit line segment is operatively connected to each of the plurality of second memory cells, and the third bit line segment is operatively connected to each of the plurality of third memory cells. [4] The memory device according to claim 2 or 3, wherein; the second memory array is arranged between the first memory array and the third memory array along the first transverse direction. [5] A storage device according to any one of claims 2 to 4, further comprising: a fourth bit line segment also extending along the first transverse direction and arranged in the first metallization layer, the fourth bit line segment connecting the second bit line segment to each of the plurality of second memory cells; and a fifth bit line segment also extending along the first transverse direction and arranged in the first metallization layer, the fifth bit line segment connecting the third bit line segment to each of the plurality of third memory cells. [6] A storage device according to any one of claims 2 to 5, further comprising: a fourth memory matrix having a plurality of fourth memory cells arranged along a corresponding one of a plurality of fourth columns and each across a plurality of fourth rows, each of the plurality of fourth columns extending along the first transverse direction and each of the plurality of fourth rows extending along the second transverse direction; and a fourth bit line segment also extending along the first transverse direction and operatively connected to each of the plurality of fourth memory cells but operatively isolated from each of the plurality of first, second, or third memory cells, the fourth bit line segment being disposed in a fourth of the plurality of metallization layers. [7] A storage device according to any one of the preceding claims, wherein; the third metallization layer is arranged above the second metallization layer, and the second metallization layer is arranged above the first metallization layer. [8] A storage device according to any one of the preceding claims, wherein; the third bit line segment is arranged directly above the second bit line segment, and the second bit line segment is arranged directly above the first bit line segment. [9] A memory device according to any one of the preceding claims, wherein; the first column along which the plurality of first memory cells are arranged, the second column along which the plurality of second memory cells are arranged, and the third column along which the plurality of third memory cells are arranged are aligned with each other in the first transverse direction. [10] A memory device according to any preceding claim, wherein; a first number of the plurality of first rows is twice a second number of the plurality of second rows and twice a third number of the plurality of third rows. [11] Storage device comprising: a first memory matrix having a plurality of first memory cells arranged along a transverse direction; a second memory matrix having a plurality of second memory cells arranged along the transverse direction; a third memory matrix having a plurality of third memory cells arranged along the transverse direction, wherein the second memory matrix is ​​arranged between the first memory matrix and the third memory matrix along the transverse direction; a first bit line segment extending along the transverse direction and operatively connected to each of the plurality of first memory cells; a second bit line segment extending along the transverse direction and operatively connected to each of the plurality of second memory cells; and a third bit line segment extending along the transverse direction and operatively connected to each of the plurality of third memory cells, wherein; the first bit line segment is fabricated in a first metallization layer, the second bit line segment is formed in a second metallization layer above the first metallization layer, and the third bit line segment is formed in a third metallization layer above the second metallization layer. [12] The memory device of claim 11, further comprising: a fourth memory matrix having a plurality of fourth memory cells arranged along the transverse direction, wherein the third memory matrix is ​​arranged between the second memory matrix and the fourth memory matrix; and a fourth bit line segment extending along the transverse direction and operatively connected to each of the plurality of fourth memory cells. [13] The memory device of claim 12, wherein; the fourth bit line segment is formed in a fourth metallization layer over the third metallization layer. [14] The memory device of any of claims 11 to 13, wherein; the second bit line segment extends across the first memory array but is functionally isolated from each of the first memory cells. [15] The memory device of any of claims 11 to 14, wherein; the third bit line segment extends across the first memory array and the second memory array, but is functionally isolated from each of the first memory cells or the second memory cells. [16] The memory device of any one of claims 11 to 15, wherein; the first bit line segment has a first length along the transverse direction, the second bit line segment has a second length along the transverse direction, and the third bit line segment has a third length along the transverse direction, the first length being less than the second length and the second length being less than the third length. [17] The memory device according to any one of claims 11 to 16, wherein; a first number of the plurality of first memory cells is greater than a second number of the plurality of second memory cells and is greater than a third number of the plurality of third memory cells. [18] A method of manufacturing a memory device, comprising: Producing a plurality of first memory cells, a plurality of second memory cells, and a plurality of third memory cells in a first region, a second region, and a third region of a substrate, respectively, wherein the second region is arranged between the first and third regions along a transverse direction; Forming a first bitline segment in a first of a plurality of metallization layers over a first surface of the substrate, the first bitline segment physically extending along the transverse direction and operatively connected to each of the plurality of first memory cells; forming a second bit line segment in a second of the plurality of metallization layers disposed over the first metallization layer, the second bit line segment physically extending along the transverse direction and being operatively connected to each of the plurality of second memory cells; and Forming a third bitline segment in a third of the plurality of metallization layers disposed over the second metallization layer, the third bitline segment physically extending along the transverse direction and operatively connecting to each of the plurality of third memory cells. [19] The method of claim 18, wherein; the first bit line segment has a first length along the transverse direction, the second bit line segment has a second length along the transverse direction, and the third bit line segment has a third length along the transverse direction, the first length being less than the second length and the second length being less than the third length. [20] A method according to claim 18 or 19, wherein; the second bit line segment is functionally isolated from each of the plurality of first memory cells, and the third bit line segment is functionally isolated from each of the plurality of first or second memory cells.

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