Electrical circuit, single-ended amplifier and operating method of an electrical circuit

Abstract

Electrical circuit (100) comprising a first operational amplifier (Av1) having a first non-inverting input, a first inverting input and a first output, a second operational amplifier (Av2) having at least a second non-inverting input and a second output, and a third operational amplifier (Av3) having at least a third inverting input and a third output, characterized in that a feedback path comprises a series connection of a resistor (Rm), a second resistor (Rm2) and a second capacitor (Cm2), wherein the feedback path is arranged between the third output and the at least one third inverting input, and a first feedback path comprises a first series connection with a first resistor (Rm1) and a first capacitor (Cm1),wherein the first feedback path is arranged between a node and the at least one second non-inverting input, wherein the node is arranged between the resistor (Rm) and the second resistor (Rm2).

Description

State of the art

[0001] The invention relates to an electrical circuit, a single-ended amplifier and an operating method of an electrical circuit.

[0002] Cascaded, multi-stage operational amplifiers are used for the evaluation and further processing of sensor signals in consumer devices, inertial navigation, vehicle safety systems, and stability control systems in cameras and camcorders. Nested Miller compensation circuits are used to increase the overall gain and bandwidth of cascaded, multi-stage operational amplifiers and reduce their power consumption.

[0003] To ensure circuit stability, the zeros of the right half-plane of a pole / zero diagram must be eliminated. Active compensation structures are known for this purpose. The disadvantage of these structures is that they increase the circuit's power consumption.

[0004] The object of the invention is to overcome this disadvantage. Disclosure of the invention

[0005] The electrical circuit comprises a first operational amplifier having a first non-inverting input, a first inverting input, and a first output, a second operational amplifier having at least a second non-inverting input and a second output, and a third operational amplifier having at least a third inverting input and a third output. According to the invention, a feedback path comprises a series circuit comprising a resistor, a second resistor, and a second capacitor, wherein the feedback path is arranged between the third output and the at least one third inverting input.Furthermore, the electrical circuit has a first feedback path comprising a first series circuit with a first resistor and a first capacitor, wherein the first feedback path is arranged between a node and the at least one second non-inverting input, wherein the node is arranged between the resistor and the second resistor. In other words, it is a three-stage operational amplifier with nested Miller compensation, comprising two nested Miller compensation loops comprising three resistors and two capacitors.

[0006] The advantage here is that stability is high with high overall gain and high bandwidth. Furthermore, the circuit size is small, ensuring reliable analog signal processing. The low power consumption of the electrical circuit is also advantageous. Another advantage is that the first and second resistors are not subject to matching conditions.

[0007] In a further development, the third operational amplifier has a third transconductance, wherein the resistance has a value that is essentially inversely proportional to the third transconductance gm3, and the sum of the resistance and the second resistance is greater than 1 / gm3. The term "essentially" in this context means that minor process fluctuations are included.

[0008] The advantage here is that the resistor, the first resistor, the second resistor, the first capacitor and the second capacitor are not subject to exact matching requirements, so that the electrical circuit is robust against process variations and mismatch.

[0009] In a further embodiment, the resistor, the first resistor, and the second resistor are each configured as a transistor in which a gate-source voltage is greater than a threshold voltage of the transistor and the gate-drain voltage is greater than or equal to the threshold voltage of the transistor. In other words, the transistors are operated in the triode region.

[0010] The advantage here is that the resistance performance is improved.

[0011] In a further development, the first operational amplifier has a differential amplifier with a first transistor and a second transistor, a first current mirror circuit with a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, and a cascode circuit with a ninth transistor and a tenth transistor.

[0012] The advantage here is that cost-effective components can be used.

[0013] In a further development, the second operational amplifier has a thirteenth transistor, a fourteenth transistor and a second current mirror circuit with a fifteenth transistor and a sixteenth transistor.

[0014] The advantage here is that the silicon area of ​​the second operational amplifier is small.

[0015] In a further embodiment, the third operational amplifier has a seventeenth transistor and an eighteenth transistor.

[0016] The advantage here is that the third operational amplifier has a low complexity.

[0017] The single-ended amplifier according to the invention comprises an electrical circuit according to the invention.

[0018] The operating method according to the invention of the electrical circuit according to the invention has a first operating mode which produces high stability and a second operating mode which produces low consumption.

[0019] The advantage here is that the electrical circuit can be used in different scenarios.

[0020] Further advantages arise from the following description of embodiments and the dependent patent claims. Short description of the drawings

[0021] The present invention is explained below with reference to preferred embodiments and the accompanying drawings. They show: Fig. 1 a small-signal equivalent circuit diagram of an electrical circuit according to the invention, Fig. 2 a block diagram of the electrical circuit according to the invention, Fig. 3 an application example of the electrical circuit according to the invention, Fig. 4 a table with different Nested Miller compensation structures.

[0022] Fig. 1 shows a small-signal equivalent circuit of the electrical circuit 100 according to the invention. The electrical circuit 100 comprises a first operational amplifier Av1 with a first non-inverting input and an inverting input, as well as a first output. The first output is electrically connected to a second non-inverting input of a second operational amplifier Av2. The second operational amplifier Av2 has a second output. The second output is electrically connected to a third inverting input of a third operational amplifier Av3. The electrical circuit 100 comprises a feedback path comprising a series circuit with a resistor Rm, a second resistor Rm2, and a second capacitor Cm2. This feedback path is arranged between the third output and the third inverting input.Furthermore, the electrical circuit 100 comprises a first feedback path with a first series circuit comprising a first resistor Rm1 and a first capacitor Cm1. The first feedback path is arranged between a node located between the resistor Rm and the second resistor and the second non-inverting input. The first capacitor Cm1 and the second capacitor Cm2 act as compensation capacitances. The resistors R1, R2, and R3 act as output resistors of the respective amplifier stage. The capacitors Cp1, Cp2, and Cp3 act as parasitic capacitances of the respective amplifier stage.

[0023] The capacitor CL represents the load capacitance. In the illustrated embodiment, the first amplifier stage is non-inverting. The second amplifier stage is non-inverting, and the third amplifier stage is inverting to ensure negative feedback via the two compensation capacitors.

[0024] The first operational amplifier Av1 has a first transconductance gm1, the second operational amplifier Av2 has a second transconductance gm2 and the third operational amplifier Av3 has a third transconductance gm3.

[0025] When designing stable amplifiers, a high figure of merit (FOM) is required. This is calculated as follows: FOM=(GBW⋅CL) / IDC,[MHz⋅pF / mA], where GBW represents the amplifier bandwidth, CL the output load, and IDC the DC power consumption. The amplifier bandwidth is determined by the transconductance gm1 of the first operational amplifier Av1 of the electrical circuit. The quality factor is inversely proportional to the bias current IBIAS.

[0026] The total gain of a three-stage operational amplifier in an open loop is given by: Av(s)=Z3R(s) / P3R(s)

[0027] Where the total gain Av(s) is the product of the transfer function of the individual operational amplifiers, Z3R(s) is the numerator polynomial of the pole zero transfer function, and P3R(s) is the denominator polynomial of the pole zero transfer function. Since the frequency compensation network according to the invention comprises the two compensation capacitors Cm1 and Cm2, as well as the resistor Rm, the first resistor Rm1, and the second resistor Rm2, the numerator polynomial of the pole zero transfer function of the electrical circuit 100 according to the invention is: Z3R(s)=1+s[Cm1(Rm1+Rm)+Cm2(Rm2+Rm1gm3)]+s2[Cm1Cm2(gm2gm3Rm1Rm2−gm2Rm1−1)(gm3Rm−1)] / (gm2gm3)

[0028] The electrical circuit 100 according to the invention, hereinafter also referred to as NMC-3R amplifier, has a zero in the left half-plane and a zero in the right half-plane of the complex plane in which the poles and zeros are represented.

[0029] The zero in the left half-plane is given by: zLHP={12Cm1Cm2gm22gm32(1−gm3Rm)(1+gm2Rm1−Rm1Rm2)⋅ (Cm2gm3−Cm1Rm−Cm2Rm−Cm1Rm1−Cm2Rm2−((−Cm2gm3+Cm1Rm+Cm2Rm+Cm1Rm1+Cm2Rm2)2−4Cm1Cm2gm22gm32(1−gm3Rm)(1+gm2Rm1−Rm1Rm2))).}

[0030] The zero in the right half-plane is given by: zPHP={12Cm1Cm2gm22gm32(1−gm3Rm)(1−gm2Rm1−Rm1Rm2)⋅ (Cm2gm3−Cm1Rm−Cm2Rm−Cm1Rm1−Cm2Rm2+((−Cm2gm3+Cm1Rm+Cm2Rm+Cm1Rm1+Cm2Rm2)2−4Cm1Cm2gm22gm32(1−gm3Rm)(1+gm2Rm1−Rm1Rm2))).}

[0031] This means that the zero of the right half-plane is determined by the interaction of the current flowing from the third output to the inputs of the second operational amplifier and the third operational amplifier and the frequency-dependent drive current flowing from the second non-inverting input of the second operational amplifier via the first capacitor Cm1 and the first resistor Rm1 to the third output and from the third inverting input of the third operational amplifier via the second capacitor Cm2 and the second resistor Rm2 to the third output. If the zero function of the right half-plane increases, the phase margin decreases and the stability decreases. For stable operation of the electrical circuit 100, the zero in the right half-plane must be eliminated. Therefore, the number of zeros must be minimized. To do this, the s 2-coefficient zero and the s-coefficient of equation (3) greater than zero.

[0032] Therefore, in one embodiment, the resistance Rm=1 / gm3 and the sum of the second resistance Rm2 and the resistance Rm is chosen to be greater than 1 / gm3. This means that the zero elimination of the right half-plane no longer depends solely on the optimal resistance value Rm, since the first resistor Rm1 and the second resistor Rm2 minimize the drive current that generates the zeros of the right half-plane. This increases the phase value. This means that the third transconductance gm3 can vary over a wider range without compromising the stability of the amplifier circuit.

[0033] In another embodiment, the value of the first capacitor Cm1 is reduced, thereby increasing the overall gain and the figure of merit. At the same time, the area requirement of the electrical circuit 100 is reduced. To prevent a reduction in the phase value, the values ​​of the first resistor Rm1 and the second resistor Rm2 can optionally be increased.

[0034] In another embodiment, the resistance Rm is increased so that the zero point of the right half-plane assumes a very large value. In another embodiment, the resistance is further increased so that the zero point of the right half-plane migrates or is shifted to the left half-plane. This increases the phase value and improves stability.

[0035] In a further embodiment, the resistor Rm, the first resistor Rm1, and the second resistor Rm2 can each be configured as a transistor in which a gate-source voltage is greater than a threshold voltage of the transistor and the gate-drain voltage is greater than or equal to the threshold voltage of the transistor. Thus, they are operated in the triode region.

[0036] In all embodiments, the compensation capacitors Cm1 and Cm2 can be determined via the amplifier poles of a third-order Butterworth frequency response at unity gain.

[0037] The electrical circuit 100 has two preferred operating modes. The first operating mode features high stability of the electrical circuit 100, known as stability mode, and the second operating mode features low power consumption of the electrical circuit 100, known as power-saving mode. The wiring of the electrical circuit 100 is the same in both cases. In stability mode, the phase margin is higher, while the FOM is slightly lower due to the higher power consumption. This mode is used for high-speed signal processing, e.g., in switched-capacitor circuits with high clock frequencies. In power-saving mode, the gain bandwidth GBW, the phase margin, the slew rate SR+, and the settling time are lower. Power consumption is 26% lower, resulting in a higher FOM. This mode is used for low-power applications.

[0038] In other words, the transistors are dimensioned to saturate for the lowest possible power consumption, while the frequency compensation elements Cm1, Cm2, Rm1, Rm2, Rm are dimensioned to ensure stability (i.e., phase margin PM and gain margin) with the smallest possible silicon size. Furthermore, transistors M5-M8 are long to minimize noise. The resistance value Rm for canceling the RHP zero point is set independently of resistors Rm1 and Rm2. A good match (i.e., matching) of the first resistor Rm1 and the second resistor Rm2 is no longer required. Regarding stability (i.e., phase margin), a higher Rm value can replace a lower value of gm3, i.e., lower current through the eighteenth transistor M18, thus reducing power consumption. These are major advantages in analog IC design.

[0039] The electrical circuit 100 can be used in charge-sensing amplifiers or signal conditioning blocks or signal conditioning chains based on operational amplifiers. Furthermore, the electrical circuit 100 can be used in pseudo-differential amplifiers.

[0040] Fig. 2 shows a block diagram of the electrical circuit 100 according to the invention. The first operational amplifier Av1 comprises a differential amplifier with a first transistor M1 and a second transistor M2, a current mirror circuit with a third transistor M3 and a fourth transistor M4, a first current mirror circuit with a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8, a cascode circuit with a ninth transistor M9 and a tenth transistor M10, and a current source having an eleventh transistor M11 and a twelfth transistor M12. The first transistor M1 and the second transistor M2, i.e. the differential amplifier, are biased by the current mirror circuit comprising the third transistor M3 and the fourth transistor M4 and a bias current IBIAS.The input current of the first operational amplifier Av1 is the sum of the cascode currents at the drain terminals of the current source. The differential amplifier is designed for an input voltage range of 300–900 mV with a nominal supply voltage of 1.2 V. The input voltage range can be extended using complementary NMOS and PMOS input pairs. To maximize the output signal amplitude, the input common-mode voltage VCM is set to a midpoint between AVDD and AVSS.

[0041] The second operational amplifier Av2 has a thirteenth transistor M13, a fourteenth transistor M14 and a second current mirror circuit with a fifteenth transistor M15 and a sixteenth transistor M16.

[0042] The third operational amplifier Av3 has a seventeenth transistor M17 and an eighteenth transistor M18.

[0043] The gate of the thirteenth transistor M13 acts as the second non-inverting input and is electrically connected to the drain of the tenth transistor M10 and the eighth transistor M8, i.e., the first output of the first operational amplifier Av1. The first output of the first operational amplifier Av1 is electrically connected to the first capacitor Cm1 and the first resistor Rm1, i.e., the so-called frequency compensation elements. The thirteenth transistor M13 forms the second transconductance gm2. The gate of the eighteenth transistor M18 acts as the third inverting input of the third operational amplifier Av3 and is electrically connected to the drain of the fourteenth transistor M14 and the sixteenth transistor M16, i.e., the second output of the second operational amplifier Av2. The eighteenth transistor M18 forms the third transconductance gm3.The second output of the second operational amplifier Av2 is electrically connected to the second capacitor Cm2 and the second resistor Rm2.

[0044] The seventh transistor M7, the eighth transistor M8, the fourteenth transistor M14, and the seventeenth transistor M17 are biased by a first voltage VBB1. The ninth transistor M9 and the tenth transistor M10 are biased by a second voltage VBB2. The eleventh transistor M11 and the twelfth transistor M12 are biased by a third voltage VBB3.

[0045] Fig. Figure 3 shows an application example of the inventive electrical circuit in the form of a CV converter. CV converter 200 comprises a three-stage operational amplifier having an inventive electrical circuit. The input Vin is connected to a series variable capacitor Cs, which generates a differential input signal. This is applied to the gates of the first transistor and the second transistor via Vinn and Vinp. Fig. 2 provided.

[0046] Using wafer-level test measurements of an ASIC that can incorporate such a C / V converter, silicon area is saved and a stable continuous output signal is generated.

[0047] In Fig. Figure 4 shows a table comparing simulation results for various nested Miller compensation structure configurations at nominal operating conditions. A temperature of 25°C, VDD=1.2 V, CL=10 pF, and a DC current consumption of IDC were assumed. The simulated transconductances are gm1=16 µS, gm2=50 µS, and gm3=314 µS. A prior art NMC, an NMC with a resistor, referred to below as NMC-R, and the inventive electrical circuit, referred to as NMC-3R, are compared. Due to the absence of nulling resistors, the NMC configuration has a high phase value of 78° but a low gain bandwidth (GBW) of 0.52 MHz and therefore a low FOM of 155. The NMC-R configuration has a FOM of 477, a typical phase margin of 58°, and a typical gain of 25 dB. The NMC-3R configuration has a FOM of 475, a typical phase margin of 66°, and a typical gain of 21 dB.

[0048] This means that the phase margin of the NMC-3R is improved by 8° compared to the NMC-R configuration. This results in better stability at a comparable FOM. The slew rate remains constant at 1V / µs.

[0049] To achieve a similar phase margin as the NMC-R configuration, the NMC-3R configuration is biased with a lower current, reducing the overall power consumption of the circuit by 26%. This increases the FOM to 488. This configuration is used in Fig. 4 listed under NMC-3R LP. In other words, it is the electrical circuit from Fig. 1, operating in power-saving mode. Total DC power consumption is 24.66 µA.

[0050] In another variation, the resistance Rm in the NMC-3R is increased from 2.6 kΩ to 10 kΩ. This increases the phase margin from 66° to 87°, while the gain decreases from 21 dB to 10 dB, and the output noise only increases slightly. If the transistor width of the seventeenth transistor M17 is reduced to 12 µm / 4 µm, the FOM increases to 742, while the phase margin remains at 68°. This result is shown in Fig. 1 as NMC-3R LA. The dynamic performance of the NMC-3R LA variant is slightly lower, as can be seen in the slew rate and settling time, but it is suitable for low-consumption applications. In other words, this is the electrical circuit of Fig. 1, which operates in stability mode.

Claims

[1] Electrical circuit (100) with • a first operational amplifier (Av1) having a first non-inverting input, a first inverting input and a first output, • a second operational amplifier (Av2) having at least a second non-inverting input and a second output, and • a third operational amplifier (Av3) having at least a third inverting input and a third output, characterized by , that • a feedback path comprises a series circuit of a resistor (Rm), a second resistor (Rm2) and a second capacitor (Cm2), wherein the feedback path is arranged between the third output and the at least one third inverting input, and • a first feedback path comprises a first series circuit with a first resistor (Rm1) and a first capacitor (Cm1), wherein the first feedback path is arranged between a node and the at least one second non-inverting input, wherein the node is arranged between the resistor (Rm) and the second resistor (Rm2). [2] Electrical circuit (100) according to claim 1, characterized by that the third operational amplifier (Av3) has a third transconductance gm3 and the resistance (Rm) has a value which is substantially inversely proportional to the third transconductance gm3 and a sum of the resistance (Rm) and the second resistance (Rm2) is greater than 1 / gm3. [3] Electrical circuit (100) according to one of claims 1 or 2, characterized bythat the resistor (Rm), the first resistor (Rm1) and the second resistor (Rm2) are each designed as a transistor in which a gate-source voltage is greater than a threshold voltage of the transistor and the gate-drain voltage is greater than or equal to the threshold voltage of the transistor. [4] Electrical circuit (100) according to one of the preceding claims, characterized by that the first operational amplifier (Av1) comprises a differential amplifier with a first transistor (M1) and a second transistor (M2), a first current mirror circuit with a fifth transistor (M5), a sixth transistor (M6), a seventh transistor (M7) and an eighth transistor (M8), and a cascode circuit with a ninth transistor (M9) and a tenth transistor (M10). [5] Electrical circuit (100) according to one of the preceding claims, characterized bythat the second operational amplifier (Av2) has a thirteenth transistor (M13), a fourteenth transistor (M14) and a second current mirror circuit with a fifteenth transistor (M15) and a sixteenth transistor (M16). [6] Electrical circuit (100) according to one of the preceding claims, characterized by that the third operational amplifier (Av3) has a seventeenth transistor (M17) and an eighteenth transistor (M18). [7] Single-ended amplifier (200) with an electrical circuit (100) according to one of the preceding claims. [8] Operating method of an electrical circuit (100) according to one of claims 1 to 6, wherein the electrical circuit (100) has a first operating mode that produces high stability and a second operating mode that produces low consumption.

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