Semiconductor device with a bipolar transmitter

Abstract

A semiconductor device (100) is proposed. The semiconductor device (100) comprises a semiconductor body (102) with a first surface (104) and a second surface (106) opposite the first surface (104) along a vertical direction (y). The semiconductor device (100) further comprises a bipolar junction transistor (BJT) (1001). The BJT (1001) comprises an emitter region (108) electrically connected to an emitter contact (E) on the first surface (104), a base region (110) electrically connected to a base contact (B) on the first surface (104), and a collector region (112) electrically connected to a collector contact (C). A dielectric insulating structure (114) extends from the first surface (104) into the semiconductor body (102).The dielectric isolation structure (114) comprises a first substructure (1141) arranged along a first lateral direction (x1) between the emitter contact (E) and the base contact (B). A field plate structure (116), comprising a field plate dielectric (117) and a field plate electrode (118), is arranged on the field plate dielectric (117). A first part (1161) of the field plate structure (116) is arranged on the first surface (104) of the semiconductor body (102), and a second part (1162) of the field plate structure (116) is arranged on the first substructure (1141) of the dielectric isolation structure (114).

Description

TECHNICAL FIELDThe present invention relates to a semiconductor device, and more particularly to a semiconductor device including a bipolar junction transistor, BJT (= bipolar junction transistor).BACKGROUNDThe technological development of new generations of semiconductor components, e.g. bipolar transistors, aims to improve the properties of electrical components and to reduce the costs by shrinking the component geometries. Although the cost may be reduced by shrinking the device geometries, various tradeoffs and challenges must be met in increasing device functionalities per unit area. For example, satisfying reliability requirements affected by, for example, the base current distribution requires design optimization.Therefore, there is a need for an improved bipolar transistor.SUMMARYAn example of the present invention relates to a semiconductor device including a semiconductor body having a first surface and a second surface opposite to the first surface along a vertical direction. The semiconductor device includes a bipolar transistor, BJT (= bipolar junction transistor). The BJT includes an emitter region electrically connected to an emitter contact at the first surface, a base region electrically connected to a base contact at the first surface, and a collector region electrically connected to a collector contact. The BJT further includes a dielectric isolation structure extending into the semiconductor body from the first surface. The dielectric isolation structure comprises a first substructure arranged along a first lateral direction between the emitter contact and the base contact. The BJT further includes a field plate structure including a field plate dielectric and a field plate electrode on the field plate dielectric. A first part of the field plate structure is arranged on the first surface of the semiconductor body and a second part of the field plate structure is arranged on the first substructure of the dielectric insulation structure.Another example of the present invention relates to a method of manufacturing a semiconductor device. The method includes providing a semiconductor body having a first surface and a second surface opposite the first surface along a vertical direction. The method further comprises forming a bipolar transistor, BJT (= bipolar junction transistor), in the semiconductor body. Forming the BJT includes forming an emitter region electrically connected to an emitter contact at the first surface. Forming the BJT further includes forming a base region electrically connected to a base contact at the first surface. Forming the BJT further includes forming a collector region electrically connected to a collector contact. Forming the BJT further includes forming a dielectric isolation structure extending from the first surface into the semiconductor body. The dielectric isolation structure comprises a first substructure arranged along a first lateral direction between the emitter contact and the base contact. Forming the BJT further includes forming a field plate structure including a field plate dielectric and a field plate electrode on the field plate dielectric. A first part of the field plate structure is arranged on the first surface of the semiconductor body and a second part of the field plate structure is arranged on the first substructure of the dielectric insulation structure.Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and viewing the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate examples of semiconductor devices and together with the description serve to explain principles of the examples. Further examples are described in the following detailed description and claims. FIGS. 1 to 3 are partial cross-sectional views for illustrating configuration examples of pnp bipolar transistors. FIG. 4 is a schematic plan view for illustrating an exemplary design of a pnp bipolar transistor. FIG. 5 schematically and exemplarily shows a configuration example of an integrated circuit.DETAILED DESCRIPTIONIn the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific examples of BJTs. It should be understood that other examples may be used and structural or logical changes may be made without departing from the scope of the present invention. For example, features illustrated or described for one example may be used in conjunction with other examples to arrive at yet another example. It is intended that the present invention cover such modifications and variations. The examples are described using a specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Corresponding elements are denoted by the same reference numerals throughout the several drawings unless otherwise indicated.The terms "having", "containing", "including", "comprising" and the like are open terms, and the terms indicate the presence of stated structures, elements or features, but do not exclude the presence of additional elements or features. The indefinite articles and the definite articles are intended to include both the plural and the singular, unless the context clearly indicates otherwise.The term "electrically connected" describes a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the relevant elements or a low-ohmic connection via a metal and / or a highly doped semiconductor material. The term "electrically coupled" includes that one or more intervening elements suitable for signal and / or power transmission may be connected between the electrically coupled elements, for example elements controllable to temporarily provide a low impedance connection in a first state and a high impedance electrical decoupling in a second state. An ohmic contact is a non-rectifying electrical junction.Ranges given for physical dimensions include the limits. For example, a range for a parameter y reads from a to b as a≤y≤b. The same applies to ranges having a limit value such as "at most" and "at least.".The terms "on" and "over" are not to be interpreted as meaning only "directly on" and "directly over". Rather, when an element is positioned "on" or "over" another element (e.g., a layer is "on" or "over" another layer or "on" or "over" a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate if the layer is "on" or "over" the substrate).An example of a semiconductor device includes a semiconductor body having a first surface and a second surface opposite the first surface along a vertical direction. The semiconductor device includes a bipolar transistor, BJT (= bipolar junction transistor). The BJT includes an emitter region electrically connected to an emitter contact at the first surface. The BJT further includes a base region electrically connected to a base contact at the first surface. The BJT further includes a collector region electrically connected to a collector contact. The BJT may further include a dielectric isolation structure extending from the first surface into the semiconductor body. The dielectric isolation structure may include a first sub-structure arranged along a first lateral direction between the emitter contact and the base contact. The BJT may further include a field plate structure including a field plate dielectric and a field plate electrode on the field plate dielectric. A first part of the field plate structure may be arranged on the first surface of the semiconductor body and a second part of the field plate structure may be arranged on the first substructure of the dielectric isolation structure.For example, the BJT may be monolithically implemented using a CMOS or mixed technology. Mixed technologies may be used, for example, to form analog circuit blocks in a chip by the bipolar devices included in this technology for providing interfaces to digital systems and to form digital circuit blocks by the complementary metal oxide semiconductor (CMOS) devices included in this technology for providing signal processing and to form low, medium or high voltage blocks or power blocks by field effect transistors included in this technology. Such mixed technologies are known as, for example, bipolar CMOS DMOS, BCD technologies or smart power technologies, SPT, and are used in a wide variety of applications in the field of, for example, lighting, engine control, automotive electronics, power management for mobile devices, audio amplifiers, power supply, hard disks, printers. The BJT may be part of a BCD or smart power chip in any of the above areas of application, for example.The semiconductor body may be based on various semiconductor materials, for example silicon (Si), silicon-on-insulator (SOI), silicon sapphire (SOS), silicon germanium, germanium, gallium arsenide, silicon carbide, gallium nitride or other compound semiconductor materials. The semiconductor body may be based on a semiconductor substrate, for example a semiconductor wafer, and may include one or more epitaxial layers deposited thereon or may be rediluted.The first surface may be, for example, a front surface or a top surface of the semiconductor body, and the second surface may be a back surface or a back surface of the semiconductor body. The semiconductor body may be attached to a lead frame via the second surface, for example. Bonding pads may be arranged over the first surface of the semiconductor body and bonding wires may be bonded to the bonding pads, for example.The emitter contact may be part of a wiring region above the semiconductor body. The wiring region may comprise one or more than one, e.g. two, three, four or even more wiring levels. Each wiring level may be formed by a single or a stack of conductive layers, e.g. metal layer(s). The wiring planes may be lithographically patterned, for example. An interlayer dielectric structure may be disposed between stacked wiring planes. Contact plugs or contact lines may be formed in openings in the interlayer dielectric structure to electrically connect portions, e.g., metal lines or contact regions, of different wiring levels to each other. For example, the emitter contact may be formed by one or more elements of the wiring region. Likewise, the base contact may be formed by one or more elements of the wiring region. For example, the emitter contact and the base contact may comprise separate parts of a patterned first wiring level, e.g. a first metal layer.The dielectric isolation structure may comprise a single dielectric material or a plurality of joined parts, which may differ in material, shape and / or function, for example. For example, the joined portions of the dielectric isolation structure may be formed by separate processes. For example, the joined parts of the dielectric isolation structure may be parts joined along the first lateral direction. For example, the dielectric isolation structure may be an insulating material such as an oxide, e.g., SiO 2, a nitride, e.g., Si 3 N 4, a high-k dielectric, or a low-k dielectric, or any combination thereof. For example, the dielectric isolation structure may be formed as a CVD (chemical vapor deposition) oxide. For example, the bottom side of the dielectric isolation structure may be at a bottom side of a recess or trench in the semiconductor body. In this case, the dielectric isolation structure may be formed as a shallow trench isolation, STI. The underside of the dielectric isolation structure may also be an underside of an oxidized part of the semiconductor body, e.g. an underside of a LOCOS (LOCOS=local oxidation of silicon). On the dielectric isolation structure, e.g. directly adjacent to a top side of at least a part of the dielectric isolation structure, an interlayer dielectric structure of the wiring region may be arranged. The interlayer dielectric structure may be disposed between the dielectric isolation structure and a first wiring plane of the wiring region over the first surface of the semiconductor body. The first wiring plane may be a wiring plane of the wiring region closest to the first surface of the semiconductor body. The first wiring level may include separate parts, e.g. separate metal layer portions. The separate parts may comprise parts of the emitter contact and / or of the base contact. On the dielectric isolation structure, e.g. directly adjacent to a top side of at least a part of the dielectric isolation structure, the field plate dielectric of the field plate structure may be arranged. The field plate electrode may be formed as part of a patterned highly doped semiconductor layer, e.g. polycrystalline silicon layer, in the wiring region, for example. The patterned semiconductor layer, e.g. highly doped polysilicon layer, may be used as a gate electrode in other circuit parts of the semiconductor body, e.g. in a CMOS circuit block. For example, the field plate structure may extend laterally over a lateral end of the emitter region or may extend laterally up to the lateral end of the emitter region or may end in front of the lateral end of the emitter region.By combining the field plate structure and the dielectric isolation structure, degradation of the device caused, e.g., by drift mechanisms associated with charge accumulation in the dielectric isolation structure caused by device current distribution may be avoided or counteracted. This may allow for improvement of device reliability, for example.For example, the base contact may be arranged between the emitter contact and a collector contact along the first lateral direction. The collector region may be electrically connected to the collector contact at the first surface. Similar to the emitter and / or base contact, the collector contact may be formed by one or more elements of the wiring region. For example, the collector, base and emitter contacts may comprise separate parts of a patterned first wiring level, e.g. a first metal layer.For example, a lateral extension of the first part of the field plate structure along the first lateral direction may have a value in a range from 30% to 90%, or in a range from 30% to 70%, or in a range from 40% to 60%, of a lateral extension of the first substructure of the dielectric isolation structure along the first lateral direction at the first surface.For example, the first part of the field plate structure may laterally protrude beyond the dielectric isolation structure towards the emitter contact. In other words, the first part of the field plate structure may be a part which extends laterally over a side end of the dielectric insulation structure in the direction of the emitter contact.For example, the first part of the field plate structure may laterally protrude beyond the dielectric isolation structure towards the base contact. In other words, the first part of the field plate structure may be a part which extends laterally over a side end of the dielectric insulation structure in the direction of the base contact.For example, a lateral extension of the second part of the field plate structure along the first lateral direction may be smaller than a lateral extension of the first substructure of the dielectric isolation structure along the first lateral direction at the first surface. In other words, only a part of the first substructure of the dielectric isolation structure may be covered by the field plate structure. The other part not covered by the field plate structure may be covered by a part of the interlayer dielectric structure of the wiring region, for example.For example, the field plate electrode may be electrically coupled to the emitter contact. This may allow suppression of undesirable parasitic device behavior. For example, the field plate electrode may be electrically coupled to the emitter contact via a conductive path in the wiring region inside or outside an active region of the BJT.For example, a vertical distance from a bottom side of the first substructure of the dielectric isolation structure to the first surface has a value in a range from 10% to 30% of a vertical distance from a bottom side of the base region to the first surface. For example, the vertical distance from the bottom side of the first substructure of the dielectric isolation structure to the first surface may have a value in a range from 100 nm to 500 nm.For example, the dielectric isolation structure may include a second substructure arranged along the first lateral direction between the base contact and the collector contact. The field plate structure may be omitted, e.g. may be absent, from the second substructure of the dielectric isolation structure. Since degradation of the device caused by, e.g., drift mechanisms associated with charge accumulation in the dielectric isolation structure caused by device current distribution may be more pronounced around the first substructure, the second substructure may not be protected by a field plate structure. This may allow for a more compact device layout, for example.For example, a lateral extension of the first substructure of the dielectric isolation structure along the first lateral direction at the first surface may be greater than a lateral extension of the second substructure of the dielectric isolation structure along the first lateral direction at the first surface.For example, the BJT may be a pnp BJT and the semiconductor body may be a p-doped semiconductor substrate. For example, the semiconductor substrate may be formed from a base substrate, e.g., a wafer or a die of a wafer that has been singulated, that has none, one, or even more semiconductor layers, such as epitaxial semiconductor layers, on the base substrate. For example, the semiconductor substrate may be a Czochralski (CZ), e.g. a magnetic Czochralski, MCZ, or a float zone (FZ), or an epitaxially deposited silicon semiconductor substrate.For example, a doping concentration profile in the base region and a doping concentration profile in the collector region are configured for a collector-to-base breakdown voltage in a range from 5 V to 20 V. For example, the breakdown voltage may be adjusted by ion implantation parameters, e.g., dose and energy, of the base region, among other things. The base region may be formed as an n-doped semiconductor well in the semiconductor body.For example, in a plan view, the field plate structure can at least partially surround the emitter region. For example, the field plate structure may be arranged along all or part, e.g. segments spaced apart from each other, of a path running around the emitter region. The path may have a shape that matches a shape of the emitter region. For example, the path may form a circle, an ellipse, a polygon such as a square or a rectangle, or a hexagon or an octagon.An example of an integrated circuit may include the semiconductor device as in any of the examples described herein. The integrated circuit may further include at least one of a voltage reference circuit and a temperature sensor circuit. The at least one of the voltage reference circuit and the temperature sensor circuit may include the BJT.For example, the integrated circuit may further include a CMOS circuit block. In some examples, the integrated circuit may further include a power semiconductor device block, e.g., a circuit block including a transistor cell region including double-diffuse metal oxide semiconductor (DMOS) or metal oxide semiconductor (MOS) or insulated gate bipolar transistor (IGBT) or junction field effect transistor (JFET) cells. Additionally or alternatively, the integrated circuit may further include a memory circuit block, e.g., a nonvolatile memory circuit block such as flash memory, electrically erasable and programmable read only memory (EEPROM), or one time programmable (OTP)Details regarding the structure or function or technical utility of features described above with respect to a semiconductor device or integrated circuit apply equally to the example methods described herein. Processing the semiconductor body or substrate may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more of the examples described above or below.An example of the present invention relates to a method of manufacturing a semiconductor device. The method includes providing a semiconductor body having a first surface and a second surface opposite the first surface along a vertical direction. The method further comprises forming a bipolar transistor, BJT (= bipolar junction transistor), in the semiconductor body. Forming the BJT includes forming an emitter region electrically connected to an emitter contact at the first surface. Forming the BJT further includes forming a base region electrically connected to a base contact at the first surface. Forming the BJT further includes forming a collector region electrically connected to a collector contact. Forming the BJT may further include forming a dielectric isolation structure extending from the first surface into the semiconductor body. The dielectric isolation structure may include a first sub-structure arranged along a first lateral direction between the emitter contact and the base contact. Forming the BJT may further include forming a field plate structure including a field plate dielectric and a field plate electrode on the field plate dielectric. A first part of the field plate structure may be arranged on the first surface of the semiconductor body and a second part of the field plate structure may be arranged on the first substructure of the dielectric isolation structure.For example, a lateral extension of the first part of the field plate structure along the first lateral direction may be set to a value in a range from 30% to 90%, or in a range from 30% to 70%, or in a range from 40% to 60% of a lateral extension of the first substructure of the dielectric isolation structure along the first lateral direction at the first surface.For example, forming the dielectric isolation structure may further include forming a second substructure arranged along the first lateral direction between the base contact and the collector contact. The field plate structure may be omitted, e.g. may be absent, from the second substructure of the dielectric isolation structure.For example, a lateral extension of the first substructure of the dielectric isolation structure along the first lateral direction at the first surface may be set to a greater value than a lateral extension of the second substructure of the dielectric isolation structure along the first lateral direction at the first surface.The examples and features described above and below may be combined.Functional and structural details described with respect to the above examples apply equally to the example examples illustrated in the figures and described further below.Hereinafter, other examples of semiconductor devices and integrated circuits will be explained in conjunction with the accompanying drawings. Functional and structural details described with respect to the above examples apply equally to the configuration examples illustrated in the figures and described further below. In the illustrated examples, the BJT is a pnp BJT. However, examples described herein may be equally applied to an npn BJT.FIGS. 1, 2, and 3 schematically and exemplarily show configuration examples of a semiconductor device 100 including a BJT 1001. A semiconductor body 102 of the semiconductor device 100 has a first surface 104, e.g. a front surface, and a second surface 106, e.g. a back or back surface, opposite the first surface 104. The first and second surfaces are opposite each other along a vertical direction y. A p+-doped emitter region 108 of the BJT 1001 is electrically connected to an emitter contact E at the first surface 104. The emitter contact E may be part of a wiring region over the first surface 104. An n-doped base region 110 of the BJT 1001 is electrically connected to a base contact B at the first surface 104. The n-doped base region 110 may comprise, for example, a highly n-doped contact region at the first surface 104 for improving the ohmic contact behavior to the base contact B. Similar to the emitter contact E, the base contact B may be part of the wiring region over the first surface 104. A p-doped collector region 112 of the BJT 1001 is electrically connected to a collector contact C, which may also be part of the wiring region over the first surface 104. The p-doped collector region 112 may include a highly p-doped contact region at the first surface 104 for improving the ohmic contact behavior to the collector contact C.A vertical distance d 1 from a bottom side of the first substructure 1141 of the dielectric isolation structure 114 to the first surface 104 may have a value in a range from 10% to 30% of a vertical distance d 2 from a bottom side of the base region 110 to the first surface 104, for example.The BJT 1001 further includes a dielectric isolation structure 114, e.g., STI or LOCOS, extending from the first surface 104 into the semiconductor body 102. The dielectric isolation structure 114 comprises a first substructure 1141 arranged along a first lateral direction x 1 between the emitter contact E and the base contact B. The BJT 1001 further includes a field plate structure 116. The field plate structure 116 includes a field plate dielectric 117 and a field plate electrode 118 on the field plate dielectric 117. A first part 1161 of the field plate structure 116 is arranged on the first surface 104 of the semiconductor body 102 and a second part 1162 of the field plate structure 116 is arranged on the first substructure 1141 of the dielectric isolation structure 114.In the configuration example illustrated in FIG. 1, the first part 1161 of the field plate structure 116 laterally protrudes via the dielectric isolation structure 114 towards the emitter contact E. Thus, the first portion 1161 of the field plate structure 116 extends laterally over a side end of the dielectric isolation structure 114 towards the emitter contact E.In the configuration example illustrated in FIG. 2, the first part 1161 of the field plate structure 116 laterally protrudes via the dielectric isolation structure 114 towards the base contact B. Thus, the first portion 1161 of the field plate structure 116 extends laterally over a side end of the dielectric isolation structure 114 towards the base contact B.In the configuration example illustrated in FIG. 3, the second portion 1162 of the field plate structure 116 completely covers the dielectric isolation structure 114. The first part 1161 of the field plate structure 116 protrudes laterally beyond the dielectric isolation structure 114 in the direction of the emitter contact E. A third portion 1163 of the field plate structure 116 extends laterally over a side end of the dielectric isolation structure 114 towards the base contact B.In the configuration examples illustrated in FIGS. 1 to 3, the dielectric isolation structure 114 comprises a second substructure 1142 arranged between the base contact B and the collector contact C along the first lateral direction x 1. Unlike over the first substructure 1141, the field plate structure 116 on the second substructure 1142 of the dielectric isolation structure 114 is omitted. A lateral extension I 2 of the first substructure 1141 of the dielectric isolation structure 114 along the first lateral direction x 1 at the first surface 104 is greater than a lateral extension I 4 of the second substructure 1142 of the dielectric isolation structure 114 along the first lateral direction x 1 at the first surface 104. The dielectric isolation structure 114 further comprises a third substructure 1143, wherein the collector contact C is arranged between the second substructure 1142 and the third substructure 1143.FIG. 4 is a schematic top view for illustrating an example layout of a pnp bipolar transistor, e.g., a pnp BJT as illustrated in FIG. 1.The emitter region 108 is surrounded by the field plate structure 116. The field plate structure 116 is surrounded by the base region 110 and the base region 110 is surrounded by the collector region 112.Although paths surrounding each of the regions illustrated in FIG. 4 define a square device geometry, the illustrated configuration example is for illustration purposes only and other device geometries, e.g., circular, ellipsoidal, polygonal, such as rectangular or hexagonal, or octagonal geometries, may be used.Contact plugs 120 are disposed on the emitter region 108 as part of the emitter contact E. The contact plugs 120 are also disposed on the base region 110 as part of the base contact B. The contact plugs are also disposed on the collector region 112 as part of the collector contact C. Further contact plugs 120 are disposed on the field plate electrode 118 for electrically coupling the field plate electrode 118 to a reference potential, e.g., to the emitter electrode E.FIG. 5 schematically and exemplarily shows a configuration example of an integrated circuit 200. The integrated circuit 200 includes the semiconductor device 100 as in any of the examples described herein. The semiconductor device 100 is part of a voltage reference or temperature sensor circuit 202. Apart from voltage reference or temperature sensor circuit 202, other circuit blocks may be part of integrated circuit 200.The aspects and features mentioned and described together with one or more of the examples and figures described above may also be combined with one or more of the other examples in order to replace a similar feature of the other example or in order to additionally introduce the feature into the other example.Although specific embodiments have been illustrated and described herein, it will be understood by those of ordinary skill in the art that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents.

Claims

A semiconductor device (100) comprising a semiconductor body (102) having a first surface (104) and a second surface (106) opposite the first surface (104) along a vertical direction (y); and a bipolar transistor, BJT (BJT = bipolar junction transistor) (1001), wherein the BJT (1001) comprises: an emitter region (108) electrically connected to an emitter contact (E) at the first surface (104); a base region (110) electrically connected to a base contact (B) at the first surface (104); a collector region (112) electrically connected to a collector contact (C); a dielectric isolation structure (114) extending from the first surface (104) into the semiconductor body (102), the dielectric isolation structure (114) comprising a first substructure (1141) arranged along a first lateral direction (x1) between the emitter contact (E) and the base contact (B); and a field plate structure (116) comprising a field plate dielectric (117) and a field plate electrode (118) on the field plate dielectric (117), wherein a first part (1161) of the field plate structure (116) is arranged on the first surface (104) of the semiconductor body (102) and a second part (1162) of the field plate structure (116) is arranged on the first substructure (1141) of the dielectric isolation structure (114).The semiconductor device (100) according to the preceding claim, wherein the dielectric isolation structure (114) is a shallow trench isolation, STI, structure or a local oxidation of silicon (LOCOS) structure.The semiconductor device (100) according to any one of the preceding claims, wherein the base contact (B) is arranged between the emitter contact (E) and a collector contact (C) along the first lateral direction (x1), and the collector region (112) is electrically connected to the collector contact (C) at the first surface (104).The semiconductor device (100) according to any of the preceding claims, wherein a lateral extension (I1) of the first part (1161) of the field plate structure (116) along the first lateral direction (x1) has a value in a range of 30% to 90% of a lateral extension (I2) of the first substructure (1141) of the dielectric isolation structure (114) along the first lateral direction (x1) at the first surface (104).The semiconductor device (100) according to any of the preceding claims, wherein the first part (1161) of the field plate structure (116) laterally protrudes beyond the first sub-structure (1141) of the dielectric isolation structure (114) towards the emitter contact (E).The semiconductor device (100) according to any one of claims 1 to 4, wherein the first part (1161) of the field plate structure (116) laterally protrudes beyond the first sub-structure (1141) of the dielectric isolation structure (114) towards the base contact (B).The semiconductor device (100) according to any of the preceding claims, wherein a lateral extension (I3) of the second part (1162) of the field plate structure (116) along the first lateral direction (x1) is smaller than a lateral extension (I2) of the first substructure (1141) of the dielectric isolation structure (114) along the first lateral direction (x1) at the first surface (104).The semiconductor device (100) of any preceding claim, wherein the field plate electrode (118) is electrically coupled to the emitter contact (E).The semiconductor device (100) according to any one of the preceding claims, wherein a vertical distance (d1) from a bottom side of the first substructure (1141) of the dielectric isolation structure (114) to the first surface (104) has a value in a range from 10% to 30% of a vertical distance (d2) from a bottom side of the base region (110) to the first surface (104).The semiconductor device (100) according to any of the preceding claims, wherein the dielectric isolation structure (114) comprises a second substructure (1142) arranged along the first lateral direction (x1) between the base contact (B) and the collector contact (C), and the field plate structure (116) is omitted on the second substructure (1142) of the dielectric isolation structure (114).The semiconductor device according to the preceding claim, wherein a lateral extension (I2) of the first substructure (1141) of the dielectric isolation structure (114) along the first lateral direction (x1) at the first surface (104) is greater than a lateral extension (I4) of the second substructure (1142) of the dielectric isolation structure (114) along the first lateral direction (x1) at the first surface (104).The semiconductor device (100) according to any one of the preceding claims, wherein the BJT (1001) is a pnp BJT and the semiconductor body (102) is a p-doped semiconductor substrate.The semiconductor device (100) according to any one of the preceding claims, wherein a doping concentration profile in the base region (110) and a doping concentration profile in the collector region (112) are configured for a collector-to-base breakdown voltage in a range of 5 V to 20 V.The semiconductor device (100) according to any of the preceding claims, wherein in a plan view the field plate structure (116) at least partially surrounds the emitter region (108).An integrated circuit comprising the semiconductor device (100) according to any one of the preceding claims, wherein the integrated circuit includes at least one of a voltage reference circuit and a temperature sensor circuit, and wherein the at least one of the voltage reference circuit and the temperature sensor circuit includes the BJT (1001).The integrated circuit of the preceding claim, further comprising a CMOS circuit block.A method of manufacturing a semiconductor device (100), the method comprising: providing a semiconductor body (102) having a first surface (104) and a second surface (106) opposite the first surface (104) along a vertical direction (y); and forming a bipolar transistor, BJT (BJT= bipolar junction transistor) (1001) in the semiconductor body, comprising: forming an emitter region (108) electrically connected to an emitter contact (E) at the first surface (104); forming a base region (110) electrically connected to a base contact (B) at the first surface (104); forming a collector region (112) electrically connected to a collector contact (C); forming a dielectric isolation structure (114) extending from the first surface (104) into the semiconductor body (102), the dielectric isolation structure (114) comprising a first substructure (1141) arranged along a first lateral direction (x1) between the emitter contact (E) and the base contact (B); and forming a field plate structure (116) comprising a field plate dielectric (117) and a field plate electrode (118) on the field plate dielectric (117), wherein a first part (1161) of the field plate structure (116) is arranged on the first surface (104) of the semiconductor body (102) and a second part (1162) of the field plate structure (116) is arranged on the first substructure (1141) of the dielectric isolation structure (114).The method according to the preceding claim, wherein a lateral extension (I1) of the first part (1161) of the field plate structure (116) along the first lateral direction (x1) is set to a value in a range of 30% to 90% of a lateral extension (I2) of the first substructure (1141) of the dielectric isolation structure (114) along the first lateral direction (x1) at the first surface (104).The method of the preceding claim, wherein forming the dielectric isolation structure (114) further comprises forming a second substructure (1142) arranged along the first lateral direction (x1) between the base contact (B) and the collector contact (C), and the field plate structure (116) is omitted on the second substructure (1142) of the dielectric isolation structure (114).The semiconductor device according to the preceding claim, wherein a lateral extension (I2) of the first substructure (1141) of the dielectric isolation structure (114) along the first lateral direction (x1) at the first surface (104) is set to a greater value than a lateral extension (I4) of the second substructure (1142) of the dielectric isolation structure (114) along the first lateral direction (x1) at the first surface (104).

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