Semiconductor component and methods for manufacturing a semiconductor component

Abstract

According to the invention, a semiconductor device with a semiconductor substrate is provided, wherein the semiconductor device comprises at least one source element, at least one drain element, and at least one field plate. The semiconductor device according to the invention is characterized in that the at least one field plate surrounds an edge of the semiconductor device and is electrically contacted with the drain element. According to another aspect of the invention, a method for manufacturing a semiconductor device designed according to the invention is proposed.

Description

[0001] The present invention relates to a semiconductor component, preferably a power MOSFET element, and a method for producing a semiconductor component. State of the art

[0002] An essential part of a semiconductor component, such as a power transistor, is the component edge. High field strengths can arise in this region due to the breaking of symmetry. For this reason, a so-called edge structure or edge shielding is usually provided. Various shielding options are known from the state of the art; for example, B. Baliga. Fundamentals of Power Semiconductor Devices. Springer US, 2008, doi:10.1007 / 978-0-387-47314-7 describes various variants. Nevertheless, the edge of the component remains a vulnerable area. Electrical breakdown can occur, which usually destroys the component. If the edge is sufficiently protected, however, the breakdown occurs in the cell array, ideally through what is known as avalanche breakdown in the drift zone. This is not destructive, provided the component is avalanche-capable (e.g., a GaN trench MOSFET).

[0003] Another approach to reducing field peaks is the provision of a field plate. This overhang, usually made of metal, promotes the distribution of the potential drop over a larger area, thus reducing the field strength.

[0004] Field plates and their use in semiconductor components are generally known from the prior art. These are elements made of a conductive material, such as metal or polysilicon, that are electrically insulated from the active semiconductor region and usually short-circuited to the source electrode.

[0005] The field plate is typically located in close proximity to the drift zone. It serves to reduce peaks in the electric field at the edge of the component and at transitions between the n-doped drift zone and other p-doped regions, such as edge structures or the channel region. It compensates for charge in the drift zone and, through its doping, influences the charge carrier concentrations in the drift zone. It enables higher doping in the drift zone, which lowers the component's resistance in the on state, while simultaneously maintaining a high breakdown voltage, which is necessary for the reliable operation of the semiconductor component. Disclosure of the invention

[0006] According to the invention, a semiconductor component comprising a semiconductor substrate is provided, wherein the semiconductor component has at least one source element, at least one drain element, and at least one field plate. The semiconductor component according to the invention is characterized in that the at least one field plate surrounds an edge of the semiconductor component and is electrically contacted with the drain element.

[0007] The invention thus relates to a new type of field plate design that ensures a more favorable field distribution, especially at the edge of the component, with a view to preventing electrical breakdowns. This allows for better utilization of advantageous material parameters, such as the high critical field strength, especially in so-called wide band gap semiconductors.

[0008] In contrast to the conventional approach, the field plate is not located at the source potential, but at the drain potential. This allows for better control of the field distribution in the semiconductor, especially at the component edge. This reduces the breakdown probability in this area and reduces the stress on the passivation layer, which in turn has a positive effect on the component's lifetime.

[0009] The semiconductor component can be, for example, a MOSFET (metal oxide semiconductor field-effect transistor). The semiconductor substrate can be, for example, silicon, another semiconductor substrate, or a silicon-on-insulator (SOI) substrate.

[0010] In a preferred embodiment, the semiconductor component can have a vertical structure. Here, the source element is formed on a first surface of the semiconductor component, and the drain element is formed on a second surface, wherein the second surface is opposite the first surface. The field plate here has a first section and a second section connected to the first region, wherein the first region is formed on the first surface of the semiconductor component, and the second region runs along an edge region of the semiconductor component and is contacted with the drain element. In other words, the field plate has a substantially L-shaped cross-section. The angle between the first section and the second section can, for example, be approximately 90° or more than 90°.

[0011] The field plate can be contacted with the drain element via the highly doped layer of the semiconductor substrate and / or via a metallization of the drain element.

[0012] In a preferred embodiment of the invention, a passivation layer is formed on a surface of the semiconductor component associated with the source element and on an edge of the semiconductor component, such that the passivation layer encloses the edge of the semiconductor component. The field plate is formed on the passivation layer.

[0013] Particularly preferably, at least one doped edge structure is formed in the region of the first surface, wherein the doping of the region differs in particular from the doping of the semiconductor substrate, and wherein the first region of the field plate extends on the surface to the edge of the doped region. The field distribution can be further influenced by this doped edge structure. The doped edge structure preferably has a doping gradient such that the doping decreases toward the edge of the semiconductor component.

[0014] In this case, a passivation layer can be formed on the first surface such that the thickness of the passivation layer increases in a region extending from the edge of the semiconductor component to the edge of the doped region, and the first region of the field plate is formed in the region of the passivation layer in which the thickness of the passivation layer increases. This measure has a positive effect on the field distribution.

[0015] In a preferred embodiment of the invention, the semiconductor component comprises a plurality of source elements, drain elements and gate elements connected in parallel, as well as a plurality of field plates.

[0016] Particularly preferably, the semiconductor component is designed as a power transistor, in particular as a power MOSFET element.

[0017] According to a further aspect of the invention, a method for producing a semiconductor component designed according to the invention is proposed. The method comprises the following steps: a. During the manufacture of an edge of the semiconductor device, etching a semiconductor substrate down to a highly doped layer of the semiconductor substrate in the region of the drain element, b. depositing a passivation layer at least on a surface of the semiconductor component associated with a source element and on the edge of the semiconductor component, c. Applying a field plate to the passivation layer in such a way that the field plate encloses an edge of the semiconductor component and is connected to the drain element in a low-resistance manner by means of the highly doped layer.

[0018] The field plate can preferably be applied during source metallization.

[0019] A contact metallization can also be deposited between the drain element and the field plate material. This can preferably be deposited and patterned together with the contact metallization of the source element.

[0020] The invention provides a semiconductor component in an efficient and cost-effective manner which is protected against electrical breakdowns in the component edge region and can thus have an improved service life and reliability. Drawings

[0021] Embodiments of the invention are explained in more detail with reference to the drawings and the following description. They show: Fig. 1 a) to c): each shows a section through a semiconductor component known from the prior art, Fig. 2: a section through a semiconductor component according to a first embodiment of the invention, Fig. 3: a section through a semiconductor component according to a second embodiment of the invention, wherein only one edge region of the semiconductor component is shown. Embodiments of the invention

[0022] In the following description of the exemplary embodiments of the invention, identical elements are designated by identical reference numerals, whereby a repeated description of these elements is omitted where appropriate. The figures only schematically illustrate the subject matter of the invention.

[0023] Fig. 1 a) shows a section through the edge region of a semiconductor component 20 according to the prior art. In this example, the semiconductor component 20 comprises an n-doped semiconductor 1 with a p-doped region 2 to create a blocking junction. The regions are contacted by contact 5 of the drain region 15 and contact 6 of the source region 16. In addition, a passivation layer 7, for example an oxide layer, is located on the surface 21 associated with the source element 6. Various measures are known from the prior art for reducing field peaks. In the example according to Fig. 1 a) below the passivation layer 7 is a p-doped edge structure with a doping gradient.

[0024] Alternatively, it is known, as in Fig. 1 b), to reduce field peaks, so-called guard rings 40, 41, 42 are provided beneath the passivation layer 7. In this example, these guard rings 40, 41, 42 are formed as annular p-doped regions on the surface 21 at the edge of the semiconductor component 20.

[0025] Furthermore, it is known how in Fig. 1 c), to reduce field peaks, one or more field plates 61 are provided above the passivation 7, which are conductively connected to the source region 2, for example, via the source contact 6. This overhang, usually made of metal, promotes the distribution of the potential drop over a larger spatial area and thus reduces the field strength.

[0026] Fig. 2 shows a section through the edge region of a semiconductor component 20 according to a first embodiment of the invention.

[0027] In this example, the semiconductor component 20 comprises an n-doped semiconductor 1. A p-doped region 2 is formed on a first surface 21, which, together with a source contact 6, forms a source element 16 of the semiconductor component 20. In the region of a second surface 22, which lies opposite the first surface 21, a highly n-doped semiconductor layer 9 is formed, which is covered by a metallic layer, the drain contact 5. The highly n-doped semiconductor layer 9 and the drain contact 5 form the drain element 15 of the semiconductor component 20. Adjacent to the source contact 6, on the surface 21 assigned to the source element 16, there is a passivation layer 7. The semiconductor component 20 furthermore has a p-doped edge structure 3 with a doping gradient.

[0028] During the production of the edge 8 of the semiconductor component 20, the so-called mesa edge, etching takes place down to the highly n-doped layer 9 in the region of the drain contact 5. After the passivation layer 7 has been deposited, a field plate 10 is also produced during the source metallization process, which encloses the edge 18 of the semiconductor component 20. The field plate 10 is connected to the drain contact 5 via the highly doped semiconductor 9 in a low-resistance manner and, separate from the passivation layer 7, covers the edge 8 of the semiconductor component 20. The field plate 10 comprises a first section 11 that runs essentially parallel to the first surface 21 of the semiconductor component 20. The field plate 10 runs around the edge 18 of the semiconductor component 20 and comprises a second section 12 that runs along the edge 8 of the semiconductor component 20 and is in contact with the drain element 15.On the front side of the semiconductor component 20, the field plate 10 bends and thus encloses the edge 18 of the semiconductor component 20. The first section 11 of the field plate extends, for example, approximately to the outer edge 13 of the p-doped edge structure 3 of the semiconductor component 20. As a result, the drain potential is advantageously impressed on all semiconductor regions adjacent to and below the field plate 10, and the potential profile toward the p-doped edge structure 3 can be influenced by the overhang of the field plate and the thickness of the passivation layer 7.

[0029] Fig. Figure 3 shows a section through the edge region of a semiconductor component 20 according to a second embodiment of the invention. In contrast to the variant according to Fig.2, the semiconductor component 20 comprises a passivation layer 7 which, on the surface 21 assigned to the source element 16, has a region 17 in the region of the edge 8 with a thickness increasing from the edge 8. The region 17 in which the thickness of the passivation layer 7 increases approximately terminates at the outer edge 13 of the p-doped edge structure 3. The first section 11 of the field plate 10 is formed on the region 17. The angle between the first section 11 and the second section 12 of the field plate is therefore more than 90° in this example.

[0030] The effectiveness of the field plate, or rather its compensating influence on the electric field in the semiconductor and at the transition from semiconductor to passivation, depends, among other things, on the spatial distance. The design shown here increases the effectiveness of the field plate continuously towards the edge, depending on the angle (steeper = faster). This provides an additional degree of freedom for optimizing the field distribution. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited non-patent literature

[0000] B. Baliga. Fundamentals of Power Semiconductor Devices. Springer US, 2008, doi:10.1007 / 978-0-387-47314-7

[0002]

Claims

[1] Semiconductor component (20) with a semiconductor substrate (1), comprising at least one source element (16), at least one drain element (15), and at least one field plate (10), characterized by that the at least one field plate (10) encloses an edge (18) of the semiconductor component (20) and that the field plate (10) is electrically contacted with the drain element (5). [2] Semiconductor component (20) according to claim 1, wherein the semiconductor component (20) has a vertical structure, wherein the source element (16) is formed on a first surface (21) of the semiconductor component (20) and the drain element (15) is formed on a second surface (22), wherein the second surface (22) is opposite the first surface and wherein the field plate has a first section (11) and a second section (12) connected to the first region (11), wherein the first region (11) is formed on the surface (21) of the semiconductor component (20) and the second region (12) runs along an edge (8) of the semiconductor component (20) and is in contact with the drain element (5). [3] Semiconductor component (20) according to one of the preceding claims, wherein the field plate (10) is contacted with the drain element (5) via a highly doped layer (9) of the semiconductor substrate (1) and / or a drain metallization (5). [4] Semiconductor component (20) according to one of the preceding claims, wherein at least one passivation layer (7) is formed on a first surface (21) of the semiconductor component (20) associated with the source element (16) and on an edge (8) of the semiconductor component (20), wherein the field plate (10) is formed on the passivation layer (7). [5] Semiconductor component (20) according to one of claims 2 to 4, wherein in the region of the first surface (21) at least one doped edge structure (3) is formed in the semiconductor substrate (1), wherein a doping of the edge structure (3) differs in particular from the doping of the semiconductor substrate (1) and wherein the first region (11) of the field plate (10) on the surface (21) extends to the outer edge (13) of the doped edge structure (3). [6] Semiconductor component (20) according to claim 5, wherein the thickness of a passivation (7) on the first surface (21) increases in a region (17) starting from the edge (18) of the semiconductor component (20) to the edge of the doped region (3) and the first region (11) of the field plate (10) is formed on the region (17) of the passivation (7). [7] Semiconductor component (20) according to one of the preceding claims, wherein the semiconductor component (20) comprises a plurality of source elements (16), drain elements (15) and gate elements connected in parallel, as well as a plurality of field plates (10). [8] Semiconductor component (20) according to one of the preceding claims, wherein the semiconductor component is designed as a power transistor, in particular as a power MOSFET element. [9] Method for producing a semiconductor component (20), in particular a semiconductor component (20) according to one of claims 1 to 8, comprising the steps: a. During the production of an edge (8) of the semiconductor component (20) with an edge (18), etching a semiconductor substrate (1) down to a highly doped layer (9) of the semiconductor substrate (1) in the region of the drain element (15), b. depositing a passivation layer (7) at least on a surface (21) of the semiconductor component (20) associated with a source element (16) and on an edge (8) of the semiconductor component (20), c. Applying, in particular during source metallization, a field plate (10) to the passivation layer (7) such that the field plate (10) encloses an edge (18) of the semiconductor component (20) and is connected to the drain element (15) in a low-resistance manner by means of the highly doped layer (9).

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