Semiconductor package and electronic power module with several such semiconductor packages

Abstract

The invention relates to a semiconductor package (212, 215, 220) for an electronic power module (202), comprising a ceramic substrate (600) having a ceramic layer (800) between a lower copper layer (805) and an upper copper layer (810), two first load terminals (300, 305) each having a leadframe (615, 620), wherein one of the first load terminals (300) is associated with at least one first power semiconductor (335) and the other first load terminal (305) is associated with at least one second power semiconductor (350), and wherein the respective power semiconductor (335, 350) is arranged between the upper copper layer (810) of the ceramic substrate (600) and the leadframe (615, 620) of the associated first load terminal (300, 305) and is electrically connected thereto, a second load terminal (310) which is connected to the upper Copper layer (810) is electrically connected, a control terminal (605) which is connected to signal pins (325, 330) for controlling the semiconductor package (212,215, 220) and is electrically connected to the power semiconductors (335, 350) via connecting elements (610). Furthermore, the invention relates to an electronic power module (202) for an engine control (200), an electric drive axle (100), and a motor vehicle (105).

Description

The present invention relates to a semiconductor package for an electronic power module and to an electronic power module for a motor controller having a plurality of such semiconductor packages. The invention further relates to an electric drive axle comprising such a power module, and to a motor vehicle.For example, DE 10 2009 044 659 A1 discloses a power semiconductor module comprising a lead frame, a power semiconductor element and a cylindrical conductor. A part of the lead frame, the power semiconductor element, and the cylindrical conductor are each sealed by an injection molding resin, terminal portions of the lead frame project from peripheral side portions of the power semiconductor module, and an opening of the cylindrical conductor is exposed at an upper surface of the power semiconductor module.It is an object of the invention to provide a compact semiconductor package which can realize improved performance in a given installation space. The invention achieves this object by means of the subject matter of the independent claims. Dependent claims represent preferred embodiments.A semiconductor package according to the invention for an electronic power module comprises a ceramic substrate which has a ceramic layer between a lower copper layer and an upper copper layer, two first load terminals each having a leadframe, wherein one of the first load terminals is assigned to at least one first power semiconductor and the other first load terminal is assigned to at least one second power semiconductor, and wherein the respective power semiconductor is arranged between the upper copper layer of the ceramic substrate and the leadframe of the associated first load terminal and is electrically connected thereto, a second load terminal which is electrically connected to the upper copper layer, a control terminal which is electrically connected to signal pins for controlling the semiconductor package and to the power semiconductors via connecting elements.The semiconductor package is to be understood as a discrete individual package of an electronic power module. The semiconductor package can be used in a half bridge of a motor controller, wherein two semiconductor packages form a half bridge. A plurality of half bridges, preferably three half bridges, can be provided separately in a controllable manner in order to actuate an electric machine of a motor vehicle. The semiconductor package serves for switching current, in particular in the case of loads in the several-10 kW range, in particular for electric machines, e.g. for a motor vehicle.By providing two first load terminals and allocating at least one power semiconductor or chip per first load terminal, the number of power semiconductors on a given area of the ceramic substrate can be increased. In other words, the packing density of the semiconductor package is maximized. By suitable arrangement of the first load terminals, the second load terminal and the power semiconductors, that is to say by suitable selection of a topology for the semiconductor package, it is also possible to realize current symmetry. The semiconductor package is configured to be current-symmetrical if the current flow within the semiconductor package is divided uniformly. This means that the current in different paths or branches of a circuit is always of equal strength. The current symmetry ensures that the circuit functions properly and that no undesired effects occur. In addition, a semiconductor package described herein improves electrical testability, which may increase yield. Furthermore, the heat dissipation of the power semiconductors can be optimized, in particular by heat spreading.The ceramic substrate may be an AMB (Active Metal Brazing) substrate, or DBC (Direct Copper Bonding) substrate or DPC (Direct Plated Copper) substrate. The ceramic layer is an electrical insulation layer. The ceramic layer is formed from aluminum oxide or from silicon nitride, for example.The lower copper layer of the ceramic substrate is configured to be connected to a heat sink. In other words, the lower copper layer is designed for cooling connection. The lower copper layer is to be understood as a rear side or underside of the package, which is connected to a heat sink in a materially bonded manner, for example. The heat sink is preferably part of a power module.The load connections can be formed from a common metal sheet and formed as stamped grids by punching and forming and brought into their final shape. After punching and forming the sheet, bonding the sheet to the ceramic substrate, and subsequent encapsulation, a remaining frame, which may be fixed during manufacturing, may be separated from the load terminals to separate the load terminals.The first load terminals are configured to electrically connect a busbar to the power semiconductors of the semiconductor package. The first load terminals together form the AC terminal and the "source" side of the semiconductor package, respectively. By providing two first load connections, the power supply can be divided and directed into the semiconductor package. The semiconductor package can thus be made more compact and current symmetry can be realized on account of the identical number of corresponding power semiconductors per first load terminal. The power density is thus increased while at the same time having a compact design. The second load terminal forms the DC plus terminal or the "drain" side of the semiconductor package.The load terminals may include a plurality of integrally connected legs, connectors, and / or arms. A connection leg of each load connection, i.e. a leg which serves as a connection element for the external connection of the semiconductor package and has a contact surface, can be arranged three-dimensionally in space in such a way that the contact surfaces of all load connections are arranged in a common plane, in particular on an upper side of the semiconductor package. The connection to the semiconductor package can thus be improved.The first load terminals comprise leadframes, i.e. connecting or guiding frames, which are shaped such that a busbar connected to the first load terminals is arranged at least indirectly on the respective power semiconductor. The respective leadframe conducts the electrical energy present at the first load terminal to the associated power semiconductor. If a plurality of first and second power semiconductors are provided, the respective leadframe can be designed in such a way that the electrical energy is distributed uniformly via cross connectors or branches to all first and second power semiconductors.The control terminal is to be understood as a gate rotor of the semiconductor package. The control terminal includes a signal substrate having a ceramic layer disposed between a lower copper layer facing the ceramic substrate and an upper copper layer. The lower copper layer of the signal substrate has the same potential as the upper copper layer of the ceramic substrate. The upper copper layer of the control terminal is electrically connected to the signal pins and the connection elements. With regard to the material of the substrate, reference is made to the explanations relating to the ceramic substrate.The connecting elements are preferably designed as bonding wires. Two bonding wires each electrically connect the upper copper layer of the control terminal to one of the power semiconductors. The bonding wires are formed, for example, from aluminum or another material with good electrical conductivity.The power semiconductor is a current valve having an input, an output and a control terminal. The input and the output are connected to the upper copper layer and the leadframe, respectively. The power semiconductor can be electrically insulated by encapsulation, in particular injection molding, preferably transfer molding. Current scaling can be effected via the number and size of the parallel-connected power semiconductors.The ceramic substrate is preferably substantially rectangular, wherein a first load terminal is respectively assigned to one of the longer sides and the second load terminal is assigned to one of the shorter sides of the ceramic substrate. In other words, the first load terminals are arranged on opposite sides of the semiconductor package and may extend in opposite directions. The semiconductor package can thus be formed symmetrically. Furthermore, the semiconductor package can be used flexibly. The second load terminal is preferably arranged centrally on one of the shorter sides of the semiconductor package.The upper copper layer of the ceramic substrate is at least electrically connected to further components of the semiconductor package. First sinter layers are preferably applied to the upper copper layer in order to at least electrically connect the upper copper layer of the ceramic substrate in each case to the second load terminal and to the power semiconductors. By the plurality of components connected to the upper copper layer, a plurality of separate first sinter layers are also arranged on the surface of the upper copper layer of the ceramic substrate. In addition to the electrical connection, the upper copper layer of the ceramic substrate is preferably thermally connected in each case to the second load terminal, to the control terminal and to the power semiconductors.The first sinter layers can be formed as receptacles, in particular for the power semiconductors, wherein power semiconductors arranged in the receptacles are electrically connected in parallel between the upper copper layer and the leadframe. A sintered layer is provided for the purpose of producing or fixing an electrical connection between two components of the semiconductor package. In addition, the sintered layer improves the thermal properties in the contact region. The sintered layer enables a reliable and permanent connection between two components. The sintering layer is produced by a sintering process in which powder particles, a sintering paste or a sintering film are melted by heat and pressure and a dense and homogeneous layer is thus produced, which in particular enables efficient heat transfer. The sinter layer can consist of different materials which on the one hand have electrically conductive and on the other hand have good thermal properties.Preferably, a second sinter layer, a bond buffer layer and a solder layer are arranged between the respective leadframe and the associated power semiconductor starting from the respective power semiconductor. In other words, the bond buffer layer is arranged between the solder layer and the second sinter layer, wherein the solder layer is assigned to the leadframe and the second sinter layer is assigned to the respective power semiconductor. The second sinter layer realizes a dense, homogeneous connection layer between the power semiconductor and the bond buffer. The bond buffer may be a copper layer. The solder layer realizes a dense, homogeneous connection layer between the bond buffer layer and the leadframe. The solder layer may alternatively be a sintered layer. Reference is made accordingly to the above statements, which can be applied analogously.The bond buffer is a layer which brings about a reduction in the mechanical stress on the power semiconductor. The bond buffer compensates for different thermal expansion coefficients between the leadframe and the power semiconductor. In addition, the heat of the power semiconductor is dissipated better by the bond buffer. Temperature hotspots can thereby be avoided, as a result of which the power semiconductor is less stressed and as a result has an improved service life. Consequently, the bond buffer layer further improves the performance of the semiconductor package.A solder layer is "softer" than a sintered layer and can thus in particular compensate for forces which can arise as a result of so-called "thermal mismatch". Thermal mismatch is understood to mean the situation when two components or materials have different coefficients of thermal expansion and therefore expand or contract differently with temperature changes. This can lead to stresses and deformations, in particular if the materials or components are connected to one another. The thermal discrepancy may lead to cracks, delaminations or other damage. The solder layer is configured to compensate for this discrepancy. The solder layer can be formed depending on the configuration of the leadframe, in particular any cross connectors or arm segments. The solder layer can be segmented and can in principle have any desired surface geometry.Preferably, exactly two signal pins are connected to the control terminal. In other words, exactly two signal pins are connected to the upper copper layer of the control terminal and the signal substrate, respectively. If only two signal pins are provided, then these pins are provided for gate control of the semiconductor package. The power semiconductors are controlled via the two signal pins, the upper copper layer of the signal substrate and the connecting elements. The signal pins are connected to the power semiconductors in a signal-transmitting manner.In a further development of the invention, the control terminal is electrically connected to further signal pins which are electrically connected via additional connecting elements to a temperature sensor arranged on the upper copper layer of the ceramic substrate. In the case of bonding wires as connecting elements, two further bonding wires are electrically conductively connected between the upper copper layer of the signal substrate of the control connection and the temperature sensor. The further signal pins are connected for controlling the temperature sensor. The further signal pins are connected to the temperature sensor in a signal-transmitting manner. The temperature sensor may be connected to the upper copper layer of the ceramic substrate via another first sintered layer to sense a temperature of the ceramic substrate. To simplify the structure and / or if a temperature of the power semiconductors or other elements of the semiconductor package can be otherwise tapped, the temperature sensor with the associated additional components can be dispensed with.The semiconductor package furthermore preferably comprises two or more first power semiconductors and a number of second power semiconductors identical thereto. In other words, the semiconductor package has just as many first power semiconductors as second power semiconductors. One first load terminal is thus electrically connected to two or more first power semiconductors via the associated leadframe, while the other first load terminal is electrically connected to the two or more second power semiconductors via the associated leadframe. Current scaling can be effected by adapting the number of chips. Preferably, six power semiconductors are provided, of which three power semiconductors are assigned to one of the first load connections and the remaining three power semiconductors are assigned to the other first load connection. The size or area of the power semiconductors can likewise be adapted in the sense of current scaling. An area of 20, 25 or 32 mm 2. is conceivable. For reasons of current symmetry, however, it is advantageous if all power semiconductors have the same size or area, i.e. the same properties.In order to further improve the current symmetry, the at least two first power semiconductors are arranged in series and at a distance from one another, wherein the at least two second power semiconductors are arranged in series and at identical distances from one another and parallel to the first power semiconductors. In the longitudinal direction of the semiconductor package, i.e. along the longer side of the rectangular ceramic substrate, the first and second power semiconductors have substantially constant distances from one another. Likewise, the first and second power semiconductors have a constant distance from one another in the transverse direction. In the case of three first and three second power semiconductors each, these are thus arranged in a 2x3 arrangement on the upper ceramic layer of the ceramic substrate. The control terminal can be elongated and oriented substantially parallel to the two power semiconductor rows. The control terminal is arranged in particular between the two power semiconductor rows.In the case of a plurality of first and second power semiconductors, the respective leadframe preferably has at least one cross connector which connects the first load terminal to in each case two first and two second power semiconductors. In other words, the leadframe of the one first load terminal has at least one first cross connector, which connects two first power semiconductors to one another in each case, wherein the leadframe of the other first load terminal in each case comprises at least one second cross connector, which connects two second power semiconductors to one another in each case.Furthermore, the respective transverse connector preferably comprises one or more arm segments which come to rest at least in sections on the solder layer. Accordingly, the first cross connector of the leadframe of one of the first load terminals has at least one first arm segment for electrically connecting the respective first load terminal to one of the first power semiconductors and at least one second arm segment for electrically connecting the same first load terminal to a further first power semiconductor. For each further first power semiconductor, the first cross connector of the leadframe may comprise at least one further arm segment in order to realize an electrical connection with the further first power semiconductor. It is also possible for two or more cross connectors to be provided in order to electrically connect the respective first load terminal to one or more power semiconductors. All that has been stated up to now and below for the one first load connection applies equally and analogously to the respective other first load connection, and vice versa. The first load connections are designed mirror-symmetrically.In order to keep the contact area between the leadframe and the power semiconductor as low as possible, it is advantageous if the respective arm segment is divided into a plurality of sections, wherein contact sections are provided for contacting and connection sections are provided for connecting two contact sections. In other words, the respective leadframe can be connected to the associated power semiconductor via a plurality of smaller areas. Said connecting section is a kind of bridge, whereby the contact surface with the chip and thus voltages within the system are reduced. The respective arm segment preferably has at least two contact sections which contact the solder layer, wherein the two contact sections are connected to one another via the connecting section which does not contact the solder layer. One of the abutment sections is connected to the respective leadframe, while the other abutment section forms a distal end of the respective arm segment.In order to further improve the current symmetry within the upper copper layer of the ceramic substrate, the semiconductor package further comprises two third load terminals which have the same potential as the second load terminal and which are each electrically connected to the upper copper layer of the ceramic substrate. The third load connections are load connections for current balancing. For this purpose, the third load terminals are preferably arranged at an opposite end of the ceramic substrate with respect to the second load terminal and have a potential identical to the second load terminal. The third load terminals also form the "drain" side of the semiconductor package. On the side of the upper copper layer facing away from the ceramic layer, a respective first sinter layer can be arranged between the respective third load terminal and the upper copper layer of the ceramic substrate in order to improve contacting.Preferably, a third load terminal is respectively assigned to one of the longer sides of the ceramic substrate. In other words, the third load terminals are arranged on opposite sides of the semiconductor package and extend in opposite directions analogously to the first load terminals. The third load connections are arranged spaced apart from the first load connections in the transverse direction, preferably so far away that no interaction can occur during operation. On each of the longer sides of the semiconductor package, a first load terminal and a third load terminal are thus arranged. The third load terminals can also have an abutment surface which lies in a plane with the abutment surfaces of the first load terminals or of the second load terminal on the upper side of the semiconductor package. Depending on the configuration of the power module, the third load terminals may be arranged on the opposite short side of the ceramic substrate with respect to the second load terminal.For insulating the components of the semiconductor package, the semiconductor package is encapsulated by injection molding. In other words, the semiconductor package is encapsulated in a so-called molding process. The molding process is a method in which a plastic package made of insulating material is molded around one or more power semiconductors. The encapsulation protects the power semiconductors from external influences such as moisture and dust. The molding process includes injecting liquid plastic as an insulating material into a mold in which the components of the semiconductor package are placed. After the plastic has cured, the mold or the tool is removed, with the semiconductor package being protected. The semiconductor package is encapsulated, for example, by means of transfer or compression molding.In transfer molding, a defined amount of a molding material, typically a thermosetting plastic or thermoplastic, is filled into a mold cavity through a gate. During transfer molding, the walls of the mold are typically heated to a temperature above the melting temperature of the mold material in order to obtain good flow properties of the material within the cavity. A large number of different thermoplastics and thermosetting plastics are suitable for transfer molding.If the semiconductor package comprises third load terminals which are likewise assigned to the longer sides of the ceramic substrate and are arranged at a distance from the first load terminals, at least one cutout is formed spatially in the insulation material between the first and third load terminals of the same side of the semiconductor package. The recess can be a bead, a shoulder or the like, which is formed or formed in the insulation material (also called "mold") and is provided for the generation of a necessary air and creep paths. The respective cutout is therefore advantageous for a compact configuration of the semiconductor package, since the first load terminal and the third load terminal of the respective side of the ceramic substrate can thereby be arranged closer to one another without the load terminals having a negative influence on one another.In a further aspect of the invention, an electronic power module according to the invention comprises a cooling body on which a plurality of semiconductor packages according to one of the preceding claims are arranged. The lower copper layer of the ceramic layer of the respective semiconductor package can be connected to the heat sink, for example, by means of so-called nanowire technology, by sintering, soldering or pressing by means of an organic insulator. The lower copper layer can be directly connected to the heat sink. Alternatively, an insulation layer can be arranged between the lower copper layer and the heat sink.Preferably, six semiconductor packages are arranged on the heat sink, wherein in each case two semiconductor packages are combined to form a half bridge and are each connected in series one behind the other. In an alternative embodiment, twelve semiconductor packages are arranged on the heat sink, wherein four semiconductor packages are combined in each case to form a half bridge. The half bridges resulting therefrom are preferably connected electrically in parallel. In the case of six semiconductor packages, one semiconductor package per switching position is provided in each case. In the case of twelve semiconductor packages, two semiconductor packages per switching position are provided in each case. Regardless of the number of semiconductor packages, all semiconductor packages can be arranged and cooled on a common cooling body, for example formed as a cooling plate or the like.In a further aspect of the invention, an electric drive axle according to the invention, also called an E-axle, comprises an electric machine and an electronic power module proposed herein. The electric machine is a three-phase electric machine. The power module is provided in a motor controller which controls the electric machine. In addition to the electric machine, the electric drive axle may include an optional transmission to provide torque and speed for driving a drive wheel of the motor vehicle. In addition to the electric machine, a motor controller may also be included. The electric machine is supplied with electrical energy from an energy store.In a further aspect of the invention, a motor vehicle according to the invention comprises an electric drive axle according to the invention or an electronic power module according to the invention. The motor vehicle can in particular comprise a motorcycle, a passenger car, a truck or an bus. The motor vehicle comprises at least two axles. Preferably, two axles are provided, wherein at least one of the axles is an electric drive axle and can be driven by at least one electric machine.The above definitions and statements regarding technical effects, advantages and advantageous embodiments of the semiconductor package according to the invention also apply analogously to the power module according to the invention according to the second aspect of the invention, to the electric drive axle according to the invention according to the third aspect of the invention and to the motor vehicle according to the invention according to the fourth aspect of the invention, and vice versa. It is understood that the features mentioned above and those still to be explained below can be used not only in the respectively specified combination, but also in other combinations or alone, without departing from the scope of the present invention.If elements are designated with the aid of a numbering, i.e. for example "first component", "second component" and "third component", this numbering is provided purely for differentiation in the designation and does not represent a dependence of the elements on one another or a obligatory sequence of the elements. This means in particular that a device does not have to have a "first component" in order to be able to have a "second component". The device can also comprise a "first component" and a "third component", but without necessarily having a "second component".The invention will now be described in more detail with reference to the accompanying figures, in which: FIG. 1 is a highly schematic view of a motor vehicle with an electric drive axle; FIG. 2 shows an exemplary motor control of the drive axle, comprising an electronic power module according to the invention with half bridges; FIG. 3 is a circuit diagram showing the circuit of the electronic power module of the present invention shown in FIG. 2; FIG. 4 shows a schematic view of the electronic power module according to the invention according to FIGS. 2 and 3 with a plurality of semiconductor packages according to the invention; FIG. 5 is a schematic perspective view of an exemplary semiconductor package of FIG. 4 according to a first embodiment; FIG. 6 shows a schematic exploded illustration of the semiconductor package according to FIG. 5 ; FIG. 7 shows a schematic perspective illustration of the semiconductor package according to FIGS. 5 and 6 without illustration of the insulation material; FIG. 8 shows a schematic side view of the semiconductor package according to FIGS. 5 to 7 without illustration of the insulation material; FIG. 9 shows a detailed sectional illustration of the semiconductor package according to FIG. 8 for illustrating the electronic connection of a power semiconductor; FIG. 10 shows a detailed perspective illustration of the semiconductor package according to FIGS. 5 to 9 for illustrating the electronic connection of a leadframe to power semiconductors; FIG. 11 shows a schematic plan view of the semiconductor package according to the invention according to a second embodiment without illustration of the insulation material; and FIG. 12 shows a schematic plan view of the semiconductor package according to the invention according to a third embodiment without illustration of the insulation material;wherein identical or similar components are provided with the same reference number.FIG. 1 shows an electric drive axle 100 in a motor vehicle 105. The motor vehicle 105 may additionally include an internal combustion engine 110 connected to a drive wheel 120 of the motor vehicle 105 via a transmission 115. In this case, the motor vehicle 105 would be a hybrid vehicle.The electric drive axle 110 comprises an electric machine 125 which can likewise act on the drive wheel 120, preferably by means of the transmission 115. Furthermore, a power converter 130 can be provided, which can be fed with electrical energy from an electrical energy store 135. The electrical energy store 135 is preferably electrochemically constructed, but a fuel cell or another current source can also be used, for example. The power converter 130 is preferably configured to provide phase-shifted alternating currents to the electric machine 125. The electric machine 125 is realized, for example, as a permanently excited synchronous machine, but other embodiments are likewise possible. Provided voltages and frequencies of the alternating currents can be determined such that the electric machine 125 converts a predetermined torque or rotates at a predetermined rotational speed. For controlling the direction of rotation and the speed of rotation, a field-oriented control can be realized. A rated voltage of the electrical energy store 135 is usually a plurality of 100 to above 1000 V. A current through the electrical drive machine 125 may be a plurality of 100 A.FIG. 2 shows a motor controller 200 having a power module 202, comprising three half bridges 205, which can be actuated by way of example by means of a common control device 210. The motor controller 200 is configured to control a rotational behavior of the electric machine 125 and usually operated digitally by means of a microcomputer.Each half bridge 205 comprises two semiconductor packages 212 according to the invention, divided into an upper semiconductor package 215 and a lower semiconductor package 220, wherein the semiconductor packages 212, 215, 220 are connected in series between DC voltage potentials of the energy store 135 in the manner shown. An intermediate circuit capacitor 225 is preferably provided between the potentials. A center tap 230 between the semiconductor packages 212, 215, 220 is connected to an associated phase of the electric machine 125. The upper semiconductor package 215 is located between a high potential of the energy store 135 and the center tap 230, and the lower semiconductor package 220 is located between the center tap 230 and a low potential of the energy store 135.The semiconductor packages 212, 215, 220 can be controlled independently of one another in each case to close or open in the manner of an electrical switch. The control device 210 is configured to close and open the semiconductor packages 212, 215, 220 alternately, so that at no time are both semiconductor packages 215, 220 of a half bridge 205 closed. A voltage which is established at the center tap 230 of the respective half bridge 205 is dependent on a ratio of switch-on durations of the upper semiconductor package 215 and of the lower semiconductor package 220. In a usual operation of the electric machine 125, predetermined currents can thus be controlled by the semiconductor packages 212, 215, 220.FIG. 3 shows a circuit diagram of the semiconductor package 212, 215, 220 of the power module 202. In the present case, the respective semiconductor package 212, 215, 220 has two first load terminals 300, 305, which are combined here to form a terminal as a "source" for simplification purposes, a second load terminal 310 and two third load terminals 315, 320, which are combined here to form a terminal as a "drain" for simplification purposes. The semiconductor package 212, 215, 220 also has two signal pins 325, 330 as control terminals, which are provided for gate control. The "gate" is the electrode between "drain", i.e. the second and the third load terminals 310, 315, 320, and "source", i.e. the first load terminals 300, 305, and serves for controlling the switching behavior of the half bridge 205. It enables the activation and deactivation of the semiconductor package 212, 215, 220 in the half bridge 205. In the present case, six parallel-connected power semiconductors 335, 340, 345, 350, 355, 360 are arranged between the load terminals 300- 320, which power semiconductors can be controlled via the signal pins 325, 330.FIG. 4 shows the electronic power module 202 according to FIG. 2 in plan view. The power module 202 comprises a heat sink 400 on which the six semiconductor packages 212, 215, 220 or the three half bridges 205 consisting of in each case two semiconductor packages 215, 220 connected in series are arranged. One semiconductor package 212, 215, 220 each is assigned as a discrete individual package to a switching position of the power module 202. The power module 202 can alternatively also be arranged on the heat sink 400 in common with twelve semiconductor packages 212, 215, 220 or six half bridges 205, wherein in each case two semiconductor packages 212, 215, 220 are assigned as discrete individual packages to a switching position of the power module 202.The semiconductor packages 212, 215, 220 are formed identically independently of their number, for which reason only one exemplary semiconductor package 212 is shown and described below in FIGS. 5 ff. The other semiconductor packages 212, 215, 220 are formed analogously thereto.FIG. 5 shows the semiconductor package 212 in the manufactured state as a separately manageable unit. The load connections 300- 320 mentioned are illustrated here, and, in addition to the signal pins 325, 330 already mentioned, two further signal pins 500, 505 for gate control, which will be discussed in more detail further below.The semiconductor package 212 is encapsulated by means of injection molding, wherein an insulation material 510 forms, so to speak, a housing of the semiconductor package 212 in order to protect the parts described below, where required, from interaction with one another and from external influences, in particular dirt and moisture. FIG. 5 shows that a cutout 515 in the form of a bead is formed in the insulation material 510 spatially between a respective first load terminal 300, 305 and a third load terminal 315, 320 of the same longer side of the semiconductor package 212 which is T-shaped in cross section and rectangular in plan view, in order to realize a required air and creepage distance. As a result, the spacing of the load terminals 300, 305, 315, 320 of the same side can be made smaller, as a result of which the semiconductor package 212 can be made more compact. In this sense, one of the third load terminals 315 is assigned to one of the longer sides of the semiconductor package 212 together with one of the first load terminals 300, wherein the respective other third load terminal 320 is assigned to the opposite side of the semiconductor package 212 together with the respective other first load terminals 305. The second load terminal 310 is associated with that shorter side of the semiconductor package 212 which is situated further away from the third load terminals 315, 320 in order to realize a current symmetry within the semiconductor package 212. The two third load terminals 315, 320 have the same potential as the second load terminal 310.The load terminals 300- 320 each have a surface that lies in a plane with a surface of the insulation material 510, thereby forming the planar top side of the semiconductor package 212 illustrated in FIG. 5. The semiconductor packages 212, 215, 220 of a half bridge 205 are connected to one another and to a busbar arrangement-not shown here-and externally via the load connections 300- 320.Referring to FIGS. 6 and 7, the semiconductor package 212 includes a ceramic substrate 600 that is substantially rectangular in plan view and, as can be seen better in FIG. 8, has a ceramic layer 800 between a lower copper layer 805 and an upper copper layer 810. Furthermore, the semiconductor package 212 comprises a control terminal 605, which is electrically connected to signal pins 325, 330 for controlling the semiconductor package 212, signal pins 500, 505 for signal-transmitting connection to a temperature sensor-not shown here-and to the power semiconductors 335- 360 via connecting elements 610 designed as bonding wires.A first load terminal 300, 305 and a third load terminal 315, 320 are each assigned to one of the longer sides of the ceramic substrate 600. The second load terminal 310 is associated with one of the shorter sides of the ceramic substrate 600. As shown in FIG. 7, a plurality of first sinter layers 700 are applied to the upper copper layer 810 of the ceramic substrate 600 in order to directly electrically connect the upper copper layer 810 of the ceramic substrate 600 to the second load terminal 310, the third load terminals 315, 320 and the control terminal 605 and the power semiconductors 335- 360 respectively. The load connections 300- 320 can be stamped out of a sheet metal as stamped grids and can be formed into the desired shape by forming.In the present case, the power semiconductors 335, 340, 345 of the triple row arranged to the left of the control terminal 605 are to be understood as first power semiconductors which are assigned to the left first load terminal 300. The power semiconductors 350, 355, 360 of the triple series arranged to the right of the control terminal 605 are to be understood as second power semiconductors which are assigned to the right first load terminal 305. Consequently, the semiconductor package 212 comprises three first power semiconductors 335, 340, 345 and a number of second power semiconductors 350, 355, 360 identical thereto. The three first power semiconductors 335, 340, 345 are arranged in series and spaced apart from one another, wherein the three second power semiconductors 350, 355, 360 are arranged in series and at identical spaced apart from one another and parallel to the first power semiconductors. Thus, the power semiconductors 335-360 are arranged in a 2x3 arrangement on the ceramic substrate 600. The power semiconductors 335- 360 are identical in design and have the same size and area. The proposed configuration of the semiconductor package 212 enables current symmetry to be realized, such that all power semiconductors 335- 360 are energized substantially uniformly, as a result of which the power of the semiconductor package 212 is in turn optimized.Each first load terminal 300, 305 comprises a respective lead frame 615, 620, which is configured as a connecting arm in order to electrically connect the respective first load terminal 300, 305 at least indirectly to the upper copper layer 810. According to FIG. 9, which exemplarily shows the layer structure between the leadframe 615 of the first load terminal 300 and one of the associated first power semiconductors 335, starting from the upper copper layer 810 of the ceramic substrate 600, i.e. from bottom to top, a first sinter layer 700, thereon the first power semiconductor 335, thereon a second sinter layer 900, thereon a bond buffer layer 905 formed as a copper layer, thereon a solder layer 910, and thereon the leadframe 615 are arranged. The leadframe 615 is therefore soldered onto the first power semiconductor 335. The connection between the leadframes 615, 620 and the further power semiconductors 340- 360 is designed analogously thereto.The configuration of the leadframes 615, 620 will be described below with reference to FIGS. 7 and 10. Accordingly, the leadframe 615 of the left first load terminal 300 comprises two cross connectors 705, 710 for connecting the left first load terminal 300 to the three first power semiconductors 335, 340, 345 to the left of the control terminal 605. The leadframe 620 of the right first load terminal 305 likewise has two cross connectors 705, 710 in mirror-inverted fashion with respect to the leadframe 615 of the left first load terminal 300 in order to connect the right first load terminal 305 to the three second power semiconductors 350, 355, 360 on the right of the control terminal 605.Each cross connector 705, 710 has three arm segments 715, 720, 725, which come to bear in sections against an associated solder layer 910, shown in FIG. 9, of the respective power semiconductor 335- 360. The solder layers 910 are formed here in parallel as strips. The solder layers 910 are adapted to the configuration of the arm segments 715, 720, 725. The solder layers 910 can be formed segment by segment, i.e. with interruptions. In order to achieve or improve the desired current symmetry, according to FIG. 7, using the example of the power semiconductor row arranged to the left of the control terminal 605, two arm segments 715, 720 of the first cross connector 705 extend to the first (335) of the three first power semiconductors and a further arm segment 725 extend to the second (340) of the three first power semiconductors, wherein two arm segments 715, 720 of the second cross connector 710 extend to the third (345) of the three first power semiconductors and a further arm segment 725 also extend to the second (340) of the three first power semiconductors. The same area of the left-hand first load terminal 300 is thus applied to each first power semiconductor 335, 340, 345, and the power semiconductors 335, 340, 345 can be uniformly energized.FIG. 10 also illustrates in this context the configuration of the respective arm segment 715, 720, 725, here using the example of the second cross connector 710 of the leadframe 615 of the left first load terminal 300. Specifically, each arm segment 715, 720, 725 is divided into a plurality of sections, namely into two contact sections 1000, 1005 for contacting the leadframe 615 with the solder layer 910, and a connecting section 1010 which connects the two contact sections 1000, 1005 to one another in one piece and is not in contact with the solder layer 910 and is designed as a bridge. The contact area between the leadframe 615 and the first power semiconductors 335, 340, 345 is thus kept as low as possible, which reduces the loading of the first power semiconductors 335, 340, 345.In order to avoid unnecessary repetitions, it is expressly pointed out that the first load terminal 305 arranged to the right of the control terminal 605, with the leadframe 620 formed thereon and the transverse connectors 705, 710 and arm segments 715, 720, 725 comprised thereby, is formed substantially mirror-reversed with respect to the previously described left first load terminal 300. What has been said with respect to the left first load terminal 300 is therefore analogously applicable to the right first load terminal 310.It can be seen from FIG. 8 that the control connection 605 is of multilayer construction. The control terminal 605 is to be understood as a gate runner or signal substrate which forwards signals which are conducted via the signal pins 325, 330 into the semiconductor package 212 via the connecting elements 610 to the power semiconductors 335- 360. The control terminal 605 comprises a ceramic layer 815 arranged between a further lower copper layer 820 and a further upper copper layer 825. The lower copper layer 820 is electrically connected to the upper copper layer 810 of the ceramic substrate 600 via a first sinter layer 700. Said connecting elements 610 are directly electrically connected to the upper copper layer 825 of the control terminal 605, wherein each two connecting elements 610 contact one of the power semiconductors 335- 360.The upper copper layer 825 of the control terminal 605 is configured in a segmented manner according to FIG. 7. In other words, the upper copper layer 825 of the control terminal 605 is comprised of multiple segments. The configuration of the segments depends on the requirements for the control connection 605. As already indicated, the control terminal 605 is furthermore electrically connected to two further signal pins 500, 505, which are electrically connected to a temperature sensor arranged on the upper copper layer 810 of the ceramic substrate 600 via connecting elements, which are not shown here and which can be designed as bonding wires analogously to the other connecting elements 610. The temperature sensor is likewise not shown here. In this regard, FIG. 7 shows a further first sinter layer 700 in the upper right corner of the ceramic substrate 600 in the region of the second load terminal 310, on which the temperature sensor can be arranged. The connecting elements 610 for connecting the control connection 605 to this first sinter layer 700 are indicated in FIG. 12.FIG. 11 shows an alternative embodiment of the semiconductor package according to FIGS. 5 to 10 described above, wherein only the differences in this respect are discussed below. As can be seen in FIG. 11, the temperature sensor, and correspondingly the associated control pins 500, 505, the connecting elements and the additional first sinter layer 700 can be dispensed with if the temperature of the semiconductor package 212 is determined or detected using other means. This can simplify the structure of the semiconductor package 212.FIG. 12 shows a further possible embodiment of the semiconductor package according to FIGS. 5 to 10 described above, wherein only the differences in this respect are discussed below. In the present case, the semiconductor package 212 has only four power semiconductors 335, 345, of which two are assigned to the one first load terminal 300 and the respective other two first load terminals 350, 360 are assigned to the respective other first load terminal 305. Depending on the requirement of the semiconductor package 212, individual power semiconductors can therefore be dispensed with according to FIG. 12. For reasons of current symmetry, the number of first power semiconductors is always to be chosen to be identical to the number of second power semiconductors. The semiconductor package 212 can be adapted to the present requirements with simple means. In this example, one, here the middle, first or second power semiconductor 340, 355 is dispensed with in each case. This also simplifies the configuration of the leadframes 615, 620. Likewise, the number of first and second power semiconductors may also be increased equally, such that, for example, eight, ten or more power semiconductors are arranged on the upper copper layer 810 of the ceramic substrate 600 and connected to the control terminal 605.Reference numerals denote reference numerals100 Electrical drive axle 105 Motor vehicle 110 Internal combustion engine 115 Transmission 120 Drive wheel 125 Electrical machine 130 Power converter 135 Energy store 200 Motor controller 202 Power module 205 Half bridge 210 Control device 212 Semiconductor package 215 Upper semiconductor package 220 Lower semiconductor package 225 Intermediate circuit capacitor 230 Center tap 300 First load terminal 305 First load terminal 310 Second load terminal 315 Third load terminal 320 Third load terminal 325 Signal pin for gate control 330 Signal pin for gate control 335 First power semiconductor 340 First power semiconductor 345 First power semiconductor 350 Second power semiconductor 355 Second power semiconductor 360 Second power semiconductor 400 Heat sink 500 Signal pin for temperature sensor 505 Signal pin for temperature sensor 510 Insulation material 515 Cutout 600 Ceramic substrate 605 Control terminal 610 Connecting element 615 Leadframe 620 Leadframe 700 First sinter layer 705 First Cross connector 710 Second cross connector 715 First arm segment 720 Second arm segment 725 Third arm segment 800 Ceramic layer of ceramic substrate 805 Lower copper layer of ceramic substrate 810 Upper copper layer of ceramic substrate 815 Ceramic layer of control terminal 820 Lower copper layer of control terminal 825 Upper copper layer of control terminal 900 Second sinter layer 905 Bond buffer layer 910 Solder layer 1000 First abutting portion of arm segment 1005 Second abutting portion of arm segment 1010 Connecting portion of arm segmentReferences included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedDE 10 2009 044 659 A1

[0002]

Claims

Semiconductor package (212, 215, 220) for an electronic power module (202), comprising a ceramic substrate (600) having a ceramic layer (800) between a lower copper layer (805) and an upper copper layer (810), two first load terminals (300, 305) each having a leadframe (615, 620), wherein one of the first load terminals (300) is assigned to at least one first power semiconductor (335) and the other first load terminal (305) is assigned to at least one second power semiconductor (350), and wherein the respective power semiconductor (335, 350) is arranged between the upper copper layer (810) of the ceramic substrate (600) and the leadframe (615, 620) of the associated first load terminal (300, 305) and is electrically connected thereto, a second load terminal (310) electrically connected to the upper copper layer (810), a control terminal (605) connected to signal pins (325, 330) for controlling the semiconductor package ( 212, 215, 220) and also electrically connected to the power semiconductors ( 335, 350) via connecting elements ( 610).The semiconductor package (212, 215, 220) according to claim 1, wherein the ceramic substrate (600) is substantially rectangular, and wherein a first load terminal (300, 305) is respectively assigned to one of the longer sides and the second load terminal (310) is respectively assigned to one of the shorter sides of the ceramic substrate (600).Semiconductor package (212, 215, 220) according to Claim 1 or Claim 2, wherein first sinter layers (700) are applied to the upper copper layer (810) of the ceramic substrate (600) in order to at least electrically connect the upper copper layer (810) in each case to the second load terminal (310), to the control terminal (605) and to the power semiconductors (335, 350).Semiconductor package (212, 215, 220) according to one of the preceding claims, wherein a second sinter layer (900), a bond buffer layer (905) and a solder layer (910) are arranged between the respective leadframe (615, 620) and the associated power semiconductor (335, 350) starting from the respective power semiconductor (335, 350).Semiconductor package (212, 215, 220) according to one of the preceding claims, wherein the control terminal (605) is electrically connected to further signal pins (500, 505) which are electrically connected via connecting elements to a temperature sensor arranged on the upper copper layer (810).Semiconductor package (212, 215, 220) according to one of the preceding claims, comprising two or more first power semiconductors (335, 340, 345) and a number of second power semiconductors (350, 355, 360) identical thereto.The semiconductor package (212, 215, 220) according to one of the preceding claims, wherein the at least two first power semiconductors (335, 340, 345) are arranged in series and at a distance from one another, and wherein the at least two second power semiconductors (350, 355, 360) are arranged in series and at identical distances from one another and parallel to the first power semiconductors (335, 340, 345).The semiconductor package (212, 215, 220) according to claim 6 or claim 7, wherein the respective lead frame (615, 620) comprises at least one cross connector (705) connecting the first load terminal (300, 305) to respectively two first or two second power semiconductors (335, 340, 345, 350, 355, 360).The semiconductor package (212, 215, 220) of claim 8 in combination with claim 4, wherein the respective cross connector (705) comprises one or more arm segments (715) that abut the solder layer (900) at least in portions.The semiconductor package (212, 215, 220) according to any one of the preceding claims, further comprising two third load terminals (315, 320) having the same potential as the second load terminal (310) and each electrically connected to the upper copper layer (810) of the ceramic substrate (600).Semiconductor package (212, 215, 220) according to Claim 10 in combination with Claim 2, wherein a respective third load terminal (315, 320) is assigned in each case to one of the longer sides of the ceramic substrate (600).The semiconductor package (212, 215, 220) of any preceding claim, wherein the semiconductor package (212, 215, 220) is encapsulated by injection molding.The semiconductor package (212, 215, 220) of claim 12 in combination with claim 11, wherein at least one recess (515) is formed spatially between the first and third load terminals (300, 305, 315, 320) of the same side of the semiconductor package (212, 215, 220) in the insulation material (510).Electronic power module (202) for a motor controller (200), comprising a cooling body (400) on which a plurality of semiconductor packages (212, 215, 220) according to one of the preceding claims are arranged.Electronic power module (202) according to Claim 14, wherein six semiconductor packages (212, 215, 220) are arranged on the heat sink (400), wherein in each case two semiconductor packages (212, 215, 220) are combined to form a half bridge (205) and are each connected in series one behind the other.Electronic power module (202) according to Claim 14, wherein twelve semiconductor packages (212, 215, 220) are arranged on the heat sink (400), wherein in each case four semiconductor packages (212, 215, 220) are combined to form a half bridge (205).An electric drive axle (100) comprising an electric machine (125) and an electronic power module (202) according to any of claims 14 16.Motor vehicle (105) comprising an electric drive axle (100) according to Claim 17.

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