Semiconductor component and use of a semiconductor component

Abstract

The invention relates to a semiconductor component, in particular a transistor, comprising a source contact layer (16) and a substrate and / or drain layer (12, 13, 14), wherein the semiconductor component has a plurality of cells comprising one or more active cells and one or more control cells (300), wherein the source contact layer (16) and the substrate and / or drain layer are assigned to each of the cells, wherein the semiconductor element has, for each of the cells, at least one source layer (9) doped in a first type and at least one channel layer (8), wherein the semiconductor element has, for each of the cells, a gate electrode (4) which is insulated from the source layer (9) and the channel layer (8), wherein the semiconductor element has, for the one or each of the plurality of active cells, an insulation layer (15) by means of which the gate electrode (304) is insulated from the source contact layer (16),wherein the semiconductor element for the one or each of the plurality of control cells (300) each has a first electrically conductive connection, in particular with a first ohmic resistor (319), by means of which the gate electrode (304) is electrically conductively connected at least in sections to the source contact layer (16).

Description

The present invention relates to a semiconductor component, in particular a transistor, e.g. a so-called trench MOSFET, and to a use of such a semiconductor component.BACKGROUND OF THE INVENTIONSemiconductor components such as field effect transistors (FETs), in particular so-called MOSFETs or MISFETs, are used in various fields. A variant of this is trench MOSFETs or T-MOSFETs, in which a channel is formed vertically. In this case, for example, an n-doped source layer and a channel layer lying between the latter and one of the n-doped drift layer are broken through by trenches ("trenches"); gate electrodes are then arranged in such trenches.Disclosure of the InventionAccording to the invention, a semiconductor component and a use for a semiconductor component having the features of the independent patent claims are proposed. Advantageous embodiments are the subject matter of the dependent claims and of the following description.The invention is concerned with semiconductor devices and their use. Suitable semiconductor components are, in particular, transistors, preferably field-effect transistors, and specifically in particular with trenches. In this case, it can be, for example, T-MOSFETs or T-MISFETs. In the case of semiconductor materials, different types of doping are used, namely n-doping and p-doping, wherein different components can be doped differently. Semiconductor components with a specific type of doping are to be described below for the sake of better intelligibility, the n-doping is to be a first type of doping, the p-doping is to be a second type of doping. However, it is to be understood that n- and p-doping can also be interchanged, i.e. the n-doping could be the second type of doping and the p-doping could be the first type of doping. Although the invention is described predominantly with reference to a field effect transistor, it is also applicable to other transistors, e.g. IGBTs.Semiconductor components such as MISFETs or other transistors are semiconductor-based switches which are used in power electronics as power switches in a multiplicity of applications, for example in converters. A typical circuit topology used there is a half bridge in which MISFETs are used as high-side switches and low-side switches.It has now been found, as will be explained in more detail later with reference to the figures, that during operation in certain situations, in particular in so-called reverse recovery, voltage peaks can occur which are undesirable and up to now cannot be bypassed in a simple and robust manner.Against this background, a semiconductor component, in particular a transistor or field effect transistor, is proposed, which comprises a plurality of cells, one or more active cells and one or more control cells. In this case, the semiconductor component has a source contact layer and a substrate and / or drain layer. The substrate and / or drain layer comprises in particular a substrate layer, optionally a buffer layer, and an n-doped drift layer. In addition, the semiconductor component can have a drain contact layer which adjoins the substrate and / or drain layer. The source contact layer serves as source terminal, the drain contact layer as drain terminal. The source contact layer and the substrate and / or drain layer, and optionally the drain contact layer, are assigned to all cells, i.e. all cells are formed on or with these layers.The semiconductor element also has at least one n-doped source layer and at least one channel layer for each of the cells. The channel layer, or even only one channel region, is generally p-doped. Furthermore, the semiconductor element has a gate electrode for each of the cells, which is insulated from the source layer and the channel layer.Furthermore, the semiconductor element for the one or each of the plurality of active cells in each case has an insulation layer, by means of which the gate electrode is insulated from the source contact layer. For the one or each of the plurality of control cells, the semiconductor element has in each case a first electrically conductive connection, in particular having a first ohmic resistor, by means of which the gate electrode is electrically conductively connected at least in sections to the source contact layer.The gate or the gate electrode material of a control cell is in particular not electrically connected to the gate or gate electrode material of an active cell. Rather, the gate of the control cell is connected to the source contact layer via the first electrically conductive connection or the first ohmic resistorIn the forward state, with VGS>Vth, the gate of the control cell remains referenced to source potential. As a result, given a corresponding selection of the doping concentration of the channel layer of the control cell, a bypass for electrons can form on the trench-side surface of the channel layer, which reduces the storage charge (initial condition for reverse recovery, RR). During RR, when the component acts as a freewheeling diode, as a result of the Miller capacitance formed from trench, insulation layer, gate electrode and drift region, an impression of current into the gate of the control cell and thus a dynamic opening of the channel forming on the trench-side surface of the channel layer occurs as the VDS increases, since the current generates a voltage increase at the first ohmic resistance. This leads to a reduction of the maximum drain voltage VDSm for the entire component compared to the case without control cells. This effect is not directly dependent on the drive voltage VGSol,h, because the gate of the control cell is not connected to the latter. Consequently, the effect is still present even if the gate drive fails in the event of a fault.In one embodiment, the semiconductor component has a second electrically conductive connection, in particular with a second ohmic resistor, for the one or at least one of the plurality of control cells, by means of which connection the source layer is electrically conductively connected at least in sections to the source contact layer. In this case, the semiconductor component for the one or at least one of the plurality of control cells can have an insulation layer, by means of which the source layer is insulated from the source contact layer. Thus, an electrical conductivity is only given via the second electrically conductive connection or the second ohmic resistor. In one embodiment, on the other hand, for the one or at least one of the plurality of control cells, the source layer is in contact at least in sections directly with the source contact layer.If a current begins to flow in the RR via the source layer and the second electrically conductive connection or the second ohmic resistor, a voltage drop is produced essentially at the second ohmic resistor, which voltage drop counteracts the dynamic current increase in the sense of a negative feedback. This dynamically limits the stream if this is desired for the application. The other behavior with regard to the reduction of VDSm changes at best to the effect that the reduction is less pronounced depending on the magnitude of the second ohmic resistor.In one embodiment, the semiconductor component for the one or the at least one of the plurality of control cells has a connection region which is conductively connected to the source layer and to which an external second ohmic resistor can be connected, by means of which connection region the source layer can be electrically conductively connected to the source contact layer. In a further embodiment, the semiconductor component for the one or the at least one of the plurality of control cells has a connection region which is conductively connected to the gate electrode and to which a first external ohmic resistor can be connected, by means of which connection region the gate electrode can be electrically conductively connected to the source contact layer. In this way, the first and / or second ohmic resistance can be adjusted as required by an external ohmic resistance in order to influence the behavior of the semiconductor component or field effect transistor.In one embodiment, the semiconductor component has an insulation layer for the one or at least one of the plurality of control cells, by means of which insulation layer the source layer is insulated from the source contact layer, wherein the semiconductor element has a second ohmic resistor for the one or the at least one of the plurality of control cells, by means of which insulation layer the source layer is electrically conductively connected to the source contact layer. In one embodiment, for the one or each of the plurality of active cells, the source layer is in contact at least in sections directly with the source contact layer. In an embodiment, the semiconductor device has a different threshold voltage for the one or each of the plurality of active cells than for the one or more control cells.A preferred use of one or more such semiconductor components or field effect transistors is in a half bridge, in particular for driving an electrical load. Such a field effect transistor may be used alone or together with others thereof, for example, as a power switch. Preferred fields of application are, for example, in an electric drive train of a vehicle, in this case, for example, in a current transformer (DC / DC converter, inverter), in charging devices for electrically operated vehicles or else in solar inverters.Further advantages and embodiments of the invention will become apparent from the description and the accompanying drawing.The invention is schematically illustrated in the drawing on the basis of exemplary embodiments and is described below with reference to the drawing.Brief Description of the DrawingsFIGS. 1 a, 1 b, 1 cschematically illustrate a use of a semiconductor device for explaining the invention. FIG. 2a schematically shows an active cell of a semiconductor device for explaining the invention. FIG. 2 bshows a diagram for explaining the active cell according to FIG. 2 a. FIGS. 3 to 6 each schematically show a control cell of a semiconductor component in various embodiments. FIGS. 7 and 8 schematically show a semiconductor component in an embodiment in a plan view.Embodiment(s) of the InventionIn FIG. 1 a, a use of a semiconductor component is schematically shown for explaining the invention. So-called "So-called Chemical Technology". MISFETs (Metal-Insulator-Semiconductor Field Effect Transistors) are semiconductor-based switches which are used in power electronics as power switches in a multiplicity of applications, for example in converters. A typical circuit topology used there is the half bridge 100 shown in FIG. 1 a, in which MISFETs are used as high-side switch, HSS, 102 and low-side switch, LSS, 104.Reference numeral 106 shows a so-called intermediate circuit voltage, VZK, which can be between several hundred volts up to kilovolts, reference numeral 126 denotes the voltage drop across a parasitic leakage inductance L. A typical operating case for power electronic switches is the alternating switching on and off of the HSS and the LSS. For this purpose, for switching on in the forward direction, the voltage between gate terminal G and source terminal S of the respective switch is brought by the voltage source VGSoh, 108 and VGSol, 110 to a positive voltage (e.g. 15 V) which is above the threshold voltage Vth (e.g. 3 V) which is decisive for switching on.In contrast, in order to switch off the respective switch in the forward direction, the voltage between gate terminal G and source terminal S of the respective switch is brought by the voltage source VGSoh, VGSolto a voltage VGSwhich is below the threshold voltage Vthwhich is decisive for the switching-on. The voltage value selected here is usually between -5 V and 0 V; negative values are usually selected in order to avoid uncontrolled switching on (also parasitic re-switching, or parasitic turn on (PTO)) of the actually switched-off switch as a result of fast switching edges of the voltage VDSh, 112 and VDSI, 114 between drain D and source S of the HSS or LSS.The forward direction is when VDSh and VDSI are positive, respectively. In order to avoid a so-called phase short circuit, the phases in which VGSohor VGSolare above the threshold voltage do not overlap. The gate resistors Rgh, 116 and Rgl, 118 serve to adjust the switching speed. In each MISFET, a so-called body diode is connected in parallel with the channel whose conductivity can be controlled by the VGS in such a way that a high current flow from source S to drain D is possible both dynamically and in the static case even in the case of VGS<<Vth. In contrast, a high static current flow from drain D to source S is not possible for VGS<<Vth via this body diode, but in the dynamic case, for example after polarity reversal from VDS<0V to VDS>0V, as a result of the storage charge of the body diode built up with VDS<0V in the time interval.A time interval relevant within the scope of the present invention is that in which the so-called reverse recovery (RR) takes place. If the RR of the HSS is considered as representative of this, there is the RR of the LSS with a corresponding selection of the control. In this case, let VGSoH<<Vth and Rgh=0Ω and the drive VGSolbe very steep-slope, so that the HSS, 102, according to FIG. 1 b, is represented as a diode in a very simplified replacement image. Furthermore, let Rgl=0Ω and the drive VGSolbe very steep-slope, so that the LSS, 104, very simply, can be represented as a switch, as likewise shown in FIG. 1 b.In Figure 1c, current i and 122, respectively, and voltage VDSh and 112, respectively, are shown on axis 150 versus time on axis 152. For t<-trr, shown in FIG. 1c in the diagram at 130, a load current lo, 120 flows through the diode representing the HSS; its voltage drop VDSh is to be ignored in terms of absolute value in the range of a few volts and compared with VZK, 106. At time t=-trr, the switch representing the LSS is closed and the RR of the HSS is initiated. The drain current at the HSS drops, as shown in FIG. 1 c, in terms of absolute value with the commutation slope of approximately IdiD / dtl=VK / L (in this case, as can be seen in FIG. 1 a, iD, 124, the drain current for which iD=-i applies) This changes its sign at t=0 and only after part of the storage charge has dissipated, so that the pn junction is "cleared" by the charge carrier plasma, does the diode clearly take up voltage VDSh.The drain current iD of the HSS increases in absolute value from t=0 all the time until the maximum current in the reverse current peak IRRM is reached at the time tRRM, 132. At tRRM, VDSh=VK and therefore the current amount no longer increases due to VL=L*di / dt=0 (VL is denoted 126 in FIG. 1 a). Between tRRMand tB, 134, where iDhas its second zero crossing, iDincreases in magnitude, which, as a result of the leakage inductance L with VL=L*di / dt, leads to an increase in VDShover VZKuntil finally the maximum VDSh=VDSm(VDSmis denoted by 136) is reached. If one switches fast, the commutation steepness is thus high, then as a rule VDSm>>VZK is due to the properties of the body diode.This overvoltage peak VDSm 136 is undesirable because the MISFET must have a correspondingly high blocking capability, which results in the resistor Ron (on-resistance) being at the expense of the switched-on forward operation and thus increases losses. Furthermore, the fast switching edges lead to increased high-frequency interference emission, which leads to damage to EMC limit values in the VHF range.In the real application, there are now several effects which influence this basic sequence. A very decisive effect is that in the drive circuit Rgh and Rgl different from 0Ω, and in the component there is a capacitance CGS between gate and source and the so-called Miller capacitance between drain and gate. At fast dHSS / dt, a current is injected into its gate via the Miller capacitance of the HSS, which leads to an increase in the VGSh as a result of the Rgh that is not different from zero. If this VGSh>Vth, the HSS is dynamically controlled in an uncontrolled manner (PTO=parasitic turn on). This is attempted to be avoided in the application because excessively high phase cross currents (up to the repetitive short circuit) are temporarily feared. Therefore, the switching speed is reduced by increasing the Rgh, Rgl, and the minimum VGSol, VGSoh is set to negative values; there are also topologies that activate different Rgl=Rgh for switching on and off, respectively. All this means an additional circuit complexity in the control, and generally an increase in the switching losses and a reduction in the efficiency.The PTO can be deliberately used to reduce VDSm and reduce the overall switching losses. However, the secure design is not simple. Furthermore, in the event of a fault in which the gate drive would be lost in the case of HSS or LSS, very high VDSm would be reached or the component would be driven into the avalanche breakdown.It is therefore desirable to provide a semiconductor component-explained below using the example of a structure of an SiC power MISFET-which reduces the voltage peak VDSm in reverse recovery and, in particular with regard to this effect, is not directly dependent on the selection of the parameters of the drive circuit (VGSoh,l, Rgh,l) on the one hand and is robust with respect to the fault case that the gate drive breaks off in the case of the HSS or LSS on the other hand.FIG. 2 aschematically illustrates an active cell 200 of a semiconductor device for explaining the invention. This will be explained below in particular with reference to a MISFET.An MISFET generally comprises an active region in which a plurality of identical cells are connected in parallel, an edge termination for receiving the blocking voltage at the edge of the active region and connections for drain D, source S and gate G together with corresponding electrical leads. The active region forms, in the narrower sense, the actual circuit breaker.An example of an active cell of a corresponding MISFET (Metal Insulator Semiconductor Field Effect Transistor) based on semiconductors (in particular on SiC) is illustrated in cross section in FIG. 2 a.For example, the active cell 200 shown has a stripe design and extends into the image plane. Here, a vertical direction is the z direction. This is a trench cell, but cells with a planar gate are also customary; instead of SiO2as gate oxide, other dielectrics, for example with increased rel, are also customary. Dielectric constant (high-k dielectrics, such as Al2O3, HfO2, TiO2) are possible, and, furthermore, instead of a strip-shaped one, a cell design can also be selected in which each cell is arranged island-shaped next to the adjacent cells. Furthermore, both geometric and dopant variations of the cell design are possible, together with additional shielding structures for the trench by p-doped regions arranged, for example, below the trench bottom and electrically connected to source potential.On a highly n+-doped substrate 12, e.g. made of SiC, there is a highly n+-doped buffer layer 13 and above this a weakly n-doped drift layer 14, which is optionally slightly higher n-doped in its upper part 11 in order to achieve a low specific on-resistance RonA in the case of forward conduction (in this case 11 it is then also a so-called spread layer). In general, a substrate and / or drain layer can also be referred to here.Above the region or the spread layer 11 there is a moderately p-doped channel layer 8 (also referred to as body region or channel region) and a highly p+ -doped shielding region 10 (pPlus region) extending as far as the top side. In this case, the highly p+-doped shielding region 10 reaches deeper into the drift layer 14 (optionally with 11) than the p-doped channel layer 8 and the gate trench 5 (also referred to as trench). Above the channel layer 8 a flat, very highly n+ doped source layer 9 is provided. Whereas the regions or layers 13, 14 are usually produced by epitaxy, the doping for the layer 11 and the regions or layers 8, 9, 10 are usually produced by ion implantation into an epitaxial layer.From the top side, a gate trench 5 (trench) is introduced into the semiconductor per cell, the end of which trench extends into the drift layer 14 or, if present, spread layer 11. The trench wall of the gate trench 5 is in contact with the source layer 9 and the channel layer 8, and a thin layer of generally silicon dioxide 6 (so-called gate oxide) is provided on the inside of the gate trench 5, which thin layer can optionally be made thicker at the bottom of the trench for better robustness or, in the case of high VDSs of high field strengths present there, referred to here as silicon dioxide 7. The gate trench lined with oxide is filled with highly doped, well-conductive, generally doped polysilicon, the so-called gate electrode 4 (also called gate poly). The gate electrode 4 is electrically insulated from the source contact layer 16 (so-called source metal) by an intermediate oxide 15.The regions or layers 9 and 10 form, on the upper side with the source contact layer 16, an ohmic contact 2 which constitutes the source contact. A drain contact layer 3 (e.g. a plurality of metal layers) applied to the rear side of the wafer forms the ohmic drain contact, optionally together with the substrate layer 12. The gate electrode 4 is likewise connected to a metal (so-called gate pad), which is not visible in the two-dimensional illustration. The gate pad may be connected to an external circuit as a gate terminal G, the drain metal as a drain terminal D, and the source metal as a source terminal S.It should be mentioned here that the gate is arranged here between two shielding regions 10, as a result of which the layers 8, 9 are also divided by the gate.For the description of the operation of the active cell, it shall be assumed that the source potential is the reference potential. In the reverse case, VGS<Vth and VDS>0V, wherein VDS can be several hundred volts up to kilovolt. Starting from the p-doped regions or layers 8, 10, a space charge zone propagates with increasing VDSinto the drift layer 14 and, if present, the spread layer 11. The drain current iDremain very low at the reverse current level until avalanche multiplication begins at very high VDSas a result of the high field strengths, iDincreases sharply and avalanche breakdown of the component ultimately occurs. This determines the upper limit of the blocking capability of the component. For this operating case, the aim of a design is a breakdown voltage which is as high as possible, which can be achieved, inter alia, by low doping of the layers 14, 11.In the forward case, VGS>Vth and VDS>0V. As a result of the gate-source voltage, a conductive channel is generated in the body region or the channel layer 8 at the boundary to the gate oxide 6 by influence and a high current iD flows even at low VDSof a few volts. For this operating case, the aim of a design is as low a specific on-resistance RonA as possible, which can be achieved, inter alia, by a not very low doping of the layers 14, 11. However, this results in a conflict of goals with the high breakdown voltage.Furthermore, by a corresponding selection of the doping concentration of the channel layer 8, the threshold voltage Vth is set such that it is not too high for a low on-resistance, but on the other hand not too low in order not to obtain a high leakage current at Vgs in the order of 0V. Higher dopings of the channel layer 8 lead here to a higher Vth.If only VDSis increased further and further, the channel finally limits the drain current iD; this limitation can be influenced within certain limits by the distance of the shielding regions 10 from the gate trench 5 and the depth thereof, as well as depth and doping concentration of the spread layer 11, because the penetration of electric fields on the body region or the channel layer 8 can thereby be influenced. The high drain current at high VDS results in a very high power loss density in the cell and can lead to its thermal destruction. This operating state is actually a fault case, the so-called short-circuit case in the external circuit of the component.If VDS<0V, the reverse operation is present in which the body diode conducts. Here, body region 8 and shielding region 10 inject holes into drift layer 14, and spread layer 11 which may be present, flow in the direction of the drain, and buffer layer 13 injects electrons which travel in the direction of the source. As a result, the current flow iD<0A und a storage charge builds up essentially in the drift layer 14 and the spread layer 11 that may be present. If VGS<<Vth (e.g. VGS<<0V), no appreciable channel exists and the electrons flow away to the source metal 16 via the layers or regions 8, 9 or 10. If VGS is selected to be increasingly higher, then a channel is increasingly introduced at the trench-like surface of the channel layer 8, through which channel electrons can increasingly flow off via the source layer 9 to the source metal 16; this channel therefore forms a bypass for electrons to the layers or regions 8, 9, 10.As a result, on the one hand, the leakage voltage VF of the diode is reduced at a given iD and, on the other hand, the storage charge is loweredThis is schematically shown in FIG. 2 b. In the diagram shown, the hole density p is plotted along the line S from FIG. 2 ain the z direction (from the shielding region 10 via the drift layer 14 and the buffer layer 13; the layer 11 is absent here for the sake of simplicity), specifically with line 210 for no channel and with line 212 for with channel.For the reverse recovery, RR, described above, this is the initial condition, which can therefore be influenced with the selection of VGS. During RR, the storage charge is extracted, wherein, for SiC, for example, due to the significantly greater mobility of the electrons with respect to the holes, the extraction mainly takes place from the boundary of the p-doped regions or layers 8, 10 into the drift region. In this case, as described above, PTO can occur, in which case the channel is temporarily opened as a bypass for electrons. This may somewhat reduce the voltage peak VDSm incurred during the RR.FIGS. 3 to 6 each schematically show a control cell of a semiconductor component in one embodiment. One or more such control cells, also different therefrom, can be combined with one or, preferably, a plurality of active cells, as shown, for example, in FIG. 2 a.The number of active cells on which a control cell comes is freely selectable; the more control cells are selected per number of active cells, the greater its influence on the component properties. It is possible here for the control cells to be arranged in each case regularly between the active cells or else irregularly, for example as a single block which comprises all control cells, or else a plurality of blocks which in each case comprise different numbers of control cells.A transistor formed in this way can then be used, for example, as the high-side switch or the low-side switch in the half bridge shown in FIG. 1 a, respectively, or similar circuits.FIG. 3 shows a cross-section of a control cell 300 in one embodiment. Reference numerals are selected here analogously to the active cell 200 according to FIG. 2 ain such a way that regions, regions or layers with reference numerals 3xx in the figure correspond in terms of their significance to those with reference numerals xx in FIG. 2 a. An exception, however, is formed by regions or layers 3, 12, 13, 14, 16 in order to emphasize that these are the same regions as the active cell only at another point of the component. In other words, the substrate layer 12 can therefore extend, for example, over the entire component in which both active cells and control cells are provided.The gate electrode 304 is not electrically connected to the gate electrode 4 of the active cell (according to FIG. 2 a). Rather, it is electrically connected to the source metal 16 by means of a contact 318 via at least one first ohmic resistor 319. By way of example, two first ohmic resistors 319 are provided, on the left and on the right. In this way, an electrically conductive connection is provided. A resistor 319 can consist of, for example, doped SiC or of polysilicon or other suitable resistive layers or boundary surfaces or can have such, is located in or on the component and is only schematically illustrated here.The contact 318, as well as contacts described later, may be schematically understood where they are not directly in the cross-sections themselves, and the contact is made, for example, in the 3rd dimension outside the cross-section shown. In particular, contact regions are intended to be low-ohmic connections from metal to highly doped semiconductor regions or between metals. The former can be produced in a conventional manner by directly bonding a metal (e.g. aluminum, AlCu, AlSiCu) to the semiconductor or by applying a silicide layer to the semiconductor with subsequent application of the metal.In reverse operation with VDS<0V, the gate electrode 304 remains at source potential. As a result, with a corresponding selection of the doping concentration of the channel layer 308, a bypass for electrons can form on the trench-side surface of the channel layer 308, which reduces the storage charge (initial condition for the RR). During RR, when the component acts as a freewheeling diode, as a result of the Miller capacitance formed by the gate electrode 304 and drift layer 14 and, if present, layer 311, an impression of current into the gate electrode 304 occurs as the VDS increases, and thus a dynamic open-circuit of the channel forming on the trench-side surface of the channel layer 308, since the current generates a voltage increase at the resistor 319. This leads to a reduction of the maximum drain voltage VDSm for the entire component compared to the case without control cells.This effect is not directly dependent on the drive voltage VGSol,h, because the gate electrode 304 is not connected to it. Consequently, the effect is still present even if the gate drive fails at G in the event of a fault.FIG. 4 shows a cross section of a control cell 400 in a further embodiment. Reference numerals are selected here analogously to the control cell 300 according to FIG. 3 in such a way that regions, regions or layers with reference numerals 4xx in the figure correspond in terms of their significance to those with reference numerals 3xx in FIG. 3.In contrast to control cell 300 according to FIG. 3, the source layers 409 are not connected directly here, but rather to the source metal 16 by means of a contact 417 via at least one second ohmic resistor 420. In this way, an electrically conductive connection is provided. By way of example, two second ohmic resistors 420 are provided, on the left and on the right, and correspondingly also two contacts 417. A resistor 420 can consist of, for example, doped SiC or of polysilicon or other suitable resistive layers or boundary surfaces or can have such, is located in or on the component and is only schematically illustrated here.If a current begins to flow in the RR via the source layer 409, contact 417 and the second ohmic resistor 420, a voltage drop is produced essentially at the resistor 420, which voltage drop counteracts the dynamic current increase in the sense of a negative feedback. This dynamically limits the stream if this is desired for the application.The other behavior with respect to the reduction of VDSm is analogous to the embodiment shown in FIG. 3, although with a less pronounced effect depending on the size of the resistor 420. The effect is not directly dependent on the drive voltage VGSol,h, because the gate electrode 404 is not connected to it. Consequently, the effect is still present even if the gate drive fails at G in the event of a fault.FIG. 5 shows a cross section of a control cell 500 in a further embodiment. The control cell 500 corresponds to the control cell 300 according to FIG. 3, but in addition to the at least one first ohmic resistor 319, which can be an internal resistor in particular, at least one first external ohmic resistor 319 eis provided, which is connected in parallel with the at least one first ohmic resistor 319. By way of example, two first external ohmic resistors 319 eare provided.For this purpose, the control cell 500 can have one or optionally a plurality of contact regions to which the at least one first external ohmic resistor 319 ecan be connected. Such a contact region can be formed, for example, on or by the contact 318. In addition, suitable connection devices can be providedA user thus has the option of adapting the dynamic reverberation of the transistor to his application. If a plurality of control cells are present in the transistor, either all of them can use the same additional connection devices jointly or can use respective additional connection devices combined in groups, by means of which external resistors can be applied in the described manner.FIG. 6 shows a cross section of a control cell 600 in a further embodiment. The control cell 600 corresponds to the control cell 400 according to FIG. 4, additionally having at least one first external ohmic resistor 419 eaccording to control cell 500 according to FIG. 5, and in addition, in addition to the at least one second ohmic resistor 420, which can be an internal resistor in particular, at least one second external ohmic resistor 420 eis provided, which is connected in parallel with the at least one second ohmic resistor 420. Two external ohmic resistors 420 eare provided by way of example.For this purpose, the control cell 600 can have one or optionally a plurality of contact regions to which the at least one second external ohmic resistor 420 ecan be connected. Such contact regions may be formed, for example, on or by the contacts 417. In addition, suitable connection devices can be provided.A user thus has the option of adapting the dynamic reverberation of the transistor to his application. If a plurality of control cells are present in the transistor, either all of them can use the same additional connection devices jointly or can use respective additional connection devices combined in groups, by means of which external resistors can be applied in the described manner.Other embodiments may be obtained when the resistors 319 and / or 419 are zero ohms. This results in the omission of the dynamic opening effect of the gate electrodes 304, 404 but influences the storage charge (initial condition of the RR) in the described manner.Further embodiments may be obtained if not both sides of the control cell are formed with resistors, but one half is structurally formed as the active cell, but the gate electrode 304, 404 is connected as shown in FIGS. 3 and 4.Further embodiments may be obtained if the control cell is not formed with a trench gate (i.e. a gate in a gate trench) but with a planar gate.Further embodiments may be obtained if the control cell has a different threshold voltage than the active cells or even different control cells have different threshold voltages. This can be achieved, for example, by different doping concentrations of the body regions or channel layers 308, 408.Further embodiments may be obtained if the control cells comprise dielectrics other than SiO2, e.g. high-k materials.Further embodiments can be obtained if, as already mentioned, control cells according to FIGS. 3 and 4 are combined with one another and with active cells. The control cells can also have island-shaped designs in addition to a strip-shaped design.Generally, the control cells can be combined with any active cells; this applies to stripe / island designs as well as to different cross sections.FIG. 7 schematically shows a semiconductor component 1000, in particular a MISFET, in an embodiment in a plan view, and FIG. 8 shows a part of the semiconductor component 1000 in a different sectional plane. This is intended to illustrate, by way of example, how active cells 200 and control cells 300 may be combined.The relation to the cross sections is shown in FIGS. 2 to 4 with reference to the x and y directions. The cross section according to FIGS. 2 to 4 is also indicated by the section line A-A' in FIG. 7.Here, the source metal layer or the source metal is again shown with 16, wherein a distinction is made with 16 (L) and 16 (R) only according to a left and right portion.In FIG. 7, the source metal layer can be seen from above, whereas in FIG. 8, the source layers 9, 309, the shielding regions 10, 310 and the gate electrodes 4, 304 can be seen. Thus, the plane shown in FIG. 8 is parallel to the plane shown in FIG. 7, but lies lower in the z-direction.1004 denotes a gate pad, i.e. a connection possibility for a gate voltage for the active cells. 1004' shows a so-called gate tuner (e.g. a metal) which serves to distribute the signal from gate pad 1004 to the gate electrodes 4 of the active cells. This is then shown in more detail in FIG. 8, with a contact of the gate gun 1004' on the gate electrode 4 being indicated by 18.A runner (e.g. a metal) for connecting the gate electrodes 304 of the control cells 301 to the first ohmic resistor 319 is shown at 1019. This is effected via the contact 318, as indicated in FIG. 8. Here, 1319 shows a region in which the resistor 319 can be arranged. It is connected on one side to the associated runner 1019 and on the other side to the source metal 16(R) or 16(L), respectively, thus establishing the required first electrically conductive connection.1101 indicates a so-called edge termination of the MISFET or of the entire chip. 1500 shows a longitudinal direction of each of the active cells 100 assumed to be strip-shaped in this example and also of the control cells 300, so that the cutting direction A-A', as mentioned, leads to the cross sections shown in FIGS. 2 and 3, for example.

Claims

Semiconductor component (1000), in particular transistor, having a source contact layer (16) and a substrate and / or drain layer (12, 13, 14), wherein the semiconductor component has a plurality of cells comprising one or more active cells (200) and one or more control cells (300, 400), wherein the source contact layer (16) and the substrate and / or drain layer are assigned to each of the cells, wherein the semiconductor element has, for each of the cells, in each case at least one first type of doped source layer (9) and at least one channel layer (8), wherein the semiconductor element has, for each of the cells, in each case a gate electrode (4, 304, 404) which is insulated from the source layer (9, 309, 409) and the channel layer (8, 308, 408), wherein the semiconductor element for the one or each of the plurality of active cells (200) has in each case an insulation layer (15), by means of which the gate electrode (4) is insulated from the source contact layer (16), wherein the semiconductor element for the one or each of the plurality of control cells (300, 400) has in each case a first electrically conductive connection, in particular with a first ohmic resistor (319, 419), by means of which the gate electrode (304, 404) is electrically conductively connected at least in sections to the source contact layer (16).The semiconductor device (1000) of claim 1, wherein the first electrically conductive connection comprises a first ohmic resistor (319, 419), respectively.Semiconductor component (1000) according to Claim 1 or 2, wherein the second electrically conductive connection, in particular a second ohmic resistor (420), for the one or at least one of the plurality of control cells (400), by means of which connection the source layer (409) is electrically conductively connected at least in sections to the source contact layer (16).The semiconductor device (1000) of claim 3, wherein the second electrically conductive connection comprises a second ohmic resistor (420), respectively.Semiconductor component (1000) according to Claim 3 or 4, which has, for the one or at least one of the plurality of control cells (400), an insulation layer (415), by means of which the source layer (409) is insulated from the source contact layer (16), and wherein, by means of the second electrically conductive connection, the source layer (409) is electrically conductively connected to the source contact layer (16).Semiconductor component (1000) according to one of the preceding claims, which has, for the one or the at least one of the plurality of control cells (400), a connection region which is conductively connected to the source layer (409) and to which an external second ohmic resistor (420e) can be connected, by means of which connection region the source layer (409) can be electrically conductively connected to the source contact layer (16).Semiconductor component (1000) according to one of the preceding claims, which has, for the one or the at least one of the plurality of control cells (300, 400), a connection region which is conductively connected to the gate electrode (304, 404) and to which an external first ohmic resistor (319e, 419e) can be connected, by means of which connection region the gate electrode (304, 404) can be electrically conductively connected to the source contact layer (16).Semiconductor component (1000) according to one of the preceding claims, wherein for the one or at least one of the plurality of control cells (300), the source layer (309) is in direct contact with the source contact layer (16) at least in sections.The semiconductor component (1000) according to any one of the preceding claims, wherein for the one or each of the plurality of active cells (200), the source layer (9) is directly in contact with the source contact layer (16) at least in sections.The semiconductor device (1000) of any of the preceding claims, having a different threshold voltage for the one or each of the plurality of active cells (200) than for the one or more control cells (300, 400).Semiconductor component (1000) according to one of the preceding claims, comprising a drain contact layer (3) adjoining the substrate and / or drain layer (12, 13, 14).Semiconductor component (1000) according to one of the preceding claims, which is formed as an SiC or GaN or gallium oxide field effect transistor.Use of at least one semiconductor component (1000) according to one of the preceding claims in a half bridge, in particular for driving an electrical load

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