Method for operating an integrated system-on-chip circuit and integrated system-on-chip circuit for carrying out such a method

Abstract

The invention relates to a method for operating an integrated system-on-chip circuit, wherein the integrated circuit comprises a plurality of processor cores and a network-on-chip architecture for communication between the processor cores. A state of the integrated circuit is determined, and the power consumption of the processor cores and network-on-chip routers is actively controlled depending on the state and in compliance with real-time requirements. The invention further relates to a corresponding integrated system-on-chip circuit.

Description

The invention relates to a method for operating a system-on-chip integrated circuit and to a system-on-chip integrated circuit for carrying out such a method.System-on-chip integrated circuits are widely used to perform complex processing operations. Such system-on-chip integrated circuits may be used, for example, in automotive applications to perform complex tasks such as driver assistance functions or autonomous driving related functionalities. In some cases, functions performed on a system-on-chip integrated circuit are time critical or even real-time applications, so that certain execution times must be observed for the execution of functions.In typical implementations, a system-on-chip integrated circuit also includes a network-on-chip, i.e., routers and other network components are located on the integrated circuit to provide communication capabilities between processor cores. Processing functionalities are performed in such processor cores, which are typically located on an integrated circuit.It has been found that power consumption and heat generation can lead to problems with increasing capabilities and increased use of system-on-chip integrated circuits.It is therefore an object of the invention to provide a method of operating a system-on-chip integrated circuit that is superior to or alternative to known methods, in particular with respect to power consumption. It is a further object of the invention to provide a corresponding integrated system-on-chip circuit.These objects are achieved with a method and an integrated system-on-chip circuit according to the respective main claims. Preferred embodiments are claimed, for example, in the respective dependent claims. The contents of the claims are made the contents of the description by explicit reference.The invention relates to a method for operating a system-on-chip integrated circuit. The system-on-chip integrated circuit includes a plurality of processor cores. The system-on-chip integrated circuit includes a network-on-chip architecture for communication between the processor cores. The method comprises the following steps:determining a state of the integrated circuit; andcontrolling the power consumption of at least one, several or all processor cores depending on the state.In such a method, power consumption of processor cores may be actively controlled. Power consumption typically means that electrical energy is consumed to operate the processor cores, which is ultimately converted to thermal energy. Such thermal energy typically heats the integrated circuit, which may lead to temperature problems. Such temperature problems can be avoided or reduced by means of an active power consumption control. In particular, controlling the power consumption of the process cores provides additional functionality for solely controlling the power consumption of the network-on-chip architecture.An integrated circuit can be formed in particular on a single semiconductor chip or on a plurality of semiconductor chips which are connected to one another in a suitable manner. A system-on-chip integrated circuit is typically a circuit that includes processor cores and the network-on-chip architecture. The processor cores are configured to perform computational functionalities and other functionalities, with some input parameters typically being communicated to the respective functionality and output parameters being generated. The network-on-chip architecture provides communication functionality between the processor cores and between the processor cores and off-board components. Typically, the network-on-chip architecture includes a plurality of routers that provide the communication capabilities, but do not perform any computing or processing functionalities outside the communication functionality.Power consumption control means performing special functions that control power consumption of a processor core or other component, beyond simply performing or not performing tasks thereon. While it may in principle be the case that a processor core performing a particular task consumes more power than a processor core that is idle, this is not meant by controlling power consumption. Rather, controlling power consumption means special measures for controlling power consumption of a processor core, typical such functions being described below.In particular, controlling power consumption may include selectively disabling and enabling one, more, or all processor cores. Therefore, processor cores may be selectively disabled, particularly when idle. For example, power to a processor core may be disabled to disable the processor core. By activating the power supply again, the processor core can be activated.The integrated circuit may include one or more processor core clocks. Each processor core clock may provide a clock signal for driving one, more, or all processor cores. Such a clock may provide a clock signal used to drive the respective processor cores.The control of power consumption may include, in particular, selectively disabling and enabling one, more, or all processor core clocks. Therefore, processor core clocks may be disabled when their clock signal is not currently needed, particularly when the processor cores to which the processor core clock is transmitting its clock signal are currently idle. This can reduce the power consumption in particular. A processor core clock may be disabled and enabled, for example, by disabling or enabling a power supply of the processor core clock.The control of the power consumption may in particular comprise varying a clock frequency of one, more or all processor core clocks. This may take into account, in particular, that even if a task is performed on a processor core, time is available to perform the task at a lower frequency without jeopardizing the expiration time. This leaves room for the reduction of the clock frequency, so that both the processor core clock and the processor core are operated at a lower frequency and therefore consume less energy.According to an embodiment, the network-on-chip architecture includes a plurality of routers for communication between the processor cores. The control of power consumption may further comprise:selectively disabling and enabling one, more or all routers and / orselectively disabling and enabling a router clock providing a clock signal for driving the routers; and / orvarying a clock frequency of a router clock providing a clock signal for driving the routers.In this case, active current management for components, in particular routers, of a network-on-chip architecture can also be used. Such stream management may be particularly applied in addition to the stream management of processor cores as described elsewhere herein. The combination of network-on-chip architecture power management and processor core power management may provide further improved power management.In particular, at least one router can be deactivated as long as it is idle. This may take into account in particular that an idle router does not have to operate and may therefore reduce power consumption when it is deactivated.In particular, the state may include an indication of a stress on one, more or all processor cores. Such a display may be derived in particular from messages that may be received by units that communicate with the processor cores, in particular from external units. For example, if an external unit requests processing capability on a processor core, such an external unit may first send a message to a stream management module to inform the stream management module of the task to be performed on a particular processor core or multiple processor cores. A state may then be updated and certain power management functions may be performed based on the state. This may also include selectively increasing the clock frequencies or selectively enabling processor cores and / or routers currently disabled.In particular, the state may include a lead time corresponding to at least one processing activity performed by one or more processor cores. The lead time can indicate in particular a time at which the processing activity will be concluded, preferably before a defined time. This is an indication of a possible buffer time, indicating that processing activity is completed too early using current settings of power management, leaving room for component deactivation or for clock frequency reduction. In particular, the lead time indicates when a processing activity satisfies real-time constraints. Typically, real-time functionality requires compliance with expiration times. Typically, a state results in power management that ensures that all expiration times are actually met.The lead time can be calculated in particular on the basis of a worst-case analysis. Such a calculation typically takes into account conditions that are worse with respect to expected ranges, so that even if the processing of a particular processing activity occurs under worse conditions, the lead time is followed. If such a calculation nevertheless indicates that margin is for more time, power saving steps may be taken.In particular, formal worst-case analysis of a task response time may be performed, including the latency penalty of the power saving method. This can be provided to take into account hard real-time systems, which in particular require temporal guarantees of critical functions. Based on this, the allowed buffer time, i.e. in particular the time difference between the worst-case reaction time of the task and its expiration time, is extracted at the construction time and used during the runtime to apply the potential power saving method. Therefore, temporal guarantees can be provided.The power saving method may employ the predictable task access model (AER). This defines a predictable access pattern of a safety critical task by subdivision into three successive phases: acquisition (read), execution and restitution (write). Power savings at the processor core may be predicted in the acquisition and restitution phases, whereas power savings at the network routers may be predicted in the execution phase.The power saving method implements protocol-based synchronization to learn the overall state of the system (e.g., concurrent active tasks). Based on the overall state and task characteristics (e.g., task periods, expiration times, allowed buffer times, priorities, and the respective frequency for each task set), the power saving method decides whether to allow the processor core (and / or a network router) to be disabled and / or disable the clock or only reduce the clock frequency.The control of the power consumption of the at least one processor core and / or the calculation of lead times can be based in particular on a predefined table which comprises task features, in particular task run times, permissible buffer times, priorities and the respective frequency for each task set and processing capabilities and / or processing times. Such a predefined table may be created, in particular, at the design time, such that each expected processing task or activity preferably has one or more entries in the table indicating the required processing capability or indicating certain lead times and certain conditions. Typically, it can be used to perform simple computations during runtime.The control of the power consumption can comprise that at least one processor core is deactivated and / or a processor core clock is deactivated and / or a clock frequency of a processor core clock is reduced, in particular if the lead time is shorter than the set expiration time. The expiration time can be, in particular, an expiration time in order to meet the temporal requirements of hard real-time systems. The lead time typically indicates when processing activity will be completed under the current conditions. If the lead time is shorter than a set elapsed time, this indicates that there is margin for power savings by reducing processing capabilities. At the time of expiration, the function typically must be complete and typically all power management steps are performed so that the time of expiration is guaranteed.Typically, at least one processor core may be disabled as long as it is idle. This may save power so that idle processor cores do not consume electrical power.Typically, during an acquisition phase and / or during a restitution phase, at least one processor core may be deactivated. This may apply to one, more or all processor cores.The acquisition phase is typically a phase in which data is received from a processor core. The acquisition phase is typically followed by an execution phase in which processing activity is performed based on the received data. The execution phase is typically followed by the restitution phase, in which the generated data are sent to other units. Typically, the processor core is not needed during the acquisition phase and the restitution phase, so that power can be saved by deactivating the processor core.The frequency of at least one processor core clock may be reduced during an execution phase of a processor served by the processor core clock. During the execution phase, processing activities are typically performed by a processor core. However, as described above, if the analysis steps indicate that there is a possibility of saving power by reducing processing capabilities while maintaining relevant expiration times, the frequency of the processor core clock may be reduced to save power.Preferably, one, more or all processor core clocks may be disabled as long as all processor cores served by the processor core clock are idle. This may apply to each processor core clock and corresponding processor clock. When a processor core is idle, it does not perform any computational or processing operations, so it does not require a clock signal. Therefore, the corresponding processor core clocks may be disabled.Preferably, at least one router timer may be disabled as long as the routers served by the router timer are idle. This can save even more power, since routers that are idle, e.g., currently do not send or receive data, do not require a clock signal.The invention further relates to a system-on-chip integrated circuit comprising a plurality of processor cores, a network-on-chip architecture for communication between the processor cores, and a power management module configured to perform a method as described herein. With respect to the method, all embodiments and variations as described herein may be applied.The invention further relates to a non-transitory computer readable medium containing program code which, when executed by a processor, causes the processor to perform a method as described herein. With respect to the method, all embodiments and variations as disclosed herein may be employed.In particular, the system-on-chip configuration may include networks-on-chip, which are the predominant solution to provide a scalable connection for the complex multiprocessor architectures. However, the energy consumption associated therewith has increased immensely. In particular, hard real-time networks on-chip must have limited power consumption to improve overall system reliability. Moreover, processor cores may also be integrated into the stream management system or such stream management may be carried out separately for processor cores.Systems-on-chip may include multiple processor cores as well as networks-on-chip. Moreover, the processor cores may induce extensive power consumption, particularly in a modern domain-based electrical / electronic (I / O) architecture where a high-performance computer is expected to meet high-performance requirements. Therefore, the associated power consumption of the processor core has increased immensely. In particular, hard real-time processor cores and networks on chip must have limited power consumption to improve overall system reliability.In particular, centralized integrated management may be introduced to provide a system level power saving method. It may be characterized by a combination of stream optimization at the processor core level (computation) and at the network-on-chip level (communication) for hard real-time systems. The design introduces a system-level power control layer that is integrated into the existing system-on-chip module and allows isolation between power optimization and task computation or data transfer. Accordingly, modern commercially available systems-on-chip can easily solve, as no modifications of the overall processor cores and network architecture are needed. The power control layer may include local units called power-aware system controllers (PASC) that integrate multiple power saving (PG) concepts in the phase of multiple power loss sources. Further, for secure application of PASC in hard real-time systems while maintaining expiration times, formal worst-case timing analysis of the additional latency induced by the power saving of the processor core and / or network-on-chip power saving methods is provided.The method also supports scalability. It is scalable with larger system-on-chip integrated circuits and its features are not limited to only small system-on-chip (e.g., 2x2 or 4x4 nodes). In particular, the system-on-chip integrated circuit may include at least 64 processor cores.The implementation of the additional features as disclosed herein that combines power savings for processor cores and a communication network simultaneously could also be implemented as an additional hardware part to extend an existing prototype. The embodiments as disclosed herein may be used in, for example, automotive ADAS or heating store units.The invention will now be described with reference to the accompanying drawings. It shows: FIG. 1 shows an integrated system-on-chip circuit according to the prior art, FIG. 2 : shows an integrated system-on-chip circuit with a control layer, and FIG. 3 is a time axis.FIG. 1 shows a system-on-chip integrated circuit IC according to the prior art. The integrated circuit IC comprises a DRAM which is designed as a typical dynamic working memory. It further comprises a plurality of nodes N designated as N0, N1,... N15. As shown, each node N comprises a router RO, a processor core T and a network interface NI connecting the processor core T to the corresponding router RO. The router RO provides communication between the nodes N and also with the DRAM and external units. Processor core T provides processing functionality, for example, for performing certain tasks. The routers RO together form a network on a chip.FIG. 2 shows an integrated circuit IC according to an embodiment of the invention. The system-on-chip as shown in FIG. 1 is in this case a data layer DL overlaid with an additional control layer CL. The control layer CL is a power control layer and includes networks of clients C providing communication with the nodes N and a power-aware node controller (PANC) module.The power management module PANC may communicate with the nodes N via the clients C. This allows the power management module PANC to perform power management functionalities.The routers RO are driven in principle by router clocks and the processor cores T are driven in principle by processor core clocks, the clocks not being shown in the drawings. The clocks typically provide a clock signal to provide a clock with which certain processing or communication tasks are performed. Three types of power management can be performed for each of the routers RO and the processor cores T:clock gating: activating and deactivating processor core clocks and / or router clocks,power gating: activating and deactivating processor cores and / or routers,dynamic voltage and frequency scaling: dynamic adaptation of clock frequencies of processor core clocks and / or router clocks.FIG. 3 provides information on how it can be determined whether power management is possible for actively reducing the power consumption. FIG. 3 shows a typical implementation of an AER task model (AER: acquisition, execution and restitution), in which each task, referred to herein as task: is divided into three phases:- Acquisition (A),execution (E) andRestitution (R).In the acquisition phase, data is retrieved from a processor core. In the execution phase, the data is processed in a specific processing activity in the processor core. In the restitution phase, the generated data is sent to another unit. As shown herein, all of these activities must occur prior to a particular expiration time, which is indicated herein on a horizontal time axis.In the AER task model, it can be predicted that in a worst case scenario giving a worst case reaction time WCRT, there is an expiration time idle between the WCRT and the expiration time, that is, a task is likely to be completed earlier than needed. In this case, power saving concepts can be used.In particular, during execution phase E, the router may be disabled or its clock may be driven at a reduced frequency. The same can occur during the expiration time idle. In addition, during the acquisition phase A and the restitution phase R, the processor core can be deactivated and / or its clock generator driven at a reduced clock frequency.Combining these two power saving methods, namely power saving using routers and power saving using processor cores, can significantly reduce overall power consumption. Alternatively, only one of these forms of implementation may be used.The steps mentioned in the process according to the invention can be carried out in the sequence indicated. However, they can also be carried out in a different sequence, as long as this is technically expedient. In one embodiment, the method according to the invention can be carried out, for example, with a specific step combination in such a way that no further steps are carried out. However, other steps may be performed, including steps not mentioned.It is to be noted that in the claims and in the description features may be described in combination, for example in order to provide a better intelligibility despite the fact that these features may be used or implemented independently of each other. Those skilled in the art will appreciate that such features may be combined with other features or combinations of features independently of each other.Reference numerals in dependent claims may indicate preferred combinations of the respective features, but further combinations of features are not excluded.List of reference charactersIC integrated circuit N node NI network interface RO router T processor core DRAM memory DL data layer CL control layer C client PANC power management module A acquisition phase E execution phase R restitution phase WCRT worst case response time

Claims

Method for operating a system-on-chip integrated circuit (IC), wherein the integrated circuit (IC) comprises a plurality of processor cores (T) and a network-on-chip architecture for communication between the processor cores (T), wherein the method comprises the following steps: - determining a state of the integrated circuit (IC) and - controlling the power consumption of at least one, more or all processor cores (T) depending on the state.The method of claim 1, - wherein controlling power consumption comprises selectively disabling and enabling one, more or all processor cores (T).Method according to one of the preceding claims, - wherein the integrated circuit (IC) comprises one or more processor core clocks, wherein each processor core clock provides a clock signal for driving one, more or all processor cores (T).The method of claim 3, - wherein controlling power consumption comprises selectively disabling and enabling one, more or all processor core clocks.The method of any of claims 3 or 4, - wherein controlling power consumption comprises varying a clock frequency of one, more or all processor core clocks.Method according to any of the preceding claims, - wherein the network-on-chip architecture comprises a plurality of routers (RO) for communication between the processor cores (T), and - wherein controlling the power consumption comprises: - selectively disabling and enabling one, more or all routers (RO) and / or - selectively disabling and enabling a router clock providing a clock signal for driving the routers (RO), and / or - varying a clock frequency of a router clock providing a clock signal for driving the routers (RO).Method according to one of the preceding claims, - wherein the state comprises an indication of a stress on one, more or all processor cores (T).Method according to any of the preceding claims, - wherein the state comprises a lead time corresponding to at least one processing activity performed by one or more processor cores (T), the lead time indicating a time at which the processing activity will be completed before a set lead time.Method according to claim 8, - wherein the lead time is calculated based on a worst case analysis.Method according to either of Claims 8 and 9, - wherein the control of the power consumption comprises at least one processor core (T) being deactivated and / or a processor core clock being deactivated and / or a clock frequency of a processor core clock being reduced if the lead time is shorter than a set expiry time.Method according to any of the preceding claims, - wherein the controlling of the power consumption of the at least one processor core and / or the calculating of the lead times is / are based on a predefined table comprising processing capabilities and / or processing times.Method according to one of the preceding claims, - wherein at least one processor core is deactivated as long as it is idle.Method according to one of the preceding claims, - wherein at least one processor core is deactivated during an acquisition phase and / or during a restitution phase.Method according to one of the preceding claims, - wherein a frequency of at least one processor core clock is reduced during an execution phase which is carried out by a processor served by the processor core clock.Method according to one of the preceding claims, - wherein one, a plurality or all processor core clocks are deactivated as long as all processor cores (T) served by the processor core clock are idle.Method according to one of the preceding claims, - wherein at least one router clock is deactivated as long as the routers served by the router clock are idle.Method according to one of the preceding claims, - wherein the integrated system-on-chip circuit (IC) comprises at least 64 processor cores.A system-on-chip integrated circuit (IC) comprising: - a plurality of processor cores (T), - a network-on-chip architecture for communication between the processor cores (T), and - a power management module configured to perform a method according to any of the preceding claims.

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