Storage device with a tracking word line with an adjustment circuit, as well as a method for operating and a method for manufacturing the same.

Abstract

A storage device comprises: a first matrix of memory cells; a second matrix of tracking cells, the second matrix being configured to emulate the first matrix; a first word line connected to corresponding memory cells in a corresponding number of rows of the first matrix and to the tracking cells; a second word line configured to emulate the first word line; a first tuning circuit connected to the first word line; a second tuning circuit connected to the second word line; and a tuning timer connected to the second tuning circuit.

Description

background

[0001] Static random access memory (SRAM) is a type of storage device. A one-bit SRAM cell has two memory nodes that store the logical state (low or high) of the bit and its counterpart, the bit_bar. A static noise margin (SNM) is a measure of the reliability of an SRAM cell. The SNM of an SRAM cell is the minimum level of noise voltage at each of the two memory nodes that is large enough to flip the states of the bit and the bit_bar values, i.e., to corrupt the data stored by the SRAM cell. Increasing the SNM makes the SRAM cell less susceptible to noise corruption, while decreasing the SNM makes the SRAM cell more susceptible.

[0002] With the development of semiconductor process technology nodes, the operating voltages of SRAMs are gradually decreasing. Lower operating voltages generally also reduce the energy consumption of the SRAM cells. Conversely, lower operating voltages tend to decrease the SNM (signal-to-noise ratio) of the SRAM cell.

[0003] Semiconductor devices are not manufactured with ideal equipment under ideal conditions; rather, they are subject to the effects of equipment tolerances and variations in materials and environment, so the manufactured devices exhibit corresponding changes in resistance, threshold voltage, or similar characteristics. The performance space (PS) of a manufactured design represents the expected range of variation. Since CMOS (complementary metal oxide semiconductor) technology uses n-channel or negative-channel MOS (NMOS) components and p-channel or positive-channel MOS (PMOS) components, the PS for CMOS is typically represented in two dimensions by a four-sided figure with corners representing extremes in the variation of each of the NMOS and PMOS components, where corner = (NMOS, PMOS), e.g., SS = (slow, slow), SF = (slow, fast), FF = (fast, fast), or FS = (fast, slow).For a given device design, a local change occurs within a single wafer (die), while a global change occurs across an entire set of wafers (dies). Examples of global corners are SSG, SFG, FFG, and FSG. Brief description of the drawings

[0004] The figures in the accompanying drawings illustrate one or more embodiments by way of example and without limitation, whereby elements with the same reference numerals consistently represent similar elements. The drawings are not to scale unless otherwise indicated. Fig. Figure 1 is a block diagram of a storage device according to some embodiments. Fig. Figure 2 is a circuit diagram of a memory according to some embodiments. Fig. Figure 3 is a time diagram with waveforms according to some embodiments. The Fig. 4A to 4C are site plans according to some embodiments. Fig. 4D is a layout diagram according to some embodiments. The Fig. 5A and Fig. 5B are corresponding cross-sections according to some embodiments. The Fig. 6A and Fig. Section 6B contains flowcharts of corresponding procedures for manufacturing a storage device according to some embodiments. Fig. Figure 7 is a flowchart of a method for operating a storage device according to some embodiments. Fig. Figure 8 is a block diagram of an EDA system (EDA: electronic design automation) according to some embodiments. Fig. Figure 9 is a block diagram of an IC manufacturing system (IC: integrated circuit) and an associated manufacturing process according to some embodiments. Detailed description

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter. Specific examples of components, materials, values, steps, operations, arrangements, or the like are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, materials, values, steps, operations, arrangements, or the like are also considered. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are only in indirect contact.Furthermore, reference numbers and / or letters may be repeated in the various examples in this disclosure. This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to easily describe the relationship of one element or structural element to one or more other elements or structural elements shown in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90° or in a different orientation), and the spatially relative descriptors used here may be interpreted accordingly. In some embodiments, the term "standard cell structure" refers to a standardized building block contained in a library of various standard cell structures.In some embodiments, different standard cell structures are selected from a library of standard cell structures and are used as components in a layout diagram that represents a circuit.

[0007] In some embodiments, a storage device comprises: a first array or matrix (e.g., a memory matrix) of memory cells; a second array or matrix (e.g., a tracking matrix) of tracking cells, the second matrix being configured to emulate the first matrix; a first word line (e.g., a word line WL) connected to corresponding memory cells in a corresponding row of the memory matrix and to the tracking cells; a second word line (e.g., a tracking word line TWL) configured to emulate the word line WL; a first tuning circuit connected to the word line WL; a second tuning circuit connected to the tracking word line TWL; and a tuning timer connected to the second tuning circuit.In some embodiments, the storage device also has a second setting circuit that is connected to the word line WL.

[0008] An SRAM storage device according to another approach is a counterpart to embodiments of the SRAM storage devices disclosed herein, e.g., storage device 100. The SRAM storage device according to the other approach provides a word line tuning scheme and a tracking word line tuning scheme. The word line tuning scheme according to the other approach includes a tuning circuit connected to the word line. The tracking word line tuning scheme according to the other approach includes a tracking word line but no tuning circuit connected to the tracking word line. As part of the development of the present embodiments, the inventors of the present invention recognized that the emulation of the word line by the tracking word line according to the other approach has inaccuracies, which reduces the SNM of the SRAM storage device according to the other approach.Based at least in part on the findings of the inventors of the present invention, embodiments of the present application provide a tracking scheme that includes a tuning circuit connected to the tracking word line. Accordingly, tracking schemes for SRAM memory devices according to embodiments of the present application include a tuning circuit connected to the tracking word line. These embodiments of the present application offer advantages, such as higher accuracy in the emulation of the word line by the tracking word line, resulting in a greater SNM of the SRAM memory devices than that of the SRAM memory device according to the other approach.In some embodiments, these SRAM memory device embodiments of the present application, which have an adjustment circuit connected to the tracking word line, show an increase in the read span in a range of ≈10.2% to ≈11.1% for the SSG process corner (and even better for the other global corners) compared to the SRAM memory device according to the other approach.

[0009] Fig. Figure 1 is a block diagram of a storage device 100 according to some embodiments.

[0010] The storage device 100 is, for example, a semiconductor storage device. In some embodiments, the storage device 100 is contained in an integrated circuit (IC). In some embodiments, the storage device 100 adopts an SRAM architecture. In some embodiments, the storage device 100 has a different storage architecture than the SRAM architecture.

[0011] The memory device 100 comprises the following: a tracking matrix, e.g., a column, 102; a bit line tracking circuit (BLT circuit) 104; a tuning timer 106; a tuning circuit 108(1); a tuning circuit 108(2); a word line driver (WL driver) 110(1); a tracking word line (TWL); a TWL driver 110(2); a bias selector 112; a multiplexer (MUX) 114; a memory matrix 116 of memory cells ( Fig. 2); and a setting circuit 122. The memory matrix 116 is connected to the WL driver 110(1) and the MUX 114. The WL driver 110(1) is connected between the setting circuit 108(1) and each of the memory matrix 116 and the tracking matrix 102. The setting circuit 108(1) is connected between the setting timer 106 and the WL driver 110(1). The multiplexer 114 is connected between the bias selector 112 and the memory matrix 116. The bias selector 112 is connected between the setting timer 106 and the TWL driver 110(2). The setting circuit 122 is connected between the tracking word line TWL and the tracking matrix 102. The tracking word line TWL is connected between (A) each of the setting circuits 108(2) and the TWL driver 110(2) and (B) the setting circuit 108(2). The setting circuit 108(2) is connected between the tracking word line TWL and the setting timer 106.The setting timer 106 is connected between (A) the BLT circuit 104 and (B) each of the setting circuit 108(1), the bias selector 112, and the setting circuit 108(2). The BLT circuit 104 is connected between the tracking matrix 102 and the setting timer 106. The tracking matrix 102 is connected between the WL driver 110(1) and the BLT circuit 104.

[0012] In Fig. 1. The WL driver 110(1) is configured to use the word line WL ( Fig. 2) drives. The tracking word line TWL is configured to emulate the word line WL, as will be explained later. In some embodiments, the TWL driver 110(2) is configured to emulate a word line driver WL. In some embodiments, the TWL driver 110(2) is configured to exhibit substantially the same operating profile as the word line driver WL. The TWL driver 110(2) is configured to output a pre_EMU signal ( Fig. 2 and Fig. 3), which is generated at a second end of the tracking word line TWL, as an emulation signal EMU ( Fig. 2 and Fig. 3) outputs to a first end of the tracking word line TWL, and the emulation signal EMU is output to an input of the BL setting circuit 122 ( Fig. 2) received. The BL setting circuit 122 uses the emulation signal EMU ( Fig. 2 and Fig. 3) to set a rate of discharge of a voltage v_TBLT of a signal TBLT ( Fig. 2 and Fig. 3) on a tracking bit line BLT ( Fig. 2), so that they correspond to a discharge rate of a signal on a bit line (e.g., the bit line BL of Fig. 2) is essentially similar to the memory matrix 116. The BL setting circuit 122 ( Fig. 2) is configured to apply a voltage v_BL on the bit line BL ( Fig. 2) based on a voltage v_EMU of the emulation signal EMU ( Fig. 2 and Fig. 3) adjusts, thereby improving the performance of the BLT circuit 104.

[0013] In Fig. 1 shows the tracking matrix has 102 tracking cells ( Fig. 2) which are arranged, for example, in a column. Each of the tracking cells is connected to a tracking bit line BLT ( Fig. 2) connected. In some embodiments, each tracking cell of the tracking matrix 102 has essentially the same structure and essentially the same performance parameters (which, for example, represent an impedance or a resistance-capacitance load) as the memory cells of the memory matrix 116. The BLT circuit 104 uses a voltage v_BLT ( Fig. 2) the tracking bit line BLT of the tracking matrix 102 for estimating a voltage drop of a bit line BL ( Fig. 2) the storage matrix 116, in order to operate the storage device 100 faster and / or more efficiently. Operation in conjunction with the tracking matrix 102 is described below with reference to Fig. 2 described in more detail.

[0014] The BLT circuit 104 has an input configured to receive a voltage v_BLT from a tracking line bit_bar on the tracking bit line BLT of the tracking matrix 102. The BLT circuit 104 is configured to detect a drop in the voltage v_BLT of the tracking line bit_bar and sends a voltage drop information to the setting timer 106. The setting timer 106 is configured to generate a time control signal TMR based on the voltage drop information from the BLT circuit 104. Fig. 2 and Fig. 3) generated. The time control signal TMR is provided for the setting circuit 108(1), the bias selector 112 and the setting circuit 108(2), respectively. During a first period ( Fig. 3) of a read cycle or a write cycle and in response to the timing signal TMR, the following applies: the setting circuit 108(1) sets a voltage v_DW of a signal DW ( Fig. 2 and Fig. 3) on the word line WL ( Fig. 2) which is activated by the WL driver 110(1); and the setting circuit 108(2) sets a voltage v_EMU of a signal EMU ( Fig. 2 and Fig. 3) on the tracking word line TWL, which is activated by the TWL driver 110(2). The setting circuit 122 is configured to apply a voltage v_BL of a signal BL ( Fig. 2 and Fig. 3) on a bit line BL ( Fig. 2) based on the voltage v_EMU of the signal EMU ( Fig. 2 and Fig. 3) sets up on the tracking word line TWL.

[0015] In Fig. 1. The bias selector 112 is configured so that it also functions during a second period ( Fig. 3) of the write cycle and in response to the timing signal TMR a selection signal SEL ( Fig. 2 and Fig. 3) generates, which controls which of a write support voltage VWA ( Fig. 2) and a reference voltage, e.g. VDD ( Fig. 2), via the multiplexer 114 to a CVDD operating voltage line ( Fig. 2) is applied. In short, based on the information obtained from the tracking matrix 102, the operating conditions of the memory matrix 116 are estimated to facilitate the use of various read and write setting schemes for the memory matrix 116, such as reducing an activated voltage of the signal DW on the word line WL or reducing a voltage applied to the operating voltage line CVDD, or the like.

[0016] Fig. Figure 2 is a circuit diagram of a storage device 200 according to some embodiments.

[0017] Memory device 200 is an example of memory device 100. A memory matrix 116 contains memory cells arranged in M ​​rows and N columns (M x N), where M and N are each positive integers. An example of the memory cells of memory matrix 116 is memory cell 206. Fig. 2 It is assumed that memory cell 206 is a six-transistor SRAM cell (6T memory cell). In some embodiments, each of the memory cells has a different configuration than the 6T memory cell described in Fig. 2 is shown. Fig. 2 is a tracking matrix 102 arranged as a one-dimensional matrix, e.g., as a column. In some embodiments, the tracking matrix 102 is a two-dimensional matrix.

[0018] Memory cell 206 comprises a latch and two metal-oxide-semiconductor field-effect transistors (MOSFETs) with negative channels (NFETs), namely NFETs N13 and N14. NFET N13 is electrically connected between a bit line BL and a first memory node nd1 of the latch. Hereinafter, the terms "electrically switched" and "electrically connected" are abbreviated as "switched" and "connected," respectively. NFET N14 is connected between a bit bar line BLB and a second memory node nd2 of the latch. In normal operating mode, the logic state of memory node nd2 is the counterpart to the logic state of memory node nd1; that is, if the logic state of memory node nd1 is low, then the logic state of memory node nd2 is high, and vice versa. In some embodiments, NFETs N13 and N14 are each referred to as a pass-through gate transistor.The bit line BL is connected not only to memory cell 206, but also to other memory cells (not shown) in the corresponding column of memory matrix 116. The bit bar line BLB is also connected not only to memory cell 206, but also to other memory cells (not shown) in the corresponding column of memory matrix 116. The gate terminals of the pass-through gate transistors N13 and N14 are connected to a word line WL.

[0019] In Fig. 2. The latch of memory cell 206 has a first and a second inverter, which are cross-connected. The first inverter has the following: a positive-channel MOSFET (PFET) P11, which is connected between the supply voltage line CVDD and the memory node nd1; and an NFET N11, which is connected between the memory node nd1 and a reference voltage, e.g., VSS, ground (GND), or the like. The second inverter has the following: a PFET P12, which is connected between the supply voltage line CVDD and the memory node nd2; and an NFET N12, which is connected between the memory node nd2 and the reference voltage VSS. The gate terminals of the PFET P11 and the NFET N11 of the first inverter are connected to the memory node nd2 of the second inverter. The gate terminals of the PFET P12 and the NFET N12 of the second inverter are connected to the storage node nd1 of the first inverter.Therefore, the first and second inverters are referred to as being cross-connected. In some embodiments, the PFETs P12 and P12 are referred to as pull-down transistors, and the NFETs N11 and N12 are referred to as pull-up transistors.

[0020] An example of the tracking cells in tracking matrix 102 is tracking cell 202. The tracking cells of tracking matrix 102 have essentially the same structure and essentially the same performance parameters as the memory cells of memory matrix 116. Therefore, tracking cell 202 has essentially the same structure and essentially the same performance parameters as memory cell 206. PFETs P13 and P14, NFETs N13 to N16, and memory nodes nd1 and nd2 correspond to PFETs P11 and P12, NFETs N11 and N12, and memory nodes nd1 and nd2, respectively, of memory cell 206. A tracking bit line BLT of tracking cell 202 corresponds to the bit_bar line BLB of memory cell 206 and is configured to emulate it. A tracking bit bar line BLBT of tracking cell 202 corresponds to the tracking bit line BLT of memory cell 206 and is configured to emulate it.The gate terminals of pass-through transistors N15 and N16 are connected to the word line WL. Thus, the gate terminals of pass-through transistors N15 and N16 of tracking cell 202 are connected to the gate terminals of pass-through transistors N13 and N14 of memory cell 206. In some embodiments, PFETs P13 and P14 are referred to as pull-down transistors, and NFETs N13 and N14 are referred to as pull-up transistors.

[0021] In the memory matrix 116 of Fig. 2. The memory cells (e.g., 206) in a row are connected to a corresponding word line (e.g., WL), and the memory cells (e.g., 206) in a column are connected to a corresponding bit line (e.g., BL) and a corresponding bit bar line (e.g., BLB). In some embodiments, a voltage v_BLB on the bit bar line BLB represents a logical state that is essentially the logical counterpart (or logical inverse) of the logical state represented by a voltage v_BL on the corresponding bit line BL. The voltage on the bit line BL determines the read and write spans of an SRAM cell. In some embodiments, the voltage on the bit bar line BLB determines the read and write spans of an SRAM cell. The relationship between the voltage on the bit line BL and the read and write spans will be discussed later with reference to Fig. 5 described in more detail.

[0022] The WL driver 110(1) comprises a "select-this-row" detector (TRS detector) 218 ​​and an inverter, the inverter comprising a PFET P1 and an NFET N1. The TRS detector 218 is configured to detect when a read or write address selects the corresponding row of the memory matrix 116. This selection is used, for example, for a read or write operation that targets one of the memory cells (e.g., 206) in the selected row. In some embodiments, the TRS detector 218 includes an address decoder. An output of the TRS detector 218 is connected to an input of the inverter of the WL driver 110(1). An output of the inverter of the WL driver 110(1) is connected to the word line WL.The TRS detector 218 is configured to reduce / lower its output signal after detecting that the corresponding line has been selected, causing the inverter of the WL driver 110(1) to not only generate a control signal on the word line (signal DW), but also a voltage v_DW of the signal DW (. Fig. 3) to increase / raise the level on the word line WL to a level sufficient to turn on each of the pass-through gate transistors N13 and N14.

[0023] In Fig. For example, during a write operation, the bit line BL and the bit_bar line BLB are set to opposite logical states corresponding to the new data being written to memory cell 206. When memory cell 206 is selected, a high logical state is used for the word line WL, which turns on the pass-through gate transistors N13 and N14. This connects the memory nodes nd1 and nd2 of the latch of memory cell 206 to the bit line BL and the bit_bar line BLB. As a result, the logical values ​​on the bit line BL and the bit_bar line BLB are written to the memory nodes nd1 and nd2.

[0024] The setting circuit 108(1) is connected between the word line WL and the setting timer 106. In Fig. 2 The setting circuit 108(1) includes an NFET N3, which is connected between the word line WL and the reference voltage VSS. One gate terminal of the NFET N3 is configured to receive a timing signal TMR, which is generated by the setting timer 106 and activates the NFET N3 for part of a read operation ( Fig. 3) or part of a writing operation ( Fig. 3) switches on to adjust the voltage v_DW of the signal DW on the word line WL. The timing control signal TMR is also received by the setting circuit 108(2) and the bias selector 112, as will be explained later. In some embodiments, the NFET N3 is configured to receive a control signal (not shown) that switches the NFET N3 on for the entire duration of a read operation or for the entire duration of a write operation. In some embodiments, for example, the NFET N3 has a permanently switched-on configuration, where the gate terminal is connected, for example, to the reference voltage VDD. In some embodiments, a PFET is used instead of the NFET N3, and the waveform of the timing control signal TMR is inverted accordingly.

[0025] In Fig. 2 The setting circuit 108(2) is connected between the tracking word line TWL and the reference voltage VSS. In Fig. 2 The setting circuit 108(2) includes an NFET N14 connected between the tracking word line TWL and the reference voltage VSS. A gate terminal of the NFET N4 is configured to receive a timing signal TMR, which activates the NFET N4 for part of a read operation ( Fig. 3) or part of a writing operation ( Fig. 3) switches on to set a voltage v_EMU of the emulation signal EMU on the tracking word line TWL. In some embodiments, the NFET N4 is configured to receive a control signal (not shown) that switches the NFET N4 on for the entire duration of a read operation or for the entire duration of a write operation. In some embodiments, for example, the NFET N4 has a permanently switched-on configuration, where the gate terminal is connected to the reference voltage VDD. In some embodiments, a PFET is used instead of the NFET N4, and the waveform of the timing control signal TMR is inverted accordingly.

[0026] In some embodiments, the tuning circuit 108(2) is configured to adjust the voltage v_EMU of the emulation signal EMU on the tracking word line TWL so that it is substantially equal to that of the tuning circuit 108(1), which is configured to adjust the voltage v_DW of the signal DW on the word line WL. In some embodiments, the tuning circuit 108(2) is configured to have substantially the same operating profile as the tuning circuit 108(1). In some embodiments, the NFET N4 is configured to have substantially the same operating profile as the NFET N3, e.g., with respect to different combinations of parameters such as current conductance, channel length, threshold voltage, or the like.

[0027] The bias selector 112 is configured to receive the time control signal TMR. The bias selector 112 is configured to generate a selection signal SEL in response to the time control signal TMR. Fig. 3) generates and outputs this to multiplexer 114. In response to the selection signal SEL ( Fig. 3) The multiplexer 114 selectively connects the write support voltage VWA or the reference voltage VDD to the operating voltage line CVDD.

[0028] In Fig. 2. The tracking word line TWL is configured to have substantially the same impedance, resistance-capacitance load, or the like as the word line WL. In some embodiments, the total length of the tracking word line TWL is substantially equal to the total length of the word line WL, and the width of segments comprising the tracking word line TWL is substantially equal to the width of segments comprising the word line WL, the width being measured with respect to a short axis of these segments. In these embodiments, the propagation delay of a signal transmitted over the tracking word line TWL is delayed similarly to a signal sent by the WL driver 110(1) over the word line WL across the memory matrix 116 to a corresponding memory cell in one of the columns of the memory matrix 116.In these embodiments, a transfer function representing the effect of the tracking word line TWL on a signal propagating through it is similar to a transfer function representing the effect of the word line WL on a signal propagating through it.

[0029] One input end of the tracking word line TWL is configured to receive a pre_EMU signal from the TWL driver 110(2). Fig. 2 The tracking word line TWL has a first line segment seg(1), a second line segment seg(2), and a third line segment seg(3) connected in series. The second line segment seg(2) is connected between the first line segment seg(1) and the third line segment seg(3). In some embodiments, the total length of the tracking word line TWL, i.e., the sum of the lengths of the first line segment seg(1), the second line segment seg(2), and the third line segment seg(3), is configured to be similar to the width of the N columns in the memory matrix 116. In some embodiments, the sum of the lengths of the line segments seg(1) to seg(3) is essentially equal to the total length of the word line WL.

[0030] In the tracking word line TWL of Fig. In some embodiments, the length of the first line segment seg(1) is substantially equal to about half the width of the memory matrix 116, i.e., the width of about N / 2 columns of the memory matrix 116. In some embodiments, the length of the third line segment seg(3) is substantially equal to about half the width of the memory matrix 116. For example, if the memory matrix 116 has 32 columns, the length of the first line segment seg(1) [and also the length of the third line segment seg(3)] is configured to be substantially equal to the width of 16 columns in the memory matrix 116. For example, if the memory matrix 116 has 128 columns, the length of the first line segment seg(1) [and also the length of the third line segment seg(3)] is configured to be essentially equal to a width of 64 columns in the memory matrix 116.In some embodiments, the length of the first line segment seg(1) [and also the length of the third line segment seg(3)] is based on the size of the memory matrix 116. The total length of the tracking word line TWL is similar to the total length of one of the word lines (e.g. WL) of the memory matrix 116.

[0031] The TWL driver 110(2) comprises a single-row select detector (ARS detector) 220 and an inverter, the inverter comprising a PFET P3 and an NFET N8. The ARS detector 220 is configured to detect when a read or write address selects the corresponding row of the memory matrix 116. This selection is used, for example, for a read or write operation that targets one of the memory cells (e.g., 206) in the selected row. In some embodiments, the ARS detector 220 includes an address decoder. An output of the ARS detector 220 is connected to an input of the inverter of the TWL driver 110(2). One output of the inverter of the TWL driver 110(2) is configured to generate a pre_EMU signal and is connected to a first end of the tracking word line TWL.The ARS detector 220 is configured to reduce / lower its output signal after detecting that a line has been selected, causing the inverter of the WL driver 110(1) to increase / raise a voltage v_pre_EMU of the signal pre_EMU, which is fed into the tracking word line TWL, in order to thereby increase a voltage v_EMU of the signal EMU ( . Fig. 3) to increase / raise the value issued by the tracking word line TWL.

[0032] The BL setting circuit 122 is configured to receive the emulation signal EMU from the tracking word line TWL. Based on the emulation signal EMU, the BL setting circuit 122 adjusts the voltage v_BL on the bit line BL. Fig. In Figure 2, the BL tuning circuit 122 has a quasi-inverter configuration. The BL tuning circuit 122 comprises a PFET P2 and NFETs N5, N6, and N7. The PFET P2 is connected between the reference voltage VDD and an output node of the BL tuning circuit 122 at node nd5. The output node nd5 of the BL tuning circuit 122 is connected to the tracking bit line BLT. A first source / drain (S / D) terminal of NFET N5 is connected to node nd5, and a second S / D terminal of NFET N5 is connected to a first S / D terminal of NFET N6. A second S / D terminal of NFET N6 is connected to a first S / D terminal of NFET N7. A second S / D terminal of NFET N7 is connected to the reference voltage VSS. The gate terminals of PFET P2 and NFETs N5 to N7 are connected to an input of the BL control circuit 122 and thus to the emulation signal EMU. The BL control circuit 122 is controlled by the emulation signal EMU.The BL setting circuit 122 is configured to discharge a voltage at node nd5 corresponding to the emulation signal EMU, thereby setting a voltage v_TBLT of signal TBLT on the tracking bit line BLT of tracking cell 202. In some embodiments, an NFET is used instead of PFET P2, and corresponding PFETs are used instead of NFETs N5 to N7, and the waveform of the signal pre_EMU, and thus the waveform of the emulation signal EMU, is inverted accordingly.

[0033] When the emulation signal EMU reaches a level sufficient to turn on NFETs N4 to N6 and turn off PFET P2, the BL tuning circuit 122 begins to discharge / reduce the voltage at node nd5, thereby discharging / reducing the voltage v_TBLT of the TBLT signal on the tracking bit line BLT, thus adjusting (or manipulating) the waveform of the TBLT signal. In some embodiments, the number of NFETs in the BL tuning circuit 122 is essentially equal to the number of NFETs contained in a pendant signal path (not shown), such as a pendant discharge path, in another part of the storage device 200. In some embodiments, the BL tuning circuit 122 is configured to emulate the pendant signal path (not shown).In some embodiments, the number of NFETs in the BL setting circuit 122 is proportional to the number of NFETs contained in the pendant signal path (not shown). In some embodiments, the number of tracking cells (e.g., 202) in the tracking matrix 102 connected to the tracking bit line BLT is essentially equal to the number of rows in the memory matrix 116, i.e., essentially equal to N. For example, if the memory matrix 116 contains 256 rows, such that N = 256, then the tracking bit line BLT is connected to a total of 256 tracking cells in the tracking matrix 102.

[0034] In Fig. 2. The tracking matrix 102 is used to estimate (or track) a change in the voltage v_SBL of a signal SBL on the bit line BL of the memory matrix 116. During a read or write operation of the memory matrix 116, a tracking operation takes place in the memory matrix 116. The tracking operation is used for one of the tracking cells (e.g., 202) of the tracking matrix 102. In some embodiments, the tracking operation is used specifically for the tracking cells of the tracking matrix 102 to compensate for operational and process variations that would otherwise affect a read or write operation performed on the memory matrix 116. In some embodiments, the mean voltage drop v_TBLT of the signal TBLT on the tracking bit line BLT is used as an estimate of the voltage drop of the signal SBL on the bit line BL of the memory matrix 116.

[0035] The BLT circuit 104 is configured to detect the drop in the voltage v_TBLT of the TBLT signal on the tracking bit line BLT. In some embodiments, the BLT circuit 104 includes a comparator (not shown) configured to compare the voltage v_TBLT of the TBLT signal on the tracking bit line BLT with a specified reference voltage. When the voltage v_TBLT reaches the specified reference voltage, the BLT circuit 104 generates a control signal and outputs it to the setting timer 106. In some embodiments, the BLT circuit 104 generates a control signal by changing a logical state of the signal currently being output by the BLT circuit 104 to the setting timer 106.

[0036] Fig. Figure 3 is a time diagram with waveforms according to some embodiments.

[0037] In Fig. Figure 3 shows the waveforms of the different data types during a read cycle and a write cycle in memory cell 206 of memory matrix 116, chosen accordingly. In the read cycle, during a first time instance t1, the WL driver 110(1) drives the word line WL when the rising edge of a read clock signal (not shown) arrives. Accordingly, the voltage v_DW on the signal DW begins to rise from a low voltage to a voltage VDD. Additionally, the TWL driver 110(2) drives the tracking word line TWL when the rising edge of a read clock signal (not shown) arrives. Accordingly, the voltage v_TWL on the tracking word line TWL begins to rise from a low voltage to a voltage VDD.

[0038] Essentially at the same time, i.e., essentially at time instance t1, the setting timer 106 changes the timing control signal TMR from a logic low state to a logic high state. In response, the setting circuit 108(1) and the setting circuit 108(2) are switched on. Specifically, in response to the change from a logic high state of the timing control signal TMR, essentially at the first time instance t1, the NFET N3 is switched on and pulls the voltage v_DW of the signal DW on the word line WL to VSS, thereby limiting the rise of the voltage v_DW to reaching a lower voltage LVDD1, where LVDD1 < VDD, ΔV1 = VDD - LVDD1, and 0 < ΔV1. By switching on the NFET N3, the voltage v_DW of the signal DW is prevented from reaching the voltage VDD by limiting the voltage v_DW, albeit only temporarily, upwards to LVDD1 while the NFET N3 is switched on.As a result, the voltage v_DW of signal DW on word line WL temporarily rises to voltage LVDD1 during the turn-on of NFET N3, but is prevented from rising above this voltage. In response to the change in the logic-high state of the timing control signal TMR, essentially in the first timing instance t1, NFET N4 is also turned on, and it pulls the voltage v_EMU of the emulation signal EMU on the tracking word line TWL to VSS, thus limiting the rise of voltage v_EMU to reaching a lower voltage LVDD2, where LVDD2 < VDD, ΔV2 = VDD - LVDD2, 0 < ΔV2, LVDD2 ≈ LVDD1, and therefore ΔV2 ≈ ΔV1. The value of LVDD2 achievable using the setting circuit 108(2) changes depending on the area in which the setting circuit 108(2) is located (. Fig. 4A to 4C). Switching on NFET N4 prevents the voltage v_EMU of the signal EMU from reaching the voltage VDD by temporarily limiting the voltage v_EMU on LVDD2 while NFET N4 is switched on. As a result, during the read cycle and temporarily while NFET N4 is switched on, the voltage v_EMU on the tracking word line TWL rises to the voltage LVDD2, but is prevented from exceeding it.

[0039] Although the voltage v_DW of the signal DW on the word line WL is temporarily limited to the relatively lower voltage LVDD1, it is sufficient to turn on the pass-gate transistors N13 and N14 of memory cell 206. An advantage of using the voltage LVDD1 instead of VDD to turn on the pass-gate transistors N13 and N14 is that the power consumption during the read operation is reduced compared to a situation where a pendant memory device does not include the setting circuit 108(1). The memory device of the other approach, which does not include a counterpart for the setting circuit 108(2), generates a signal on the pendant tracking word line that has a voltage VDD between the time instances t1 and t2 of the read cycle, i.e.,It generates a voltage discrepancy of magnitude ΔV2 (discrepancy ΔV2) between the signal on the pendant-tracking word line and the signal on the pendant word line between time instances t1 and t2 of the read cycle. The voltage discrepancy ΔV2 that arises in the other approach between time instances t1 and t2 of the read cycle reduces the accuracy of the emulation of the signal on the pendant word line by the pendant-tracking word line. An advantage of using the tuning circuit 108(2) in the storage device 200 is that the emulation of the word line WL by the tracking word line TWL becomes more accurate than with the other approach, since, for example, no voltage discrepancy ΔV2 arises; that is, it is prevented between time instances t1 and t2 of the read cycle.The emulation accuracy of the signal EMU (which is output with the tracking word line TWL) is improved because the voltage v_EMU of the stimulation signal EMU of the tracking word line TWL is temporarily pulled to VSS by means of the setting circuit 108(2) in essentially the same way as the voltage v_DW of the signal DW is temporarily pulled to VSS by means of the setting circuit 108(1).

[0040] As an example, in Fig. Figure 3 assumes that memory node nd1 of memory cell 206 stores a logical one / high and memory node nd2 of memory cell 206 stores a corresponding logical zero / low at the beginning of the read operation. From the first time instance t1, the voltage on bit line BL begins to drop because the logically low value stored in memory node nd1 discharges bit line BL through the switched-on pass-through NFET N13, while the voltage on bit bar line BLB does not drop due to the logically high value stored in memory node nd2. In some embodiments, in response to the rising edge of a read clock (not shown), tracking cell 202 performs a read "0" operation. Fig. 3. The waveform of the signal TBLT on the tracking bit line BLT is similar to the waveform of the signal SBL on the bit line BL of memory cell 206, since, as explained above, the structure and parameters of the tracking cell 202 are essentially the same as those of the memory cell (e.g. 206) in the memory matrix 116.

[0041] In response to a read clock signal (not shown), the bias selector 112 ignores the timing signal TMR. Therefore, the bias selector 112 does not respond to the change in the logic-state timing signal TMR, essentially in the first timing instance t1, from the logic-low state to the logic-high state t1. Rather, the bias selector 112 holds the selection signal SEL in the logic-low state during the read cycle.

[0042] In Fig. 3. From the first time instance t1 to the second time instance t2, the voltage v_DW of the signal DW on the word line WL is limited upwards to the voltage LVDD1. Similarly, from the first time instance t1 to the second time instance t2, the voltage v_EMU of the signal EMU on the tracking word line TWL is limited upwards to the voltage LVDD2.

[0043] As soon as, in the second time instance t2, the BLT circuit 104 detects that the voltage v_TBLT of the signal TBLT on the tracking bit line BLT reaches a defined threshold, the BLT circuit 104 changes the state of the control signal that is currently being output to the setting timer 106. In response to the change in the state of the control signal, the setting timer 106 changes the time control signal TMR from a logic high state to a logic low state. As a result of the time control signal TMR being in the logic low state, and essentially in the second time instance t2, the NFET N3 of the setting circuit 108(1) is switched off. After being switched off, the NFET N3 no longer prevents the voltage v_DW of the signal DW on the word line WL from rising. Thus, the voltage v_DW of the signal DW on the word line WL rises from the voltage LVDD1 to the voltage VDD shortly after the second time instance t2.

[0044] In response to the timing signal TMR being in the logic low state, and essentially during the second time instance t2, the NFET N4 of the setting circuit 108(2) is also switched off. After being switched off, the NFET N4 no longer prevents the voltage v_EMU of the emulation signal EMU on the tracking word line TWL from rising. Thus, the voltage v_EMU of the signal EMU on the tracking word line TWL rises from the voltage LVDD2 to the voltage VDD shortly after the second time instance t2.

[0045] As in Fig. As shown in Figure 3, an advantage of using the adjustment circuit 108(2) in the storage device 200 is that it better prevents read errors. As can be seen from the waveforms representing the corresponding voltages in the storage nodes nd1 and nd2, the use of the adjustment circuits 108(1) and 108(2) reduces and thus better prevents read errors of the voltages in the storage nodes nd1 and nd2.

[0046] After the read cycle and before the write cycle, the voltage v_BL of signal BL on bit line BL and the voltage v_BLB of signal BLB on bit line BLB are each pre-charged to a logically high state. To further develop the example, it is assumed that during the write cycle a logical zero / low is stored / written in memory node nd1 of memory cell 206, and correspondingly a logical one / high is stored / written in memory node nd2 of memory cell 206.

[0047] In Fig. 3. The write cycle begins in a third time instance t3. When the rising edge of a write clock signal (not shown) arrives, the WL driver 110(1) drives the word line WL. Accordingly, the voltage v_DW on the signal DW begins to rise from a low voltage to a voltage VDD. Additionally, the TWL driver 110(2) drives the tracking word line TWL when the rising edge of a write clock signal (not shown) arrives. Accordingly, the voltage v_TWL on the tracking word line TWL begins to rise from a low voltage to the voltage VDD.

[0048] Essentially at the same time, i.e., essentially in the third timing instance t3, the setting timer 106 changes the timing control signal TMR from the logic low state to the logic high state. In response, the setting circuit 108(1) and the setting circuit 108(2) are respectively switched on. In particular, in response to the logic high state of the timing control signal TMR, the NFET N3 is switched on and pulls the voltage v_DW of signal DW on word line WL to VSS, thereby limiting the rise of the voltage v_DW to reaching a lower voltage LVDD1, where LVDD1 < VDD. By switching on the NFET N3, the voltage v_DW of signal DW is prevented from reaching the voltage VDD by limiting the voltage v_DW, albeit only temporarily, to LVDD1 while the NFET N3 is switched on.As a result, the voltage v_DW of signal DW on word line WL temporarily rises to voltage LVDD1 during the turn-on of NFET N3, but it is prevented from rising above this voltage. In response to the logic high state of the timing signal TMR, NFET N4 is also turned on, and it pulls the voltage v_EMU of emulation signal EMU on tracking word line TWL to VSS, thus limiting the rise of voltage v_EMU to reaching the lower voltage LVDD2. Again, LVDD2 ≈ LVDD1, and the value of LVDD2 achievable using tuning circuit 108(2) changes depending on the area in which tuning circuit 108(2) is located. Fig. 4A to 4C). Here too, LVDD2 < VDD, ΔV2 = VDD - LVDD2, 0 < ΔV2, and thus ΔV2 ≈ ΔV1. Turning on NFET N4 prevents the voltage v_EMU of the signal EMU from reaching the voltage VDD by temporarily limiting the voltage v_EMU upwards to LVDD2 while NFET N4 is turning on. Therefore, during the write cycle and temporarily while NFET N4 is turning on, the voltage v_EMU on the tracking word line TWL rises to the voltage LVDD2, but is prevented from exceeding it.

[0049] In response to the write clock signal (not shown), the bias selector 112 stops ignoring the timing signal TMR. In response to the change in the logic high state of the timing signal TMR, essentially in the third timing instance t3, the bias selector 112 changes the selection signal SEL from a logic low state to a logic high state. In response to the change in the selection signal SEL to a logic high state, the multiplexer 114 changes the voltage connected to the supply voltage line CVDD; that is, it disconnects the voltage VDD from the supply voltage line CVDD and instead connects a write support voltage VWA to the supply voltage line CVDD. If the bias selector 112 does not complete the write cycle, it keeps the selection signal SEL in a logic low state.Accordingly, if the multiplexer 114 is not in the write cycle, it is controlled to connect the voltage VDD to the operating voltage line CVDD instead of the write support voltage VWA. The write support voltage VWA is lower than the voltage VDD, i.e., VWA < VDD. By connecting the operating voltage line CVDD to a lower voltage during a write operation, the write operation is performed faster and / or more easily.

[0050] Although the voltage v_DW of the signal DW on the word line WL is temporarily limited upwards to the relatively lower voltage LVDD1, it is sufficient to turn on the pass-gate transistors N13 and N14 of memory cell 206. An advantage of using the voltage LVDD1 instead of VDD to turn on the pass-gate transistors N13 and N14 is that the power consumption during the write operation is reduced compared to a situation where a pendant memory device does not include the setting circuit 108(1). The memory device of the other approach, which does not include a counterpart for the setting circuit 108(2), generates a signal on the pendant tracking word line that has a voltage VDD between the time instances t1 and t2 and t3 and t4 of the write cycle, i.e.,It generates a voltage discrepancy of magnitude ΔV2 (discrepancy ΔV2) between the signal on the pendant-tracking word line and the signal on the pendant word line between time instances t3 and t4 of the write cycle. The voltage discrepancy ΔV2 that arises in the other approach between time instances t3 and t4 of the write cycle reduces the accuracy of the emulation of the signal on the pendant word line by the pendant-tracking word line. An advantage of using the setting circuit 108(2) in the storage device 200 is that the emulation of the word line WL by the tracking word line TWL becomes more accurate than with the other approach, since, for example, no voltage discrepancy ΔV2 arises, i.e., it is prevented between time instances t3 and t4 of the write cycle.The emulation accuracy of the signal EMU (which is output with the tracking word line TWL) is improved because the voltage v_EMU of the stimulation signal EMU of the tracking word line TWL is temporarily pulled to VSS by means of the setting circuit 108(2) in essentially the same way as the voltage v_DW of the signal DW is temporarily pulled to VSS by means of the setting circuit 108(1).

[0051] Let's return to the example. To reset the logical state of memory cell 206 as part of the write cycle, the voltage v_BL of the bit_bar line BLB is set to a logically low state. In some embodiments, the tracking cell 202 performs a read "0" operation in response to the rising edge of the write clock (not shown). Fig. 3 remains the waveform DW of the voltage v_DW of the word line WL up to a fourth time instance t4 on LVDD1.

[0052] As soon as in Fig. In the fourth time instance t4, when the BLT circuit 104 detects that the voltage v_TBLT of the signal TBLT on the tracking bit line BLT has reached the defined threshold, the BLT circuit 104 changes the state of the control signal that is currently being output to the setting timer 106. In response to the change in the state of the control signal, the setting timer 106 changes the timing control signal TMR from a logic high state to a logic low state, essentially in the fourth time instance t4. As a result of the timing control signal TMR being in the logic low state, and essentially in the fourth time instance t4, the NFET N3 of the setting circuit 108(1) is switched off. After being switched off, the NFET N3 no longer prevents the voltage v_DW of the signal DW on the word line WL from rising. Thus, the voltage v_DW of signal DW on word line WL rises from voltage LVDD1 to voltage VDD shortly after the fourth time instance t4.

[0053] In response to the timing signal TMR being in the logic low state, and essentially at the fourth timing instance t4, the NFET N4 of the setting circuit 108(2) is also switched off. After being switched off, the NFET N4 no longer prevents the voltage v_EMU of the emulation signal EMU on the tracking word line TWL from rising. Thus, the voltage v_EMU of the signal EMU on the tracking word line TWL rises from the voltage LVDD2 to the voltage VDD shortly after the fourth timing instance t4.

[0054] Furthermore, in a delayed response to the change of the timing signal TMR from the logic high state to the logic low state, and essentially in a fifth timing instance t5, the bias selector 112 changes the selection signal SEL from a logic high state to a logic low state. The time elapsed between the fourth timing instance t4 and the fifth timing instance t5 is represented by a delay 324. In response to the change to the logic low state of the selection signal SEL, the multiplexer 114 changes the voltage connected to the supply voltage line CVDD; that is, it disconnects the write-support voltage VWA from the supply voltage line CVDD and instead connects the voltage VDD to the supply voltage line CVDD.

[0055] A bias selector N14 is configured to generate two different variants of the selection signal SEL depending on whether the write operation is a high-speed or a low-speed operation.

[0056] In Fig. 3. It is assumed that the write cycle is based on a high-speed SRAM operation. Specifically, if the write operation is performed at a higher speed (and thus has higher power consumption), the bias selector N14 generates a relatively wider / longer variant of the selection signal SEL insofar as the state of the selection signal SEL is changed to the logic high state in the fourth time instance t4. Conversely, if the write operation is performed at a lower speed (and thus has lower power consumption), the bias selector N14 generates a relatively narrower / shorter variant of the selection signal SEL by waiting until the fifth time instance t5 to change the state of the selection signal SEL to the logic high state. This delay in changing the state of the selection signal SEL is in Fig. 3 represented by a phantom / dashed line as a delay 326.

[0057] The Fig. 4A to 4C are corresponding site plans 430A to 430C according to some embodiments.

[0058] In particular, each of the site plans 430A to 430C represents a normal projection of a corresponding storage device onto a reference plane, e.g., a plane defined by the x-axis and the y-axis. The storage device of each of the Fig. 4A to 4C is an example of the storage device 100 from Fig. 1, although some of the components of the storage device 100 in the Fig. 4A to 4C are not shown. Therefore, each of the layout plans 430A to 430C is representative of the corresponding storage device. Structures in the storage devices are represented by patterns (also referred to as configurations) in the layout plans 430A to 430C. For the sake of simplicity, elements in each of the layout plans 430A to 430C are referred to as if they were structures rather than patterns per se. The storage devices corresponding to the layout plans 430A to 430C are examples of storage device 100, storage device 200, or the like.

[0059] Each of the layouts 430A to 430C is arranged in the following non-overlapping areas: a bit cell area 432; a main input / output area (main I / O area) 434A / B / C; a main controller area 436A / B / C; and a word line driver area 438A / B / C. Each area is contiguous and is generally defined by the components / circuits located within it, as will be explained later.

[0060] In the Fig. 4A and Fig. In 4B, the memory matrix 116, the tracking matrix 102, and the BL setting circuit 122 are arranged in the bit cell area 432; the tracking word line TWL is arranged in the main I / O area 434A / B / C; the TWL driver 110(2) and the setting timer 106 are arranged in the main controller area 436A / B / C; and the WL driver 110(1) and the setting circuit 108(1) are arranged in the word line driver area 438A. In contrast, a setting circuit 408(2) is located in a different area in the corresponding Fig. 4A to 4C, wherein the setting circuit 408(2) is an example of the setting circuit 108(2). Normally, the main I / O area 434A / B / C additionally contains I / O components / circuits by means of which the corresponding storage device communicates with other components / circuits that do not have the corresponding storage device. In some embodiments, the main controller area 436A / B / C additionally contains address decoders, e.g., row decoders and column decoders, or the like. In some embodiments, the main controller area 436A / B / C additionally contains read amplifiers or the like. In some embodiments, the main controller area 436A / B / C additionally contains timing circuits other than the setting timer 106. In some embodiments, the BL setting circuit 122 is arranged in the main controller area 436A / B / C.In some embodiments, the BL setting circuit 122 is located in a different area than the bit cell area 432 or the main controller area 436A / B / C.

[0061] In the Fig. 4A and Fig. 4B, the adjustment circuit 408(2) is arranged in another of the non-overlapping regions, where the adjustment circuit 408(2) is an example of the adjustment circuit 108(2). The value of the voltage LVDD2 achievable using the adjustment circuit 408(2) changes depending on the region in which the adjustment circuit 408(2) is arranged.

[0062] In the site plan 430A of Fig. 4A, the setting circuit 408(2) is arranged in the main controller area 436A in addition to the TWL driver 110(2) and the setting timer 106. Therefore, in Fig. 4A the setting circuit 408(2) and a setting circuit 408(1) are not arranged in the same area.

[0063] In the site plan 430B of Fig. 4B, the setting circuit 408(2) is arranged in addition to the tracking word line TWL in the main I / O area 434B. Therefore, in Fig. 4B the setting circuit 408(2) and the setting circuit 408(1) are not arranged in the same area, while the setting circuit 408(2) and the tracking word line TWL are arranged in the same area, namely in the main I / O area 434B.

[0064] In the site plan 430C of Fig. 4C, the setting circuit 408(2) is arranged in addition to the WL driver 110(1) and the setting circuit 408(1) in the word line driver area 438C. Therefore, in Fig. 4C the setting circuit 408(2) and the setting circuit 408(1) are arranged in the same area, namely in the word line driver area 438C.

[0065] It should be noted that the voltage LVDD2 is a maximum value of the voltage v_DW of the signal DW ( Fig. 2 and Fig. 3) on the word line WL ( Fig. 2) is, which is activated by the WL driver 110(1), and that in general a lower value of LVDD2 enables lower energy consumption of the corresponding storage device. The value of LVDD2 achievable using the setting circuit 408(2) changes partly depending on the area in which the setting circuit 408(2) is located ( Fig. 4A to 4C). The value of LVDD2, which corresponds to site plan 430C of Fig. The value of LVDD2 (LVDD2_430C) is lower than the value of LVDD2, which corresponds to the location plan 430B. Fig. 4B is reachable (LVDD2_430B), such that LVDD2_430C < LVDD2_430B. The value of LVDD2, which corresponds to site plan 430B of Fig. The value 4B is achievable is lower than the value of LVDD2, which corresponds to site plan 430A from Fig. 4A is reachable (LVDD2_430A), so LVDD2_430B < LVDD2_430A. Overall, LVDD2_430C < LVDD2_430B < LVDD2_430A.

[0066] Since LVDD2_430B < LVDD2_430A, the energy consumption of the storage device with site plan 430B (pw_430B) is lower than the energy consumption of the storage device with site plan 430A (pw_430A), so pw_430B < pw_430A. Since LVDD2_430C < LVDD2_430B, the energy consumption of the storage device with site plan 430C (pw_430C) is lower than the energy consumption of the storage device with site plan 430B (pw_430B), so pw_430C < pw_430B. Overall, pw_430C < pw_430B < pw_430A.

[0067] Bearing in mind that ΔV2 = VDD - LVDD2, the value of ΔV2, which is derived from site plan 430A, is Fig. 4A is reachable (ΔV2_430A), smaller than the value of ΔV2, which corresponds to the site plan 430B from Fig. 4B is reachable (ΔV2_430B), such that ΔV2_430A < ΔV2_430B. The value of ΔV2, which corresponds to the site plan 430B of Fig. 4B is reachable, is smaller than the value of ΔV2, which is determined using site plan 430C from Fig. 4C is achievable (ΔV2_430C), such that ΔV2_430B < ΔV2_430C. Overall, ΔV2_430A < ΔV2_430B < ΔV2_430C.

[0068] Fig. 4D is a layout diagram of part 454 of a storage device according to some embodiments.

[0069] The semiconductor device, whose layout diagram of Fig. Figure 4D, which shows part 454 (represented by wavy lines 455), is in particular a storage device. Examples of the storage device whose layout diagram shows part 454 are storage device 100 of Fig. 1, the storage device 200 of Fig. 2, the storage devices 430A to 430C of the corresponding Fig. 4A to 4C or the like.

[0070] In general, a layout diagram represents a semiconductor device. Entities in the layout diagram represent corresponding components within the semiconductor device. The layout diagram itself is a top view. Entities in the layout diagram are two-dimensional with respect to, for example, the x- and y-axes, while the depicted semiconductor device is three-dimensional. Typically, the semiconductor device is organized with respect to the z-axis as a stack of layers in which corresponding structures are arranged. Accordingly, each entity in the layout diagram specifically represents a component within a corresponding layer of the corresponding semiconductor device. The layout diagram typically represents a relative depth, i.e.,Positions along the z-axis of structures, and thus of layers, are represented by placing a second structure on top of a first structure in such a way that the second structure at least partially overlaps the first. For the sake of clarity, i.e., as an aid to the discussion, some elements are shown in the layout diagram of [the diagram]. Fig. 4D is described as if it were a counterpart structure in a corresponding semiconductor device, rather than a structure / organization per se. For example, an element 460(2) is referred to as a gate structure 460(2) rather than a gate pattern 460(2).

[0071] Layout diagrams vary in terms of the level of detail they depict. For example, selected layers of a layout diagram may be combined into a single layer for simplification. Alternatively and / or additionally, not all layers or components of the corresponding semiconductor device may be shown; that is, selected layers of the layout diagram may be omitted, for example, for the sake of clarity. For instance, in Fig. 4D through-hole plating M1 structures (V1 structures), M2 segments in a third metallization layer (M2 layer) or the like.

[0072] In Fig. 4D has a layer 575(1) in an active region (AR) ( Fig. 5A and Fig. 5B), represented by part 454 of the storage device, ARs 456B and 458B extend in a first direction, e.g., parallel to the x-axis. AR 456B has a first conductivity type, and AR 458B has a second conductivity type. In Fig. In 4D, it is assumed that the first conductivity type is a positive conductivity (p-type conductivity), corresponding to PMOS transistors, and the second conductivity type is a negative conductivity (n-type conductivity), corresponding to NMOS transistors. Alternatively, in some embodiments, the first conductivity type is an n-type conductivity, and the second conductivity type is a p-type conductivity.

[0073] In Fig. 4D has 575(4) in a gate and MD layer (GMD layer) ( Fig. 5A and Fig. 5B) Part 454 of the storage device further comprises gate structures 460(1) to 460(4) and metal drain / source structures (MD structures) 462(1) to 462(6) extending in a second direction perpendicular to the first direction, e.g., parallel to the y-axis. In some embodiments, the first and second directions are Cartesian axes that are not parallel to the x-axis and y-axis, respectively. The gate structures 460(2) and 460(3) are substantially collinear. The MD structures 462(1) and 462(2), the MD structures 462(3) and 462(4), and the MD structures 462(5) and 462(6) are also substantially collinear. With respect to the x-axis, the positions of gate structures 460(x) alternate with MD structures 462(x). For example, with respect to the x-axis, gate structure 460(1) is located between (A) the essentially collinear MD structures 462(1) and 462(2) and (B) the essentially collinear MD structures 462(3) and 462(4).The essentially collinear MD structures 462(3) and 462(4) are, for example, arranged between (A) the gate structure 460(1) and (B) the essentially collinear gate structures 460(2) and 460(3).

[0074] In Fig. 4D exhibits 575(5) in a VGD layer ( Fig. 5A and Fig. 5B) above the GMD layer 575(4), part 454 of the memory device further comprises via-hole gate structures (VG structures) 464 and via-hole MD structures 466 (VD structures) 466 corresponding to the gate structures 460(1) to 460(4) and the MD structures 462(1) to 462(6). Part 454 of the memory device is arranged as a grid containing reference lines designated as alpha traces α1, α2, α3, α4, α5, and α6, extending in a direction parallel to the x-axis. With respect to the y-axis, the VG structures 464 and the VD structures 466 are aligned corresponding to the alpha traces α1 to α6. For example, an instance of the VG structure 464 under a Mo segment 468(9) is aligned to the alpha conductor α3, an instance of the VD structure 466 under a Mo segment 468(12) is aligned to the alpha conductor α5, or the like.In part 454 of the storage device, neither an instance of the VG structure 464 nor an instance of the VD structure 466 is arranged above the alpha conductor α1.

[0075] In Fig. 4D exhibits 575(4) in a first metallization layer (M*1st layer) ( Fig. 5A and Fig. 5B) above the VGD layer 575(5), part 454 of the storage device further includes M*1-th segments 468(1) to 468(13) extending parallel to the x-axis, aligned with the alpha traces α1 to α6, and thus located above a corresponding VG structure 464 and VD structure 466. With respect to the y-axis, a distance between adjacent alpha traces is an instance of a unit of measurement called a trace spacing (TP).

[0076] In Fig. 4D is assumed to have a naming rule in which the M*1-th layer is a metallization layer zero (Mo) and, accordingly, a first compound layer (VIA*1-th layer) is a compound layer zero (Vo). Accordingly, the M*1-th segments 468(1) to 468(13) are M0 468(1) to 468(13). In some embodiments, depending on the naming rule of the corresponding process node, where part 454 of the storage device is the Fig. 4C, Fig. 5A and Fig. 5B corresponds to the M*1th layer being a metallization layer one (M1), and correspondingly the VIA*1th layer is a compound layer one (V1).

[0077] With respect to the x-axis, gate structures 460(1) to 460(4) are separated from each other by a uniform distance. Fig. 4D represents the uniform distance as a contacted poly spacing (CPP) for the corresponding semiconductor process technology node. Here, the term "poly" in the phrase "contacted poly spacing (CPP)" does not necessarily mean that the gate structures in the semiconductor devices corresponding to it are Fig. 4D based, must be made from polysilicon, but "poly" represents a historical convenience, i.e., "poly" is used because gate structures in ICs manufactured according to a predecessor semiconductor process technology node were usually made from polysilicon.

[0078] In Fig. 4D part 454 also has a first interconnect layer (VIA*1st layer) 575(5) ( Fig. 5A and Fig. 5B), which is here designated as Vo layer 575(5) according to the adopted naming rule and which is arranged above Mo layer 575(4). In Vo layer 575(5), part 454 further features instances of a via-M*1-th structure (VIA*1-th structure), i.e., a via-Mo structure (Vo structure) 470, above corresponding Mo segments 468(9), 468(10), and 468(13). With respect to the y-axis, the Vo structures 470 are essentially aligned with the longitudinal axes of the corresponding Mo segments 468(9), 468(10), and 468(13).

[0079] Part 454 also has a second metallization layer (M*2-th layer) 575(6) ( Fig. 5A and Fig. 5B), which, according to the assumed naming rule, is designated here as an M1 layer 575(6) and is arranged above the Vo layer 575(5). In the M1 layer 575(6), part 454 further has M*2-th segments, i.e., M1 segments 472(1) and 472(2), which extend parallel to the y-axis and are arranged above corresponding Vo structures 470.

[0080] Among other things, the NFET N4 ( Fig. 2 and 4A to 4C) are shown in part 454. The NFET N4 is connected between the Mo segment 468(12), which carries the emulation signal EMU ( Fig. 2 and Fig. 3) is connected, and the Mo segment 468(13) is switched, which is connected to the voltage VSS ( Fig. 2) is connected. The gate terminal of NFET N4 is connected to the M1 segment 472(1), which in turn is connected to the timing signal TMR ( Fig. 2 and Fig. 3) is connected.

[0081] The Fig. 5A and Fig. 5B are corresponding cross-sections 574A and 574B of part 454 of Fig. 4C, according to some embodiments.

[0082] Cross sections 574A and 574B follow a similar naming scheme to that of the layout diagram of part 454 of Fig. 4C. Although some components are similar, they are nevertheless different. To aid in the identification of components that are similar but still have differences, numbers from the 5 series are used for the naming rule for cross-sections 574A and 574B, while in Fig. 4C numbers from the 4-series are used. For example, the MD structure corresponds to 562(4) in the Fig. 5A and Fig. 5B of the MD structure 462(4) of Fig. 4C, where the similarity is indicated by _62(4) and the differences are reflected in the corresponding leading digit (5 or 4). For the sake of brevity, the discussion focuses more on the differences between the Fig. 5A, Fig. 5B and Fig. 4C as in the similarities.

[0083] In Fig. 5A corresponds to the cross-section 574A of a section line 5A - 5A' of Fig. 4C. In Fig. 5B corresponds to the cross-section 574B of a section line 5B - 5B' of Fig. 4C. Each of the Fig. 5A and Fig. 5B contains layers 575(1) to 575(6).

[0084] In each of the Fig. 5A and Fig. 5B has AR layer 575(1) and AR 558. In each of the Fig. 5A and Fig. 5B has the GMD layer 575(3), a gate structure 560(3), and MD structures 562(4) and 562(6). In Fig. 5A has VGD layer 575(3) containing an instance of VG structure 564 and an instance of VD structure 566. In Fig. 5B has an instance of the VD structure 566 in VGD layer 575(3). Fig. 5A contains the Mo layer 574(4) and Mo segments 568(9) and 568(10). In Fig. 5B contains the Mo layer 574(4) and a Mo segment 568(12). In Fig. In 5A, Vo layer 575(5) contains an instance of Vo structure 570, and M1 layer 575(6) contains M1 segments 572(1) and 572(2). Fig. 5B contains the M1 layer 575(6) and the M1 segment 572(2).

[0085] Fig. Figure 6A is a flowchart 600 of a method for manufacturing a storage device according to some embodiments.

[0086] The process of flowchart 600 can, in some embodiments, for example, be combined with an EDA system 800 (EDA: electronic design automation), which will be described later with reference to Fig. 8 is discussed, and an IC manufacturing system 900 (which is later referred to in reference to Fig. 9 is discussed) are implemented. Examples of a semiconductor device that can be manufactured according to the procedure of flowchart 600 are the semiconductor devices of the Fig. 1 and Fig. 2, which are shown on the site plans of the Fig. 4A to 4C based; semiconductor devices based on the layout diagrams disclosed herein; semiconductor devices based on the cross-sections disclosed herein, or the like.

[0087] In Fig. Section 6 comprises the process of flowchart 600 blocks 602 and 604. In block 602, a layout diagram is generated, which is, among other things, one or more of the layout diagrams disclosed herein or the like. According to some embodiments, block 602 can, for example, be combined with the one described later with reference to Fig. The EDA system 800 discussed in section 8 will be implemented. The process continues from block 602 to block 604.

[0088] In block 604, based on the layout diagram, at least one of the following steps is performed: (A) performing one or more photolithographic exposures; (B) fabricating one or more semiconductor masks; and (C) fabricating one or more components in a layer of a semiconductor device. See the discussion below of IC Fabrication System 900 with reference to Fig. 9.

[0089] Fig. 6B is a flowchart 605 of a method for manufacturing a semiconductor device and in particular a storage device, according to some embodiments.

[0090] Flowchart 605 is an example for block 604 of Fig. 6A. Flowchart 605 comprises blocks 606 to 622. The process of flowchart 605 can, in some embodiments, for example, be implemented using the IC manufacturing system 900 (which is described later with reference to Fig. 9 is discussed) are carried out. Examples of a semiconductor device that can be manufactured according to the procedure of flowchart 605 are the semiconductor devices of Fig. 1 and Fig. 2, which are shown on the site plans of the Fig. 4A to 4C based; semiconductor devices based on the layout diagrams disclosed herein; semiconductor devices based on the cross-sections disclosed herein, or the like.

[0091] In Fig. In block 6B, 606 active regions (ARs) are created in a substrate by doping corresponding areas of the substrate. Examples of active regions are ARs 456 and 458 of Fig. 4D, the AR 558 of the Fig. 5A and Fig. 5B, or something similar. From block 606, the process continues to block 608.

[0092] In block 608, source / drain regions (S / D regions), representing first transistor components (TCs), are created in the ARs by doping corresponding first regions of the active areas. Second regions of the ARs, located between corresponding S / D regions, are channel regions representing second TCs. Examples of S / D regions are parts of AR 558 corresponding to MD structures 562(4) and 562(6). Fig. 5A and Fig. 5B, or the like. Examples of channel sections are parts of AR 558 between the aforementioned exemplary S / D sections, or the like. From block 609, the process continues to block 610.

[0093] In block 610, gate structures representing third TCs are fabricated in a GMD layer over corresponding active regions and, in particular, over corresponding channel areas. An example of the GMD layer is GMD layer 575(2) of the Fig. 5A and Fig. 5B. Examples of the gate structures are gate structures 460(1) to 460(4) of Fig. 4D, the gate structure 560(3) of the Fig. 5A and Fig. 5B, or something similar. From block 610, the process continues to block 612.

[0094] In block 612, metal S / D contact structures (MD contact structures), representing fourth TCs, are fabricated in the GMD layer over corresponding S / D regions. Examples of the MD contact structures are MD structures 462(1) to 462(6) of Fig. 4D, the MD contact structures 562(4) and 564(6) of the Fig. 5A and Fig. 5B, or something similar. From block 612, the process continues to block 614.

[0095] In block 614, through-hole gate / MD structures (VGD structures) are fabricated over corresponding gate structures and MD contact structures. The VGD structures comprise two types: through-hole gate structures (VG structures) and through-hole MD structures (VD structures). Examples of VG structures are instances of VG structure 464. Fig. 4D, the VG structure 564 of Fig. 5A, or the like. Examples of the VD structure of the VGD structure are the instances of VD structure 466 of the Fig. 4B to 4D, the VD structure 566 of the Fig. 5A and Fig. 5B, or something similar. From block 614, the process continues to block 616.

[0096] With respect to a normal projection of the storage device (which is produced by the process of flowchart 605) onto a reference plane, the storage device is arranged in non-overlapping areas that represent a bit cell range (e.g. 432 of the Fig. 4A to 4C), a main I / O area (e.g. 434A / B / C of the corresponding Fig. 4A to 4C), a main controller area (e.g. 436A / B / C of the corresponding Fig. 4A to 4C) and a word line driver section (e.g. 438A / B / C of the corresponding Fig. 4A to 4C).

[0097] In Fig. In some embodiments, the creation of the active regions in block 606, the creation of the S / D regions and the corresponding channel regions in block 608, the fabrication of the gate structures in block 610, the fabrication of the MD contact structures in block 612, and the fabrication of the VGD structures in block 614 result in VGD structures that electrically connect corresponding groups of the first to fourth transistor components as follows: a first group as a first matrix (e.g., 116) of memory cells (e.g., 206) in the bit cell region (e.g., 432 of the Fig. 4A to 4C); a second group as a second matrix (e.g. 102) of tracking cells (e.g. 202) in the bit cell area (e.g. 432 of the Fig. 4A to 4C), configured to emulate the first matrix (e.g., 116); a third group as a first tuning circuit (e.g., 122) in the word line driver area (e.g., 438x); a fourth group as a second tuning circuit [e.g., 108(2)] in one of the non-overlapping areas other than the bit cell area (e.g., 432); and a fifth group as a tuning timer (e.g., 106) in the main controller area (e.g., 436x), each connected to the first tuning circuit [e.g., 108(1)] and the second tuning circuit [e.g., 108(2)].

[0098] In block 616, metallization segments are produced in corresponding metallization layers, and connection structures are produced in corresponding connection layers based on an interlocking layer. Examples of metallization layers will be discussed later. An example of the connection layers will be discussed later. In block 616, the process continues to block 618.

[0099] In block 618, M*1-th metallization segments are produced in a first metallization layer over corresponding instances of the VGD structures. An example of the first metallization layer is the Mo layer 575(4) of the Fig. 5A and Fig. 5B, or the like. Examples of the M*1-th metallization segments are the Mo segments 468(1) to 468(13) of Fig. 4C, Fig. 568(9) and Fig. 568(10) of Fig. 5A, Fig. 568(12) of Fig. 5B, or something similar. From block 618, the process continues to block 620.

[0100] In block 620, V*1-th compound structures are fabricated in a first compound layer and over corresponding M*1-th metallization segments. An example of the first compound layer is the Vo layer 575(5) of the Fig. 5A and Fig. 5B, or the like. Examples of the V*1-th connection structures are instances of the Vo structure 470 in Fig. 4C, the V0 structure 570 in Fig. 5B, or something similar. From block 620, the process continues to block 622.

[0101] In block 622, M*2-th metallization segments are produced in a second metallization layer over corresponding instances of the VGD structures. An example of the second metallization layer is the M1 layer 575(6) of the Fig. 5A and Fig. 5B, or the like. Examples of the M*2-th metallization segments are the M1 segments 472(1) and 472(2) of Fig. 4C, Fig. 572(1) and Fig. 572(2) of Fig. 5A and Fig. 5B, or something similar.

[0102] In some embodiments, the following is created by producing the metallization segments and the connection structures in block 616: a first word line (e.g., a word line WL) in the bit cell area (e.g., 432 of the Fig. 4A to 4C), which is connected to some memory cells (e.g., 206) in a corresponding row of a first matrix (e.g., 116) and to tracking cells (e.g., 202); a bit line (e.g., a bit line BL) which is connected to some of the memory cells (e.g., 206) in a corresponding column of the first matrix (e.g., 116); and a second word line (e.g., the tracking word line TWL) in the main I / O area (e.g., 434A / B / C of the corresponding Fig. 4A to 4C), which is configured to emulate the first word line (e.g., the word line WL). In some embodiments, a fourth group representing the second setting circuit [108(2)] is located in the main controller area (436A). In some embodiments, the fourth group representing the second setting circuit [108(2)] is located in the main I / O area (434B). In some embodiments, the fourth group representing the second setting circuit [108(2)] is located in the word line driver area (438C).

[0103] In some embodiments, the following are electrically connected by the fabrication of the metallization segments and the connection structures: the first tuning circuit (e.g. 122) between the second word line (e.g. the tracking word line TWL) and the bit line (e.g. BL); the second tuning circuit [e.g. 108(2)] with the second word line (e.g. TWL); and the tuning timer (e.g. 106) with each of the second tuning circuits [e.g. 108(2)].

[0104] Fig. Figure 7 is a flowchart 700 of a method for operating a storage device according to some embodiments.

[0105] Examples of storage devices that operate according to Flowchart 700 are the storage devices of the Fig. 1, 2, 4A to 4C or the like.

[0106] Flowchart 700 comprises blocks 702 to 718. In block 702, an active edge of a trigger signal is received at the word line driver and the setting timer. Examples of the trigger signal are the read clock signal or the write clock signal, which are discussed in the section on Fig. 3 have been mentioned, or the like. From block 702, the sequence continues to block 704.

[0107] In block 704, a first voltage on a first word line is increased to a first reference voltage. An example of the first word line is word line WL of the Fig. 1 and Fig. 2 or the like. An example of the first voltage is the voltage v_DW of the signal DW on the word line WL, which is discussed in the discussion of Fig. 3 has been mentioned, or the like. An example of the first reference voltage is VDD, which is discussed in section 3. Fig. 3 has been mentioned, or something similar. From block 704, the sequence continues to block 706.

[0108] In block 706, a second voltage on a second word line is increased to the first reference voltage. An example of the second word line is the tracking word line (TWL) of the... Fig. 1 and Fig. 2 or the like. An example of the second voltage is the voltage v_EMU of the signal EMU on the tracking word line TWL, which is discussed in the discussion of Fig. 3 has been mentioned, or something similar. From block 706, the sequence continues to block 708.

[0109] In block 708, the first voltage is prevented from reaching, essentially, the first reference voltage. Block 708 includes a block 710. An example of the first voltage is the voltage v_DW of signal DW on word line WL of the Fig. 1, 2, 4A to 4C or the like. Block 710 provides an example of preventing the first voltage from reaching the first reference voltage by switching on a first adjustment circuit. An example of the first adjustment circuit is adjustment circuit 108(1) of the Fig. 1, 2, 4A to 4C or the like, which has a pull-down transistor NFET N3. When NFET N3 is switched on, it pulls the voltage v_DW of the signal DW on the word line WL up to the reference voltage VSS, which is a more concrete example of preventing the first voltage from nearly reaching the first reference voltage. In block 710, the sequence leaves block 708 and continues to block 712.

[0110] In block 712, the second voltage is prevented from essentially reaching the first reference voltage. An example of the second voltage is the voltage v_EMU of the signal EMU on the word line TWL of the Fig. 1, 2, 4A to 4C or the like. Block 712 contains a block 714. A second adjustment circuit is switched on in block 714. An example of preventing the second voltage from reaching the first reference voltage is switching on a second adjustment circuit. An example of the second adjustment circuit is adjustment circuit 108(2) of the Fig. 1, 2, 4A to 4C or the like, which has a pull-down transistor NFET N4. When NFET N4 is switched on, it pulls the voltage v_EMU of the signal EMU on the tracking word line TWL up to the reference voltage VSS, which is a more concrete example of preventing the second voltage from nearly reaching the first reference voltage. In block 714, the sequence leaves block 712 and continues to block 716.

[0111] Block 716 detects a condition indicating that a third voltage on a first bit line has reached a defined value. An example of this third voltage is the voltage v_TBLT of the signal TBLT on the tracking bit line TBLT. Fig. 2 or the like. An example of detecting that the third voltage on the first bit line has reached the specified value is the operation of the BLT circuit 104 of the Fig. 1 and Fig. 2 or the like. From block 716, the process continues to block 718.

[0112] In block 718, each of the first and second setting circuits is switched off. Bearing in mind that examples of the first and second setting circuits are corresponding setting circuits 108(1) and 108(2) of the Fig. 1, 2 and 4A to 4C or the like are examples of each of the first and second setting circuits in the discussion of Fig. 3 have been mentioned, which concern the second time instance t2 and the fourth time instance t4 or the like.

[0113] In some embodiments, blocks 702 to 718 are executed as part of a read operation. An example of a read operation is, for instance, in connection with Fig. 3 for the first time instance t1 and the second time instance t2 or the like. In some embodiments, blocks 702 to 718 are executed as part of a write operation. An example of a write operation is, for instance, in connection with Fig. 3 for the third time instance t3, the fourth time instance t4 and the fifth time instance t5 or the like has been discussed.

[0114] In some embodiments where blocks 702 to 718 are executed as part of a write operation, the method further comprises the following: after receiving the active edge of the trigger signal for the write operation, applying a write setting voltage VWA (e.g., a voltage VWA of the Fig. 2 and Fig. 3) as a positive supply voltage CVDD for the first matrix (e.g., 116), such that CVDD = VWA. In these embodiments, the write-setting voltage VWA is less than a reference supply voltage VDD for a larger system containing the first matrix (e.g., 116), where VWA < VDD and CVDD < VDD. In these embodiments, where blocks 702 to 718 are executed as part of a write operation, the method further comprises: at a specified time after the application of the write-setting voltage VWA, applying the reference supply voltage VDD as the positive supply voltage CVDD, such that CVDD = VDD.

[0115] In these embodiments, where blocks 702 to 718 are executed as part of a write operation, the method further comprises the following: after receiving an active edge of a trigger signal for the write operation, controlling a multiplexer (e.g., 114 of the Fig. 1, 2 and 4A to 4C) so that it selects the write setting voltage VWA as the positive supply voltage CVDD instead of the reference supply voltage VDD.

[0116] Fig. Figure 8 is a block diagram of an EDA system 800 (EDA: electronic design automation) according to some embodiments.

[0117] In some embodiments, the EDA system 800 includes an APR system (APR: automatic placement and tracing). In some embodiments, the EDA system 800 is a general-purpose computing device with a hardware processor 802 and a non-volatile, machine-readable storage medium 804. The storage medium 804 is encoded, among other things, with computer program code 806; that is, it stores the computer program code 806, i.e., the set of executable instructions. According to one or more embodiments, the execution of the instructions 806 is performed (at least partially) by the hardware processor 802 using an EDA tool that implements some or all of the following methods: the method of Fig. 6 (Block 602); Methods for generating layout diagrams; Methods for generating layout diagrams corresponding to block diagrams; or the like (hereinafter: “the specified processes and / or methods”). The storage medium 804 stores, among other things, layout diagrams 811, such as the layout diagrams disclosed herein or the like.

[0118] The processor 802 is electrically connected to the machine-readable storage medium 804 via a bus 808. The processor 802 is also electrically connected to an I / O interface 810 via the bus 808. Furthermore, a network interface 812 is electrically connected to the processor 802 via the bus 808. The network interface 812 is connected to a network 814, enabling the processor 802 and the machine-readable storage medium 804 to connect to external elements via the network 814. The processor 802 is configured to execute the computer program code 806, which is encoded in the machine-readable storage medium 804, so that the system 800 can be used to perform some or all of the specified processes and / or procedures.In one or more embodiments, the 802 processor is a main processor (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC) and / or a suitable processing unit.

[0119] In one or more embodiments, the machine-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device). The machine-readable storage medium 804 is, for example, a semiconductor or solid-state memory, a magnetic tape, a removable disk, a random-access memory (RAM), a solid-state memory (ROM), a rigid magnetic disk, and / or an optical disk. In one or more embodiments in which optical disks are used, the machine-readable storage medium 804 is a compact disc read-only memory (CD-ROM), a compact disc read / write (CD-R / W), and / or a digital video disk (DVD).

[0120] In one or more embodiments, the storage medium 804 stores computer program code 806 configured such that the system 800 (where processing is at least partially carried out by the EDA tool) can be used to perform some or all of the specified processes and / or procedures. In one or more embodiments, the storage medium 804 also stores information enabling the performance of some or all of the specified processes and / or procedures. In one or more embodiments, the storage medium 804 stores a library 807 of standard cells, including the standard cells disclosed herein. In some embodiments, the storage medium 804 stores one or more layout diagrams 811.

[0121] The EDA system 800 has an I / O interface 810. The I / O interface 810 is connected to external circuitry. In one or more embodiments, the I / O interface 810 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor keys for sending information and commands to the processor 802.

[0122] The EDA System 800 also features the Network Interface 812, which is connected to the Processor 802. The Network Interface 812 allows the System 800 to communicate with the Network 814, to which one or more other computer systems are connected. The Network Interface 812 is a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA, or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the specified processes and / or procedures are implemented in two or more Systems 800.

[0123] The System 800 is configured to receive information via the I / O interface 810. The information received via the I / O interface 810 includes commands, data, design rules, libraries of standard cells, and / or other parameters for processing by the Processor 802. This information is sent to the Processor 802 via the bus 808. The EDA System 800 is also configured to receive user interface (UI) information via the I / O interface 810. This information is stored on the machine-readable medium 804 as a UI 842.

[0124] In some embodiments, some or all of the specified processes and / or procedures are implemented as an independent software application for execution by a processor. In some embodiments, some or all of the specified processes and / or procedures are implemented as a software application that is part of another software application. In some embodiments, some or all of the specified processes and / or procedures are implemented as a plug-in for a software application. In some embodiments, at least one of the specified processes and / or procedures is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the specified processes and / or procedures are implemented as a software application used by the EDA System 800. In some embodiments, a layout containing standard cells is created using a tool such as VIRTUOSO.® , which is supplied by CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0125] In some embodiments, the processes are implemented as functions of a program stored in a non-volatile, machine-readable recording medium. Examples of non-volatile, machine-readable recording media include external / removable and / or internal / built-in storage units, such as an optical disc like a DVD, a magnetic disk like a hard drive, a semiconductor memory like a ROM, RAM, and / or a memory card, or the like.

[0126] Fig. Figure 9 is a block diagram of an IC manufacturing system 900 and an associated IC manufacturing process according to some embodiments.

[0127] Based on the one in block 602 of Fig. The layout diagram generated by 6A implements the IC manufacturing system 900 block 604. Fig. 6A, in which (A) one or more semiconductor masks and / or (B) at least one component in a layer of an unfinished integrated semiconductor circuit are manufactured using the 900 manufacturing system.

[0128] In Fig. Figure 9 comprises the IC manufacturing system 900 units, such as a design house 920, a mask house 930, and an IC manufacturer (“microchip factory”) 950, which interact with each other in the design, development, and manufacturing cycles and / or in the services associated with the manufacture of an IC device 960. The units in the system 900 are connected by a communication network. In some embodiments, the communication network is a single network. In other embodiments, the communication network comprises many different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each unit interacts with one or more of the other units, providing services to and / or receiving services from one or more of the other units.In some embodiments, two or more of the units Design House 920, Mask House 930, and IC Factory 950 are owned by a single larger company. In some embodiments, two or more of the units Design House 920, Mask House 930, and IC Factory 950 exist side-by-side in a shared facility and utilize common resources.

[0129] Design House (or Design Team) 920 creates an IC design layout 922. The IC design layout 922 contains various geometric structures designed for an IC device 960. These geometric structures correspond to structures of metal, oxide, or semiconductor layers that form the various components of the IC device 960 to be manufactured. The different layers together form various IC structural elements. For example, part of the IC design layout 922 includes various IC structural elements, such as an active region, a gate electrode, a source and a drain, metal traces or vias of an interlayer connection, and openings for bond pads to be fabricated in a semiconductor substrate (such as a silicon wafer) and various material layers arranged on the semiconductor substrate.Source / drain areas can, depending on the context, individually or collectively designate a source or a drain. Design House 920 implements a suitable design process for generating the IC design layout 922. This design process includes a logic design, a physical design, or placement and routing. The IC design layout 922 is represented in one or more data files containing information about the geometric structures. For example, the IC design layout 922 is represented in a GDSII or DFII file format.

[0130] In the mask house 930, data preparation 932 and mask fabrication 934 are performed. The mask house 930 uses the IC design layout 922 to fabricate one or more masks 935, which are to be used for fabricating the various layers of the IC device 960 according to the IC design layout 922. The mask house 930 performs data preparation 932, in which the IC design layout 922 is translated into a representative data file (RDF). During mask data preparation 932, the RDF is made available for mask fabrication 934. A mask writer is used in mask fabrication 934. The mask writer converts the RDF into an image on a substrate, such as a mask (reticule) or a semiconductor wafer. The design layout is manipulated during mask data preparation 932 so that it corresponds to certain properties of the mask writer and / or meets the requirements of the IC factory 950. In Fig.Figure 9 shows the mask data preparation 932, the mask production 934, and the mask 935 as separate elements. In some embodiments, the mask data preparation 932 and the mask production 934 can be referred to collectively as mask data preparation.

[0131] In some embodiments, the mask data preparation 932 includes optical proximity correction (OPC), for which lithographic enhancement methods are used to compensate for image defects such as those that may arise from diffraction, interference, other process effects, and the like. The IC design layout 922 is adapted by the OPC. In some embodiments, the mask data preparation 932 includes further resolution enhancement methods (RET), such as off-axis exposure, partial resolution support elements, phase-shift masks, other suitable methods, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats the OPC as an inverse imaging problem.

[0132] In some embodiments, during mask data preparation 932, a mask rule checker (MRC) verifies the IC design layout 922, which has undergone processes in the OPC, against a set of mask generation rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to accommodate variability in semiconductor manufacturing processes and the like. To comply with the mask generation rules, in some embodiments the MRC modifies the IC design layout 922 to compensate for constraints encountered during mask fabrication 934 that may undo some of the modifications performed by the OPC.

[0133] In some embodiments, the mask data preparation 932 includes a lithography process check (LPC) that simulates the machining operations implemented by the IC factory 950 to manufacture the IC fixture 960. In the LPC, this machining is simulated based on the IC design layout 922 to produce a simulated manufactured fixture, such as the IC fixture 960. The machining parameters in the LPC simulation may include: parameters associated with various processes of the IC manufacturing cycle; parameters associated with tools used to manufacture ICs; and / or other aspects of the manufacturing process. The LPC considers various factors, such as intermediate image contrast, depth of field (DOF), mask defect improvement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, if, after the fabrication of a simulated manufactured device by LPC, the simulated device deviates too far from compliance with the design rules in terms of shape, the OPC and / or the MRC must be repeated to further improve the IC design layout 922.

[0134] The preceding description of the mask data preparation 932 has been simplified for clarity. In some embodiments, the mask data preparation 932 includes further elements, such as a logical operation (LOP), to modify the IC design layout 922 according to the manufacturing rules. Furthermore, the processes used for the IC design layout 922 during the mask data preparation 932 can be performed in many different sequences.

[0135] Following mask data preparation 932 and during mask fabrication 934, a mask 935 or a group of masks 935 is fabricated based on the modified IC design layout 922. In some embodiments, an electron beam or a multi-electron-beam mechanism is used to generate a structure on a mask (photomask or reticule) based on the modified IC design layout 922. The masks are fabricated using various technologies. In some embodiments, the mask is fabricated using binary technology. In some embodiments, a mask structure has opaque and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose a photosensitive material layer (e.g., photoresist) deposited on a wafer, is blocked by the opaque region and passes through the transparent regions.In one example, a binary mask has a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chromium) applied to the opaque areas of the mask. In another example, the mask is fabricated using phase-shift technology. In a phase-shift mask (PSM), various elements in the structure created on the mask are configured to have a phase difference suitable for improving resolution and image quality. In various examples, the phase-shift mask is either a mask with a reduced phase shift or a mask with a variable phase shift. The masks produced by the 934 mask fabrication process are used in many different processes.Such masks are used, for example, in an ion implantation process to create different doped areas in the semiconductor wafer, in an etching process to create different etched areas in the semiconductor wafer and / or in other suitable processes.

[0136] IC Factory 950 is an IC manufacturing company that has one or more production facilities for manufacturing many different IC products. In some embodiments, IC Factory 950 is a semiconductor manufacturing facility. For example, there might be one production facility for the front-end manufacturing of multiple IC products [front-end-of-line manufacturing (FEOL manufacturing)], while a second production facility might handle the back-end manufacturing for connecting and packaging the IC products [back-end-of-line manufacturing (BEOL manufacturing)], and a third production facility might provide other services for the manufacturing operation.

[0137] In IC Factory 950, one or more masks 935 produced by Mask House 930 are used to manufacture IC Device 960 using manufacturing tools 952. Thus, IC Factory 950 uses, at least indirectly, the IC design layout 922 to manufacture IC Device 960. In some embodiments, a semiconductor wafer 953 is produced by IC Factory 950 using one or more masks 935 to manufacture IC Device 960. The semiconductor wafer 953 has a silicon substrate or other suitable substrate on which layers of material are produced. The semiconductor wafer 953 further has one or more different doped regions, dielectric structural elements, multi-layer interconnects, and the like (which are produced in later manufacturing steps).

[0138] In some embodiments, a storage device comprises: a first matrix of memory cells; a second matrix of tracking cells, the second matrix being configured to emulate the first matrix; a first word line connected to corresponding memory cells in a corresponding number of rows of the first matrix and to the tracking cells; a second word line configured to emulate the first word line; a first tuning circuit connected to the first word line; a second tuning circuit connected to the second word line; and a tuning timer connected to the second tuning circuit.

[0139] In some embodiments, the second tuning circuit is configured to selectively reduce a voltage level of the second word line based on a signal from the tuning timer.

[0140] In some embodiments, the second tuning circuit includes a metal oxide semiconductor field-effect transistor (MOSFET) with a negative channel (NFET) that is connected between the second word line and a node of the storage device with a low reference voltage.

[0141] In some embodiments, with respect to a normal projection of the memory device onto a reference plane, the memory device is arranged in different regions comprising a matrix region, a main input / output region (main I / O region), a main controller region, and a word line driver region. The first matrix of memory cells, a majority of the first word line, and the second matrix are each located in the matrix region; a majority of the second word line is located in the main I / O region; and the first setting circuitry is located in the word line driver region.

[0142] In some embodiments, the second setting circuit is located in the main controller area.

[0143] In some embodiments, the second setting circuit is located in the main I / O area.

[0144] In some embodiments, the second setting circuit is located in the word line driver area.

[0145] In some embodiments, the first tuning circuit is configured to selectively reduce a voltage level of the first word line based on a signal from the tuning timer, and the tuning timer is also connected to the first tuning circuit.

[0146] In some embodiments, the second setting circuit is still configured to exhibit essentially the same operating profile as the first setting circuit.

[0147] In some embodiments, with respect to a normal projection of the storage device onto a reference plane, the storage device is arranged in corresponding areas that do not overlap, and the first and second setting circuits are arranged in one and the same area of ​​the areas.

[0148] In some embodiments, with respect to a normal projection of the storage device onto a reference plane, the storage device is arranged in corresponding areas that do not overlap, and the first and second setting circuits are not arranged in the same area.

[0149] In some embodiments, the first tuning circuit includes a metal oxide semiconductor field-effect transistor (MOSFET) with a negative channel (NFET) that is connected between the first word line and a node of the storage device with a low reference voltage.

[0150] In some embodiments, the storage device also has a third setting circuit that is connected to the first word line.

[0151] In some embodiments, the third setting circuit is configured to set a voltage on the tracking bit line based on a voltage on the second word line.

[0152] In some embodiments, a method (for operating a storage device) comprises the following: increasing a first voltage on a first word line to a first reference voltage, wherein the first word line is connected to a first matrix of memory cells as well as to some of the memory cells in a corresponding number of rows of the first matrix; increasing a second voltage on a second word line to the first reference voltage; hindering the first voltage on the first word line so that it does not substantially reach the first reference voltage; and hindering the second voltage on the second word line so that it does not substantially reach the first reference voltage.

[0153] In some embodiments, the method is part of a read operation or a write operation of the memory cells.

[0154] In some embodiments, the hindrance of the second voltage begins substantially at the same time as the hindrance of the first voltage, and the method further comprises: (1) after the first voltage has been hindranced but before the increase of the first voltage is completed, terminating the hindrance of the first voltage; and (2) after the second voltage has been hindranced but before the increase of the second voltage is completed, terminating the hindrance of the second voltage, the terminating of the hindrance of the second voltage beginning substantially at the same time as the terminating of the hindrance of the first voltage.

[0155] In some embodiments, the method further comprises receiving an active edge of a trigger signal at a word line driver and at a tuning timer, wherein the trigger signal is a signal to trigger a read operation or a write operation, wherein, after receiving the active edge of the trigger signal, blocking the first voltage comprises turning on a first tuning circuit connected to the first word line, and, after receiving the active edge of the trigger signal, blocking the second voltage comprises turning on a second tuning circuit connected to the second word line.

[0156] In some embodiments, the method further comprises detecting that a third voltage on a first bit line reaches a specified value, wherein the first bit line is connected to tracking cells of a second matrix, wherein in response to the third voltage reaching the specified value, hindering the first voltage includes turning off the first tuning circuit and hindering the second voltage includes turning off the second tuning circuit.

[0157] In some embodiments, turning on the first setting circuit includes the following: using a metal oxide semiconductor field-effect transistor (MOSFET) with a negative channel (NFET) connected between the first word line and a node of the storage device with a low reference voltage to prevent the first voltage on the first word line from substantially reaching the first reference voltage.

[0158] In some embodiments, turning on the second tuning circuit includes the following: using a negative channel MOSFET (NFET) connected between the second word line and the node of the storage device with a low reference voltage to prevent the second voltage on the second word line from substantially reaching the first reference voltage.

[0159] In some embodiments, the method will be performed as part of a write operation of the memory cells, the method further comprising: after receiving an active edge of a trigger signal for the write operation, applying a write setting voltage VWA as a positive supply voltage CVDD for the first matrix such that CVDD = VWA, wherein the write setting voltage VWA is less than a reference supply voltage VDD for a larger system containing the first matrix, where VWA < VDD and CVDD < VDD.

[0160] In some embodiments, the method further includes the following: at a specified time after the application of the write setting voltage VWA, applying the reference supply voltage VDD as the positive supply voltage CVDD, such that CVDD = VDD.

[0161] In some embodiments, applying the write setting voltage VWA as a positive supply voltage CVDD includes the following: after receiving the active edge of the trigger signal for the write operation, controlling a multiplexer so that it selects the write setting voltage VWA as the positive supply voltage CVDD instead of the reference supply voltage VDD.

[0162] In some embodiments, applying the write setting voltage VWA as a positive supply voltage CVDD includes the following: at a specified time after controlling the multiplexer to select the write setting voltage VWA, controlling the multiplexer to select the reference supply voltage VDD as the positive supply voltage CVDD instead of the write setting voltage VWA.

[0163] In some embodiments, a method (for fabricating a storage device) comprises the following: creating active regions in a substrate; creating, in the active regions, source / drain regions (S / D regions) as first transistor components, wherein regions of the active regions between corresponding S / D regions are channel regions representing second transistor components; creating, across corresponding channel regions, gate structures as third transistor components; creating, across corresponding S / D regions, metal S / D contact structures (MD contact structures) as fourth transistor components; and creating, across corresponding gate structures and MD contact structures, through-hole gate / MD structures (VGD structures) as fifth transistor components.With respect to a normal projection of the memory device onto a reference plane, the memory device is arranged in non-overlapping regions comprising a bit cell region, a main input / output region (main I / O region), a main controller region, and a word line driver region. The VGD structures electrically connect corresponding groups of the first through fourth transistor components as follows: a first group as a first matrix of memory cells in the bit cell region; a second group as a second matrix of tracking cells in the bit cell region, configured to emulate the first matrix; a third group as a first tuning circuit in one of the non-overlapping regions other than the bit cell region; and a fourth group as a tuning timer in the main controller region, connected to the first tuning circuit.The method further comprises fabricating metallization segments in corresponding metallization layers and interconnection structures in corresponding interconnection layers based on an interlocking layer corresponding to the first through fourth groups, whereby the fabrication of the metallization segments and interconnection structures results in: a first word line in the bit cell area, which is connected to some of the memory cells in a corresponding number of rows of the first matrix and to the tracking cells; and a second word line in the main I / O area, which is configured to emulate the first word line. The fabrication of the metallization segments and interconnection structures electrically connects the first tuning circuit to the second word line, and the tuning timer is electrically connected to the first tuning circuit.

[0164] In some embodiments, the third group, which represents the first setting circuit, is located in the main controller area.

[0165] In some embodiments, the third group, which represents the first setting circuit, is located in the main I / O area.

[0166] In some embodiments, the third group, which represents the first setting circuit, is located in the word line driver area.

[0167] A person skilled in the art should readily recognize that one or more of the disclosed embodiments offer one or more of the aforementioned advantages. After reading the foregoing patent description, a person skilled in the art should be able to implement various modifications, substitutions of equivalents, and various other embodiments that have been outlined herein. Therefore, the protection granted thereon is to be limited only by the definitions contained in the appended claims and their equivalents. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] AR 456B

[0072] AR 458B

[0072]

Claims

[1] Storage device with: a first matrix of memory cells; a second matrix of tracking cells, the second matrix configured to emulate the first matrix; a first word line connected to corresponding ones of the memory cells in a corresponding one of the rows of the first matrix and to the tracking cells; a second word line configured to emulate the first word line; a first setting circuit connected to the first word line; a second setting circuit connected to the second word line; and a setting timer connected to the second setting circuit. [2] The memory device of claim 1, wherein the second adjustment circuit is configured to selectively reduce a voltage level of the second word line based on a signal from the adjustment timer. [3] A storage device according to claim 1 or 2, wherein With respect to a normal projection of the memory device onto a reference plane, the memory device is arranged in different regions comprising a matrix region, a main input / output region (main I / O region), a main controller region and a word line driver region, the first matrix of memory cells, a majority of the first word line and the second matrix are each arranged in the matrix area, a majority of the second word line is arranged in the main I / O area, and the first setting circuit is arranged in the word line driver region. [4] The memory device according to claim 3, wherein the second setting circuit is arranged in the main controller area. [5] The semiconductor device according to claim 3, wherein the second adjustment circuit is arranged in the main I / O area. [6] The memory device according to claim 3, wherein the second adjustment circuit is arranged in the word line driver region. [7] A semiconductor device according to any one of the preceding claims, wherein the first adjustment circuit is configured to selectively reduce a voltage level of the first word line based on a signal from the adjustment timer, and the setting timer is also connected to the first setting circuit. [8] The memory device of any preceding claim, wherein the second adjustment circuit is further configured to exhibit substantially the same operating profile as that of the first adjustment circuit. [9] Storage device according to one of the preceding claims, wherein with respect to a normal projection of the storage device onto a reference plane, the storage device is arranged in corresponding regions which do not overlap each other, and the first and second adjustment circuits are arranged in one and the same area of ​​the areas. [10] A storage device according to any one of claims 1 to 8, wherein With respect to a normal projection of the storage device onto a reference plane, the storage device is arranged in corresponding regions which do not overlap each other, and the first and second adjustment circuits are not arranged in one and the same area of ​​the areas. [11] A storage device according to any one of the preceding claims, further comprising: a third adjustment circuit connected between the second word line and a tracking bit line, the tracking bit line being connected to some of the tracking cells in the second matrix. [12] The memory device of claim 11, wherein the third adjustment circuit is configured to adjust a voltage on the tracking bit line based on a voltage on the second word line. [13] A method of operating a memory device, comprising: Increasing a first voltage on a first word line to a first reference voltage, the first word line being connected to a first matrix of memory cells and to some of the memory cells in a corresponding one of rows of the first matrix; Increasing a second voltage on a second word line to the first reference voltage; Preventing the first voltage on the first word line from reaching the first reference voltage; and Obstructing the second voltage on the second word line from substantially reaching the first reference voltage. [14] The method of claim 13, wherein the obstruction of the second voltage begins at substantially the same time as the obstruction of the first voltage, and the procedure further includes: after the first voltage has been impeded but before the increase of the first voltage is completed, terminating the impeding of the first voltage; and after the second voltage has been inhibited but before the increasing of the second voltage is completed, ceasing the inhibiting of the second voltage, wherein ceasing the inhibiting of the second voltage begins at substantially the same time as ceasing the inhibiting of the first voltage. [15] A method according to claim 13 or 14, further comprising: Receiving an active edge of a trigger signal at a word line driver and at a set timer, wherein the trigger signal is a signal for triggering a read operation or a write operation, wherein after receiving the active edge of the trigger signal, hindering the first voltage comprises turning on a first adjustment circuit connected to the first word line, and after receiving the active edge of the trigger signal, hindering the second voltage comprises turning on a second adjustment circuit connected to the second word line. [16] The method of claim 15, further comprising: Detecting that a third voltage on a tracking bit line reaches a specified value, the tracking bit line being connected to tracking cells of a second matrix, wherein in response to the third voltage reaching the specified value, inhibiting the first voltage comprises turning off the first adjustment circuit and inhibiting the second voltage comprises turning off the second adjustment circuit. [17] A method of manufacturing a memory device, comprising: Creating active regions in a substrate; Creating, in the active regions, source / drain (S / D) regions as first transistor components, wherein portions of the active regions between corresponding S / D regions are channel regions representing second transistor components; Fabricating, over corresponding ones of the channel regions, gate structures as third transistor components; Producing, over corresponding ones of the S / D regions, metal S / D contact structures (MD contact structures) as fourth transistor components; and Producing, over corresponding ones of the gate structures and the MD contact structures, through-hole gate / MD structures (VGD structures) as fifth transistor components, wherein with respect to a normal projection of the memory device onto a reference plane, the memory device is arranged in non-overlapping regions comprising a bit cell region, a main input / output region (main I / O region), a main controller region, and a word line driver region, and the VGD structures electrically connect corresponding groups of the first to fourth transistor components as follows: a first group as a first matrix of memory cells in the bit cell area, a second group as a second matrix of tracking cells in the bit cell area configured to emulate the first matrix, a third group as a first setting circuit in a non-overlapping area other than the bit cell area, and a fourth group as a setting timer, in the main controller area, which is connected to the first setting circuit; and Producing metallization segments in corresponding metallization layers and connecting structures in corresponding connecting layers on the basis of an interlocked layer correspondingly over the first to fourth groups, wherein By producing the metallization segments and the connecting structures, the following is created: a first word line in the bit cell area connected to some of the memory cells in a corresponding one of rows of the first matrix and to the tracking cells, and a second word line in the main I / O area configured to emulate the first word line, and by producing the metallization segments and the connecting structures, the first setting circuit is electrically connected to the second word line and the setting timer is electrically connected to the first setting circuit. [18] The method of claim 17, wherein the third group representing the first adjustment circuit is arranged in the main controller area. [19] The method of claim 17, wherein the third group representing the first adjustment circuit is arranged in the main I / O area. [20] The method of claim 17, wherein the third group representing the first adjustment circuit is arranged in the word line driver region.

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