Semiconductor Device and Method

Abstract

One embodiment comprises a method that includes forming a first interconnect structure over a first substrate, wherein the first interconnect structure comprises dielectric layers and metallization structures therein. The method further comprises forming a redistribution via and a redistribution pad over the first interconnect structure, wherein the redistribution via and the redistribution pad are electrically connected to at least one of the metallization structures of the first interconnect structure, and wherein the redistribution via and the redistribution pad have the same material composition. The method further comprises forming a dielectric distortion control layer over the redistribution pad.The method further comprises forming a bond via and a bond pad over the redistribution pad, wherein the bond pad is located in the dielectric distortion control layer, and wherein the bond via is electrically connected to the redistribution pad.

Description

CLAIM PRIORITY AND CROSS REFERENCESThis application claims priority to U.S. Provisional Application No. 63 / 584,562 filed Sep. 22, 2023 and U.S. Provisional Application No. 63 / 607,843 filed Dec. 8, 2023, which applications are hereby incorporated by reference herein.BACKGROUNDThe semiconductor industry has experienced rapid growth due to progressive improvements in integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). The improvement in integration density largely resulted from a repeated reduction in minimum element size, allowing more components to be integrated into a given area. With the increasing demand for smaller and smaller electronic devices, a need has arisen for smaller and more conservative packaging techniques for semiconductor dies. An example of such packaging systems is package-on-package (PoP) technology. In a PoP device, an upper semiconductor package is stacked on a lower semiconductor package, which provides a high degree of integration and component density. The PoP technology generally enables the manufacture of semiconductor devices with improved functionality and low footprint on a printed circuit board (PCB).BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read with the accompanying drawings. It is noted that, according to the usual industry practice, various elements are not drawn to scale. Indeed, for clarity of description, the dimensions of the various elements may be arbitrarily increased or decreased.FIGS. 1-25 show cross-sectional views of intermediate stages in the formation of a package, in accordance with some embodiments. FIG. 26 illustrates a cross-sectional view of an intermediate stage in the formation of a package, in accordance with some embodiments. FIG. 27 illustrates a cross-sectional view of an intermediate stage in the formation of a package, in accordance with some embodiments.FIGS. 28A, 28B, 28C, and 28D illustrate cross-sectional views of bond redistribution structures, in accordance with some embodiments.FIGS. 29A, 29B, 29C, and 29D illustrate cross-sectional views of bond redistribution structures, in accordance with some embodiments.FIGS. 30A and 30B illustrate cross-sectional views of bond redistribution structures, in accordance with some embodiments.FIGS. 31A, 31B, 31C, and 31D illustrate cross-sectional views of bond redistribution structures, in accordance with some embodiments.FIGS. 32A and 32B illustrate cross-sectional views of bond redistribution structures, in accordance with some embodiments.FIGS. 33A and 33B illustrate cross-sectional views of bond redistribution structures, in accordance with some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples to implement various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, in the following description, forming a first element over or on a second element may cover embodiments in which the first and second elements are formed in direct contact, and may also cover embodiments in which additional elements may be formed between the first and second elements, such that the first and second elements need not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.Further, spatially relative terms such as "bottom," "below," "lower," "above," "upper," and the like, may be used herein for convenience of description to describe the relationship of an element or portion with one or more other elements or portions as shown in the figures. The spatially relative terms are intended to cover various orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be otherwise (rotated 90 degrees or oriented in another orientation) oriented and the spatially relative terms used herein may also be interpreted as such.Embodiments described herein may be described in a particular context, namely a redistribution structure that may be incorporated into a device (e.g., a chip or die) or package (e.g., as a chip-on-wafer (CoW) package structure or a wafer-on-wafer (WoW) package structure. The redistribution structure includes a redistribution via and line having a planar top surface to allow a smaller center distance and minimum distance between adjacent redistribution lines and bond pads as well as bond pad vias (vias). In some embodiments, redistribution via and line are formed in a same process, such as a dual damascene process. In some embodiments, warpage layers and bonding layers having high elastic modulus and high thermal conductivity are formed over the redistribution line and improve warpage control and heat dissipation. In addition, the ratio of the thickness of the bond pad vias to the bond pads is less than in conventional bond pad vias and bond pads. This lower thickness ratio improves the electrical and thermal conductivity of the structure.Moreover, the teachings of this disclosure are applicable to all redistribution structures where a flat top surface of a redistribution via and / or redistribution pad may reduce the minimum pitch of the redistribution structures. Other embodiments contemplate other applications, such as other package types or other configurations, which would be readily apparent to those skilled in the art upon reading this disclosure. It should be noted that the embodiments described herein do not necessarily show all components or elements that may be present in a structure. For example, multiples of a component may be omitted from a figure, such as where the description of one of the components is sufficient to convey aspects of the embodiment. Moreover, method embodiments described herein may be described as being performed in a particular order; however, other method embodiments may be performed in any logical order.FIGS. 1-26 show cross-sectional views of intermediate stages in forming a package, in accordance with some embodiments.FIG. 1 shows a cross-sectional view of an integrated circuit die 20 in accordance with some embodiments. The integrated circuit die 20 is packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 20 may be a logic die (e.g., a central processing unit (CPU), a graphics unit (GPU), a system on a chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory die (DRAM die), a static random access memory die (SRAM die), etc.), a power management die (e.g., a power management integrated circuit (PMIC die) die, a radio frequency (RF die), a sensor die, a microsystem die (MEMS die), a signal processing die (e.g., a digital signal processing die (DSP die)), a front-end die (e.g., an analog front-end die (AFE die)), the like, or combinations thereof.The integrated circuit die 20 may be formed in a wafer that may have various device regions that are singulated in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 20 may be processed according to suitable manufacturing processes to form integrated circuits. For example, integrated circuit die 20 includes a substrate 22, such as doped or undoped silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. The substrate 22 may include other semiconductor materials such as germanium; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates may also be used, for example multilayer or gradient substrates. The substrate 22 has an active surface (e.g., the upward surface in FIG. 1 ), sometimes referred to as a front side, and an inactive surface (e.g., the downward surface in FIG. 1 ), sometimes referred to as a back side.Devices (not shown) may be formed on the front side of the substrate 22. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc., or a combination thereof. Overlying the front side of the substrate 22 is an interlayer dielectric (ILD) (not shown separately). The ILD surrounds and may cover the devices. The ILD may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.Conductive plugs (not separately shown) extend through the ILD for electrically and physically connecting the devices. For example, if the devices are transistors, the conductive plugs may connect the gates and source / drain regions of the transistors. The conductive plugs may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, or the like, or combinations thereof. An interconnect structure 24 is located over the ILD and the conductive plugs. The interconnect structure 24 connects the devices to form an integrated circuit. The interconnect structure 24 may be formed, for example, by metallization structures in dielectric layers on the ILD. The metallization structures include metal lines and vias (vias) formed in one or more low-k dielectric layers. The metallization patterns of the interconnect structure 24 are electrically connected to the devices by the conductive plugs. The metallization structures may be formed using any suitable process, such as a single damascene process, a dual damascene process, a plating process, combinations thereof, or the like.As shown in FIG. 2, after the interconnect structure 24 is formed, a mask 30 is formed and patterned on the interconnect structure 24. In some embodiments, the mask 30 is made of a photoresist and may be formed by spin coating or the like and exposed to light for patterning. The pattern of the photoresist corresponds to an upper portion of the subsequently formed through silicon via (TSV) 44 (see, for example, FIG. 6 ). The patterning forms at least one opening through the photoresist 30 exposing the interconnect structure 24. In some embodiments, a stop layer (not shown), such as a chemical mechanical polishing (CMP) stop layer, is deposited over a top surface of the interconnect structure 24 prior to the mask 30. The CMP stop layer may be used to prevent too much material from being removed during a subsequent CMP process by being resistant to the subsequent CMP process and / or by providing a recognizable stop point for the subsequent CMP process. In some embodiments, the CMP stop layer may include one or more layers of dielectrics. Suitable dielectrics may include oxides (such as silicon oxide, aluminum oxide, or the like), nitrides (such as SiN or the like), oxynitrides (such as SiON or the like), oxycarbides (such as SiOC or the like), carbonitrides (such as SiCN or the like), carbides (such as SiC or the like), combinations thereof, or the like, and may be formed using spin coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or the like, or a combination thereof.In FIG. 3, the remaining mask 30 is used as a mask during an etching process to remove exposed and underlying portions of the one or more dielectric layers of the interconnect structure 24 and the substrate 22. A single etching process may be used to etch an opening 34 in the interconnect structure 24 and the substrate 22, or a first etching process may be used to etch the interconnect structure 24 and a second etching process may be used to etch the substrate 22. In some embodiments, the opening 34 is formed with a plasma dry etch process or a reactive ion etch (RIE) process, such as a deep RIE (DRIE) process. In some embodiments, the DRIE process includes one or more etch cycles and one or more passivation cycles, where the one or more etch cycles use SF 6 for example, and the one or more passivation cycles use C 4 F 8. for example. The use of a DRIE process with one or more etch cycles and one or more passivation cycles enables a highly anisotropic etch process. In some embodiments, the one or more etching processes may be any suitable etching process, for example, wet or dry etching.As shown in FIG. 4, the photoresist 30 is removed after the opening 34 is formed. The photoresist 30 may be removed by a suitable ashing or stripping process, for example, using an oxygen plasma or the like.Further, in FIG. 4, a liner layer 38 is conformally deposited on the interconnect structure 24 and on the bottom surface and sidewalls of the opening 34. In some embodiments, the liner layer 38 includes one or more layers of dielectrics and may be used to physically and electrically isolate the subsequently formed vias (vias) from the substrate 22. Suitable dielectrics may include oxides (such as silicon oxide, aluminum oxide, or the like), nitrides (such as SiN or the like), oxynitrides (such as SiON or the like), combinations thereof, or the like. The liner layer 38 may be formed using CVD, PECVD, ALD, or the like, or a combination thereof.As shown in FIG. 4, in a subsequent step, a seed layer 40 is formed over the liner layer 38. In some embodiments, the seed layer 40 is a metal layer that may be a single layer or a composite layer that includes multiple sub-layers formed from different materials. In some embodiments, the seed layer 40 includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. In some embodiments, a barrier layer (not shown) may be formed on the liner layer 38 prior to forming the seed layer 40. The barrier layer may include Ti, TiN, the like, or a combination thereof.In FIG. 5, a conductive material 42 is formed on the seed layer 40 and in the openings 34. The conductive material 42 may be formed by plating such as electroplating, such as electrochemical plating, electroless plating, or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like.After the conductive material 42 is formed, a anneal process is performed. The annealing process may be performed to prevent subsequent extrusion of the conductive material from the TSV 44 (sometimes referred to as TSV pumps). TSV pumping is caused by a coefficient of thermal expansion (CTE) mismatch of the conductive material 42 and the substrate 22, and may result in damage to structures (e.g., metallization structures) over the TSV.Following the annealing process, a planarization process is performed to remove portions of the conductive material 42, the seed layer 40, and the liner layer 38 outside of the openings 34 so that a TSV 44 is formed, as shown in FIG. 6. The top surfaces of the TSV 44 and the top dielectric layer of the interconnect structure 24 are coplanar within process variations after the planarization process. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, or the like. The upper portion of the TSV 44 (formed in the interconnect structure 24) has a greater width than the lower portion of the TSV 44 (formed in the substrate 22).Referring to FIG. 7, an interconnect structure 50 is formed over the structure of FIG. 6. The interconnect structure 50 includes dielectric layers 52, metallization structures and vias (vias) 54, and a top metal 56. More or fewer dielectric layers and metallization structures and vias may be formed than shown in FIG. 7. The interconnect structure 50 is connected to the interconnect structure 24 and the TSV 44 through the metallization structures and vias formed in the one or more dielectric layers 52. The metallization patterns and vias may be formed with processes and materials similar to the interconnect structure 24, and the description will not be repeated here. In some embodiments, there is more than one layer of the top metal 56, for example two layers of the top metal.In some embodiments, the dielectric layers 52 are made of a same material as the dielectric layers of the interconnect structure 24, e.g., a low-k dielectric. In further embodiments, the dielectric layers 52 are formed of a silicon-containing oxide (which may or may not contain oxygen). For example, the dielectric layers 52 may include an oxide such as silicon oxide, a nitride such as silicon nitride, or the like.The metallization structures and vias 54 and the top metal 56 may be formed using any suitable process, such as a single damascene process, a dual damascene process, a plating process, combinations thereof, or the like. An example of forming metallization structures and vias 54 and top metal 56 by a damascene process includes etching dielectric layers 52 to form openings, depositing a conductive barrier layer in the openings, plating with a metallic material such as copper or copper alloy, and performing planarization to remove the excess portions of the metallic material. In further embodiments, the formation of the dielectric layers 52, metallization patterns and vias 54, and the top metal 56 may include forming the dielectric layer 52, patterning the dielectric layer 52 to form openings, forming a metal seed layer (not shown), forming a patterned plating mask (such as photoresist) that covers some portions of the metal seed layer while leaving other portions exposed, plating the metallization patterns and vias 54 and the top metal 56, removing the plating mask, and etching unwanted portions of the metal seed layer. The metallization structures and vias 54 and the top metal 56 may be made of tungsten, cobalt, nickel, copper, silver, gold, aluminum, or the like, or combinations thereof. In some embodiments, the top metal 56 is thicker than the metallization patterns 54, for example three times as thick, five times as thick, or it has any suitable thickness ratio over the metallization layers.FIG. 7 further illustrates the formation of a passivation layer 58 over the dielectric layers 52. In some embodiments, the passivation layer 58 may be made of a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), or the like; or a combination thereof. The dielectric layer 58 may be formed by, for example, spin coating, lamination, chemical vapor deposition (CVD), or the like. The passivation layer 58 may have a top surface that is substantially planar within process variations.In FIG. 8, openings 59 are formed through the passivation layer and expose surfaces of the top metal 56. The openings may be formed by any suitable process, such as an etching process.In FIG. 9, a seed layer 60 is formed over the passivation layer 58, in the openings 59, and on exposed portions of the top metal 56 in the openings 59. In some embodiments, the seed layer 60 is a metal layer, which may be a single layer or a composite layer having multiple sub-layers formed of different materials. In some embodiments, the seed layer 60 includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using PVD or the like, for example. In some embodiments, a barrier layer (not shown) may be formed prior to forming the seed layer 60. The barrier layer may include Ti, TiN, the like, or a combination thereof.In FIG. 10, a photoresist 62 is formed over the seed layer 60 and patterned. The photoresist 62 may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to redistribution pads 66 (see FIG. 12 ).In FIG. 11, a conductive material 64 is formed on the seed layer 60 exposed in the openings of the photoresist 62. The conductive material 42 is formed on the seed layer 60 and fills the via openings 59. the conductive material 42 may be formed by plating such as electroplating, such as electrochemical plating, electroless plating, or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. In some embodiments, the electroplating process is a bottom-up plating process that results in a planar top surface of the conductive material 64.In FIG. 12, the photoresist 62 and the underlying portion of the seed layer 60 are removed so that redistribution pads and vias (vias) 66 are formed. The photoresist 62 may be removed by a suitable ashing or stripping process, for example, using an oxygen plasma or the like. The portions of the seed layer 60 may be removed by a suitable etching process. Since the top surfaces of the passivation layer 58 are flat, the top surface of the redistribution pad 66 is also flat. Because the top surface of redistribution pad 66 is flat, bonding vias and bond pads overlying the pad may be formed directly over the redistribution via and have a reduced minimum center-to-center distance.In FIG. 13, a dielectric layer 68 is formed over the passivation layer 58 and redistribution pads 66. In some embodiments, the dielectric layer 68 is a conformal layer. The dielectric layer 68 may serve as an etch stop for the subsequently formed bond via via via openings (see, e.g., FIG. 17 ) and may be considered an etch stop or via definition layer 68. In some embodiments, the dielectric layer 68 is comprised of a silicon-containing layer. For example, the dielectric layer 68 may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, or the like, or a combination thereof.In FIG. 14, a dielectric layer 70 is formed over the dielectric layer 68. The dielectric layer 70 provides a planar top surface on which the subsequent layers (see, for example, FIG. 15 ) are formed and may be considered a planarization dielectric layer 70. In some embodiments, the dielectric layer 70 is comprised of a silicon-containing layer. For example, the dielectric layer 70 may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, or the like, or a combination thereof. In some embodiments, the dielectric layer 70 has a different material composition than the dielectric layer 68, such that the dielectric layer 68 may be more easily detected during an etching process that etches through the dielectric layers 70 and 68. For example, the dielectric layer 68 may be formed of silicon nitride and the dielectric layer 70 may be formed of silicon oxide.In FIG. 15, dielectric layers 72 and 74 are formed over dielectric layer 70. The dielectric layer 72 may serve for warpage control and may be regarded as a warpage control layer 72. The dielectric layer 74 may serve for dielectric bonding and may be considered as a dielectric bonding layer 74.In some embodiments, the warp control layer 72 and the bonding dielectric layer 74 may be formed of a material having a high modulus of elasticity and a high thermal conductivity. In some embodiments, high elastic modulus materials have an elastic modulus of over 100 gigapascals (GPa). In some embodiments, high thermal conductivity materials have a thermal conductivity greater than 2 watts per meter-kelvin (W / mK). High elastic modulus, high thermal conductivity materials include materials such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, silicon oxycarbide, and the like, or combinations and sub-layers thereof.In some embodiments, the dielectric layer 72 has a different material composition than the dielectric layer 70, such that the dielectric layer 70 may be more easily detected during an etching process that etches through the dielectric layers 74 and 72. Although FIG. 15 shows three dielectric layers 70, 72, and 74, more or less than three dielectric layers may be formed (see, e.g., FIGS. 29A-D ).By the presence of the warping layers and bonding layers with high modulus of elasticity and high thermal conductivity, the warping control and the heat dissipation of the structure are improved.FIGS. 16-19 show the formation of bond pad vias 86 and bond pads 88 in the dielectric layers 70, 72, and 74, Bond pad vias 86 and bond pads 88 may be formed using any suitable process, such as a single damascene process, a dual damascene process, combinations thereof, or the like. Figs. 16 to 19 show a dual damascene process.In FIG. 16, openings 78 are in the dielectric layers 74 and 72. In some embodiments, a photoresist (not shown) is formed and patterned on the dielectric layer 74. The photoresist may be formed by spin coating or the like and exposed to light for patterning. The pattern of the photoresist corresponds to the openings 78 for the bond pads 88 (see FIG. 19 ). Further, in FIG. 16, the dielectric layers 74 and 72 are patterned to form the openings 78, using the patterned photoresist as a mask, and the patterning process on the dielectric layer 72 continues. The dielectric layer 70 serves to stop the etching process for the openings 78. The exposed portions of the dielectric layer 74 may be removed, for example, by using a suitable etching process, such as wet and / or dry etching.FIG. 17 illustrates the patterning of the dielectric layer 70. the photoresist may be removed by a suitable ashing or stripping process, for example, using an oxygen plasma or the like. A new photoresist (not shown) may be formed and patterned on the patterned dielectric layer 74 and at least partially in the opening 78. The photoresist may be formed by spin coating or the like and exposed to light for patterning. The pattern of the photoresist corresponds to the openings 80 for the bond pad vias 86 (see FIG. 19 ). Further, in FIG. 17, the dielectric layer 70 is patterned to form the openings 80 using the patterned photoresist as a mask, exposing portions of the redistribution pad 66 through the patterning process. The exposed portions of the dielectric layer 70 may be removed, for example, by using a suitable etching process, such as wet and / or dry etching.FIG. 18 illustrates the formation of a barrier layer 84 in the openings 78 and 80. In some embodiments, the barrier layer 84 may include Ti, TiN, the like, or a combination thereof. The barrier layer 84 may be formed in the openings before the bond pad vias 86 and bond pads 88 are formed.In FIG. 19, bond pad vias 86 and bond pads 88 may be formed on barrier layer 84 in openings 78 and 80. Bond pad vias 86 and bond pads 88 may be formed by processes and materials similar to metallization structures and vias 54 and redistribution vias and pads 66, and the description will not be repeated herein. The bond pads 88 may be formed of or include copper, for example. Adjacent bond pads 88 have a center-to-center pitch P 1. In some embodiments, the center-to-center distance P 1 is only 3.0 μm. In some embodiments, the center-to-center distance P 1 is in a range of 3.0 μm to 5.4 μm. According to certain embodiments where the bond vias and bond pads are formed directly over (e.g., overlap) redistribution via 66, adjacent redistribution and bond structures may have a smaller minimum center-to-center distance.The top surfaces of the bond pads 88 are coplanar with the top surface of the uppermost dielectric layer 74. planarization is achieved by a chemical mechanical polishing (CMP) process or a mechanical grinding process.As shown in FIG. 20, the integrated circuit die 20 is thinned by thinning the substrate 22 before the subsequent dicing process. The thinning may be performed by a planarization process such as a mechanical grinding process or a CMP process. The thinning process exposes the TSV 44 and the liner 38. After thinning, the TSV 44 establishes an electrical connection from a back side of the substrate 22 to a front side of the substrate 22 (e.g., to the interconnects 24 and 50 and the bond pads 88).FIG. 21 illustrates a package structure 100. Package structure 100 includes a substrate 102 similar to substrate 22 of integrated circuit die 20, and an interconnect structure 104 having bond pads 106. The interconnect structure 104 and bond pads 106 may be similar to the interconnect structures 24 and 50 and bond pads 88, respectively, described above, and the descriptions are not repeated herein.In FIG. 22, the integrated circuit die 20 is bonded to the package structure 100. Bonding the integrated circuit die 20 to the package structure 100 may be performed by direct bonding, wherein both metal-metal direct bonding (between the bond pads 88 and 106) and dielectric-dielectric bonding (such as by Si-O-Si bonding between the dielectric surface layers of the integrated circuit die 20 and the package structure 100). Moreover, there may be a single integrated circuit die 20 or multiple dies 20 bonded to the same package structure 100. The plurality of dies 20 bonded to the same package structure 100 may be the same or different, such that a homogeneous or heterogeneous structure is formed.The die 20 is arranged front side down such that the front sides of the die 20 face the package structure 100 and the back sides of the die 20 face away from the package structure 100. The die 20 is bonded to the package structure 100 at an interface 108. As shown in FIG. 22, the direct bonding process bonds the uppermost dielectric layer of the interconnect 104 of the package structure 100 directly to the uppermost dielectric layer 74 of the die 20 by melt bonding at the interface 108. In one embodiment, the bonding of the uppermost dielectric layer of the interconnect 104 to the uppermost dielectric layer 74 of the die 20 may be comprised of oxide-oxide bonding. The direct bonding process also bonds the bond pads 88 of the die 20 directly to the bond pads 106 of the package structure 100 by metal-to-metal direct bonding at the interface 108. Thus, by physically connecting bond pads 88 and bond pads 106, an electrical connection may be established between die 20 and package structure 100.For example, the direct bonding process begins with aligning the die 20 to the package structure 100, for example, by aligning the bond pads 88 to the bond pads 106. When the die 20 and package structure 100 are aligned, the bond pads 88 may overlap with the corresponding bond pads 106. Next, the direct bonding includes a pre-bonding step of bringing the die 20 into contact with the package structure 100. The hybrid bonding process continues with performing a anneal, for example at a temperature between about 150° C. and about 400° C. for a duration between about 0.5 hours and about 3 hours, such that the copper in the bond pads 88 and the bond pads 106 diffuses into each other and thus metal-to-metal direct bonding is achieved.Next, as shown in FIG. 23, a gap filling process is performed to encapsulate the integrated circuit die 20 in an encapsulation material 110. After formation, the encapsulation material 110 encapsulates the integrated circuit die 20. The encapsulation material 110 may include an oxide. Alternatively, the encapsulation material may be a molding compound, a mold underfill, a resin, an epoxy resin, or the like. The encapsulation material 110 may be applied by compression molding, transfer molding, or the like, and may be applied in liquid or semi-liquid form and then subsequently cured. After depositing the encapsulation material 110, a planarization process is performed that level the back side of the integrated circuit die 20 with the top surface of the encapsulation material 110 and expose the TSVs 44. The surfaces of the TSVs 44, the substrate 22, and the encapsulation material 110 are coplanar within process variations after the planarization process. The planarization process may be, for example, a CMP, a grinding process, or the like. In some embodiments, planarization may be omitted, for example, when TSVs 44 are already exposed.In FIG. 24, redistribution structure 112 is deposited on encapsulant 110, TSVs 44, and integrated circuit die 20. Redistribution structure 112 may include redistribution lines (RDLs), such as metal traces (or metal lines), and vias underlying and connected to the metal traces. The redistribution lines of redistribution structure 112 are physically and electrically connected to the TSVs 44 of die 20.According to some embodiments of the present disclosure, the RDLs are formed by plating processes, each of the RDLs including a seed layer (not shown) and a metallic plating material over the seed layer. The seed layer may be formed using PVD or the like, for example. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and exposed to light for patterning. The pattern of the photoresist corresponds to the RDLs. The patterning forms openings through the photoresist that expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, for example, electroplating or electroless plating, or the like. The seed layer and the metallic plating material may be formed of the same or different materials. The conductive material may be made of a metal such as copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by a suitable ashing or stripping process, for example, using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed, for example, using a suitable etching process, for example, by wet and / or dry etching. The remaining portions of the seed layer and the conductive material form the RDLs.Dielectric layers or passivation layers may be formed over each layer of the metal traces. In some embodiments, the dielectric or passivation layers are formed from a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask. In further embodiments, the dielectric layers or passivation layers are formed from a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layers or passivation layers may be formed by spin coating, lamination, CVD, etc., or a combination thereof.By means of a patterning process, openings may be formed in the upper dielectric layer or passivation layer, exposing the upper metal layer of the redistribution structure 112 in whole or in part. The patterning process may be a suitable process, for example, exposing the dielectric layer or passivation layer to light when the dielectric layer is made of a photosensitive material, or it is etched using, for example, anisotropic etching.As shown in FIG. 25, bumps 114 are formed through the openings in the dielectric layers of redistribution structure 112 to contact metallization structures in redistribution structure 112. The bumps 114 may be metal pillars, flip-chip (C4) connection bumps, micro bumps, bumps formed by ENEPIG (electroless nickel electroless palladium gold immersion) technique, ball grid array (BGA) bumps, or the like. In one embodiment, the bumps 114 are C4 bumps. The bumps 114 may be formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The bumps 114 may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on top of the bumps 114. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or a combination thereof, and may be formed by a plating process.As further shown in FIG. 25, conductive connectors 116 are formed on the bumps 114. The conductive connectors 116 may be formed of a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, bismuth, or a combination thereof. In some embodiments, the conductive connectors 116 are formed by first forming a solder layer by methods such as vapor deposition, electroplating, printing, solder transfer, ball placement, or the like. When a solder layer is formed on the structure, reflow may be performed to form the conductive connectors 116 into desired bump shapes.The embodiment shown in FIG. 25 is a chip-on-wafer structure bonded in a front-side configuration. Alternatively, the integrated circuit die 20 and the package structure 100 may be bonded in a front-back configuration as shown in FIG. 26. For example, in FIG. 26, the back side of the die 20 (e.g., exposed ends of the TSVs 44 and the substrate 22) are bonded to the front side of the package structure 100. Details regarding this embodiment similar to those of the above-described embodiment will not be repeated here.FIG. 27 illustrates a cross-sectional view of a wafer-on-wafer structure, in accordance with some embodiments. This embodiment is similar to the embodiment shown in Figures 1 to 25, except that this embodiment is a wafer-on-wafer structure rather than a chip-on-wafer structure. Details regarding this embodiment similar to those of the above-described embodiment will not be repeated here.In Figure 27, the structure is a wafer-on-wafer structure bonded in a front-side-to-front configuration, the top structure being formed by a wafer 20. The wafer 20 is formed similarly to the die 20 described above, and the description will not be repeated here. In this embodiment, the steps of singulating the die 20 and forming the encapsulation material 110 are no longer required in the previous embodiment and these steps may be omitted in this embodiment. In this embodiment, wafer 20 and package structure 100 are both wafers and are of equal size.In further embodiments, the wafer 20 may be bonded to the package structure 100 in a front-back configuration. For example, the back side of the wafer 20 (e.g., exposed ends of the TSVs 44 and the substrate 22) may be bonded to the front side of the package structure 100.The die / wafer 20 may be integrated into various other packages, such as fan-out integrated packages or chip-on-wafer-on-substrate packages. For example, in a chip-on-wafer-on-substrate package, the die 20 may be bonded to an interposer bonded to a package substrate. Moreover, multiple dies 20 may be packaged together with a redistribution structure (similar to 112 described above) in a fan-out integrated package. Moreover, the die 20 may be encapsulated in a molding compound and include vias adjacent to the die 20, with another package structure in a fan-out integrated package bonded over the die 20. In other words, the described bond pad and redistribution structures may be incorporated into any suitable package structure.FIGS. 28A, 28B, 28C, and 28D show cross-sectional views of detailed views of redistribution and bond pad structures, according to various embodiments. FIGS. 28A-28D show various orientations of redistribution via 66 and bond pad via 86, in accordance with some embodiments. In FIG. 28A, an edge of redistribution via 66 is aligned with an edge of bond pad via 86 such that there is little or no overlap between the two vias 66 and 86 (see, e.g., line 120A). In FIG. 28B, an edge of redistribution via 66 is aligned with a center of bond pad via 86 such that there is some overlap (e.g., substantially half an overlap) between the two vias 66 and 86 (see, e.g., line 120B). In FIG. 28C, an edge of redistribution via 66 is aligned with an edge of bond pad via 86 such that there is substantially complete overlap between the two vias 66 and 86 (see, e.g., line 120C). In FIG. 28D, a center of redistribution via 66 is aligned with a center of bond pad via 86 such that there is a complete overlap between the two vias 66 and 86 (see, e.g., line 120D). These embodiments show various configurations of the alignment of bond pad vias 86 and redistribution vias 66.FIGS. 29A, 29B, 29C, and 29D show cross-sectional views of detailed views of redistribution and bond pad structures, according to various embodiments. FIGS. 29A to 29D show various configurations of the warp control layer 72 and the bonding layer 74, according to some embodiments. In Figure 29A, the two layers 74 and 72 are replaced by a single layer 72 / 74 which functions as both a warp control layer and a bond layer. In FIG. 29B, the planarization layer 70, the warp control layer 72, and the bonding layer 74 are separate layers, respectively, similarly to the embodiment in FIGS. 1 to 20. In FIGS. 29C and 29D, the warp control layer 72 includes the sub-layers 72A-C. In FIG. 29C, there are two sub-layers 72A and 72B of the warp control layer 72. in FIG. 29D, there are three sub-layers 72A, 72B, and 72C of the warp control layer 72.In the embodiments of FIGS. 29A through 29D, the warp control layer 72 and the bonding layer 74 are made of high elastic modulus, high thermal conductivity materials such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, silicon oxycarbide, the like, or combinations and sub-layers thereof.FIGS. 30A, 30B, 31A, 31B, 31C, and 31D show cross-sectional views of detailed views of redistribution and bond pad structures, in accordance with various embodiments. Figures 30A-B and 31A-D show various configurations of layers 70, 72 and 74 having intermediate layers 130 between these layers. The intermediate layers 130 are interposed between the bonding layer 74 and the warp control layer 72, between the warp control layers 72, and / or between the planarization layers 70 and the warp control layers 72 to improve adhesion between these layers. The intermediate layers 130 include first elements from the underlying layer and second elements from the overlying layer. For example, the intermediate layer 130 may be made of SiCN when the underlying layer is made of SiN and the overlying layer is made of SiC. As another example, when the bonding layer 74 and the warp control layer 72 each include SiN, SiON, SiC, SiCN, and / or SiCO, the intermediate layers 130 between them may include SiCN, SiON, and / or SiCO.FIGS. 30A and 30B show configurations including intermediate layers 130 and a warp control layer 72. in FIG. 30A, an intermediate layer 130 is interposed between the warp control layer 72 and the bonding layer 74. in FIG. 30B, there are two intermediate layers 130A and 130B. The intermediate layer 130A is interposed between the warp control layer 72 and the bonding layer 74, and the intermediate layer 130B is interposed between the warp control layer 72 and the planarization layer 70.FIGS. 31A to D show configurations including intermediate layers 130 and a plurality of warp control layers 72. in FIG. 31A, an intermediate layer 130 is interposed between the warp control layer 72A and the bonding layer 74. in FIG. 31B, a first intermediate layer 130A is interposed between the warp control layer 72A and the bonding layer 74, and a second intermediate layer 130B is interposed between the warp control layers 72A and 72B. In FIG. 31C, a first intermediate layer 130A is interposed between the warp control layer 72A and the bonding layer 74, a second intermediate layer 130B is interposed between the warp control layers 72A and 72B, and a third intermediate layer 130C is interposed between the warp control layers 72B and 72C. In FIG. 31D, a first intermediate layer 130A is interposed between the warp control layer 72A and the bonding layer 74, a second intermediate layer 130B is interposed between the warp control layers 72A and 72B, a third intermediate layer 130C is interposed between the warp control layers 72B and 72C, and a fourth intermediate layer 130D is interposed between the warp control layer 72C and the planarization layer 70.FIGS. 32A-B and 33A-B show cross-sectional views of detailed views of redistribution and bond pad structures, according to various embodiments. FIGS. 32A to B and 32A to B show various configurations of the height and width of the bond pad vias 86 and the bond pads 88 In FIGS. 32A and 32B, the bond pad 88 has a height H 1 measured from a bottom surface to a top surface, and the bond pad via 86 has a height H 2 measured from a bottom surface to a top surface. In some embodiments, the ratio of the heights H 2 / H 1 may be 0.5 to 15. In some embodiments, it may be less than 1, for example 0.5. Increasing the height of bond pads H 1 relative to the height of bond pad vias H 2 provides improved electrical and thermal conductivity.In FIGS. 33A and 33B, the bond pad 88 has a width W 1 measured from the outer surfaces, and the bond pad via 86 has a width W 2 measured from the outer surfaces. In some embodiments, the ratio of the widths W 1 / W 2 may be 1 to 1.38. When the ratio W 1 / W 2 is 1, the bond pad vias 86 and the bond pad 88 may be formed with a single lithography process.Considering the height and width settings together, the height ratio H2 / H1may be between 1 and 10 and the width ratio W1 / W2may be between 1 and 3.The above-described various configurations from 28A to 33B may be connected to each other in various configuration combinations. Only a portion of the contemplated configurations have been shown, but other configurations are also within the scope of this disclosure.Other elements and processes may also be provided. For example, test structures may be provided to aid in verification testing of the 3D packages or 3DIC devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate that allow testing of the 3D package or the 3DICs, use of probes and / or probe plates, and the like. In some embodiments, for more reliable probe testing, a solder layer may be formed over redistribution pad 66, and the solder is then removed prior to forming the overlying layers and bond pads. Verification testing may be performed on both intermediate structures and the finished structure. In addition, the structures and methods disclosed herein may be used in conjunction with test methods including intermediate testing of well known good dies to increase yield and decrease cost.Embodiments described herein may be described in a particular context, namely a redistribution structure that may be incorporated into a device (e.g., a chip or die) or package (e.g., as a chip-on-wafer (CoW) package structure or wafer-on-wafer (WoW) package structure. The redistribution structure includes a redistribution via and line having a planar top surface to allow a smaller center distance and minimum distance between adjacent redistribution lines and bond pads as well as bond pad vias. In some embodiments, redistribution via and line are formed in a same process, such as a dual damascene process. In some embodiments, warpage layers and bonding layers having high elastic modulus and high thermal conductivity are formed over the redistribution line and improve warpage control and heat dissipation. In addition, the ratio of the thickness of the bond pad vias to the bond pads is less than in conventional bond pad vias and bond pads. This lower thickness ratio improves the electrical and thermal conductivity of the structure.An embodiment includes a method including forming a first interconnect structure over a first substrate, the first interconnect structure having dielectric layers and metallization structures therein. The method further includes forming a redistribution via and a redistribution pad over the first interconnect structure, wherein the redistribution via and the redistribution pad are electrically connected to at least one of the metallization structures of the first interconnect structure, wherein the redistribution via and the redistribution pad have a same material composition. The method further includes forming a dielectric warp control layer over the redistribution pad. The method further includes forming a bond via and a bond pad over the redistribution pad, the bond pad lying in the dielectric warp control layer, the bond via electrically connected to the redistribution pad.Certain embodiments may include one or more of the following features. The method wherein the redistribution contacts and the redistribution pad each include copper. The bond pad and the bond via each contain copper. The redistribution via and the redistribution pad are formed in a single deposition process. Forming a redistribution via and redistribution pad over the first interconnect structure includes forming a dielectric layer over the metallization structures of the first interconnect structure, forming openings in the dielectric layer exposing top metal structures of the first interconnect structure, and forming a seed layer over the dielectric layer and on the exposed top metal structures in the openings of the dielectric layer, forming and patterning a mask layer over the seed layer, and performing a plating process to form the redistribution via and redistribution pad in the patterned mask layer, wherein the redistribution via is in the opening of the dielectric layer. The method further includes removing the patterned mask layer, and removing the exposed seed layer from a top surface of the dielectric layer. The bond pad via overlaps the redistribution via. The method further includes forming a dielectric layer over the metallization structures of the first interconnect structure, the redistribution via passing through the dielectric layer and the redistribution pad overlying the dielectric layer, forming a conformal dielectric layer over the dielectric layer and the redistribution pad, forming a planarization dielectric layer over the conformal dielectric layer, the distortion control dielectric layer overlying the planarization dielectric layer, and forming a bond dielectric layer on the distortion control dielectric layer. The bond via extends through the planarization dielectric layer and the conformal dielectric layer, and wherein the bond pad extends through the bond dielectric layer and the warp control dielectric layer. The method further includes forming a second dielectric warp control layer on the dielectric warp control layer, wherein the material composition of the second dielectric warp control layer is different from that of the dielectric warp control layer. The method further includes an intermediate layer between the second dielectric warpage control layer and the dielectric warpage control layer, wherein the material composition of the intermediate layer is different from that of the second dielectric warpage control layer and the dielectric warpage control layer. The method further includes forming a first bonding dielectric layer on the warpage control dielectric layer, and directly bonding the first bonding dielectric layer and the bonding pad to a second bonding dielectric layer and a second bonding pad of a package structure, the package structure having a second substrate and a second interconnect structure over the second substrate.An embodiment includes a structure including a first interconnect structure over a first substrate, the first interconnect structure including dielectric layers and metallization structures therein. The structure further includes a passivation layer over the metallization structures of the first interconnect structure. The structure further includes a redistribution via and a redistribution pad over the first interconnect structure, the redistribution via and the redistribution pad being electrically connected to at least one of the metallization structures of the first interconnect structure, the redistribution via passing through the passivation layer and the redistribution pad overlying the passivation layer, the redistribution via and the redistribution pad having a same material composition, and a conformal dielectric layer over the passivation layer and the redistribution pad. The structure further includes a planarization dielectric layer over the conformal dielectric layer. The structure further includes one or more dielectric warp control layers overlying the planarization dielectric layer. The structure further includes a bonding dielectric layer on the warpage control dielectric layer. The structure further includes a bond via and a bond pad over the redistribution pad, the bond pad residing in the dielectric warp control layer and the dielectric bond layer, the bond via residing in the planarization dielectric layer and electrically connected to the redistribution pad.Certain embodiments may include one or more of the following features. The structure where the height of the bond pad is greater than the height of the bond via. The redistribution via, the redistribution pad, the bond pad, and the bond via each include copper. The bond via overlaps the redistribution via. The one or more dielectric warp control layers include a plurality of dielectric warp control layers. The bonding dielectric layer and the plurality of dielectric warp control layers each include silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, silicon oxycarbide, or combinations and sub-layers thereof.An embodiment includes a structure including a first interconnect structure over a first substrate, the first interconnect structure including dielectric layers and metallization structures therein. The structure further includes a through silicon via extending through the first interconnect structure and the first substrate. The structure further includes a redistribution via over the first interconnect structure, the redistribution via being electrically connected to at least one of the metallization structures of the first interconnect structure. The structure further includes a redistribution pad over the redistribution via, the redistribution pad being electrically connected to the redistribution via, the redistribution pad and the redistribution via being made of a continuous conductive material. The structure further includes a via definition layer over the redistribution pad, wherein the via definition layer is a conformal dielectric layer. The structure further includes a planarization dielectric layer over the via definition layer. The structure further includes one or more dielectric warp control layers over the planarization dielectric layer. The structure further includes a bond via in the planarization dielectric layer and the via definition layer, the bond via being electrically connected to the redistribution pad, the bond via overlapping the redistribution via. The structure further includes a bond pad in the one or more dielectric warp control layers, the bond pad electrically connected to the bond via, the bond pad overlapping the redistribution via.Certain embodiments may include one or more of the following features. The structure further includes a bonding dielectric layer over the one or more warp control dielectric layers, the bonding via being in the bonding dielectric layer.The foregoing describes features of various embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same objects and / or to realize the same advantages of the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.References included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedUS 63 / 584 562

[0001] US 63 / 607 843

[0001]

Claims

A method, comprising: forming a first interconnect structure over a first substrate, the first interconnect structure having dielectric layers and metallization structures therein; forming a redistribution via and a redistribution pad over the first interconnect structure, the redistribution via and the redistribution pad being electrically connected to at least one of the metallization structures of the first interconnect structure, the redistribution via and the redistribution pad having a same material composition; forming a dielectric warpage control layer over the redistribution pad; and forming a bond via and a bond pad over the redistribution pad, the bond pad being in the dielectric warpage control layer, the bond via being electrically connected to the redistribution pad.The method of claim 1, wherein the redistribution contacts and the redistribution pad each include copper.The method of claim 1 or 2, wherein the bond pad and the bond via each include copper.The method of any preceding claim, wherein the redistribution via and the redistribution pad are formed in a single deposition process.The method of any preceding claim, wherein forming a redistribution via and redistribution pad over the first interconnect structure comprises: forming a dielectric layer over the metallization structures of the first interconnect structure; forming openings in the dielectric layer that expose upper metal structures of the first interconnect structure; and forming a seed layer over the dielectric layer and on the exposed upper metal structures in the openings of the dielectric layer; forming and patterning a mask layer over the seed layer; and performing a plating process to form the redistribution via and redistribution pad in the patterned mask layer, wherein the redistribution via is in the opening of the dielectric layer.The method of claim 5, further comprising: removing the patterned mask layer; and removing the exposed seed layer from a top surface of the dielectric layer.The method of any preceding claim, wherein the bond pad via overlaps the redistribution via.The method of any preceding claim, further comprising: forming a dielectric layer over the metallization structures of the first interconnect structure, wherein the redistribution via passes through the dielectric layer and the redistribution pad overlies the dielectric layer; forming a conformal dielectric layer over the dielectric layer and the redistribution pad; forming a planarization dielectric layer over the conformal dielectric layer, wherein the dielectric warp control layer overlies the planarization dielectric layer; and forming a bond dielectric layer on the warp control dielectric layer.The method of claim 8, wherein the bond via extends through the planarization dielectric layer and the conformal dielectric layer, and wherein the bond pad extends through the bond dielectric layer and the warp control dielectric layer.The method of any preceding claim, further comprising: forming a second dielectric warp control layer on the dielectric warp control layer, wherein the material composition of the second dielectric warp control layer is different from that of the dielectric warp control layer.The method of claim 10, further comprising: an intermediate layer between the second dielectric warp control layer and the dielectric warp control layer, wherein the material composition of the intermediate layer is different from that of the second dielectric warp control layer and the dielectric warp control layer.The method of any preceding claim, further comprising: forming a first dielectric bonding layer on the dielectric warp control layer; and directly bonding the first dielectric bonding layer and the bonding pad to a second dielectric bonding layer and a second bonding pad of a package structure, the package structure having a second substrate and a second interconnect structure over the second substrate.A structure, comprising: a first interconnect structure over a first substrate, the first interconnect structure having dielectric layers and metallization structures therein; a passivation layer over the metallization structures of the first interconnect structure; a redistribution via and a redistribution pad over the first interconnect structure, the redistribution via and the redistribution pad being electrically connected to at least one of the metallization structures of the first interconnect structure, the redistribution via passing through the passivation layer and the redistribution pad overlying the passivation layer, the redistribution via and the redistribution pad having a same material composition; a conformal dielectric layer over the passivation layer and the redistribution pad; a planarization dielectric layer over the conformal dielectric layer; one or more dielectric warp control layers overlying the dielectric planarization layer; a bonding dielectric layer on the dielectric warp control layer; and a bonding via and a bonding pad over the redistribution pad, the bonding pad being in the dielectric warp control layer and the bonding dielectric layer, the bonding via being in the dielectric planarization layer and electrically connected to the redistribution pad.The structure of claim 13, wherein a height of the bond pad is greater than a height of the bond via.The structure of claim 13 or 14, wherein the redistribution via, the redistribution pad, the bond pad, and the bond via each include copper.The structure of any of claims 13 to 15, wherein the bond via overlaps the redistribution via.The structure of any of claims 13 to 16, wherein the one or more dielectric warp control layers comprise a plurality of dielectric warp control layers.The structure of claim 17, wherein the bonding dielectric layer and the plurality of dielectric warp control layers each include silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, silicon oxycarbide, or combinations and sub-layers thereof.A structure comprising: a first interconnect structure over a first substrate, the first interconnect structure having dielectric layers and metallization structures therein; a silicon via extending through the first interconnect structure and the first substrate; a redistribution via over the first interconnect structure, the redistribution via being electrically connected to at least one of the metallization structures of the first interconnect structure; a redistribution pad over the redistribution via, the redistribution pad being electrically connected to the redistribution via, the redistribution pad and the redistribution via being made of a continuous conductive material; a via definition layer over the redistribution pad, the via definition layer being a conformal dielectric layer; a planarization dielectric layer over the via definition layer; one or more dielectric warp control layers over the planarization dielectric layer; a bond via in the planarization dielectric layer and the via definition layer, the bond via being electrically connected to the redistribution pad, the bond via overlapping the redistribution via; and a bond pad in the one or more dielectric warp control layers, the bond pad being electrically connected to the bond via, the bond pad overlapping the redistribution via.The structure of claim 19, further comprising: a bonding dielectric layer over the one or more warp control dielectric layers, wherein the bonding via is in the bonding dielectric layer.

Images