INTEGRATION OF STORAGE CELL AND LOGIC CELL

Abstract

Semiconductor structure with: a memory cell (30); a logic cell (40) configured to provide a logic function for the memory cell (30); and a transition area (370) between the memory cell (30, 352) and the logic cell (40), where: the memory cell (30) has at least one first active area (305A) extending longitudinally in a first direction and a plurality of first gate structures (340) extending longitudinally in a second direction perpendicular to the first direction and spaced apart from each other in the first direction by a gate pitch, the logic cell (40) has a second active area (305B) extending longitudinally in the first direction and a plurality of second gate structures (340) extending longitudinally in the second direction and spaced apart from each other in the first direction by the gate pitch, the transition region (370) has a first dielectric structural element (374) extending longitudinally in the second direction, and a second dielectric structural element (374) extending longitudinally in the second direction, the first dielectric structural element (374) divides the first active region (305A) into a first segment that is partially in the transition region (370) and a second segment that is completely in the transition region (370), and the second dielectric structural element (374) divides the second active region (305B) into a third segment, which is partially in the transition region (370), and a fourth segment, which is completely in the transition region (370).

Description

BACKGROUND

[0001] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each generation featuring smaller and more complex circuits than the previous one. Throughout IC evolution, feature density (i.e., the number of interconnected devices per unit area) has generally increased, while feature size (i.e., the smallest component (or trace) that can be produced using a manufacturing process) has decreased. This miniaturization process generally offers advantages by increasing production output and reducing associated costs. However, this miniaturization has also increased the complexity of machining and manufacturing ICs.

[0002] Integrated circuits (ICs) commonly use memory. Static random-access memory (SRAM), for example, is a volatile memory used in electronic applications where high speed, low power consumption, and ease of operation are required. Embedded SRAM is particularly common in high-speed data transfers, image processing, and system-on-a-chip (SoC) applications. SRAM has the advantage of being able to retain data without requiring refreshing. An SRAM structure consists of memory cells and logic cells. During IC design, designers retrieve the necessary cells from cell libraries and position them in the desired locations. Then, the circuit layout is performed to create connections between the cells and other circuit blocks, thus generating the desired integrated circuit.The placement of memory and logic cells follows predefined design rules. For example, cells are positioned close to each other, with the space between them determined by predefined rules. However, this space, reserved between cells and their boundaries, significantly increases the overall device size. Furthermore, it contains structures that increase manufacturing complexity and introduce a risk of defects, impacting circuit performance. Consequently, the performance of the resulting circuit is reduced. Layout structures and configurations influence the yield and design performance of the IC. Therefore, there is a need for an IC structure that addresses these issues.

[0003] DE 10 2021 115 959 A1 describes a static random access memory (SRAM). For example, embodiments here place bit lines in a metal-one layer (M1 layer), which is the lowest metallization layer of an interconnect structure of a memory cell.

[0004] DE 10 2021 100 870 A1 describes a method for generating an IC layout diagram with adjacent active areas of different widths. DE 10 2018 115 573 A1 describes an integrated circuit (IC) with a semiconductor-on-insulator (SOI) substrate comprising a handling substrate, an insulating layer above the handling substrate, and a semiconductor device layer above the insulating layer. A logic device includes a logic gate arranged above the semiconductor device layer. The logic gate is located within a high-κ dielectric layer. The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows a block diagram of a semiconductor device having a memory macro, according to some embodiments of the present disclosure. Fig. Figure 2 shows a circuit diagram for a static random-access memory cell (SRAM cell) according to the state of the art. Fig. Figure 3 shows a perspective view of a multi-gate transistor according to the state of the art. Fig. Figure 4 shows a layout of the SRAM cell as it is used in Fig. 2 is shown, according to some embodiments of the present disclosure. The Fig. 5 and Fig. Figure 6 shows block diagrams of a part of the memory macro as it is implemented in Fig. 1 is shown according to some embodiments of the present disclosure. The Fig. 7, Fig. 9, Fig. 10, Fig. 11, Fig. 12 and Fig. Figure 14 shows layouts of a part of the memory macro, as it appears in Fig. 1 is shown according to some embodiments of the present disclosure. The Fig. 8, Fig. 13 and Fig. Figure 15 shows sectional views along a section line of the layouts, as shown in the Fig. 7, Fig. Figures 12 and 14 are shown, according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0006] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the fabrication of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact.

[0007] Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention. This repetition serves for simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed. Moreover, in the present invention described below, the fabrication of an element on another element and / or the fabrication of an element that is connected and / or coupled to another element may include embodiments in which the elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the elements so that the elements are not in direct contact.Furthermore, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "above," "over," "below," "under," "upward," "downward," "above," "below," etc., and their derivatives (e.g., the adverbs "horizontal," "downward," "upward," etc.) are used here to easily describe the relationship of one element to another. These spatially relative terms are intended to cover different orientations of the device that incorporates the elements. Additionally, when a number or range of numbers is described using terms like "about," "approximately," and the like, the term is intended to include numbers that are within ±10% of the specified number, unless otherwise stated. For example, the term "about 5 nm" encompasses the dimensional range from 4.5 nm to 5.5 nm.

[0008] This disclosure relates generally to static random-access memory (SRAM) structures comprising memory cells and logic cells. The memory cells, also referred to as bit cells, are configured to store memory bits. They can be arranged in rows and columns of a matrix. The logic cells can be standard cells (STD cells), such as Inventor (INV), AND, OR, NAND, NOR, flip-flip, SCAN, and so on. The logic cells are arranged around the memory cells and configured to implement various logic functions. The placement of memory cells and logic cells follows predefined design rules. For example, dummy cells can be placed in a reserved space between the memory cells and the logic cells to promote uniformity in manufacturing and / or memory cell performance.This reserved space between cells, however, leads to a significant increase in the overall device size. Various SRAM structures with a reduced transition area between the memory and logic cells, and corresponding layouts, are provided according to several exemplary embodiments. Several variations of these embodiments are also discussed. Throughout the various views and embodiments shown, the same reference numbers are used to denote identical elements.

[0009] Reference will now be made to Fig. 1 taken. Fig. Figure 1 is a simplified block diagram of a semiconductor device (or IC) 10 according to some embodiments of the present disclosure. The semiconductor device 10 may be, for example, a microprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), or a part thereof.The various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), fin field-effect transistors (FinFETs), gate-all-around transistors (GAA transistors) (such as nanolayer FETs or nanowire FETs), other types of multi-gate FETs, metal-oxide semiconductor field-effect transistors (MOSFETs), complementary metal-oxide semiconductor transistors (CMOS transistors), bipolar junction transistors (BJTs), and side-diffused MOS transistors (LDMOS transistors). (LDMOS: laterally diffused MOS), high-voltage transistors, high-frequency transistors, storage devices, other suitable components or combinations thereof.The exact functionality of the semiconductor device 10 is not a limitation of the item provided.

[0010] The semiconductor device 10 comprises a circuit macro (hereinafter referred to as macro) 20. In some embodiments, the macro 20 is a static random-access memory (SRAM) macro, such as a single-port SRAM macro, a dual-port SRAM macro, or other types of SRAM macros. However, the present disclosure also considers embodiments in which the macro 20 is another type of memory, such as dynamic random-access memory (DRAM), non-volatile random-access memory (NVRAM), flash memory, or other suitable memory. For the sake of clarity, Fig. Figure 1 has been simplified to make the inventive concepts of the present disclosure more understandable. Further features can be added to the memory macro 20, and some of the features described below can be replaced, modified, or omitted in other embodiments of the memory macro 20.

[0011] In some embodiments, the macro 20 comprises memory cells and peripheral circuitry. The memory cells, also referred to as bit cells, are configured to store memory bits. The peripheral cells, also referred to as logic cells, are arranged around the bit cells and configured to implement various logic functions. These logic functions include, for example, write and / or read decoding, word line selection, bit line selection, data control, and memory self-checking. The logic functions of the logic cells described above are given for illustrative purposes. Various logic cell functions are possible. In the illustrated embodiment, the macro 20 comprises a circuit area 22 in which at least one memory cell block 30 and at least one logic cell block 40 are positioned in close proximity to each other.Memory block 30 contains at least one memory cell. In general, memory block 30 can contain many memory cells arranged in rows and columns of a matrix. Logic block 40 contains at least one logic cell. In general, logic block 40 can contain many logic cells to provide read and / or write operations for the memory cells in memory block 30. Transistors in the one or more memory blocks 30 and the one or more logic blocks 40 can be implemented with various pFETs and nFETs, such as planar transistors or non-planar transistors, such as various FinFET transistors, GAA transistors, or a combination thereof.GAA transistors relate to transistors with gate electrodes that enclose transistor channels, such as vertically stacked gate-all-around devices, horizontal nanowire or nanolayer MOSFET devices. The following disclosure continues with one or more GAA examples to illustrate different embodiments of the present disclosure. However, it is understood that the application should not be limited to a particular type of device unless specifically claimed. For example, aspects of the present disclosure may also apply to an implementation based on FinFETs or planar FETs.

[0012] Memory cell block 30 is separated from logic cell block 40 by a gap S, which reserves a space between memory cell block 30 and logic cell block 40. Dummy edge cells and / or trough-band cells of varying sizes can be placed in the reserved space to serve as a transition between memory cell block 30 and logic cell block 40. For example, memory cell block 30 and logic cell block 40 can each have corresponding dummy edge cells. Dummy edge cells designed for memory cell block 30 promote uniformity in the manufacturing and / or performance of memory cells in memory cell block 30. Dummy edge cells designed for logic cell block 40 promote uniformity in the manufacturing and / or performance of logic cells in logic cell block 40.Well-shaped ribbon cells designed for memory cell block 30 promote the stability of n-well and p-well potentials in memory cell block 30. Well-shaped ribbon cells designed for logic cell block 40 promote the stability of n-well and p-well potentials in logic cell block 40. The spacing S would need to be large enough to accommodate these non-functional cells, which would result in a significant increase in the overall device size.

[0013] Fig. Figure 2 is a circuit diagram of an exemplary SRAM cell 60, which can be implemented as a memory cell of an SRAM matrix according to various aspects of the present disclosure. In some implementations, the SRAM cell 60 is located in one or more memory cell blocks 30 of the macro 20 ( Fig. 1) implemented. In the illustrated embodiment, the SRAM cell 60 is a single-port SRAM cell with six transistors (SP-6T SRAM cell) (SP: single port). In various embodiments, the SRAM cell 60 can be a different type of memory cell, such as a dual-port memory cell or a memory cell with more than six transistors. For clarity, Fig. Section 2 has been simplified to make the inventive concepts of the present disclosure more understandable. Further features can be added to the single-port SRAM cell 60, and some of the features described below can be replaced, modified, or omitted in other embodiments of the single-port SRAM cell 60.

[0014] The exemplary SRAM cell 60 comprises six transistors: a pass-gate transistor PG-1, a pass-gate transistor PG-2, a pull-up transistor PU-1, a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-2. In operation, the pass-gate transistors PG-1 and PG-2 provide access to a memory portion of the SRAM cell 60, which includes a cross-coupled pair of inverters, inverter 82 and inverter 84. Inverter 82 comprises pull-up transistor PU-1 and pull-down transistor PD-1, and inverter 84 comprises pull-up transistor PU-2 and pull-down transistor PD-2. In some implementations, the pull-up transistors PU-1, PU-2 are configured as p-FinFET transistors or p-GAA transistors, and the pull-down transistors PD-1, PD-2 are configured as n-FinFET transistors or n-GAA transistors.

[0015] One gate of the pull-up transistor PU-1 is connected between a source (electrically) and a supply voltage (V). DD ) connected) and a first common drain (CD1), and a gate of the pull-down transistor PD-1 is connected between a source (electrically connected to a supply voltage (V)) and a first common drain (CD1), and a gate of the pull-down transistor PD-1 is connected between a source (electrically connected to a supply voltage (V)). SS ) connected, which can be an electrical ground) and arranged at the first common drain. A gate of the pull-up transistor PU-2 is connected between a source (electrically connected to a supply voltage (V)). DD ) connected) and a second common drain (CD2), and a gate of the pull-down transistor PD-2 is connected between a source (electrically connected to a supply voltage (V)) and a second common drain (CD2), and a gate of the pull-down transistor PD-2 is connected between a source (electrically connected to a supply voltage (V)). SSThe gate of pull-up transistor PU-1 and the gate of pull-down transistor PD-1 are connected to the second common drain (CD2), and the gate of pull-up transistor PU-2 and the gate of pull-down transistor PD-2 are connected to the first common drain (CD1). A gate of pass-gate transistor PG-1 is positioned between a source (electrically connected to a bit line BL) and a drain that is electrically connected to the first common drain (CD1). In some implementations, the first common drain (CD1) is a memory node (SN) that stores data in its true form, and the second common drain (CD2) is a memory node (SNB) that stores data in a complementary form. The gate of pull-up transistor PU-1 and the gate of pull-down transistor PD-1 are connected to the second common drain (CD2), and the gate of pull-up transistor PU-2 and the gate of pull-down transistor PD-2 are connected to the first common drain (CD1). A gate of pass-gate transistor PG-1 is positioned between a source (electrically connected to a bit line BL) and a drain that is electrically connected to the first common drain (CD1).One gate of pass-gate transistor PG-2 is located between a source (electrically connected to a complementary bit line BLB) and a drain that is electrically connected to the second common drain (CD2). The gates of pass-gate transistors PG-1 and PG-2 are electrically connected to a word line WL. In some implementations, pass-gate transistors PG-1 and PG-2 provide access to memory nodes SN and SNB during read and / or write operations. For example, in response to a voltage applied to the gates of pass-gate transistors PG-1 and PG-2 through word line WL, pass-gate transistors PG-1 and PG-2 connect memory nodes SN and SNB to bit lines BL and BLB, respectively.

[0016] Fig. Figure 3 shows a perspective view of a multi-gate transistor 100, which is one of the transistors in the SRAM cell 60 ( Fig. 2), which can serve as the pull-up transistor PU-1, the pull-up transistor PU-2, the pull-down transistor PD-1, the pull-down transistor PD-2, the pass-gate transistor PG-1, and the pass-gate transistor PG-2. In some embodiments, the multi-gate transistor 100 is a FinFET transistor having a channel region exhibiting a fin-like structure. In some embodiments, the multi-gate transistor 100 is a GAA transistor having a channel region exhibiting vertically stacked, horizontally oriented nanostructures (e.g., nanowires or nanolayers).

[0017] In the illustrated embodiment, the multi-gate transistor 100 is fabricated on a substrate 102. The substrate 102 can comprise: an elemental semiconductor (single-element semiconductor), such as silicon, germanium, and / or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 102 can be a single-layer material with a uniform composition. Alternatively, the substrate 102 can comprise multiple material layers with similar or different compositions suitable for fabricating IC devices.In one example, substrate 102 can be a semiconductor-on-insulator (SOI) substrate, comprising a semiconductor silicon layer fabricated on a silicon oxide layer. In another example, substrate 102 can comprise a conductive layer, a semiconductor layer, a dielectric layer, other layers, and / or combinations thereof. Various doped regions, such as source / drain (S / D) regions, can be fabricated in or on substrate 102. Depending on the design requirements, the doped regions can be doped with n-type dopants, such as phosphorus or arsenic, and / or p-type dopants, such as boron. The doped regions can be fabricated directly on substrate 102, in a p-well structure, an n-well structure, a double-well structure, or using a raised structure.The doped areas can be produced by implanting doping atoms, epitaxial growth with in-situ doping and / or by other suitable methods.

[0018] A three-dimensional active region 104 is fabricated on the substrate 102. An active region for a transistor refers to the area in which a source region, a drain region and a channel region are fabricated under a gate structure of the transistor.

[0019] Since the active regions are occasionally located within or defined by a silicon oxide-containing insulation structural element (such as shallow trench insulation or STI), the active regions can be referred to as oxide definition regions or "ods". The active region 104 comprises a source region 106a, a drain region 106b, a channel region (beneath the gate structure 110) located between the source region 106a and the drain region 106b, and a fin base 112 on which the source region 106a, the drain region 106b, and the channel region are arranged. The source region 106a and the drain region 106b are also collectively referred to as the source / drain regions (S / D regions) 106.In some embodiments, the source / drain regions 106 are formed from epitaxially grown structural elements and are also referred to as source / drain structural elements 106 or epitaxial source / drain structural elements 106. The fin base 112 protrudes from the substrate 102. In a FinFET transistor, the channel region beneath the gate structure 110 can be a fin-like structure extending continuously upwards from the fin base 112e. In a GAA transistor, the channel region beneath the gate structure 110 can comprise vertically stacked, horizontally oriented nanostructures suspended above the fin base 112. The suspended nanostructures connect the source region 106a and the drain region 106b, which are opposite each other.

[0020] An SRAM cell has several active regions. In some embodiments, the fabrication of the active regions, such as the three-dimensional active regions 104, which are described in Fig. Figure 3 shows the structuring of an upper portion of the substrate in a structuring process. For example, the active areas 104 can be structured using one or more photolithographic processes, such as dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithographic and self-aligning processes, enabling the creation of structures with, for example, pitches smaller than those achievable with a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is produced over a substrate and then structured using a photolithographic process. Spacers are produced along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used to structure the active area 104.

[0021] In some embodiments, an insulating structure 114 is arranged on side walls of the fin base 112. The insulating structure 114 can electrically isolate the active area 104 from other active areas. In some embodiments, the insulating structure 114 is a shallow trench insulation (STI), a field oxide (FOX), or another suitable electrically insulating structural element.

[0022] Furthermore, with reference to Fig. 3 In some embodiments, the gate structure 110 comprises a gate dielectric 116 and a gate electrode 118 fabricated above the gate dielectric 116. In a FinFET transistor, the gate structure 110 is positioned above sidewalls and the top surface of a fin. In a GAA transistor, the gate structure 110 surrounds each of the channel layers (e.g., nanowire or nanolayer). Therefore, the gate structure 110 defines a portion of the active region 104 below it as a channel region. In some embodiments, the gate dielectric 116 is a dielectric material with a high dielectric constant (high-k dielectric material). A high-k dielectric material has a dielectric constant (k) that is higher than that of silicon dioxide.Examples of high-k dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, silicon nitride, hafnium dioxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon nitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, another suitable high-k material, or a combination thereof. In some embodiments, the gate electrode 118 is made of a conductive material such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or another suitable material.

[0023] In some embodiments, gate spacers 120 are arranged on side walls of the gate structure 110. In some embodiments, the gate spacers 120 are made of silicon nitride, silicon oxide nitride, silicon carbide, another suitable material, or a combination thereof.

[0024] In some embodiments, parts of the active region 104 that are not covered by the gate structure 110 and the gate spacers 120 serve as the source / drain regions 106. In some embodiments, the source / drain regions 106 of p-transistors, for example the pull-up transistors PU-1, PU-2, are formed by implanting the parts of the active region 104 that are not covered by the gate structure 110 and the gate spacers 120 with a p-type dopant, such as boron, indium, or the like. In some embodiments, the source / drain regions 106 of n-transistors, for example the pass-gate transistors PG-1, PG-2, the pull-down transistors PD-1, PD-2, are formed by implanting the parts of the active region 104 that are not covered by the gate structure 110 and the gate spacers 120 with an n-doping material, such as phosphorus, arsenic, antimony or the like.

[0025] In some embodiments, the source / drain regions 106 are produced by etching portions of the active regions 104 not covered by the gate structure 110 and the gate spacers 120 to form recesses and by growing epitaxial structural elements in these recesses. The epitaxial structural elements can be made of Si, Ge, SiP, SiC, SiPC, SiGe, SiAs, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, C, or a combination thereof. Accordingly, in some exemplary embodiments, the source / drain regions 106 can be made of silicon germanium (SiGe), while the remaining active region 104 can be made of silicon. In some embodiments, during the epitaxial growth of the source / drain regions 106 of p-transistors, for example the pull-up transistors PU-1, PU-2, p-doping materials are doped in situ into the source / drain regions 106.Furthermore, during the epitaxial growth of the source / drain regions 106 of n-transistors, for example the pass-gate transistors PG-1, PG-2, the pull-down transistors PD-1, PD-2, n-doping materials are doped in situ into the source / drain regions 106.

[0026] Fig. Figure 4 shows an example layout of the SRAM cell 60, as used in Fig. Figure 2 shows a limit of the SRAM cell 60. Fig. Figure 4 is illustrated using a rectangular box 202 with dashed lines. The rectangular box 202 is longer in the y-direction than in the x-direction, for example, about 3.5 times to about 6 times longer. The first dimension of the rectangular box 202 along the x-direction is called a cell width W, and the second dimension of the rectangular box 202 along the y-direction is called a cell height H. Where the SRAM cell 60 repeats in a memory matrix, the cell width W can represent and be called a memory cell pitch in the memory matrix along the x-direction, and the cell height H can represent and be called a memory cell pitch in the memory matrix along the y-direction. In the illustrated embodiment, the cell width W is twice a poly-pitch.A poly-pitch refers to a minimum center-to-center distance between two adjacent gate structures along the x-direction.

[0027] The SRAM cell 60 comprises active regions 205 (with 205A, 205B, 205C, and 205D) oriented longitudinally along the x-direction, and gate structures 240 (with 240A, 240B, 240C, and 240D) oriented longitudinally along the y-direction perpendicular to the x-direction. Active regions 205B and 205C are arranged above an n-well (or n-dish) 204N. Active regions 205A and 205D are arranged above p-wells (or p-dishes) 204P, which are on both sides of the n-well 204N along the y-direction. The gate structures 240 engage with the channel regions of the respective active regions 205 to form transistors.In this respect, the gate structure 240A engages the channel area 215A of the active area 205A to form an n-transistor, such as the pass-gate transistor PG-1; the gate structure 240B engages the channel area 215B of the active area 205A to form an n-transistor, such as the pull-down transistor PD-1, and engages the channel area 215C of the active area 205B to form a p-transistor, such as the pull-up transistor PU-1; The gate structure 240C engages in the channel area 215E of the active area 205D to form an n-transistor, such as the pull-down transistor PD-2, and engages in the channel area 215D of the active area 205C to form a p-transistor, such as the pull-up transistor PU-2; and the gate structure 240D engages in the channel area 215F of the active area 205D to form an n-transistor, such as the pass-gate transistor PG-2.In the present embodiment, each of the channel regions 215A-F is in the form of vertically stacked nanostructures, and each of the transistors PU-1, PU-2, PD-1, PD-2, PG-1 and PG-2 is a GAA transistor. Alternatively, each of the channel regions 215A-F is in the form of a fin, and each of the transistors PU-1, PU-2, PD-1, PD-2, PG-1 and PG-2 is a FinFET transistor.

[0028] Different active regions in various transistors of SRAM cell 60 can have different widths (e.g., dimensions measured in the y-direction) to optimize device performance. Specifically, active region 205A of pull-down transistor PD-1 and pass-gate transistor PG-1 has a width W1, active region 205B of pull-up transistor PU-1 has a width W2, active region 205C of pull-up transistor PU-2 has a width W3, and active region 205D of pass-gate transistor PG-2 and pull-down transistor PD-2 has a width W4. Widths W1-W4 can also be measured in portions of the active regions corresponding to channel regions 215A-F. In other words, these parts of the active regions (whose widths W1-W4 are measured) are the channel regions (e.g. the vertically stacked nanostructures of GAA devices) of the transistors.To optimize SRAM performance, in some embodiments, and in an effort to balance the speed between the n-transistors and the p-transistors, the two widths W1 and W4 are configured to be larger than the two widths W2 and W3. For example, the ratio W1 / W2 (or W4 / W3) may range from approximately 1.2 to approximately 3. In some embodiments, the widths W2 and W3 may be equal, and the widths W1 and W4 may be equal.

[0029] Furthermore, with reference to Fig. 4 The SRAM cell 60 also includes source / drain contacts arranged over the source / drain areas of the active areas 205 (the source / drain areas are arranged on both sides of the respective channel area), a butted contact (Butt_Co) 209 arranged over and connecting the active area 205B and the gate structure 240C, another butted contact 409 arranged over and connecting the active area 205C and the gate structure 240B, source / drain vias (VC) arranged over and connected to the source / drain contacts, and two gate vias (VG) arranged over and connected to the gate structures 240A and 240D respectively.Since the source / drain vias VC and the gate vias VG are normally fabricated in a via zero layer (V0 layer) of a multilayer interconnect (MLI) located above the device layer (where the active areas and gate structures are formed), in this context the vias VC and VG can also be collectively referred to as vias “V0”. Fig. Figure 4 also shows the circuit nodes Vss node, Vdd node, bit line node and complementary bit line node (or BLB node) (BLB: bit line bar), which connect the circuit nodes Vss, Vdd, BL and BLB in Fig. 2 correspond. The BLB (bitline bar) is also called the complementary bitline or the inverse bitline. As in Fig. As shown in the layout 200, the source / drain vias VC and the gate vias VG can also be positioned on the boundary of the SRAM cell 60 (e.g., positioned on the dashed lines of the rectangular box 202), since the source / drain vias VC and the gate vias VG can be shared by adjacent SRAM cells to electrically connect the respective same signal lines.

[0030] Furthermore, with reference to Fig. Figure 4 further states that the SRAM cell 60 comprises a plurality of dielectric gate-section structural elements extending longitudinally along the x-direction, with dielectric structural elements 252A, 252B, 252C, 252D (collectively dielectric structural elements 252). In the illustrated embodiment, dielectric structural element 252A is arranged between the active regions 205C, 205D and is adjacent to gate structure 240B and gate structure 240D. Dielectric structural element 252A divides an otherwise continuous gate structure into two isolated segments corresponding to gate structure 240B and gate structure 240D. Similarly, dielectric structural element 252B is arranged between the active regions 205A, 205B and is adjacent to gate structure 240A and gate structure 240C. The dielectric structural element 252B divides an otherwise continuous gate structure into two isolated segments, corresponding to gate structure 240A and gate structure 240C.The dielectric structural element 252C is positioned between the active region 205A and the active region in an adjacent SRAM cell to the left of SRAM cell 60, separating the gate structure 240B from the gate structure in the adjacent SRAM cell. Similarly, the dielectric structural element 252D is positioned between the active region 205D and the active region in an adjacent SRAM cell to the right of SRAM cell 60, separating the gate structure 240C from the gate structure in the adjacent SRAM cell. Each of the dielectric structural elements 252 is fabricated by filling a corresponding cut-metal gate (CMG) trench at the position of the dielectric structural elements. The dielectric structural elements 252 are also referred to as CMG structural elements.In the illustrated embodiment, each of the dielectric structural elements 252A, 252B is arranged above an interface between the n-tub 204N and the respective p-tub 204P, and the dielectric structural elements 252C, 252D are arranged above the respective p-tub 204P.

[0031] A CMG process involves a manufacturing process in which, after replacing a dummy gate structure (e.g., a polysilicon gate) with a metal gate (e.g., a high-k metal gate or HKMG), the metal gate is cut (e.g., by an etching process) to separate it into two or more gate segments. Each gate segment acts as a metal gate for a single transistor. Subsequently, an insulating material is filled into trenches between adjacent portions of the metal gate. These trenches are referred to in this disclosure as metal gate cut trenches or CMG trenches. The dielectric material used to fill a CMG trench for insulation is called a CMG structural element. To ensure that a metal gate is completely cut, a CMG structural element often extends further into adjacent areas, such as dielectric layers that fill a space between the metal gates.A CMG structural element often has an elongated shape in a top view. For example, in . Fig. As shown in Figure 4, each of the CMG structural elements 252 has an elongated shape that extends lengthwise in the x-direction.

[0032] Fig. Figure 5 shows simplified block diagrams of a portion of circuit area 22, as in Fig. Figure 1 is shown. In particular, block diagram 22A represents a simplified top view of a portion of the circuit area 22 according to some embodiments of the present disclosure, and block diagram 22B represents a simplified top view of a portion of the circuit area 22 according to some other embodiments of the present disclosure. The circuit area 22 can be implemented using either block diagram 22A or 22B based on circuit performance requirements, but independently of each other. Alternatively, the circuit area 22 can be implemented using both block diagrams 22A and 22B, each being implemented in a different part of the circuit area 22. For clarity, Fig. Figure 5 has been simplified to make the inventive concepts of the present disclosure more understandable. Further features may be added in block diagrams 22A, 22B, and some of the features described below may be replaced, modified, or omitted in other embodiments of block diagrams 22A, 22B.

[0033] In the illustrated embodiment, the memory cell block 30 is a SRACM cell block comprising at least one SRAM cell. Accordingly, the memory cell block 30 is also referred to as the SRAM cell block. In general, the SRAM cell block 30 can contain several SRAM cells, such as the SRAM cell 60 in Fig. 2, which are arranged in rows and columns of a matrix. Two SRAM edge cell regions 32 each border the opposite edges of the SRAM cell block 30 along the x-direction. An SRAM edge cell region 32 is configured with edge cells, such as dummy cells and / or trough-band cells, to promote uniformity of fabrication and / or performance of SRAM cells in the SRAM cell block 30. Dummy cells are physically and / or structurally similar to an SRAM cell, such as the SRAM cell 60 in Fig. 2. Dummy cells are configured but do not store data. For example, dummy cells can have p-wells, n-wells, channels (e.g., fabricated in one or more fins or one or more floating channel layers (e.g., nanowires or nanolayers)), gate structures, source / drains, and / or interconnects (e.g., contacts, vias, and / or metal traces). Well-band cells are generally non-functional cells configured to connect a voltage to an n-well of the SRAM cells, a p-well of the SRAM cells, or both. For example, an n-well band is configured to electrically connect an n-well corresponding to at least one p-transistor of an SRAM cell to a voltage source, and a p-well band is configured to electrically connect a p-well corresponding to at least one n-transistor of an SRAM cell to a voltage source.

[0034] In the illustrated embodiment, the logic cell block 40 has at least one logic cell. In general, the logic cell block 40 can have multiple logic cells to provide read and / or write operations for the SRAM cells in the SRAM cell block 30. A logic tap area 44 is positioned between two adjacent logic cell blocks 40 along the x-direction. The logic tap area 44 has tap cells similar to the well-band cells discussed above. The tap cells can take the form of a transistor within the logic cell block 40, but they do not have functional gate structures. The tap cells can be implemented to connect specific wells to the appropriate voltage sources.For example, an n-tap cell is configured to electrically connect an n-well corresponding to at least one p-transistor of a logic cell to a voltage source, and a p-tap cell is configured to electrically connect a p-well corresponding to at least one n-transistor of a logic cell to a voltage source. A logic edge cell region 42 is positioned between an SRAM edge cell region 32 and a logic cell block 40. The logic edge cell region 42 borders an edge of the SRAM edge cell region facing the logic cell block 40 and an opposite edge of the logic cell block 40 facing the SRAM edge cell region 32. The logic edge cell region 42 is configured with dummy cells to promote uniformity of manufacturing and / or performance of logic cells in the logic cell block 40.The dummy cells can take the form of a transistor in the logic cell block 40, but they have no functional gate structures. As shown in block diagram 22A, a combination comprising a first logic cell block 40, a logic tap area 44, and a second logic cell block 40 can be positioned between two logic edge cell areas 42. In block diagram 22A, the SRAM edge cell area 32 and the adjacent logic edge cell area 42 together define a reserved space extending over a distance S between the SRAM cell block 30 and the logic cell block 40.

[0035] For clarity and simplicity, similar elements in block diagram 22B are designated with the same reference numbers as in block diagram 22A, and these similar aspects are not repeated. One difference between block diagrams 22A and 22B is that the logic-related circuits (e.g., blocks and / or areas 40, 42, 44, designated for logic functions, collectively designated as logic area 46) are located on one side of the memory-related circuits (e.g., blocks and / or areas 30, 32, designated for memory functions, collectively designated as memory area 36) in block diagram 22A, whereas in block diagram 22B they are located on both sides. The placement of the logic-related circuits on one or both sides of the memory-related circuits is determined by predefined design rules and / or circuit performance requirements.In the two block diagrams 22A and 22B, the SRAM area 36 and the logic area 46 each have their own boundary cell areas, and the SRAM cells and the logic cells will hardly be directly adjacent to each other. A distance S between the boundaries of the SRAM cell block 30 and the logic cell block 40, intended to reserve space for the SRAM boundary cell area 32 and the logic boundary cell area 42, occupies an inappropriately large amount of usable space in a macro.

[0036] This is because, although well-band cells in the SRAM edge cell region 32 can be fabricated in the same active regions as the SRAM cells in the SRAM cell block 30, the different doping methods prevent them from being placed directly adjacent to each other. For example, the n-wells and p-wells in the SRAM region 36 can extend along the same direction from the SRAM cell block 30 into the SRAM edge cell region 32, each having an elongated shape and arranged alternately. Fins or vertical stacks of channel layers can be fabricated over the n-wells or the p-wells and doped with different types of dopants. However, if an active region of the well-band cells borders an active region of a different conductivity type of memory cell, this leads to a drift in the electrical properties of the memory cells and to poorer performance.To isolate a trough-band cell from an adjacent storage cell, interruptions in the active regions are introduced. As discussed above, the active regions can be referred to as oxide definition regions or "ODs," and the interruptions in the active regions can be referred to as OD interruptions because the active regions are occasionally located within and defined by a silicon oxide-containing isolation structure element (such as shallow trench isolation or STI). In some embodiments, OD interruptions are formed prior to the deposition of the isolation structure element and the fabrication of the source / drain structure elements. Because the OD interruptions are formed prior to the deposition of the isolation structure element, the isolation structure element material is also deposited within the OD interruptions.Since the OD interruptions are formed before the source / drain structural elements, which apply mechanical stresses to the active area, are manufactured, the active areas adjacent to the OD interruptions are exposed to different environments and can exhibit different properties. Therefore, where the active area of ​​the standard cell is interrupted by another active area of ​​the trough belt cells, the OD interruptions also produce a certain layout-dependent effect.

[0037] To address the layout-dependent effect caused by OD breaks, dummy cells can be inserted between the SRAM cells and the OD breaks to act as a transition between the OD break and the SRAM cells. In one example, the SRAM boundary cell region 32 can have a width of 10 poly-pitches measured in the x-direction. Of these 10 poly-pitches, 4 are designated for the trough-band cells, and 6 are designated for dummy cells, with OD breaks between the trough-band cells and the dummy cells. Furthermore, the logic edge cell area 42 has a width of 2.5 poly-pitches, which are designated for the dummy cells for the logic cells, with OD breaks between the trough ribbon cells in the SRAM edge cell area 32 and the logic edge cell area 42.Consequently, a distance S between the boundaries of the SRAM cell block 30 and the logic cell block 40 has 12.5 poly-pitches to reserve space for accommodating the SRAM edge cell area 32 and the logic edge cell area 42. Assume an SRAM cell 60, as shown in . Fig. As shown in Figure 4, which has a cell width of 2 poly-pitches, the reserved space between the SRAM cell block 30 and the logic cell block 40 occupies an area that could have filled 5 or 6 additional columns of SRAM cells, resulting in a considerable increase in the overall device size. Considering the above, it is evident that in a macro, usable area is occupied to an unreasonable extent if the SRAM cell block 30 is to have its own trough-band cells and associated additional dummy cells as insulating structures between the SRAM cells and the trough-band cells.

[0038] It will now be on Fig. 6. Referenced. Fig. Figure 6 shows simplified block diagrams 22C, 22D of a part of the circuit area 22, which is in Fig. Figure 1 shows the alternative embodiments to those (22A, 22B) in Fig. 5 are. Circuit area 22 can be implemented using either block diagram 22C or 22D, based on circuit performance requirements, but independently of each other. Alternatively, circuit area 22 can be implemented using either block diagram 22C or 22D, each in a different part of circuit area 22. For clarity, Fig. Section 6 has been simplified to make the inventive concepts of the present disclosure more understandable. Further structural elements may be used in block diagrams 22C and 22D, and some of the structural elements described below may be replaced, modified, or omitted in other embodiments of block diagrams 22C and 22D.

[0039] For the sake of simplicity and clarity, similar structural elements in block diagrams 22C and 22D are designated with the same reference numbers as in block diagrams 22A and 22B, and these similar aspects are not repeated. One difference between block diagrams 22C and 22D and block diagrams 22A and 22B is that SRAM cell block 30 adjoins logic cell block 40 without an intervening SRAM border cell area 32 and logic border cell area 42. In block diagram 22C, the logic-related circuits are located on a single side of SRAM cell block 30. In block diagram 22D, the logic-related circuits are located on both sides of SRAM cell block 30. The placement of the logic-related circuits on one or both sides of the memory-related circuits is determined by predefined design rules and / or circuit performance requirements.

[0040] Since the n-wells and p-wells in the SRAM cell block 30 also extend into the logic cell block 40 and the logic tap area 44, the tap cells in the logic tap area 44 can be configured to provide potential stability for wells not only for the logic cell block 40 but also for the SRAM cell block 30. Therefore, the well band cells are not required separately for the SRAM cell block 30, and dummy cells such as isolation structures between the SRAM cells and the OD breaks associated with the well band cells are no longer needed. Accordingly, the entire SRAM edge cell area 32 can be omitted.Furthermore, the dummy cells in the logic edge cell region 42, which act as isolation structures between the logic cells and the OD interruptions associated with the trough band cells, are no longer needed. The logic edge cell region 42, which originally bordered the SRAM edge cell region 32, can also be omitted. In other words, by sharing the function of the tap cells in the logic region between the SRAM cell block 30 and the logic cell block 40, the SRAM cell block 30 and the logic cell block 40 can be directly adjacent to each other, without the SRAM edge cell region 32 and the logic edge cell region 42 in between. As a result, the utilization of the usable area in a macro can be significantly improved. In some embodiments, a reduction of approximately 40% of the macro area can be achieved.

[0041] Fig. Figure 7 shows a layout 300A of a circuit area 50 of block diagram 22C and / or block diagram 22D in Fig. 6 according to the present disclosure, comprising a part of the SRAM cell block 30 and a part of the logic cell block 40, and extending across an interface between the SRAM cell block 30 and the logic cell block 40. For clarity, Fig. Figure 7 has been simplified to make the inventive ideas of the present disclosure more understandable. For example, active areas, gate structures, gate-section structural elements and vias Vo in the SRAM cells are shown, while other structural elements in Fig. Number 7 can be omitted.

[0042] The circuit area 50 comprises a first type of active areas 305A in the SRAM cell block 30 and a second type of active areas 305B in the logic cell block 40 (collectively referred to as active areas 305). The active areas 305A are arranged along the y-direction and oriented longitudinally in the x-direction. As discussed above, the active areas 305A can have different widths (e.g., W1-W4 in Fig. 4) exhibit. The active regions 305B are arranged along the y-direction and oriented longitudinally in the x-direction. In the illustrated embodiment, the active regions 305B are uniformly distributed along the y-direction, and each has a uniform width. Furthermore, the circuit region 50 has gate structures 340 that are arranged along the x-direction and extend longitudinally in the y-direction. In the illustrated embodiment, the gate structures 340 are uniformly distributed along the x-direction, with a uniform distance between two adjacent gate structures 340. The uniform distance is referred to as a gate pitch or a poly-pitch (“PP”). Gate-cutting structural elements, in particular the CMG structural elements 352, divide the otherwise continuous gate structures into isolated segments corresponding to the illustrated gate structures 340.The gate structures 340 intersect the active areas 305A and 305B, forming transistors. Transistors formed at the intersections of active areas 305A and gate structures 340 are located within SRAM cell block 30 and are intended for the formation of SRAM cells. Transistors formed at the intersections of active areas 305B and gate structures 340 are located within logic cell block 40 and are intended for the formation of logic cells.

[0043] In the illustrated embodiment, the transistors in the SRAM cell block 30 form a plurality of SRAM cells 302a, 302b, 302c, and 302d (collectively referred to as SRAM cells 302). The SRAM cells 302 are arranged in the x-direction and the y-direction, forming a 2x2 matrix of SRAM cells. Each SRAM cell 302 in the matrix can have the layout 200 of the SRAM cell 60, which is in Fig. Figure 4 illustrates this. In some embodiments, two adjacent SRAM cells are line-symmetric in the x-direction with respect to a common boundary between them, and two adjacent SRAM cells are line-symmetric in the y-direction with respect to a common boundary between them. That is, SRAM cell 302b is a duplicate of SRAM cell 302a, but flipped along the y-axis; SRAM cell 302c is a duplicate of SRAM cell 302a, but flipped along the x-axis; and SRAM cell 302d is a duplicate of SRAM cell 302b, but flipped along the x-axis.

[0044] Some active regions 305 extend through several SRAM cells in a row. For example, the active region for transistors PD-1, PG-1 in SRAM cell 302b extends through SRAM cell 302a as the active region for their transistors PG-1, PD-1; the active region for transistors PG-2, PD-2 in SRAM cell 302b extends through SRAM cell 302a as the active region for their transistors PD-2, PG-2; and the active region for transistor PU-2 in SRAM cell 302b extends into SRAM cell 302a as the active region for their transistor PU-2. The active regions in SRAM cells 302c, 302d are arranged similarly.

[0045] In the illustrated embodiment, the transistors in the logic cell block 40 form a plurality of logic cells. The logic cells can be standard cells, such as Inventor (INV), AND, OR, NAND, NOR, Flip-flip, SCAN, and so on. The logic cells implement various logic functions for the SRAM cells 302. The logic functions of the logic cells include, for example, write and / or read decoding, word line selection, bit line selection, data control, and memory self-checking.

[0046] Between the opposing boundary lines of the SRAM cells and the logic cells is an active-area transition region 370, also referred to as the OD transition region or simply the transition region. In transition region 370, the active areas 305A, extending from the edge column of the SRAM cells, meet the active areas 305B, extending from the edge column of the logic cells. Since a pair of meeting active areas 305A and 305B have different widths, an OD jump is created where the active areas 305A and 305B meet. A jump is a junction where two segments of different widths meet. For example, in region 372A, marked by a circle with a dashed line, a relatively wide active area 305A meets a relatively narrow active area 305B, creating an OD jump.The upper edges of active areas 305A and 305B are in a straight line, while their lower edges form a stepped profile. Similarly, in area 372B, marked by another dashed circle, a relatively narrow active area 305A and a relatively wide active area 305B meet, creating another OD jump. The lower edges of active areas 305A and 305B are in a straight line, while their upper edges form a stepped profile.

[0047] As shown in layout 300A, the transition region 370 spans three poly-pitches between the opposing boundary lines of the SRAM cells and the logic cells along the x-direction. In the transition region 370, a plurality of dielectric structural elements 374 are arranged along the x-direction and oriented longitudinally in the y-direction. The dielectric structural elements 374 provide insulation between the active regions 305A and 305B. In layout 3004, the dielectric structural elements 374 extend continuously along the boundary lines of the SRAM cells and the logic cells in the y-direction. In other words, the dielectric structural elements 374 are taller than the SRAM cell height H. In layout 300A, the dielectric structural elements 374 are at least twice the SRAM cell height H. In some embodiments, the SRAM matrix has approximately 100000 SRAM cells in a column, and the dielectric structural elements 374 can extend continuously in the y-direction along the boundary line of the edge column. That is, the ratio of the length of the dielectric structural elements 374 to the SRAM cell height H can be as large as approximately 100,000 : 1. The length of the dielectric structural elements 374, measured in micrometers (µm), can be 150 µm in some embodiments.

[0048] The dielectric structural elements 374 are fabricated in a continuous poly-on-diffusion-edge (CPODE) process. In a CPODE process, a polysilicon gate is replaced by a dielectric structural element. For the purposes of this disclosure, a "diffusion edge" can be equivalently referred to as an active edge, where, for example, an active edge borders adjacent active regions. Prior to the CPODE process, the active edge may comprise a dummy GAA structure with a dummy gate structure (e.g., a polysilicon gate) and a plurality of vertically stacked nanostructures as channel layers. Furthermore, internal spacers may be arranged between adjacent nanostructures at the lateral ends of the nanostructures.In various examples, epitaxial source / drain structural elements are arranged on each side of the dummy GAA structure, such that the adjacent epitaxial source / drain structural elements are in contact with the internal spacers and nanostructures of the dummy GAA structure. The subsequent CPODE etching process removes the dummy gate structure and channel layers from the dummy GAA structure to form a CPODE trench. The dielectric material used to fill a CPODE trench for insulation is referred to as a CPODE structural element. In some embodiments, after the formation of the CPODE structural elements, the remaining dummy gate structures are replaced by metal gate structures in a gate-last process.In other words, in some embodiments, the otherwise continuous gate structure is partially or completely replaced by the CPODE structural element, and the CPODE structural element is enclosed between the opposing gate spacers of the replaced portion of the gate structure. In contrast, the CMG structural element truncates the otherwise continuous gate structure and extends into adjacent areas of the gate structure. Accordingly, circuit area 50 in layout 300A comprises two types of gate-cutting structural elements. The first gate-cutting structural elements are the CMG structural elements 352, which, in the illustrated embodiment, are located in the SRAM cells or logic cells but not in the transition area 370. The CMG structural elements 352 extend longitudinally along the x-direction.The second gate-section structural elements are the CPODE structural elements 374, which are arranged in the transition region 370. The CPODE structural elements 374 extend longitudinally along the y-direction.

[0049] Since the CPODE structural elements 374 are produced by replacing the previously manufactured polysilicon gate structures, the arrangement of the gate structures 340 is adopted by the CPODE structural elements 374. That is, the CPODE structural elements 374 can have the same width and pitch as the gate structures 340. Because the transition region 370 spans three poly-pitches and contains three polysilicon gates that were placed there before the CPODE process, there are three CPODE structural elements 374 after the CPODE process, arranged in the transition region 370 as shown in layout 300A. The leftmost CPODE structural element 374 borders the active regions 305A, and the rightmost CPODE structural element 374 borders the active regions 305B.The segments of active regions 305A and 305B, located between the outermost left and outermost right CPODE structural elements 374, are effectively separated from the main parts of active regions 305A and 305B and can be considered active dummy regions or dummy ODs. Two dummy OD segments from the same row, one from the end of active region 305A and another from the end of active region 305B, are located between the three CPODE structural elements 374. These two dummy OD segments can also be considered the OD jump.

[0050] Fig. Figure 8 is a fragmentary schematic sectional view along line AA of Fig. 7, which intersects a pair of active areas 305A and 305B. Active area 305A extends continuously through SRAM cells 302a, 302b (and other SRAM cells in the same row of a memory matrix). Active area 305B extends continuously through the logic cells in the same row of a logic matrix. Active areas 305A, 305B are arranged on an identical continuous p-trough that extends across SRAM cell block 30, logic cell block 40, and logic tap area 44 ( Fig. 6) extends and is biased to a supply voltage by the tap cells in the logic tap area 44. In other words, the tap cells in the logic tap area 44 also bias the wells for the SRAM cells in the SRAM cell block 30. Each of the active areas 305A, 305B comprises channel areas formed by the nanostructures 376 and source / drain structural elements 378 adjacent to the ends of the nanostructures 376. The gate structures 340 enclose the nanostructures 376 and form the transistors PG-2, PD-2 in SRAM cell 302b, the transistors PD-2, PG-2 in SRAM cell 302a, and the logic transistors in the logic cells. The CPODE structural elements 374 otherwise replace three gate structures 340 in the row. Source / Drain structural elements 378 are also arranged on side walls of the CPODE structural element 374.As also shown in the sectional view, the CPODE structural element has a width, designated E, and a depth, designated D. In some embodiments, the CPODE width E is in a range of approximately 15 nm to approximately 20 nm; the CPODE depth D is in a range of approximately 150 nm to approximately 250 nm. If the depth D is less than approximately 150 nm, the insulation performance may be impaired; if the depth D is greater than approximately 250 nm, the CPODE structural element 374 may extend too deeply into the well (e.g., the p-well 204P in [reference]). Fig. 8) extend, and the bias from the tap cells in the logic area may be insufficient to bias the well in the SRAM area. The CPODE structural elements 374 may extend deeper downwards than the CMG structural elements 352. As also shown in the sectional view, there are no OD breaks in the transition area 370.

[0051] Fig. Figure 7 shows all CPODE structural elements 374 as continuous lines, while the CPODE structural elements 374 in different embodiments can be continuous lines or can have the form of islands. Fig. Figure 9 shows a layout 300B of circuit area 50, in which at least some of the CPODE structural elements have the form of islands. Referring to Fig. For the sake of clarity and simplicity, similar elements in layouts 300A and 300B are designated by the same reference numbers, and these similar aspects are not repeated. One difference between layouts 300A and 300B is that the central CPODE structural elements in layout 300b are not a continuous line but several islands distributed in the y-direction. Each central CPODE structural element 374 extends longitudinally along the y-direction and separates at least one pair of the active areas 305A, 305B at the OD jump. In the embodiment shown in Fig. 9 Each central CPODE structural element 374 separates two pairs of the active regions 305A, 305B. The length of the central CPODE structural element 374, measured in the y-direction, can be at least 5 nm in some embodiments. The length of the central CPODE structural element 374 can be less than the SRAM cell height H or even less than half the SRAM cell height H.

[0052] Fig. Figure 7 shows that all gate structures in the transition region 370 have been replaced by the CPODE structural elements 374, while in various embodiments some gate structures may remain in the transition region 370. Fig. Figure 10 shows a layout 300C of circuit area 50, in which at least some of the gate structures 340 remain in the transition area 370. With reference to Fig. For the sake of clarity and simplicity, similar elements in layouts 300A and 300C are designated by the same reference numbers, and these similar aspects are not repeated. One difference between layouts 300A and 300C is that in layout 300C, the gate structures 340 remain between the leftmost and rightmost CPODE structure elements 374. The remaining gate structures 340 are located across the OD jumps. Isolation between active regions 305A and 305B is provided by two CPODE structure elements 374. In contrast, in layout 300A or layout 300B, isolation between active regions 305A and 305B is provided by three CPODE structure elements 374.

[0053] Similarly, it shows Fig. 11 a layout 300D of the circuit area 50, in which at least some of the gate structures 340 remain in the transition area 370. With reference to Fig. For the sake of clarity and simplicity, similar elements in layouts 300A and 300D are designated by the same reference numbers, and these similar aspects are not repeated. One difference between layouts 300A and 300D is that the gate structures 340 remain in the leftmost and rightmost columns of the transition area 370, with a CPODE structural element 374 located between them, positioned above the OD jumps. Isolation between the active areas 305A and 305B is provided by the single CPODE structural element 374. It should be noted that the CMG structural elements 352 are located in the Fig. In the embodiment shown in Figure 11, the gate structure lines extend into the transition region 370 to divide the otherwise continuous gate structure lines into segments corresponding to the gate structures 340 in the transition region 370. In other words, in such an embodiment, the transition region 370 has two types of gate cut structural elements, namely the CPODE structural element 374 and the CMG cut structural elements 352.

[0054] Layouts 300A-300D show the transition area 370 extending over three poly-pitches in the x-direction, while in various embodiments the transition area 370 may extend over fewer than three poly-pitches. Fig. Figure 12 shows a layout 300E of circuit section 50, in which the transition section 370 extends over two poly-pitches in the x-direction. Referring to Fig. For clarity and simplicity, similar elements in layouts 300A and 300E are designated by the same reference numbers, and these similar aspects are not repeated. One difference between layouts 300A and 300E is that the transition area 370 in layout 300E spans two poly-pitches and contains two CPODE structure elements 374. The active areas located between the two CPODE structure elements 374 are considered dummy ODs with OD jumps. The OD jumps are located between the two CPODE structure elements 374. A distance from the position of the OD jump to one of the CPODE structure elements 374 is referred to as an offset S1. The position of the OD jump does not have to be exactly at the midpoint of the two CPODE structure elements 374. The ratio of S1 to the poly-pitch can range from approximately 0.1 to approximately 1.Similar to the preceding discussion, the CPODE structural elements 374 can have the form of continuous lines or islands, as long as sufficient insulation can be provided. In some embodiments, the length of the CPODE structural element 374, measured in the y-direction, is in the range of about 0.2 µm to about 150 µm.

[0055] Fig. Figure 13 is a fragmentary schematic sectional view along line AA of Fig. 12, which intersects a pair of active regions 305A and 305B. Referring to Fig. For the sake of clarity and simplicity, 13 similar elements will be used in the Fig. 8 and Fig. 13 are designated by the same reference numbers, and these similar aspects are not repeated. A difference between the sectional views in the Fig. 8 and Fig. 13 consists in the fact that the transition area 370 in Fig. 13 in the x-direction spans two poly pitches, which is one less than in Fig. 8, and the transition area 370 in Fig. 13 has two CPODE structural elements 374, which is one less than in Fig. 8.

[0056] Layouts 300A-300D show the transition area 370 extending over three poly-pitches in the x-direction, while in various embodiments the transition area 370 may extend over fewer than three poly-pitches. Fig. Figure 14 shows a layout of circuit section 50, in which the transition section 370 extends over a poly-pitch in the x-direction. Referring to Fig. For the sake of clarity and simplicity, similar elements in layouts 300A and 300F are designated by the same reference numerals, and these similar aspects are not repeated. One difference between layouts 300A and 300F is that the transition region 370 in layout 300F extends over a single poly-pitch and has a single CPODE structural element 374. This single CPODE structural element 374 overlaps the OD jumps. Similar to the preceding discussion, the CPODE structural element 374 can have the form of a continuous line or the form of islands, as long as sufficient isolation can be provided. In some embodiments, the length of the CPODE structural element 374, measured in the y-direction, is in the range of about 0.2 µm to about 150 µm.

[0057] Fig. Figure 15 is a fragmentary schematic sectional view along line AA of Fig. 14, which intersects a pair of active regions 305A and 305B. Referring to Fig. For the sake of clarity and simplicity, 15 similar elements will be included in the Fig. 8 and Fig. 15a is designated by the same reference numbers, and these similar aspects are not repeated. A difference between the sectional views in the Fig. 8 and Fig. 15 consists in the fact that the transition area 370 in Fig. 15 in the x-direction extends over one poly-pitch, i.e., two fewer than in Fig. 8, and the transition area 370 in Fig. 15 has a single CPODE structural element 374, i.e., two fewer than in Fig.8. It should be noted that although various embodiments of the transition region 370 with a span (width) of one, two, and three poly-pitches are shown in the present disclosure, other embodiments consider other numbers of poly-pitches. For example, the transition region 370 may have a width extending over N poly-pitches, where N is an integer, such as 1, 2, 3, 4, 5, 6, and so on.

[0058] From the foregoing, it is evident that the present disclosure offers advantages over conventional semiconductor structures. However, it is clear that other embodiments may offer other advantages, not all advantages are necessarily discussed here, and no specific advantage is required for all embodiments. For example, the present disclosure provides a memory macro in which the memory cell block and the logic cell block can be adjacent to one another by sharing the access cells for the logic cell block with the memory cell block. Edge cells, which are conventionally inserted between the memory cell block and the logic cell block, may then no longer be required. A memory macro area can be reduced by more than 40% in some embodiments.

[0059] In one exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure comprises: a memory cell, a logic cell configured to provide a logic function to the memory cell, and an interface between the memory cell and the logic cell. The memory cell includes at least one first active region extending longitudinally in a first direction and a plurality of first gate structures extending longitudinally in a second direction perpendicular to the first direction and spaced apart in the first direction by a gate pitch. The logic cell includes a second active region extending longitudinally in the first direction and a plurality of second gate structures extending longitudinally in the second direction and spaced apart in the first direction by the gate pitch.The transition region comprises a first dielectric structural element extending longitudinally in the second direction and a second dielectric structural element extending longitudinally in the second direction. The first dielectric structural element divides the first active region into a first segment that is partially within the transition region and a second segment that is entirely within the transition region. The second dielectric structural element divides the second active region into a third segment that is partially within the transition region and a fourth segment that is entirely within the transition region. In some embodiments, the first dielectric structural element is spaced from one of the first gate structures by the gate pitch. In some embodiments, the second dielectric structural element is spaced from one of the second gate structures by the gate pitch.In some embodiments, the width of the transition region, measured in the first direction, is an integer multiple of the gate pitch. In some embodiments, the second segment of the first active region borders the fourth segment of the second active region. In some embodiments, the transition region has a plurality of third gate structures, one of which is located over an interface between the second segment of the first active region and the fourth segment of the second active region. In some embodiments, the transition region has a third dielectric structural element that extends longitudinally in the second direction and between the first and second dielectric structural elements.In some embodiments, the third dielectric structural element separates the second segment of the first active region in such a way that it does not contact the fourth segment of the second active region. In some embodiments, the third dielectric structural element has a length, measured in the second direction, that is shorter than that of the first and second dielectric structural elements. In some embodiments, the memory cell has a gate-cut structural element that is adjacent to one of the first gate structures and extends longitudinally in the first direction. In some embodiments, the gate-cut structural element extends into the transition region.

[0060] In another exemplary aspect, the present disclosure relates to an integrated circuit layout. The integrated circuit layout comprises: a memory circuit with a first boundary, a logic circuit with a second boundary, and a transition region extending from an edge of the first boundary to an edge of the second boundary, with a width equal to an integer multiple of the gate pitch. The memory circuit includes a plurality of first active regions and a plurality of first gate structures across the first active regions, the first gate structures having a gate pitch. The logic circuit includes a plurality of second active regions and a plurality of second gate structures across the second active regions, the second gate structures having a gate pitch equal to the gate pitch.The transition region comprises at least one dielectric structural element that separates the first active regions so that they do not contact the second active regions. In some embodiments, the transition region has a width of one gate pitch, and the at least one dielectric structural element has a first side wall that contacts the first active regions and a second side wall that contacts the second active regions. In some embodiments, the transition region has a width of two gate pitches, and the transition region has a first and a second dielectric structural element that are spaced apart from each other by one gate pitch. In some embodiments, the transition region has a width of three gate pitches, and the at least one dielectric structural element is arranged on a centerline of the transition region.In some embodiments, the transition region has a width of three gate pitches, and the transition region comprises a first and a second dielectric structural element spaced apart by two gate pitches, and comprises a plurality of third gate structures arranged between the first and the second dielectric structural element. In some embodiments, the transition region has a width of three gate pitches, and the transition region comprises a first, a second, and a third dielectric structural element spaced from their neighbors by the gate pitch.

[0061] In yet another exemplary aspect, the present disclosure relates to a static random-access memory (SRAM) circuit. The SRAM circuit comprises an SRAM cell with a first pass-gate transistor and a first pull-down transistor fabricated on a first active region, and a second pass-gate transistor and a second pull-down transistor fabricated on a second active region, wherein the first and second active regions extend longitudinally in a first direction, and a dielectric structural element extending longitudinally in a second direction perpendicular to the first direction, the dielectric structural element having a side wall in contact with the first active region and the second active region.In some embodiments, the first pass-gate transistor has a first gate structure extending longitudinally in the second direction, the first pull-down transistor has a second gate structure extending longitudinally in the second direction, and the first gate structure, the second gate structure, and the dielectric structural element are uniformly spaced along the first direction. In some embodiments, the length of the dielectric structural element measured in the second direction is greater than the height of the SRAM cell measured in the second direction.

Claims

[1] Semiconductor structure with: a memory cell (30); a logic cell (40) configured to provide a logic function for the memory cell (30); and a transition area (370) between the memory cell (30, 352) and the logic cell (40), where: the memory cell (30) has at least one first active area (305A) extending longitudinally in a first direction and a plurality of first gate structures (340) extending longitudinally in a second direction perpendicular to the first direction and spaced apart from each other in the first direction by a gate pitch, the logic cell (40) has a second active area (305B) extending longitudinally in the first direction and a plurality of second gate structures (340) extending longitudinally in the second direction and spaced apart from each other in the first direction by the gate pitch, the transition region (370) has a first dielectric structural element (374) extending longitudinally in the second direction, and a second dielectric structural element (374) extending longitudinally in the second direction, the first dielectric structural element (374) divides the first active region (305A) into a first segment that is partially in the transition region (370) and a second segment that is completely in the transition region (370), and the second dielectric structural element (374) divides the second active region (305B) into a third segment, which is partially in the transition region (370), and a fourth segment, which is completely in the transition region (370). [2] Semiconductor structure according to claim 1, wherein the first dielectric structural element (374) is spaced apart from one of the first gate structures (340) by the gate pitch. [3] Semiconductor structure according to claim 1 or 2, wherein the second dielectric structural element (374) is spaced apart from one of the second gate structures (340) by the gate pitch. [4] Semiconductor structure according to one of the preceding claims, wherein a width of the transition region (370) measured in the first direction is an integer multiple of the gate pitch. [5] Semiconductor structure according to one of the preceding claims, wherein the second segment of the first active region (305A) is adjacent to the fourth segment of the second active region (305B). [6] Semiconductor structure according to one of the preceding claims, wherein the transition region (370) has a plurality of third gate structures, one of the third gate structures being arranged over an interface between the second segment of the first active region (305A) and the fourth segment of the second active region (305B). [7] Semiconductor structure according to one of claims 1 to 4, wherein the transition region (370) has a third dielectric structural element (374) extending longitudinally in the second direction and between the first dielectric structural element (374) and the second dielectric structural element (374). [8] Semiconductor structure according to claim 7, wherein the third dielectric structural element (374) separates the second segment of the first active region (305A) in such a way that it does not contact the fourth segment of the second active region (305B). [9] Semiconductor structure according to claim 7 or 8, wherein the third dielectric structural element (374) has a length measured in the second direction that is smaller than the first dielectric structural element (374) and the second dielectric structural element (374). [10] Semiconductor structure according to one of the preceding claims, wherein the memory cell (30) has a gate-cut structural element adjacent to one of the first gate structures (340) and extending longitudinally in the first direction. [11] Semiconductor structure according to claim 10, wherein the gate cut structural element extends into the transition region (370). [12] Integrated circuit layout with: a memory circuit with a first boundary, wherein the memory circuit has the following: a majority of first active areas (305A), and a plurality of first gate structures (340) across the first active areas, wherein the first gate structures (340) have a gate pitch; a logic circuit with a second boundary, wherein the logic circuit has the following: a plurality of second active areas (305B), and a plurality of second gate structures (340) across the second active areas, wherein the second gate structures (340) have the gate pitch; and a transition region (370) extending from an edge of the first boundary to an edge of the second boundary with a width equal to an integer multiple of the gate pitch, wherein the transition region has the following: at least one dielectric structural element (374) that separates the first active regions in such a way that they do not contact the second active regions. [13] Integrated circuit layout according to claim 12, wherein the transition region (370) has a width of one gate pitch, and the at least one dielectric structural element (374) has a first side wall contacting the first active areas (305A) and a second side wall contacting the second active areas (305A). [14] Integrated circuit layout according to claim 12, wherein the transition region (370) has the width of two gate pitches, and the transition region (370) comprises a first dielectric structural element (374) and a second dielectric structural element (374) spaced apart from each other by a gate pitch. [15] Integrated circuit layout according to claim 12, wherein the transition region (370) has the width of three gate pitches, and the at least one dielectric structural element (374) is arranged on a center line of the transition region (370). [16] Integrated circuit layout according to claim 12, wherein the transition region (370) has a width of three gate pitches, and the transition region (370) comprises a first dielectric structural element (374) and a second dielectric structural element (374) spaced apart by two gate pitches, and comprises a plurality of third gate structures arranged between the first dielectric structural element (374) and the second dielectric structural element (374). [17] Integrated circuit layout according to claim 12, wherein the transition region (370) has the width of three gate pitches, and the transition region (370) comprises a first, a second and a third dielectric structural element (374) spaced apart from the adjacent ones by the gate pitch. [18] SRAM drivetrain with: an SRAM cell (60, 302) comprising a first pass-gate transistor (PG-1) and a first pull-down transistor (PD-1) fabricated on a first active region (305A), and a second pass-gate transistor (PG-2) and a second pull-down transistor (PD-2) fabricated on a second active region, the first and second active regions extending longitudinally in a first direction; and a dielectric structural element (374) which extends longitudinally in a second direction perpendicular to the first direction, wherein the dielectric structural element (374) has a side wall which is in contact with the first active area (305A) and the second active area (305B). [19] SRAM circuit according to claim 18, wherein the first pass-gate transistor (PG-1) has a first gate structure (340) extending longitudinally in the second direction, the first pull-down transistor (GD-1) has a second gate structure (340) extending longitudinally in the second direction, and the first gate structure (340), the second gate structure (340) and the dielectric structural element (374) are spaced evenly along the first direction. [20] SRAM circuit according to claim 18 or 19, wherein a length of the dielectric structural element (374) measured in the second direction is greater than a height of the SRAM cell (60) measured in the second direction.

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