UNIQUELY PROGRAMMABLE STORAGE DEVICES

Abstract

A storage device is disclosed. The storage device comprises a memory matrix with a plurality of memory cells. At least one of the memory cells permanently represents a first logical state based on a short circuit. At least one of the memory cells permanently represents a second logical state, opposite to the first logical state, based on an open circuit.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 578,204, filed August 23, 2023, entitled "OTP MEMORY ARRAY WITH DEFAULT DATA BITS," which is incorporated by reference into the present application. BACKGROUND

[0002] In general, there are two main types of data storage devices. The first type is a volatile storage device, in which information stored in a particular storage device is lost when the power to the storage device is interrupted. The second type is a non-volatile storage device, in which the information is retained even after the power is interrupted. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 shows a block diagram of an example memory device with a memory array according to some embodiments. Fig. Figure 2 shows a schematic diagram of part of the memory matrix of Fig. 1, in which each of its memory cells is implemented as an eFuse memory cell according to some embodiments. Fig. 3 shows an example layout configured to form a non-preconfigured eFuse cell according to some embodiments. Fig. 4 shows an example layout configured to form a default 0 eFuse cell according to some embodiments. Fig. 5 shows an example layout configured to form a default 1 eFuse cell according to some embodiments. The Fig. 6 and Fig. 7 show sectional views of a semiconductor device based on the layout of Fig. 3 is manufactured according to some embodiments. The Fig. 8, Fig. 9 and Fig. 10 show sectional views of a semiconductor device based on the layout of Fig. 4 is manufactured according to some embodiments. The Fig. 11, Fig. 12 and Fig. 13 show sectional views of a semiconductor device based on the layout of Fig. 5 is manufactured according to some embodiments. Fig. 14 shows a flow diagram of an example method for manufacturing a memory device having a non-preconfigured eFuse cell, a default 0 eFuse cell, and a default 1 eFuse cell, according to some embodiments. Fig. Figure 15 shows a schematic diagram of part of the memory matrix of Fig. 1, in which each of its memory cells is implemented as an antifuse memory cell according to some embodiments. Fig. 16 shows an exemplary schematic diagram of a non-preconfigured antifuse cell according to some embodiments. Fig. 17 shows an exemplary schematic diagram of a default 0 antifuse cell according to some embodiments. Fig. 18 shows an exemplary schematic diagram of a default 1 antifuse cell according to some embodiments. Fig. 19 shows an example layout configured to form a number of antifuse cells according to some embodiments. Fig. 20 shows a flow diagram of an example method for manufacturing a memory device having a non-preconfigured antifuse cell, a default 0 antifuse cell, and a default 1 antifuse cell, according to some embodiments. Fig. 21 shows a flowchart of an example method for testing a memory device according to some embodiments. DETAILED DESCRIPTION

[0004] The present disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0006] A one-time programmable (OTP) memory device is one of various types of non-volatile memory devices. Example implementations of the OTP memory device include metal fuses, gate oxide fuses, and so on. The metal fuse uses a metal resistor that serves as a programming element of the corresponding OTP memory device. Such a metal fuse is sometimes referred to as an eFuse memory device, in which the metal resistor can typically be programmed (e.g., once). The programming process typically involves blowing the metal resistor from a short circuit to an open circuit. The gate oxide fuse uses a gate oxide (or another gate dielectric material, such as a high-k dielectric material) as a programming element of the corresponding OTP memory device.The gate oxide fuse is sometimes referred to as an antifuse memory device, where the gate oxide can typically be programmed (e.g., once). The programming process typically involves breaking the gate oxide from an open circuit to a short circuit.

[0007] The OTP memory device is commonly used in integrated circuits to adjust circuits after an integrated circuit has been fabricated. For example, the OTP memory device is used to provide repair information that controls the use of redundant cells to replace defective cells of a memory array. Another use is to tune analog circuits by adjusting a capacitive or resistive value of an analog circuit or enabling and disabling parts of the system. In yet another example, a recent trend is to use a memory array with a plurality of OTP memory cells to test peripheral circuits that are operatively connected to the memory array or integrated into the memory array.Such a peripheral circuit includes a sense amplifier, which is typically configured to access (e.g., read) the OTP memory cells. In existing technologies, one or more of the OTP memory cells are preconfigured to represent a specific logical state. Using the preconfigured logical states at the known positions (i.e., the known OTP memory cells) of the memory array, the peripheral circuit can be verified. For this purpose, these OTP memory cells are each programmed to the preconfigured logical state through a series of the aforementioned programming processes.

[0008] With advances in IC technology, more circuitry can be implemented in an integrated circuit. In other words, various device structural elements of an integrated circuit are generally arranged in a more compact manner. The programming process of an OTP memory device (or cell) is typically associated with applying a high voltage to its programming element or passing a high current through its programming element. Such a strong (voltage / current) signal used during the programming process may inadvertently damage other device structural elements (e.g., the OTP memory cells that are not preconfigured to represent a logic state). Furthermore, the programming process typically consumes additional power, e.g., due to the applied strong signal.Consequently, existing OTP storage devices have not been entirely satisfactory in certain aspects.

[0009] The present disclosure provides various embodiments of a one-time programmable (OTP) memory device comprising a number of memory cells, each of which represents a preconfigured logic state by default, without any programming process. In one aspect of the present disclosure, the memory cells disclosed herein may each be an eFuse (eFuse: electronical fuse) memory cell. The eFuse memory cell may be operatively formed as a transistor and a fuse resistor connected in series. In these embodiments, the eFuse memory cell representing a logic 1 (hereinafter, a "default 1 eFuse cell") may be formed based on an open circuit, and the default memory cell representing a logic 0 (hereinafter, a "default 0 eFuse cell") may be formed based on a short circuit.For example, the open circuit may be formed by electrically disconnecting various metal traces of the default 1 eFuse cell, and the short circuit may be formed by electrically connecting various metal traces of the default 0 eFuse cell. In another aspect of the present disclosure, the memory cells disclosed herein may each be an antifuse memory cell. The antifuse memory cell may be operatively formed as a programming transistor and a sense resistor connected in series with each other. In these embodiments, the antifuse memory cell representing logic 1 (hereinafter, "default 1 antifuse cell") may be formed based on an open circuit, and the default memory cell representing logic 0 (hereinafter, "default 0 antifuse cell") may be formed based on a short circuit.For example, the open circuit may be formed by using a programming transistor with a relatively high threshold voltage for the default 1 antifuse cell, and the short circuit may be formed by using a programming transistor with a relatively low threshold voltage for the default 0 antifuse cell.

[0010] Fig. 1 shows a block diagram of a memory device 100 according to various embodiments. In the illustrated embodiment of Fig. 1, the memory device 100 comprises a memory matrix 102, a row decoder 104, a column decoder 106, an input / output (I / O) circuit 108, and a control logic circuit 110. Although not explicitly shown in Fig. 1, all components of the memory device 100 may be connected to each other and to the control logic circuit 110. Although in the illustrated embodiment of Fig. 1 for clarity each component is shown as a separate block, in some other embodiments some or all of the components shown in Fig. 1 may be integrated together. For example, memory array 102 may include embedded I / O circuitry (e.g., 108).

[0011] The memory array 102 is a hardware component that stores data. In various embodiments, the memory array 102 is implemented as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or other memory units) 103. The memory array 102 includes a number of rows R1, R2, R3...R M , each extending in a first direction (e.g. an x-direction), and a number of columns C1, C2, C3...C N, each extending in a second direction (e.g., a y-direction). Each of the rows and columns may include one or more conductive structures (e.g., metal structures) that function as access lines. Each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column and may be operated according to the voltages and currents through the respective conductive structures of the column and row. For example, each of the rows may include one or more corresponding word lines (WLs), and each of the columns may include one or more corresponding bit lines (BLs).

[0012] In some embodiments, each memory cell 103 is implemented as an eFuse memory cell, which may include a fuse resistor and a WL transistor. The fuse resistor and the WL transistor are connected in series with each other. Furthermore, a corresponding WL may be connected to a gate terminal of the WL transistor. The fuse resistor may have a first end connected to a corresponding BL and a second end connected to a first source / drain terminal of the WL transistor. A second source / drain terminal of the WL transistor may be connected to a supply voltage (e.g., ground). Details of the eFuse memory cell are described with reference to Fig. 2 is discussed in more detail.

[0013] In some embodiments, each memory cell 103 is implemented as an antifuse memory cell, which may include a programming transistor and a read transistor. The programming transistor and the read transistor are connected in series with each other. Furthermore, a corresponding programming WL may be connected to a gate terminal of the programming transistor, and a corresponding read WL may be connected to a gate terminal of the read transistor. A corresponding BL may be connected to a first source / drain terminal of the read transistor, with a second source / drain terminal of the read transistor connected to a first source / drain terminal of the programming transistor. A second source / drain terminal of the programming transistor may be floating. Details of the antifuse memory cell are described with reference to Fig. 3 is discussed in more detail.

[0014] Row decoder 104 is a hardware component that can receive a row address of memory array 102 and control a conductive structure (e.g., the word line) at that row address. Column decoder 106 is a hardware component that can receive a column address of memory array 102 and control a conductive structure (e.g., the bit line) at that column address. I / O circuit 108 is a hardware component that can access (e.g., read, program) each of the memory cells 103 controlled by row decoder 104 and column decoder 106. Control logic circuit 110 is a hardware component that can control the connected components (e.g., 102 to 108).

[0015] Fig. 2 shows a schematic Fig. a portion of the memory device 100 (e.g., some of the memory cells 103), in which each of the memory cells 103 is implemented as an eFuse memory cell according to some embodiments. In the illustrated examples of Fig. 2 are eFuse memory cells 103 00 , 103 01 , 103 02 , 103 03 , 103 10 , 103 11 , 103 12 , 103 13 , 103 20 , 103 21 , 103 22 , 103 23 , 103 30 , 103 31 , 103 32 and 103 33 of the memory matrix 102, where the first subscript and the second subscript may represent their corresponding row and column, respectively. Although sixteen eFuse memory cells 103 00 up to 103 33 , it is understood that the memory array 102 may include any number of similar eFuse memory cells without departing from the scope of the present disclosure.

[0016] As shown, each of the eFuse memory cells 103 00 up to 103 33 a fuse resistor and a WL transistor connected in series, or consists of these and each of the eFuse memory cells 103 00 up to 103 33 is operatively connected to a WL and a BL located in the corresponding row and column, respectively. Using the eFuse memory cell 103 00 As a representative example, the eFuse memory cell 103 00a fuse resistor 210 and a WL transistor 220 connected in series, and it is arranged at an intersection point of BL0 and WL0 (column C0 and row R0). The fuse resistor 210 has one end connected to BL0 and the other end connected to a first source / drain terminal of the WL transistor 220. The WL transistor 220 has a second source / drain terminal connected to ground and a gate terminal connected to WL0.

[0017] In some embodiments, the WL transistor 220 may be formed along the main surface of a substrate (sometimes referred to as part of the "front-end-of-line (FEOL) process / network"). Such a transistor may sometimes be referred to as an FEOL transistor. A number of metallization layers may be fabricated over the FEOL network (sometimes referred to as part of the "back-end-of-line (BEOL) process / network"). The fuse resistor 210 may be fabricated in the BEOL network or through the BEOL network. For example, the fuse resistor 210 may include a number of metal traces arranged in one or more corresponding metallization layers.Depending on whether the eFuse memory cell is preconfigured as a default 0 eFuse cell or a default 1 eFuse cell, some of the metal traces are electrically connected to each other or electrically isolated from each other. Consequently, these default eFuse cells can each permanently represent a preconfigured logic state after their manufacture (or fabrication). In other words, the default eFuse cells disclosed herein cannot be further programmed to represent a desired logic state after their manufacture, and consequently, such a logic state cannot be changed.

[0018] In Fig. 2, for example, of the eFuse memory cells, 103 00 up to 103 33 , the eFuse memory cells 103 21 and the eFuse memory cells 103 12as a default 0 eFuse cell (default 0) or a default 1 eFuse cell (default 1), respectively, while other eFuse cells remain as virgin eFuse cells. The term "virgin eFuse cell" used here may refer to an eFuse cell that represents a short circuit (or logic 0) in the as-manufactured state and can be programmed to represent an open circuit (or logic 1). Unlike the non-preconfigured eFuse cells, the eFuse cell 103 21 represent a logical 0 in the manufactured state, and cannot be programmed to a logical 1, and the eFuse memory cell 103 12can represent a logic 1 in the as-manufactured state and cannot be programmed to a logic 0. Respective structures or configurations of the non-preconfigured eFuse cell, the default 0 eFuse cell and the default 1 eFuse cell are described with reference to the Fig. 3, Fig. 4 and 5 respectively are discussed in further detail.

[0019] Although a default 0 eFuse cell and a default 1 eFuse cell are provided in the illustrative embodiment of Fig. 2, it is understood that an array may include any number of default 0 eFuse cells and any number of default 1 eFuse cells. Furthermore, in some embodiments, respective positions of the one or more default 0 eFuse cells and the one or more default 1 eFuse cells in the array may also be preconfigured. If the positions of these default cells in an array are known, respective functionalities of one or more peripheral circuits (e.g., sense amplifiers) operatively connected to the array may be verified. For example, the logical state of a default cell, and where such a default cell is located in an array, may be preconfigured (e.g., known).If a sense amplifier operatively connected to the default cell reads a logical state that conflicts with the preconfigured logical state, the sense amplifier may be determined to be malfunctioning. As another example, given that the logical state and position of a default cell are both preconfigured and an operatively connected sense amplifier has been determined to be malfunctioning, one or more peripheral circuits (e.g., a corresponding column decoder and / or a corresponding row decoder) may be determined to be malfunctioning if the sense amplifier still reads a conflicting logical state.

[0020] With reference first to Fig. 3 shows an exemplary layout 300 used to manufacture the non-preconfigured eFuse cell (e.g., 103 00 from Fig. 2) can be used according to various embodiments. As mentioned above, the non-preconfigured eFuse cell disclosed herein is formed from a WL transistor and a fuse resistor connected in series, where the fuse resistor can be programmed to a desired logic state. In some embodiments, the WL transistor can be constructed from a number (e.g., 100) of sub-transistors connected in parallel; and the fuse resistor can be constructed from at least one metal trace disposed over these sub-transistors.

[0021] For example, each of the sub-transistors of the non-preconfigured eFuse cell 103 00have a channel structure formed by a number of nanostructures (e.g., nanolayers, nanowires, nanobridges) according to some embodiments of the present disclosure. Although the present disclosure is directed to fabricating the channel structure as a combination of discrete nanostructures, it is understood that the channel structure of the sub-transistor of the non-preconfigured eFuse cell 103 00 as an integral one-piece structure (e.g., a semiconductor fin structure) without departing from the scope of the present disclosure.

[0022] As in Fig. 3, the layout 300 includes: structures 302 and 304, each configured to form an active region (hereinafter "active region 302" and "active region 304", respectively); and structures 310, 315, 320, 325, 330, 335, 340, and 345, each configured to form a gate structure (hereinafter "gate structure 310", "gate structure 315", "gate structure 320", "gate structure 325", "gate structure 330", "gate structure 335", "gate structure 340", respectively). In some embodiments, the active regions 302-304 may each extend along a first lateral direction (e.g., x-direction), while the gate structures 310-345 may each extend along a second, different lateral direction (e.g., y-direction). However, it should be understood that the layout 300 may include any number of active regions and gate structures without departing from the scope of the present disclosure.

[0023] In addition, each of the gate structures 310 to 345 crosses one of the active regions 302 or 304 in the illustrated embodiment of Fig. 3. In other words, gate structure 310 is aligned with but spaced apart from a corresponding gate structure, e.g., gate structure 315, along the y-direction; gate structure 310 is aligned with but spaced apart from a corresponding gate structure, e.g., gate structure 325, along the y-direction; and so on. However, it should be understood that each of gate structures 310-345 may extend continuously across both of active areas 302 and 304 in some other embodiments.

[0024] In some embodiments, each of the active regions 302 to 304 is formed from a stack structure protruding from a main surface of a substrate. The stack comprises a number of semiconductor nanostructures (e.g., nanolayers) extending along the x-direction and vertically separated from each other. Parts of the semiconductor structures in the stack that are covered by the gate structure remain, while other parts are replaced by a number of epitaxial structures. The remaining parts of the semiconductor structures may be configured as the channel of a corresponding transistor (or sub-transistor), the epitaxial structures connected to both sides (or ends) of the remaining parts of the semiconductor structures may be configured as source / drain structures (or terminals) of the transistor (or sub-transistor), and a part of the gate structure that covers the remaining parts of the semiconductor structures (e.g.,spanned), can be configured as a gate structure (or terminal) of the transistor (or sub-transistor).

[0025] In Fig. 3, for example, the portion of the active region 302 covered by the gate structure 310 may include a number of nanostructures vertically separated from each other, which may function as the channel of a first sub-transistor. The portions of the active region 302 arranged on opposite sides of the gate structure 310 are replaced by epitaxial structures. These epitaxial structures may function as source / drain terminals of the first sub-transistor. The gate structure 310 may function as a gate terminal of the first sub-transistor. Similarly, a second sub-transistor may be formed by the active region 302 and the gate structure 320. It is therefore understood that the layout 300 may be used to fabricate a certain number of these sub-transistors.In some embodiments, these sub-transistors fabricated based on structures 302 to 304 and 310 to 345 may be connected in parallel to each other to collectively serve as the WL transistor of the non-preconfigured eFuse cell 103. 00 ( Fig. 2) to function.

[0026] The layout 300 further includes structures 350, 355, 360, 362, 364, 366, 368, 370, 372, 374, 376, and 378, each configured to form a metal structure / conductor track (hereinafter "metal track 350," "metal track 355," "metal track 360," "metal track 362," "metal track 364," "metal track 366," "metal track 368," "metal track 370," "metal track 372," "metal track 374," "metal track 376," and "metal track 378," respectively). In some embodiments, these metal traces 350 to 378 are formed across a plurality of metallization layers formed over the main surface of the substrate (e.g., along which the WL transistor or its subtransistors are formed). These metallization layers are sometimes referred to as Mo layer, M1 layer, M2 layer, etc., where the Mo layer may be the layer closest to the main surface of the substrate.Each of the metallization layers comprises a number of metal conductor lines embedded in one or more corresponding inter-layer dielectric (ILD) or inter-metal dielectric (IMD) materials.

[0027] Compared to the WL transistor (or its subtransistors), which is typically referred to as being fabricated in a front-end-of-line (FEOL) network, the metallization layers are typically referred to as being fabricated in a back-end-of-line (BEOL) network. Although not shown for brevity, the layout 300 may include a number of structures to form respective middle-end-of-line (MEOL) metal structures. These MEOL metal structures may electrically connect one or more of the FEOL components (e.g., the gate terminal, the drain terminal, the source terminal) to a corresponding one of the BEOL components (e.g., the metal trace in one of the metallization layers).For example, the layout 300 may include structures for forming respective MD structures, each of which may be connected to a source or drain terminal, structures for forming respective VG structures, each of which may connect a gate terminal to a metal trace in the Mo layer, and structures for forming respective VD structures, each of which may connect an MD structure to a metal trace in the Mo layer. Some of these MEOL metal structures are shown in the cross-sectional views of FIG. Fig. 6-7 shown for explanatory purposes.

[0028] Further with reference to Fig. 3, in some embodiments, metal traces 350 to 355 may be formed in the Mo layer and extend along the first lateral direction (e.g., the x-direction); metal traces 360 to 368 may be formed in the M1 layer and extend along the second lateral direction (e.g., the y-direction); and metal traces 372 to 378 may be formed in the M2 layer and extend along the first lateral direction (e.g., the x-direction). Accordingly, metal traces 350 to 355 may occasionally each be referred to as a Mo trace; metal traces 360 to 368 may occasionally each be referred to as an M1 trace; and metal traces 372 to 378 may occasionally each be referred to as an M2 trace.

[0029] In some embodiments of the present disclosure, the M2 traces 370 to 378 may be collectively configured as part of the fuse resistance of the non-preconfigured eFuse cell 103 00 ( Fig. 2). In particular, the M2 trace 370 has a first (e.g., right) end connected to one of the source / drain terminals of each of the sub-transistors fabricated thereunder, and a second (e.g., left) end connected to a BL, which may be fabricated as one or more metal traces across at least one of the metallization layers. Furthermore, on the sides of the right end of the M2 trace 370 (along the y-direction), the M2 traces 376 and 378 are spaced from the M2 trace 370; and on the sides of the left end of the M2 trace 370 (along the y-direction), the M2 traces 372 and 374 are spaced from the M2 trace 370. In some embodiments, the M2 traces 384 and 388 may also be electrically connected to the source / drain terminal of each of the sub-transistors fabricated thereunder, and the M2 traces 376 and 378 may also be electrically connected to the BL.Additionally, in some embodiments, the M2 trace 370 may be fabricated with a narrower width (along the y-direction) than each of the M2 traces 372-378, but the M2 trace 370 may be fabricated with a longer length (along the x-direction) than each of the M2 traces 372-378.

[0030] The layout 300 further includes structures for forming via structures, each configured to electrically connect a first metal trace in a lower metallization layer to a second metal trace in an upper metallization layer. For example, each of the Mo traces 350 and 350 is electrically connected to a number of sub-transistors formed thereunder and to a number of M1 traces formed thereon by a number of via structures 382, ​​each occasionally referred to as a V0 structure. Similarly, each of the M2 traces 372 to 378 is electrically connected to a number of M1 traces formed thereunder by a number of via structures 384, 386, 388, 390, 392, and 394, etc., each occasionally referred to as a V1 structure.

[0031] The right end of the M2 trace 370, along with the M2 traces 376 and 378, may thus be connected to the underlying WL transistor through the V1 structures 390-394, the M1 traces 366-368, the corresponding Vo structures 382, ​​and the Mo traces 350-355; and according to some embodiments, the left end of the M2 trace 370, along with the M2 traces 372 and 374, may be connected to the BL, which may be formed in the next upper M3 layer, through a number of via structures (not shown). In some other embodiments, the BL may be formed in one of various other upper metallization layers or on a backside of the substrate without departing from the scope of the present disclosure. Operationally, a programming voltage can be applied through the BL and to the left end of the M2 trace 370 and the M2 traces 372 and 374.When the underlying WL transistor is turned on, metal trace 370 may carry a current flowing from the left end to the right end, which may blow metal trace 370. Similarly, after programming, a read voltage may be applied through the BL and to the left end of M2 trace 370 and M2 traces 372 and 374. When the underlying WL transistor is turned on, metal trace 370 may carry a current flowing from the left end to the right end. If metal trace 370 has been blown (i.e., an open circuit has been formed), such a current cannot flow, and a programmed logic state of the non-preconfigured eFuse cell 103 is maintained. 00can be determined as a logic 1. If the metal trace 370 has not been burned through (e.g., as a short circuit remains), such a current can flow through, and the programmed logic state of the non-preconfigured eFuse cell 103 00 can be determined as logical 0.

[0032] In the illustrated embodiment of Fig. 3, the left end of the M2 trace 370 is connected to the M1 traces 360 to 364 through the V1 structures 384 to 388, but these M1 traces 360 to 364 cannot be connected to the underlying WL transistor. In other words, no Vo structure 382 is formed between the Mo trace 350 / 355 and the M1 trace 360 / 362 / 364. The right end of the M2 trace 370 is connected to the M1 traces 366 and 368, and these M1 traces 366 to 368 can be further connected to the underlying WL transistor through at least some of the Vo structures 382 and the Mo traces 350-355. Although three M1 tracks (e.g. 360-364) separated from the WL transistor and two M1 tracks (e.g. 366 and 368) connected to the WL transistor are Fig. 3, it is also understood that the layout 300 may include any number of M1 traces fabricated at either end of the M2 trace 370 (e.g., symmetrical numbers) without departing from the scope of the present disclosure.

[0033] Now with reference to Fig. 4 shows an exemplary layout 400 used to manufacture the default 0 eFuse cell (e.g., 103 21 from Fig. 2) can be used according to various embodiments. As mentioned above, the default 0 eFuse cell disclosed herein is formed from a WL transistor and a fuse resistor connected in series, wherein the fuse resistor is operatively configured as a short circuit (after manufacturing), i.e., a logic 0, and cannot be programmed to any other logic state. In some embodiments, the WL transistor can be constructed by a number (e.g., 100) of sub-transistors connected in parallel; and the fuse resistor can be constructed by at least one metal trace disposed over these sub-transistors.

[0034] Similar to the layout 300 of the non-preconfigured eFuse cell 103 00 each of the sub-transistors of the default 0-eFuse cell 103 21have a channel structure formed by a number of nanostructures (e.g., nanolayers, nanowires, nanobridges) according to some embodiments of the present disclosure. Although the present disclosure is directed to fabricating the channel structure as a combination of discrete nanostructures, it is understood that the channel structure of the sub-transistor of the default 0 eFuse cell 103 21 as an integral one-piece structure (e.g., a semiconductor fin structure) without departing from the scope of the present disclosure.

[0035] In some embodiments, a portion of layout 400 is configured to fabricate the WL transistor substantially similar to the portion of layout 300 (e.g., active areas 302 to 204 and gate structures 310 to 345), and thus, the following description of layout 400 focuses on the difference. Fig. 4, for example, the layout 400 includes structures 402 and 404, each configured to form an active region (hereinafter "active region 402" and "active region 404", respectively); and structures 410, 415, 420, 425, 430, 435, 440, and 445, each configured to form a gate structure (hereinafter "gate structure 410", "gate structure 415", "gate structure 420", "gate structure 425", "gate structure 430", "gate structure 435", "gate structure 440", and "gate structure 445", respectively). The sub-transistors of the WL transistor of the default 0 eFuse cell 103 21 can be formed by the active regions 402 to 404 and the gate structures 410 to 445.

[0036] The layout 400 further includes structures 450, 455, 460, 462, 464, 466, 468, 470, 472, and 474, each configured to form a metal structure / conducting line (hereinafter, "metal line 450," "metal line 455," "metal line 460," "metal line 462," "metal line 464," "metal line 466," "metal line 468," "metal line 470," "metal line 472," and "metal line 474," respectively). In some embodiments, these metal lines 450 to 478 are formed across a plurality of metallization layers disposed over the main surface of the substrate (e.g., along which the WL transistor or its sub-transistors are formed). These metallization layers are sometimes referred to as Mo layer, M1 layer, M2 layer, etc., where the Mo layer may be the layer closest to the main surface of the substrate.Each of the metallization layers comprises a number of metal conductor lines embedded in one or more corresponding inter-layer dielectric (ILD) or inter-metal dielectric (IMD) materials.

[0037] Compared to the WL transistor (or its subtransistors), which is typically referred to as being fabricated in a front-end-of-line (FEOL) network, the metallization layers are typically referred to as being fabricated in a back-end-of-line (BEOL) network. Although not shown for brevity, the layout 400 may include a number of structures to form respective middle-end-of-line (MEOL) metal structures. These MEOL metal structures may electrically connect one or more of the FEOL components (e.g., the gate terminal, the drain terminal, the source terminal) to a corresponding one of the BEOL components (e.g., the metal trace in one of the metallization layers).For example, the layout 400 may include structures for forming respective MD structures, each of which may be connected to a source or drain terminal, structures for forming respective VG structures, each of which may connect a gate terminal to a metal trace in the Mo layer, and structures for forming respective VD structures, each of which may connect an MD structure to a metal trace in the Mo layer. Some of these MEOL metal structures are shown for illustrative purposes in the cross-sectional views of FIG. Fig. 8-10 shown.

[0038] Further with reference to Fig. 4, in some embodiments, metal traces 450-455 may be formed in the Mo layer and extend along the first lateral direction (e.g., the x-direction); metal traces 460-468 may be formed in the M1 layer and extend along the second lateral direction (e.g., the y-direction); and metal traces 470-474 may be formed in the M2 layer and extend along the first lateral direction (e.g., the x-direction). Accordingly, metal traces 450-455 may occasionally each be referred to as a Mo trace; metal traces 460-468 may occasionally each be referred to as an M1 trace; and metal traces 470-474 may occasionally each be referred to as an M2 trace.

[0039] In some embodiments of the present disclosure, the M2 traces 470 to 474 may collectively be used as part of the fuse resistance of the default 0 eFuse cell 103 21 ( Fig. 2). On the sides of the M2 trace 470 (along the Y-direction), the M2 traces 472 and 474 are spaced from the M2 trace 470. Each of the M2 traces 472 and 474 may extend the same length as the M2 trace 470. Unlike in the layout 300 (the non-preconfigured eFuse cell 103 00), the metal trace 470 is electrically isolated from the underlying components (e.g., the corresponding WL transistor) in some embodiments. As shown, no via structure is formed between the M2 trace 470 and any of the underlying M1 traces (e.g., 460 to 468). Instead, the first (e.g., right) end of the M2 traces 472 and 474 may each be electrically connected to the source / drain terminal of each of the sub-transistors formed thereunder, and the second (e.g., left) end of the M2 traces 472 and 474 may each be electrically connected to a BL, which may be formed as one or more metal traces across at least one of the metallization layers. Additionally, in some embodiments, the M2 trace 470 may be fabricated with a narrower width (along the y-direction) than the M2 traces 472 and 474.

[0040] The layout 400 further includes structures for forming via structures, each configured to electrically connect a first metal trace in a lower metallization layer to a second metal trace in an upper metallization layer. For example, each of the M0 traces 450 and 455 is electrically connected to a number of sub-transistors formed thereunder and to a number of M1 traces formed thereon by a number of via structures 482, each occasionally referred to as a V0 structure. Similarly, each of the M2 traces 472 to 474 is electrically connected to a number of M1 traces formed thereunder by a number of via structures 484, 488, 490, and 494, etc., each occasionally referred to as a V1 structure.

[0041] The right end of the M2 traces 472 and 474 may thus be connected to the underlying WL transistor through the V1 structures 490-494, the M1 traces 466-468, the corresponding Vo structures 482, and the M0 traces 450-455; and according to some embodiments, the left end of the M2 traces 470-474 (or simply 472 and 474) may be connected to the BL, which may be fabricated in the next upper M3 layer, through a number of via structures (not shown). In some other embodiments, the BL may be fabricated in one of various other upper metallization layers or on a backside of the substrate without departing from the scope of the present disclosure. Since the M2 traces 472 and 474 are each fabricated to connect the BL to the WL transistor below it, a short circuit is operatively formed between the BL and the WL transistor.M2 traces 472 and 474 may occasionally be referred to as short tracks. Furthermore, the width of M2 trace 470 is significantly narrower than the width of each of M2 traces 472 and 474. Although a voltage signal is applied to the BL (which may be connected to M2 traces 470 through 474), the wider M2 traces 472 through 474 cannot be programmed, meaning they cannot change from a short circuit to an open circuit. Consequently, the default 0 eFuse cell 103. 21 represent a logic 0 (equivalent to a short circuit across their fuse resistor) in the manufacturing state, and this logic 0 cannot be changed even if a programming voltage is applied.

[0042] In the illustrated embodiment of Fig. 4, the left end of the M2 trace 470 is not connected to any of the M1 traces 460 to 464, and these M1 traces 460 to 464 cannot be connected to the underlying WL transistor. In other words, no Vo structure 482 is formed between the Mo trace 450 / 455 and the M1 trace 460 / 462 / 464. The right end of the M2 trace 470 is also not connected to any of the M1 traces 466 to 468, but these M1 traces 466 to 468 can be connected to the underlying WL transistor through at least some of the Vo structures 482 and the M0 traces 450 to 455. Although three M1 tracks (e.g. 460 to 464) that are separated from the WL transistor and two M1 tracks (e.g. 466 and 468) that are connected to the WL transistor are Fig. 4, it is also understood that the layout 400 may include any number of M1 traces fabricated at either end of the M2 trace 470 (e.g., symmetrical numbers) without departing from the scope of the present disclosure.

[0043] Now with reference to Fig. 5 shows an exemplary layout 500 used to manufacture the default 1 eFuse cell (e.g., 103 12 from Fig. 2) can be used according to various embodiments. As mentioned above, the Default 1 eFuse cell disclosed herein is formed from a WL transistor and a fuse resistor connected in series, wherein the fuse resistor is operatively configured as an open circuit (after manufacturing), i.e., a logic 1, and cannot be programmed to a different logic state. In some embodiments, the WL transistor can be constructed by a number (e.g., 100) of sub-transistors connected in parallel; and the fuse resistor can be constructed by at least one metal trace disposed over these sub-transistors.

[0044] Similar to the layout 300 of the non-preconfigured eFuse cell 103 00 each of the sub-transistors of the default 1 eFuse cell 103 12have a channel structure formed by a number of nanostructures (e.g., nanolayers, nanowires, nanobridges) according to some embodiments of the present disclosure. Although the present disclosure is directed to fabricating the channel structure as a combination of discrete nanostructures, it is understood that the channel structure of the sub-transistor of the default 1 eFuse cell 103 12 as an integral one-piece structure (e.g., a semiconductor fin structure) without departing from the scope of the present disclosure.

[0045] In some embodiments, a portion of the layout 500 is configured such that the WL transistor is fabricated substantially similarly to the portion of the layout 300 (e.g., the active areas 302 to 204 and the gate structures 310 to 345), and thus the following description of the layout 500 focuses on the difference. In Fig. 5, for example, the layout 500 includes structures 502 and 504, each configured to form an active region (hereinafter "active region 502" and "active region 504," respectively); and structures 510, 515, 520, 525, 530, 535, 540, and 545, each configured to form a gate structure (hereinafter "gate structure 510," "gate structure 515," "gate structure 520," "gate structure 525," "gate structure 530," "gate structure 535," "gate structure 540," and "gate structure 545," respectively). The sub-transistors of the WL transistor of the default 1 eFuse cell 103 12 can be formed by the active regions 502 to 504 and the gate structures 510 to 545.

[0046] The layout 500 further includes structures 550, 555, 560, 562, 564, 566, 568, 570, 572, 574, 576, and 578, each configured to form a metal structure / conductor trace (hereinafter "metal trace 550," "metal trace 555," "metal trace 560," "metal trace 562," "metal trace 564," "metal trace 566," "metal trace 568," "metal trace 570," "metal trace 572," "metal trace 574," "metal trace 576," and "metal trace 578," respectively). In some embodiments, these metal traces 550 to 578 are formed across a plurality of metallization layers disposed over the main surface of the substrate (e.g., along which the WL transistor or its subtransistors are formed). These metallization layers are sometimes referred to as Mo layer, M1 layer, M2 layer, etc., where the Mo layer may be the layer closest to the main surface of the substrate.Each of the metallization layers comprises a number of metal conductor lines embedded in one or more corresponding inter-layer dielectric (ILD) or inter-metal dielectric (IMD) materials.

[0047] Compared to the WL transistor (or its subtransistors), which is typically referred to as being fabricated in a front-end-of-line (FEOL) network, the metallization layers are typically referred to as being fabricated in a back-end-of-line (BEOL) network. Although not shown for brevity, the layout 500 may include a number of structures to form respective middle-end-of-line (MEOL) metal structures. These MEOL metal structures may electrically connect one or more of the FEOL components (e.g., the gate terminal, the drain terminal, the source terminal) to a corresponding one of the BEOL components (e.g., the metal trace in one of the metallization layers).For example, the layout 500 may include structures for forming respective MD structures, each of which may be connected to a source or drain terminal, structures for forming respective VG structures, each of which may connect a gate terminal to a metal trace in the Mo layer, and structures for forming respective VD structures, each of which may connect an MD structure to a metal trace in the Mo layer. Some of these MEOL metal structures are shown for illustrative purposes in the cross-sectional views of FIG. Fig. 11-13 shown.

[0048] Further with reference to Fig. 5, in some embodiments, metal traces 550-555 may be formed in the Mo layer and extend along the first lateral direction (e.g., the x-direction); metal traces 560-568 may be formed in the M1 layer and extend along the second lateral direction (e.g., the y-direction); and metal traces 572-578 may be formed in the M2 layer and extend along the first lateral direction (e.g., the x-direction). Accordingly, metal traces 550-555 may occasionally each be referred to as a Mo trace; metal traces 560-568 may occasionally each be referred to as an M1 trace; and metal traces 572-578 may occasionally each be referred to as an M2 trace.

[0049] In some embodiments of the present disclosure, the M2 traces 570 to 578 may collectively be used as part of the fuse resistance of the default 1 eFuse cell 103 12 ( Fig. 2). On the sides of the right end of the M2 trace 570 (along the y-direction), the M2 traces 576 and 578 are spaced from the M2 trace 570, and on the sides of the left end of the M2 trace 570 (along the y-direction), the M2 traces 572 and 574 are spaced from the M2 trace 570. Unlike in the layout 300 (the non-preconfigured eFuse cell 103 00), the metal trace 570 is electrically isolated from the underlying components (e.g., the corresponding WL transistor) in some embodiments. As shown, no via structure is formed between the M2 trace 570 and any of the underlying M1 traces (e.g., 560 to 568). Instead, the M2 traces 576 and 578 may be electrically connected to the source / drain terminal of each of the sub-transistors formed thereunder, and the M2 traces 572 and 574 may each be electrically connected to a BL, which may be formed as one or more metal traces across at least one of the metallization layers.Additionally, in some embodiments, the M2 trace 570 may be fabricated with a narrower width (along the y-direction) than the M2 traces 572-578, but the M2 trace 570 may be fabricated with a longer length (along the x-direction) than each of the M2 traces 572-578.

[0050] The layout 500 further includes structures for forming via structures, each configured to electrically connect a first metal trace in a lower metallization layer to a second metal trace in an upper metallization layer. For example, each of the Mo traces 550 and 555 is electrically connected to a number of sub-transistors formed thereunder (not explicitly described in Fig. 5) and connected to a number of M1 traces formed thereon by a number of via structures 582, each occasionally referred to as a V0 structure. Similarly, each of the M2 traces 572 through 578 is electrically connected to a number of M1 traces formed thereunder by a number of via structures 584, 588, 590, and 594, etc., each occasionally referred to as a V1 structure.

[0051] Thus, the M2 traces 576 and 578 may be connected to the underlying WL transistor through the V1 structures 590-594, the M1 traces 566-568, the corresponding Vo structures 582, and the M0 traces 550-555; and the M2 traces 570-574 (or simply 572 and 574) may be connected to the BL, which may be formed in the next upper M3 layer, through a number of via structures (not shown) according to some embodiments. In some other embodiments, the BL may be formed in one of various other upper metallization layers or on a backside of the substrate without departing from the scope of the present disclosure. Operationally, M2 traces 572 and 574 are each formed to connect to the BL, and M2 traces 576 and 578 are each formed to connect to the underlying WL transistor.Because each of the M2 traces 572 and 574 is electrically isolated from each of the M2 traces 576 or 578, an open circuit is formed between the BL and the WL transistor. The M2 traces 572 and 576 (or 574 and 578) may occasionally be referred to as open traces. Furthermore, the width of the M2 trace 570 is significantly narrower than the width of each of the M2 traces 572 through 578. Consequently, the default 1 eFuse cell 103 can be used. 12 represent a logic 1 (equivalent to an open circuit across their fuse resistor) in the manufacturing state, and this logic 0 state cannot be changed even if a programming voltage is applied.

[0052] In the illustrated embodiment of Fig. 5, the left end of the M2 trace 570 is not connected to any of the M1 traces 560 to 564, and these M1 traces 560 to 564 cannot be connected to the underlying WL transistor. In other words, no Vo structure 582 is formed between the M0 trace 550 / 555 and the M1 trace 560 / 562 / 564. The right end of the M2 trace 570 is also not connected to any of the M1 traces 566 to 568, but these M1 traces 566 to 568 can be connected to the underlying WL transistor through at least some of the Vo structures 582 and the M0 traces 550-555. Although three M1 tracks (e.g. 560-564) that are separated from the WL transistor and two M1 tracks (e.g. 566 and 568) that are connected to the WL transistor are Fig. 5, it is also understood that the layout 500 may include any number of M1 traces fabricated at either end of the M2 trace 570 (e.g., symmetrical numbers) without departing from the scope of the present disclosure.

[0053] The Fig. 6 and Fig. 7 each show a sectional view of a semiconductor device 600 formed according to the layout 300 of Fig. 3 according to some embodiments. Therefore, the semiconductor device 600 may include at least one non-preconfigured eFuse cell 103 00 In some embodiments, the sectional view of Fig. 6 along a longitudinal direction of the active region 302, and the sectional view of Fig. 7 has been cut along a longitudinal direction of the M2 conductor track 370. It is understood that the sectional view of Fig. 7 also the sectional view of Fig. 6 as a reference. Accordingly, some of the references of Fig. 3 is used again in the discussion of semiconductor device 600 below.

[0054] First, with reference to Fig. 6, a number of channels 610 and epitaxial structures 620 may be formed along the active region 302. Each of the channels 610 may be covered or enclosed by a corresponding one of the gate structures, e.g., 310, 320, 330, 340, and some of the epitaxial structures may be covered by a corresponding MD, e.g., 630. As discussed above, at least a portion of the WL transistor of the non-preconfigured eFuse cell 103 00by the active region 302 and the gate structures 310 to 340. For example, a first subset of the subtransistors of the WL transistor is formed by the active region 302 and the gate structures 310 to 340, while a second subset of the subtransistors of the WL transistor is formed by the active region 304 and the gate structures 315, 325, 335 and 345 (in the exemplary sectional view of Fig. 6 not shown).

[0055] In addition, these subtransistors can be connected in parallel. Accordingly, every second epitaxial structure 620 is connected to one or more metal conductors formed thereon by a respective one of the MDs 630. For example, the Fig. 6 are connected to the M0 conductor 350 by a number of VD structures 640. As described with reference to Fig. 3, the M0 trace 350 has one (e.g., right) end connected to the one or more overlying metal traces, while the other (e.g., left) end is isolated from the one or more overlying metal traces. Accordingly, the Vo structures 382 exist only between the right end of the M0 trace 350 and the respective overlying M1 traces 366 through 368.

[0056] Now with reference to Fig. 7 shows that the M2 conductive line 370 is connected to the M1 conductive lines 360 to 368 by a number of V1 structures 386 and 392, respectively. In other words, to manufacture the non-preconfigured eFuse cell 103 00 each of the M1 tracks (e.g. in the layout 300 of Fig. 3) is connected to the M2 trace 370 (which operatively serves as at least part of its fuse resistor) through a corresponding one of the V1 structures 386 / 392, regardless of whether the M1 trace is connected to the underlying WL transistor. Consequently, the non-preconfigured eFuse cell (or its fuse resistor, e.g., M2 trace 370) is programmable.

[0057] The Fig. 8, Fig. 9 and Fig. 10 each show a sectional view of a semiconductor device 800 formed according to the layout 400 of Fig. 4 according to some embodiments. Therefore, the semiconductor device 800 may include at least one default 0 eFuse cell 103 21 In some embodiments, the sectional view of Fig. 8 along a longitudinal direction of the active region 402, the sectional view of Fig. 9 has been cut along a longitudinal direction of the M2 conductor track 470, and the sectional view of Fig. 10 has been cut along a longitudinal direction of the M2 conductor track 472. It is understood that the sectional views of the Fig. 9 and Fig. 10 also the sectional view of Fig. 8 as a reference. Accordingly, some of the references of Fig. 4 is used again in the discussion of semiconductor device 800 below.

[0058] First, with reference to Fig. 8, a number of channels 810 and epitaxial structures 820 may be formed along the active region 402. Each of the channels 810 may be covered or enclosed by a corresponding one of the gate structures, e.g., 410, 420, 430, 440, and some of the epitaxial structures may be covered by a corresponding MD, e.g., 830. As discussed above, at least a portion of the WL transistor of the default 0 eFuse cell 103 21 by the active region 402 and the gate structures 410 to 440. For example, a first subset of the subtransistors of the WL transistor is formed by the active region 402 and the gate structures 410 to 440, while a second subset of the subtransistors of the WL transistor is formed by the active region 404 and the gate structures 415, 425, 435 and 445 (in the exemplary sectional view of Fig. 8 not shown).

[0059] In addition, these subtransistors can be connected in parallel. Accordingly, every second epitaxial structure 820 is connected to one or more metal conductors formed thereon by a respective one of the MDs 830. For example, the Fig. 8 are connected to the M0 conductor track 450 by a number of VD structures 840. As described with reference to Fig. 4, the M0 trace 450 has one (e.g., right) end connected to the one or more overlying metal traces, while the other (e.g., left) end is isolated from the one or more overlying metal traces. Accordingly, the Vo structures 482 exist only between the right end of the M0 trace 450 and the respective overlying M1 traces 466 through 468.

[0060] Now with reference to Fig. 9, it is shown that the M2 trace 470 is separated from each of the M1 traces 460 to 468. In other words, to produce the default 0 eFuse cell 103 21 each of the M1 tracks (e.g. in the layout 400 of Fig. 4) is separated from the M2 trace 470 (which operatively serves as at least part of its fuse resistor), regardless of whether the M1 trace is connected to the underlying WL transistor. Consequently, the default 0 eFuse cell (or its fuse resistor, e.g., the M2 trace 470) is not programmable. Instead, these M1 traces are, in the as-manufactured state, separated by another M2 trace, e.g., 472, and the V1 structures 484 and 490, as shown in the cross-sectional view of Fig. 10, are connected to each other (e.g., forming a short circuit). Accordingly, the fuse resistance of the Default 0 eFuse cell represents a default logic 0 according to the short circuit.

[0061] The Fig. 11, Fig. 12 and Fig. 13 each show a sectional view of a semiconductor device 1100 constructed according to the layout 500 of Fig. 5 according to some embodiments. Therefore, the semiconductor device 1100 may include at least one default 1 eFuse cell 103 12 In some embodiments, the sectional view of Fig. 11 along a longitudinal direction of the active region 502, the sectional view of Fig. 12 has been cut along a longitudinal direction of the M2 conductor track 570, and the sectional view of Fig. 13 has been sectioned along a longitudinal direction of the M2 conductor track 572 / 576. It is understood that the sectional views of the Fig. 12 and Fig. 13 also the sectional view of Fig. 11 as a reference. Accordingly, some of the references of Fig. 5 is used again in the discussion of semiconductor device 1100 below.

[0062] First, with reference to Fig. 11, a number of channels 1110 and epitaxial structures 1120 may be formed along the active region 502. Each of the channels 1110 may be covered or enclosed by a corresponding one of the gate structures, e.g., 510, 520, 530, 540, and some of the epitaxial structures may be covered by a corresponding MD, e.g., 1130. As discussed above, at least a portion of the WL transistor of the default 1 eFuse cell 103 12by the active region 502 and the gate structures 510 to 540. For example, a first subset of the subtransistors of the WL transistor is formed by the active region 502 and the gate structures 510 to 540, while a second subset of the subtransistors of the WL transistor is formed by the active region 504 and the gate structures 515, 525, 535 and 545 (in the exemplary sectional view of Fig. 11 not shown).

[0063] In addition, these subtransistors can be connected in parallel. Accordingly, every second epitaxial structure 1120 is connected to one or more metal conductors formed thereon by a respective one of the MDs 1130. For example, the Fig. 11 are connected to the M0 trace 550 by a number of VD structures 1140. As described with reference to Fig. 5, the M0 trace 550 has one (e.g., right) end connected to the one or more overlying metal traces, while the other (e.g., left) end is isolated from the one or more overlying metal traces. Accordingly, the Vo structures 582 exist only between the right end of the M0 trace 550 and the respective overlying M1 traces 566 through 568.

[0064] Now with reference to Fig. 12, it is shown that the M2 trace 570 is separated from each of the M1 traces 560 to 568. In other words, to manufacture the default 1 eFuse cell 103 12 each of the M1 tracks (e.g. in the layout 500 of Fig. 5) is separated from the M2 trace 570 (which operatively serves as at least part of its fuse resistor), regardless of whether the M1 trace is connected to the underlying WL transistor. Consequently, the default 1 eFuse cell (or its fuse resistor, e.g., M2 trace 570) is not programmable. Instead, these M1 traces, in the as-manufactured state, are grouped into two subsets that are separated from each other (e.g., forming an open circuit), as shown in the cross-sectional view of Fig. 13. In particular, the first subset of M1 traces 560-564 are connected to the M2 trace 572, and the second subset of M1 traces 566-568 are connected to the M2 trace 576, with the M2 trace 572 and the M2 trace 576 being physically spaced apart and electrically isolated from each other. Accordingly, the fuse resistance of the default 1 eFuse cell represents a logic 1 according to the open circuit.

[0065] Fig. 14 shows a flow diagram of an exemplary method 1400 for manufacturing a memory device with a memory array according to some embodiments. The memory array includes a number of non-preconfigured eFuse cells, a number of default 0 eFuse cells, and a number of default 1 eFuse cells. In some embodiments, the method 1400 may be performed to manufacture a memory device based on the layouts 300, 400, and 500 shown in the Fig. 3, Fig. 4 and 5 respectively, and consequently some of the references of the Fig. 3 to 5 (and associated sectional views of the Fig. 6 to 13) will be used again in the following discussion of method 1400. It should be noted that method 1400 is merely an example and is not intended to limit the present disclosure. Accordingly, it is understood that before, during, and after method 1400, Fig. 14 further operations may be provided and that some of these other operations can only be described briefly here.

[0066] The method 1400 begins with operation 1402, in which a substrate is provided according to various embodiments. The substrate comprises a semiconductor material substrate, for example, silicon. Alternatively, the substrate may comprise another elemental semiconductor material, such as germanium. The substrate may also comprise a compound semiconductor, such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The substrate may comprise an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate comprises an epitaxial layer. For example, the substrate may comprise an epitaxial layer located over a bulk semiconductor. Furthermore, the substrate may comprise a semiconductor-on-insulator (SOI) structure.For example, the substrate may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or another suitable method such as wafer bonding and grinding.

[0067] The method 1400 continues with operation 1404, in which a stack comprising an alternating sequence of first nanostructures and second nanostructures is fabricated according to various embodiments. Such a stack may be fabricated based on one of the (active region) structures discussed above. The stack may be fabricated in a front side of the substrate. In some embodiments, the first nanostructures may comprise sacrificial SiGe nanostructures, and the second nanostructures may comprise Si channel nanostructures. Such a stack may occasionally be referred to as a superlattice. In one non-limiting example, the sacrificial SiGe nanostructures may be SiGe 25%. The notation "SiGe 25%" is used to indicate that 25% of the SiGe material is Ge.It is understood that the percentage of Ge in each of the sacrificial SiGe nanostructures can be any value between 0 and 100 (except 0 and 100) without departing from the scope of the present disclosure. In some other embodiments, the second nanostructures may comprise a first semiconductor material other than Si, and the first nanostructures may comprise a second semiconductor material other than SiGe, as long as the first and second semiconductor materials are each characterized by different etching properties (e.g., etching rates).

[0068] The alternating sequence of nanostructures can be created by epitaxially growing one layer and then the next layer until the desired number and thickness of the nanostructures are reached. Epitaxial materials can be grown from gaseous or liquid precursors. Epitaxial materials can be grown using vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), or another suitable process. Epitaxial silicon, silicon-germanium, and / or carbon-doped silicon (Si:C) can be doped (in-situ doped) by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), during deposition, depending on the type of transistor.

[0069] The method 1400 continues with operation 1406, in which a number of dummy gate structures are fabricated according to various embodiments. Such a dummy gate structure may be fabricated based on one of the (gate structure) structures discussed above. The dummy gate structure may extend along a direction perpendicular to the longitudinal direction of the dielectric fin structure (and the stack). Furthermore, in one of various embodiments, the dummy gate structure may be fabricated shorter than the dielectric fin structure, and consequently, the dummy gate structure is cut (or otherwise separated) by the dielectric fin structure in the fabricated state.

[0070] The dummy gate structure can be formed by depositing amorphous silicon (a-Si) over the stack. Other materials suitable for forming dummy gates (e.g., polysilicon) can also be used without departing from the scope of the present disclosure. The a-Si is then planarized to a desired level. A hard mask is deposited over the planarized a-Si and patterned. The hard mask can be made of a nitride or an oxide layer. An etching process (e.g., a reactive ion etch (RIE) process) is applied to the a-Si to form the dummy gate structure. After forming the dummy gate structure, gate spacers can be formed to extend along sidewalls of the dummy gate structure. The gate spacers can be formed by conformal deposition of a dielectric material (e.g.,Silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC or a suitable combination of these materials) followed by a directed etch (e.g. RIE).

[0071] The method 1400 continues with operation 1408, in which inner spacers are formed by replacing end portions of each of the sacrificial SiGe nanostructures with a dielectric material according to various embodiments. After forming the dummy gate structure covering certain portions of the stack (e.g., the portions of the stack separated by the dielectric fin structure), the portions of the stack not covered by the dummy gate structure are removed. Subsequently, respective end portions of each sacrificial SiGe nanostructure of the covered stack are removed. The inner spacers are formed by filling such recesses of each sacrificial SiGe nanostructure with a dielectric material by chemical vapor deposition (CVD) or monolayer doping (MLD) of nitride followed by a spacer RIE.The material of the inner spacers may be made of the same material as the gate spacers described above or of a different material. For example, the inner spacers may be made of silicon nitride, silicon borocarbonitride, silicon carbonitride, silicon carbonoxynitride, or another dielectric material (e.g., a dielectric material with a dielectric constant k less than about 5).

[0072] The method 1400 continues with operation 1410, in which a number of epitaxial structures are fabricated according to various embodiments. After fabricating the inner spacers, the epitaxial structures are fabricated using an epitaxial layer growth process on exposed ends of the Si nanostructures. In-situ doping (ISD) can be used to fabricate doped epitaxial structures, thereby creating the required junctions for a corresponding transistor (or sub-transistor). N- and P-FETs are fabricated by implanting various types of dopants into selected regions of the device to create the one or more required junctions. N-type devices can be fabricated by implanting arsenic (As) or phosphorus (P), and P-type devices can be fabricated by implanting boron (B).After the epitaxial structures have been produced, an interlayer dielectric (e.g. silicon dioxide) is deposited to cover the epitaxial structures.

[0073] The method 1400 continues with operation 1412, in which the dummy gate structures and the remaining sacrificial SiGe nanostructures are replaced with respective active gate structures according to various embodiments. Following the formation of the interlayer dielectric, the dummy gate structures are removed using an etching process, e.g., RIE or chemical oxide removal (COR). Then, the remaining sacrificial SiGe nanostructures are removed, while the Si channel nanostructure is kept substantially intact by applying a selective etch (e.g., a hydrochloric acid (HCl)). After removal of the sacrificial SiGe nanostructures, top and bottom surfaces and sidewalls of each of the Si channel nanostructures may be exposed, except for the sidewall in contact with the dielectric fin structure.Then, a number of active gate structures can be fabricated to enclose each of the Si channel nanostructures, except for the sidewall, which is in contact with the dielectric fin structure. Each of the active gate structures includes at least one gate dielectric layer (e.g., a high-k dielectric layer) and one gate metal layer (e.g., a work function metal layer). After fabricating the active gate structures, respective WL transistors of the disclosed eFuse memory cells can be fabricated using the non-preconfigured eFuse cells, default 0 eFuse cells, and default 1 eFuse cells.

[0074] The method 1400 continues with operation 1414, in which a number of front-end interconnect structures are formed according to various embodiments. After the WL transistors are formed, a number of middle-end interconnect structures (e.g., VGs, VDs, MDs) are formed over the WL transistors. For example, a number of VGs may be formed to each connect to the gate terminals of the one or more WL transistors, and a number of MDs may be formed to each connect to the source / drain terminals of the one or more WL transistors. In addition, a number of back-end metal traces (e.g., M0 traces, M1 traces, M2 traces, etc.) may be formed over the middle-end interconnect structures.

[0075] The front-side interconnect structure is formed from a metal material. The metal material can be selected from the group consisting of aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. Other metal materials are within the scope of the present disclosure. The front-side interconnect structures can be formed, for example, by covering the front side of the substrate with the above-mentioned metal material by chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating, electroplating, or combinations thereof.

[0076] In some embodiments, the respective fuse resistors of the disclosed non-preconfigured eFuse cells, default 0 eFuse cells, and default 1 eFuse cells may be formed by connecting or disconnecting these back-end metal traces. For example, operation 1414 may further include operation 1416 of connecting an M2 trace (fuse resistor) to M1 traces, operation 1418 of disconnecting an M2 trace (fuse resistor) from the M1 traces and creating shorted traces, and operation 1420 of disconnecting an M2 trace (fuse resistor) from the M1 traces and creating open traces.

[0077] Firstly, with reference to Operation 1416 (and in connection with the Fig. 3, Fig. 6 and Fig. 7) the M2 conductor track 370, which serves as at least part of the fuse resistance of the non-preconfigured eFuse cell 103 00 serves, is connected to the underlying M1 traces 360 to 368 by the V1 structures 386 and 392. Furthermore, the M2 trace 370 is connected (e.g., downward) to the WL transistor formed by the active regions 302 to 304 and the gate structures 310 to 345 through the M1 traces 366-368, the M0 traces 350-355, the VDs 640, and the MDs 630; and the M2 trace 370 is connected (e.g., upward) to the BL formed thereon. Consequently, the M2 trace 370 is programmable (e.g., from a short to an open) by the BL and the activated WL transistor.

[0078] Then, with reference to Operation 1418 (and in conjunction with the Fig. 4, Fig. 8, Fig. 9 and Fig. 10) the M2 conductor track 470, which serves as at least part of the fuse resistance of the non-preconfigured eFuse cell 103 21 is separated from the underlying M1 traces 460 to 468. In addition, the M2 traces 472 and 474 are each connected (e.g., downwards) by the M1 traces 466-468, the M0 traces 450-455, the VDs 840, and the MDs 830 to the WL transistor formed by the active regions 402 to 404 and the gate structures 410 to 445; and the M2 traces 472 and 474 are each connected (e.g., upwards) to the BL fabricated thereon. Consequently, if the M2 trace 470 is not programmable (e.g., by not connecting to the underlying WL transistor), the M2 traces 472 and 474 are each formed as a short circuit to electrically connect the WL transistor to the BL, thereby representing a logic 0 after fabrication.

[0079] Then, with reference to Operation 1420 (and in conjunction with the Fig. 5, Fig. 11, Fig. 12 and Fig. 13) the M2 conductor track 570, which serves as at least part of the fuse resistance of the non-preconfigured eFuse cell 103 12is separated from the underlying M1 traces 560 to 568. In addition, the M2 traces 576 and 578 are each connected (e.g., downward) by the M1 traces 566-568, the Mo traces 550-555, the VDs 1140, and the MDs 1130 to the WL transistor formed by the active regions 502 to 504 and the gate structures 510 to 545; and the M2 traces 572 and 574 are each connected (e.g., upward) to the BL fabricated thereon. Consequently, if the M2 trace 570 is not programmable (e.g., by not connecting to the underlying WL transistor), the pair of M2 traces 572 and 576 (and the pair of M2 traces 574 and 578) are each formed as an open circuit to electrically isolate the WL transistor from the BL, thereby representing a logic 1 after fabrication.

[0080] Fig. 15 shows a schematic Fig. a portion of the memory device 100 (e.g., some of the memory cells 103), in which each of the memory cells 103 is implemented as an antifuse memory cell according to some embodiments. In the illustrated examples of Fig. 15 antifuse memory cells 103 00 , 103 01 , 103 02 , 103 03 , 103 10 , 103 11 , 103 12 , 103 13 , 103 20 , 103 21 , 103 22 , 103 23 , 103 30 , 103 31 , 103 32 and 103 33 of the memory matrix 102, where the first subscript and the second subscript can represent their corresponding row and column, respectively. Although sixteen antifuse memory cells 103 00 up to 103 33, it is understood that the memory array 102 may have any number of similar antifuse memory cells without departing from the scope of the present disclosure.

[0081] As shown, each of the antifuse memory cells has 103 00 up to 103 33 a programming transistor and a reading transistor connected in series, and it is operatively connected to a programming WL, a reading WL, and a BL. The programming and reading WLs are arranged in the corresponding row, and the BL is arranged in the corresponding column. Using the antifuse memory cell 103 00 As a representative example, the antifuse memory cell 103 00a programming transistor 1510 and a read transistor 1520 connected in series, and it is located at an intersection of BL0 and WLP / R0 (column C0 and row R0). The programming transistor 1510 has a floating first source / drain terminal and a second source / drain terminal connected to a first source / drain terminal of the read transistor 1520. The read transistor 1520 has a second source / drain terminal connected to BL0. The gate terminal of the programming transistor 1510 and the gate terminal of the read transistor 1520 are connected to WLP0 and WLR0, respectively.

[0082] In some embodiments, both the programming transistor 1510 and the read transistor 1520 may be fabricated along the main surface of a substrate (sometimes referred to as part of the "front-end-of-line" (FEOL) process / network), sometimes referred to as FEOL transistors. A number of metallization layers may be fabricated over the FEOL network (sometimes referred to as part of the "back-end-of-line" (BEOL) process / network). In some other embodiments, the programming transistor 1510 and / or the read transistor 1520 may be fabricated in the BEOL network, sometimes referred to as BEOL transistors. Depending on whether the antifuse memory cell is preconfigured as a default 0 antifuse cell or a default 1 antifuse cell, its programming transistor and reading transistor may each have different threshold voltages.For example, the programming transistor of the default 0 antifuse cell may have a significantly lower threshold voltage than its read transistor. Consequently, the programming transistor may be easily turned on or remain enabled most of the time (sometimes referred to as "always on"). Similarly, the programming transistor of the default 1 antifuse cell may have a significantly higher threshold voltage than its read transistor, causing the programming transistor to rarely turn on or remain disabled most of the time (sometimes referred to as "always off"). Consequently, these default antifuse cells may each permanently represent a preconfigured logic state after their manufacture (or fabrication). In other words, the default antifuse cells disclosed herein cannot be further programmed to represent a desired logic state after their manufacture, and such a logic state cannot be changed.

[0083] In Fig. 15, for example, of the antifuse memory cells, 103 00 up to 103 33 the antifuse memory cells 103 21 and the antifuse memory cells 103 12 as a default 0 antifuse cell or a default 1 antifuse cell, respectively, while other antifuse memory cells remain as non-preconfigured antifuse cells. The term "non-preconfigured antifuse cell" used herein may refer to an antifuse memory cell that represents an open circuit (or a logic 1) in the as-manufactured state and can be programmed to represent a short circuit (or a logic 0). Unlike the non-preconfigured antifuse memory cells, the antifuse memory cell 103 21 represent a logical 0 in the manufactured state and cannot be programmed to a logical 1, and the antifuse memory cell 103 12can represent a logical 1 in the as-manufactured state and cannot be programmed to a logical 0. Respective structures or configurations of the non-preconfigured antifuse cell, default 0 antifuse cell and default 1 antifuse cell are described with reference to the Fig. 16, Fig. 17 and 18 respectively are discussed in further detail.

[0084] Although a default 0 antifuse cell and a default 1 antifuse cell are used in the illustrative embodiment of Fig. 15, it is understood that an array may include any number of default 0 antifuse cells and any number of default 1 antifuse cells. Furthermore, in some embodiments, respective positions of the one or more default 0 antifuse cells and default 1 antifuse cells in the array may also be preconfigured. If the positions of these default cells in an array are known, respective functionalities of one or more peripheral circuits (e.g., sense amplifiers) operatively connected to the array may be verified. For example, the logical state of a default cell, and where such a default cell is located in an array, may be preconfigured (e.g., known).If a sense amplifier operatively connected to the default cell reads a logical state that conflicts with the preconfigured logical state, the sense amplifier may be determined to be malfunctioning. As another example, given that the logical state and position of a default cell are both preconfigured and an operatively connected sense amplifier has been determined to be malfunctioning, one or more peripheral circuits (e.g., a corresponding column decoder and / or a corresponding row decoder) may be determined to be malfunctioning if the sense amplifier still reads a conflicting logical state.

[0085] With reference first to Fig. 16 is an exemplary schematic Fig. the non-preconfigured antifuse cell (e.g. 103 00 from Fig. 15) according to various embodiments. While the programming transistor 1520 and the reading transistor 1510 are each implemented as an n-type metal-oxide-semiconductor field-effect-transistor (n-MOSFET) or are sometimes referred to as an NMOS transistor, it should be understood that the programming and reading transistors may each be implemented as a p-type metal-oxide-semiconductor field-effect-transistor (p-MOSFET) without departing from the scope of the present disclosure.

[0086] In some embodiments, the programming transistor 1520 and the reading transistor 1510 of the non-preconfigured antifuse cell 103 00have a similar threshold voltage in common. For example, a gate structure of the programming transistor 1520 may have a gate dielectric layer with a first thickness, and a gate structure of the reading transistor 1510 may have a gate dielectric layer with a second thickness, where the first thickness may be substantially similar to the second thickness. In another example, a gate structure of the programming transistor 1520 may have a gate dielectric layer with a first dielectric constant, and a gate structure of the reading transistor 1510 may have a gate dielectric layer with a second dielectric constant, where the first dielectric constant may be substantially similar to the second dielectric constant.In yet another example, a gate structure of the programming transistor 1520 may have a first combination of working output layers (resulting in a first flat band voltage), and a gate structure of the reading transistor 1510 may have a second combination of working output layers (resulting in a second flat band voltage), where the first flat band voltage may be substantially similar to the second flat band voltage.

[0087] With reference first to Fig. 17 is an exemplary schematic Fig. the default antifuse cell (e.g., 103 21 from Fig. 15) according to various embodiments. While the programming transistor 1520 and the reading transistor 1510 are each implemented as an n-type metal-oxide-semiconductor field-effect-transistor (n-MOSFET) or are sometimes referred to as an NMOS transistor, it should be understood that the programming and reading transistors may each be implemented as a p-type metal-oxide-semiconductor field-effect-transistor (p-MOSFET) without departing from the scope of the present disclosure.

[0088] In some embodiments, the programming transistor 1520 and the reading transistor 1510 of the default antifuse cell 103 21each have different threshold voltages, wherein the programming transistor 1520 may have a substantially lower threshold voltage than the reading transistor 1510. For example, a gate structure of the programming transistor 1520 may have a gate dielectric layer with a first thickness, and a gate structure of the reading transistor 1510 may have a gate dielectric layer with a second thickness, wherein the first thickness may be substantially thinner than the second thickness. In another example, a gate structure of the programming transistor 1520 may have a gate dielectric layer with a first dielectric constant, and a gate structure of the reading transistor 1510 may have a gate dielectric layer with a second dielectric constant, wherein the first dielectric constant may be substantially higher than the second dielectric constant.In yet another example, a gate structure of the programming transistor 1520 may have a first combination of working output layers (resulting in a first flat band voltage) and a gate structure of the reading transistor 1510 may have a second combination of working output layers (resulting in a second flat band voltage), where the first flat band voltage may be substantially lower than the second flat band voltage.

[0089] With reference first to Fig. 18 is an exemplary schematic Fig. the default 1 antifuse cell (e.g., 103 12 from Fig. 15) according to various embodiments. While the programming transistor 1520 and the reading transistor 1510 are each implemented as an n-type metal-oxide-semiconductor field-effect-transistor (n-MOSFET) or are sometimes referred to as an NMOS transistor, it should be understood that the programming and reading transistors may each be implemented as a p-type metal-oxide-semiconductor field-effect-transistor (p-MOSFET) without departing from the scope of the present disclosure.

[0090] In some embodiments, the programming transistor 1520 and the reading transistor 1510 of the default 1 antifuse cell 103 00each have different threshold voltages, wherein the programming transistor 1520 may have a substantially higher threshold voltage than the reading transistor 1510. For example, a gate structure of the programming transistor 1520 may have a gate dielectric layer with a first thickness, and a gate structure of the reading transistor 1510 may have a gate dielectric layer with a second thickness, wherein the first thickness may be substantially thicker than the second thickness. In another example, a gate structure of the programming transistor 1520 may have a gate dielectric layer with a first dielectric constant, and a gate structure of the reading transistor 1510 may have a gate dielectric layer with a second dielectric constant, wherein the first dielectric constant may be substantially lower than the second dielectric constant.In yet another example, a gate structure of the programming transistor 1520 may have a first combination of working output layers (resulting in a first flat band voltage) and a gate structure of the reading transistor 1510 may have a second combination of working output layers (resulting in a second flat band voltage), where the first flat band voltage may be substantially higher than the second flat band voltage.

[0091] To program the non-preconfigured antifuse cell 103 00 The read transistor 1510 is turned on by applying a sufficiently high voltage (e.g., a positive voltage corresponding to a logic H state) to its gate terminal via WLR0. Before, simultaneously with, or after the read transistor 1510 is turned on, a sufficiently high voltage (e.g., a breakdown voltage (V BD), sometimes referred to as a programming voltage) is applied to WLP0, and a sufficiently low voltage (e.g., a positive voltage or ground voltage corresponding to a logic L state) is applied to BL0. When sense transistor 1510 is turned on, the low voltage (applied to BL0) can be directed to the source terminal of programming transistor 1520. By having V BD simultaneously across one of the source / drain terminals that is not floating (and connected to the read transistor 1510) and the gate terminal of the programming transistor 1520, a portion of the gate dielectric layer of the programming transistor 1520 (e.g., the portion between its gate and non-floating source / drain terminal) will break down.

[0092] After the gate dielectric layer (or a portion of the gate dielectric layer) has been penetrated, the behavior of the portion of the gate dielectric layer connecting the gate terminal and the source / drain terminal is equivalently resistive. In particular, before the programming process, no conduction path exists, even when the read transistor 1510 is turned on. After the programming process, a conduction path exists between the BL0 and the WLP0 (e.g., via the resistor formed across the penetrated portion of the gate dielectric layer) when the read transistor 1510 is turned on. Accordingly, the non-preconfigured antifuse cell 103 00 , which represents an open circuit (e.g. a logic state 1) in the manufactured state, can be programmed to have a short circuit (e.g. a logic state 0).

[0093] In comparison: since the programming transistor 1520 of the default antifuse cell 103 21 has a significantly lower threshold voltage than its read transistor 1510, the programming transistor 1520 can be activated even if a low or almost no voltage signal is applied to the WLP2. Such a low threshold voltage forms a conduction path across the WLP2 to the source / drain terminal of the programming transistor 1520, which is connected to the read transistor 1510 after the default 0 antifuse cell 103 21 When the read transistor 1510 is turned on, a short circuit is formed from WLP2 to BL1. Accordingly, the default antifuse cell 103 21 represent a logical 0, even without being programmed. Since the programming transistor 1520 of the default 1 antifuse cell 103 12has a significantly higher threshold voltage than its read transistor 1510, the programming transistor 1520 may similarly be barely activated, or not at all, even if a high voltage signal is applied to WLP1. Such a high threshold voltage equivalently forms an open circuit across WLP1 to the source / drain terminal of the programming transistor 1520, which is connected to the read transistor 1510 after the default 1 antifuse cell 103 12 Furthermore, this open circuit can hardly become a short circuit, even if a strong programming voltage is applied to the WLP1. Accordingly, the default 1 antifuse cell 103 12 represent a logical 1, even if a programming process is applied.

[0094] In Fig. 19 is an exemplary layout 1900 used to manufacture a number of the antifuse memory cells of Fig. 15, according to various embodiments. For example, with layout 1900, two antifuse memory cells may be formed that are arranged along the same column, e.g., share the same BL, and are connected to respective WLPs and respective WLRs. In one embodiment, these two cells (formed with layout 1900) may both be non-preconfigured antifuse cells. In another embodiment, these two cells (formed with layout 1900) may both be default 0 antifuse cells. In yet another embodiment, these two cells (formed with layout 1900) may both be default 1 antifuse cells. In yet another embodiment, one of these two cells (formed with layout 1900) may be a non-preconfigured antifuse cell, while the other may be a default 1 or a default 0 antifuse cell.

[0095] As shown, layout 1900 includes structures 1902, 1904, 1906, 1908, and 1910, wherein structure 1902 is configured to form an active region (hereinafter, "active region 1902"), and structures 1904 to 1910 are each configured to form a gate structure (hereinafter, "gate structure 1904," "gate structure 1906," "gate structure 1908," and "gate structure 1910," respectively). Active region 1902 may extend along a first lateral direction (e.g., the x-direction), while gate structures 1904 to 1910 may each extend along a second lateral direction (e.g., the y-direction). With the active region 1902 and the gate structures 1904-1910, a first antifuse memory cell 1920 and a second antifuse memory cell 1930 can be formed.In some embodiments, the first antifuse memory cell 1920 may be formed by the active region 1902 and the gate structures 1904-1906; and the second antifuse memory cell 1930 may be formed by the active region 1902 and the gate structures 1908-1910.

[0096] For example, the portion of the active region 1902 covered by the gate structure 1904 may include a number of vertically separated nanostructures that may function as a channel of the programming transistor of the first antifuse memory cell 1920. The portions of the active region 1902 disposed on opposite sides of the gate structure 1904 are replaced by epitaxial structures. These epitaxial structures may function as source / drain terminals of the programming transistor of the first antifuse memory cell 1920. The gate structure 1904 may function as a gate terminal of the programming transistor of the first antifuse memory cell 1920. The part of the active region 1902 covered by the gate structure 1906 may include a number of nanostructures spaced vertically from each other, which may function as a channel of the read transistor of the first antifuse memory cell 1920.The portions of the active region 1902 located on opposite sides of the gate structure 1906 are replaced by epitaxial structures. These epitaxial structures may function as source / drain terminals of the read transistor of the first antifuse memory cell 1920. The gate structure 1906 may function as a gate terminal of the read transistor of the first antifuse memory cell 1920. Similarly, a read transistor of the second antifuse memory cell 1930 may be formed by the active region 1902 and the gate structure 1908, and a programming transistor of the second antifuse memory cell 1930 may be formed by the active region 1902 and the gate structure 1910. Consequently, the gate structures 1904 to 1910 may operatively serve as a first programming word line (e.g., WLP0), a first sense word line (e.g., WLR0), a second sense word line (e.g., WLR1), and a second programming word line (e.g., WLP1), respectively, as shown in FIG. Fig. 19 is specified.

[0097] The layout 1900 further includes structures 1932, 1934, and 1936, each configured to form a metal structure / conducting line (hereinafter, "metal line 1932," "metal line 1934," and "metal line 1936," respectively). In some embodiments, these metal lines 1932 to 1936 are formed in one of a plurality of metallization layers disposed over the main surface of a substrate (e.g., along which the antifuse memory cells, e.g., 1920 and 1930, are formed). These metallization layers are occasionally referred to as Mo layer, M1 layer, M2 layer, etc., where the Mo layer may be the layer closest to the main surface of the substrate.Each of the metallization layers comprises a number of metal conductor lines embedded in one or more corresponding inter-layer dielectric (ILD) or inter-metal dielectric (IMD) materials.

[0098] The metal lines 1932 to 1936 may all be formed in the Mo layer (and thus each may be referred to below as a Mo line). In some embodiments, the Mo line 1932 may operatively serve as a bit line (e.g., BL0) connecting the first antifuse memory cell 1920 to the second antifuse memory cell 1930. The read transistors of the first antifuse memory cell 1920 and the second antifuse memory cells have a common source / drain terminal connected to BL0 through a via structure formed by a structure 1938. The Mo conductive line 1934 and the Mo conductive line 1936 may be connected to the gate structure 1904 (WLP0) and the gate structure 1910 (WLP1) by a via structure (formed by a structure 1940) and a via structure (formed by a structure 1942), respectively.

[0099] Fig. 20 shows a flow diagram of an exemplary method 2000 for manufacturing a memory device with a memory array according to some embodiments. The memory array includes a number of non-preconfigured antifuse cells, a number of default 0 antifuse cells, and a number of default 1 antifuse cells. In some embodiments, the method 2000 may be performed to manufacture a memory device based on the layout 1900 shown in Fig. 19, and consequently, some of the references of the Fig. 19 may be used again in the following discussion of method 2000. It should be noted that method 2000 is merely an example and is not intended to limit the present disclosure. Accordingly, it is understood that before, during, and after method 1400, Fig. 14 further operations may be provided and that some of these other operations can only be described briefly here.

[0100] The method 2000 begins with operation 2002, in which a substrate is provided according to various embodiments. The substrate comprises a semiconductor material substrate, for example, silicon. Alternatively, the substrate may comprise another elemental semiconductor material, such as germanium. The substrate may also comprise a compound semiconductor, such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The substrate may comprise an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate comprises an epitaxial layer. For example, the substrate may comprise an epitaxial layer located over a bulk semiconductor. Furthermore, the substrate may comprise a semiconductor-on-insulator (SOI) structure.For example, the substrate may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or by another suitable method such as wafer bonding and grinding.

[0101] The method 2000 continues with operation 2004, in which a stack comprising an alternating sequence of first nanostructures and second nanostructures is fabricated according to various embodiments. Such a stack may be fabricated based on one of the (active region) structures discussed above. The stack may be fabricated in a front side of the substrate. In some embodiments, the first nanostructures may comprise sacrificial SiGe nanostructures, and the second nanostructures may comprise Si channel nanostructures. Such a stack may occasionally be referred to as a superlattice. In one non-limiting example, the sacrificial SiGe nanostructures may be SiGe 25%. The notation "SiGe 25%" is used to indicate that 25% of the SiGe material is Ge.It is understood that the percentage of Ge in each of the SiGe sacrificial nanostructures can be any value between 0 and 100 (except 0 and 100) without departing from the scope of the present disclosure. In some other embodiments, the second nanostructures may comprise a first semiconductor material other than Si, and the first nanostructures may comprise a second semiconductor material other than SiGe, as long as the first and second semiconductor materials are each characterized by different etching properties (e.g., etching rates).

[0102] The alternating sequence of nanostructures can be created by epitaxially growing one layer and then the next layer until the desired number and thickness of the nanostructures are reached. Epitaxial materials can be grown from gaseous or liquid precursors. Epitaxial materials can be grown using vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), or another suitable process. Epitaxial silicon, silicon-germanium, and / or carbon-doped silicon (Si:C) can be doped (in-situ doped) by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), during deposition, depending on the type of transistor.

[0103] The method 2000 continues with operation 2006, in which a number of dummy gate structures are fabricated according to various embodiments. Such a dummy gate structure may be fabricated based on one of the (gate structure) structures discussed above. The dummy gate structure may extend along a direction perpendicular to the longitudinal direction of the dielectric fin structure (and the stack). Furthermore, in one of various embodiments, the dummy gate structure may be fabricated shorter than the dielectric fin structure, and thus, the dummy gate structure is cut (or otherwise separated) by the dielectric fin structure in the fabricated state.

[0104] The dummy gate structure can be formed by depositing amorphous silicon (a-Si) over the stack. Other materials suitable for forming dummy gates (e.g., polysilicon) can also be used without departing from the scope of the present disclosure. The a-Si is then planarized to a desired level. A hard mask is deposited over the planarized a-Si and patterned. The hard mask can be made of a nitride or an oxide layer. An etching process (e.g., a reactive ion etch (RIE) process) is applied to the a-Si to form the dummy gate structure. After forming the dummy gate structure, gate spacers can be formed to extend along sidewalls of the dummy gate structure. The gate spacers can be formed by conformal deposition of a dielectric material (e.g.,Silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC or a suitable combination of these materials) followed by a directed etch (e.g. RIE).

[0105] The method 2000 continues with operation 2008, in which inner spacers are formed by replacing end portions of each of the sacrificial SiGe nanostructures with a dielectric material according to various embodiments. After fabricating the dummy gate structure covering certain portions of the stack (e.g., the portions of the stack separated by the dielectric fin structure), the portions of the stack not covered by the dummy gate structure are removed. Subsequently, respective end portions of each sacrificial SiGe nanostructure of the covered stack are removed. The inner spacers are formed by filling such recesses of each sacrificial SiGe nanostructure with a dielectric material by chemical vapor deposition (CVD) or monolayer doping (MLD) of nitride followed by a spacer RIE.The material of the inner spacers can be made of the same material as the gate spacers described above or of a different material. For example, the inner spacers can be made of silicon nitride, silicon borocarbonitride, silicon carbonitride, silicon carbonoxynitride, or another dielectric material (e.g., a dielectric material with a dielectric constant k of less than about 5).

[0106] The method 2000 continues with operation 2010, in which a number of epitaxial structures are fabricated according to various embodiments. After fabricating the inner spacers, the epitaxial structures are fabricated using an epitaxial layer growth process on exposed ends of the Si nanostructures. In-situ doping (ISD) can be used to fabricate doped epitaxial structures, thereby creating the required junctions for a corresponding transistor (or sub-transistor). N- and P-FETs are fabricated by implanting various types of dopants into selected regions of the device to create the one or more required junctions. N-type devices can be fabricated by implanting arsenic (As) or phosphorus (P), and P-type devices can be fabricated by implanting boron (B).After the epitaxial structures have been produced, an interlayer dielectric (e.g. silicon dioxide) is deposited to cover the epitaxial structures.

[0107] The method 2000 continues with operation 2012, in which the dummy gate structures and the remaining sacrificial SiGe nanostructures are replaced with respective active gate structures according to various embodiments. Following the formation of the interlayer dielectric, the dummy gate structures are removed using an etching process, e.g., RIE or chemical oxide removal (COR). Then, the remaining sacrificial SiGe nanostructures are removed, while applying a selective etch (e.g., a hydrochloric acid (HCl)) to keep the Si channel nanostructure substantially intact. After removal of the sacrificial SiGe nanostructures, top and bottom surfaces and sidewalls of each of the Si channel nanostructures may be exposed, except for the sidewall in contact with the dielectric fin structure.Then, a number of active gate structures can be fabricated to enclose each of the Si channel nanostructures, except for the sidewall, which is in contact with the dielectric fin structure. Each of the active gate structures includes at least one gate dielectric layer (e.g., a high-k dielectric layer) and one gate metal layer (e.g., a work function metal layer). After fabricating the active gate structures, respective programming and reading transistors of the disclosed antifuse memory cells can be fabricated using the non-preconfigured antifuse cells, the default 0 antifuse cells, and the default 1 antifuse cells.

[0108] In some embodiments, the active gate structures of the programming transistors of the non-preconfigured antifuse cell, the default 0 antifuse cell, and the default 1 antifuse cell may each have different compositions or other configurations that cause their programming transistors to have a threshold voltage that is equal to, lower than, or higher than a threshold voltage of their corresponding read transistors. Some non-limiting examples for implementing the different threshold voltages include different thicknesses of the gate dielectric layers, different dielectric constants of the gate dielectric layer, different combinations of working exit metal layers, etc.

[0109] The method 2000 continues with operation 2014, in which a number of front-end interconnect structures are formed according to various embodiments. After the programming and reading transistors are formed, a number of middle-end interconnect structures (e.g., VGs, VDs, MDs) are formed over the programming and reading transistors. For example, a number of VGs may be formed to connect to the gate terminals of the programming and reading transistors, respectively, and a number of MDs may be formed to connect to the source / drain terminals of the programming and reading transistors, respectively. In addition, a number of back-end metal traces (e.g., Mo traces, M1 traces, M2 traces, etc.) may be formed.) are fabricated over the middle-end interconnect structures, which are operatively configured as the WLPs, WLRs and BLs to connect to the respective programming and reading transistors.

[0110] The front-side interconnect structure is formed from a metal material. The metal material can be selected from the group consisting of aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. Other metal materials are within the scope of the present disclosure. The front-side interconnect structures can be formed, for example, by covering the front side of the substrate with the above-mentioned metal material by chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating, electroplating, or combinations thereof.

[0111] Fig. 21 shows a flowchart of an exemplary method 2100 for testing a storage device according to some embodiments. Operations of the method 2100 may be performed to test the storage device 100 from Fig. 1, which includes a memory array, e.g., 102, and a number of peripheral circuits, e.g., 104, 106, and 108. Furthermore, the memory array 102 may include a number of default OTP memory cells with preconfigured logic states and positions with which the peripheral circuits can be tested. It should be noted that the method 2100 is merely an example and is not intended to limit the present disclosure. Accordingly, it is understood that further operations may be performed before, during, and after the method 2100 of Fig. 21, and that some other operations are only briefly described here.

[0112] The method 2100 begins with operation 2102, in which a memory array having a plurality of OTP memory cells is provided. Using the memory array 102 as a representative example, the memory array 102 includes a number of OTP memory cells 103. For example, the OTP memory cells 103 may be fabricated with a first logic state, and if programmable, the OTP memory cells 103 may be conversely programmed to a second, opposite logic state. In one aspect of the present disclosure, the OTP memory cells 103 are each implemented as an eFuse memory cell, e.g., comprising a fuse resistor and a WL transistor electrically connected in series with each other. In another aspect of the present disclosure, the OTP memory cells 103 are each implemented as an antifuse memory cell, e.g.,at least one programming transistor and one reading transistor which are electrically connected in series with each other.

[0113] The method 2100 continues with operation 2104, in which a first position of a first of the OTP memory cells in the memory array is determined. In some embodiments, the first OTP memory cell is configured to permanently represent a first logic state based on a short circuit. The first position of the first OTP memory cell may be selected by a user of the memory device. Continuing the above example, such a first OTP memory cell may be a default 0 eFuse cell, e.g., 103 21 from Fig. 2, or a default 0 antifuse cell, e.g., 103 21 from Fig. 15. The default 0 eFuse cell may default to represent a logic 0 through one or more shorted traces, as discussed above, and such a logic 0 may not be changed, provided that the default 0 eFuse cell is fabricated to represent the logic 0. The default o-antifuse cell may default to represent a logic 0 through a low threshold voltage programming transistor, as discussed above, and such a logic 0 may not be changed, provided that the default o-antifuse cell is fabricated to represent the logic 0.

[0114] The method 2100 continues with operation 2106, in which a second position of a second of the OTP memory cells in the memory array is determined. In some embodiments, the second OTP memory cell is configured to permanently represent a second logic state based on an open circuit. Similarly, the second position of the second OTP memory cell may be selected by the user of the memory device. Continuing the above example, such a second OTP memory cell may be a default 1 eFuse cell, e.g., 103 12 from Fig. 2, or a default 1 antifuse cell, e.g., 103 12 from Fig.15. The default 1 eFuse cell may default to represent a logic 1 through one or more open conductive lines, as discussed above, and such a logic 1 may not be changed, provided that the default 1 eFuse cell is fabricated to represent the logic 1. The default 1 antifuse cell may default to represent a logic 1 through a high threshold voltage programming transistor, as discussed above, and such a logic 1 may not be changed, provided that the default 1 antifuse cell is fabricated to represent the logic 1.

[0115] The method 2100 continues with operation 2108, in which, based on the first logic state in the first position and / or the second logic state in the second position, a functionality of a peripheral circuit operatively connected to the memory array may be verified. In some embodiments, the first and second positions of the first and second OTP memory cells may be preconfigured. Furthermore, respective numbers of the first and second OTP memory cells may also be preconfigured. Based on their positions in the memory array and respective predetermined logic states, respective functionalities of the one or more peripheral circuits (e.g., sense amplifiers of the I / O circuit) operatively connected to the memory array may be verified.For example, the logical state of a target cell, and where such a target cell is located in an array, may be preconfigured (e.g., known). If a sense amplifier operatively connected to the target cell reads a logical state that conflicts with the preconfigured logical state, the sense amplifier may be determined to be malfunctioning. In another example, given that the logical state and position of a target cell are both preconfigured and an operatively connected sense amplifier has been determined to be malfunctioning, one or more peripheral circuits (e.g., a corresponding column decoder and / or a corresponding row decoder) may be determined to be malfunctioning if the sense amplifier still reads a conflicting logical state.

[0116] In one aspect of the present disclosure, a memory device is disclosed. The memory device comprises a memory array having a plurality of memory cells. At least a first of the memory cells defaults to a permanent first logic state based on a short circuit. At least a second of the memory cells defaults to a permanent second logic state, opposite to the first logic state, based on an open circuit.

[0117] In another aspect of the present disclosure, a memory device is disclosed. The memory device comprises a memory array with a plurality of one-time programmable (OTP) memory cells. A first subset of the OTP memory cells is configured to permanently represent a first logic state based on a short circuit. A second subset of the OTP memory cells is configured to permanently represent a second logic state, opposite to the first logic state, based on an open circuit.

[0118] In yet another aspect of the present disclosure, a method is disclosed. The method includes fabricating a plurality of transistors along a major surface of a substrate. The method includes fabricating a plurality of metal traces over the plurality of transistors. A first of the transistors, together with at least a first of the plurality of metal traces, collectively forms a first memory cell in which the first metal trace forms a short circuit connected to the first transistor. A second of the transistors, together with at least a third and a fourth of the plurality of metal traces, collectively form a second memory cell in which the third and fourth metal traces form an open circuit connected to the second transistor.

[0119] The terms "about" and "approximately" as used herein generally indicate the value of a given quantity, which may vary depending on a particular technology node associated with the semiconductor device according to the invention. Depending on the specific technology node, the term "about" may indicate a value of a given quantity that varies within a range of, for example, 10 to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0120] Features of various embodiments have been described above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other methods and structures for achieving the same objectives and / or obtaining the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent interpretations do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 578,204

[0001]

Claims

[1] Storage device with: a memory matrix having a plurality of memory cells; wherein at least a first of the memory cells permanently represents a first logic state based on a short circuit as a default; and wherein at least a second of the memory cells defaults to a second logic state opposite to the first logic state based on an open circuit. [2] The memory device of claim 1, wherein the memory cells each comprise an eFuse memory cell. [3] The memory device according to claim 1 or 2, wherein the first memory cell comprises a transistor formed along a main surface of a substrate. [4] The memory device of claim 3, wherein the first memory cell further comprises: a first metal conductive line disposed over the main surface and extending along a first lateral direction; a second metal trace disposed over the main surface, extending along the first lateral direction, and spaced from the first metal trace along a second lateral direction perpendicular to the first lateral direction; a third metal trace disposed over the first and second metal traces and extending along the second lateral direction; a fourth metal conductor arranged over the first and second metal conductors and extending along the second lateral direction; and a fifth metal trace disposed over the first and second metal traces, extending along the second lateral direction, and located between the third and fourth metal traces; wherein the third and fourth metal traces each electrically connect the first metal trace to the second metal trace to form the short circuit; and wherein the fifth metal conductor track is electrically insulated from each of the first metal conductor track and the second metal conductor track. [5] The memory device of claim 4, wherein the third and fourth metal lines each have a first width along the first lateral direction and the fifth metal line has a second width along the first lateral direction, and wherein the first width is substantially greater than the second width. [6] The memory device of claim 2, wherein the second memory cell comprises a transistor formed along a major surface of a substrate. [7] The memory device of claim 6, wherein the second memory cell further comprises: a first metal conductive line disposed over the main surface and extending along a first lateral direction; a second metal trace disposed over the main surface, extending along the first lateral direction, and spaced from the first metal trace along a second lateral direction perpendicular to the first lateral direction; a third metal trace disposed over the first metal trace and extending along the second lateral direction; a fourth metal trace disposed over the second metal trace and extending along the second lateral direction; a fifth metal trace disposed over the first metal trace, extending along the second lateral direction, and spaced from the third metal trace along the first lateral direction; a sixth metal trace disposed over the second metal trace, extending along the second lateral direction, and spaced from the fourth metal trace along the first lateral direction; and a seventh metal trace disposed over the first and second metal traces, extending along the second lateral direction, and located between the third and fifth metal traces and between the fourth and sixth metal traces; wherein the third and fifth metal conductors are each electrically connected to the first metal conductor, and the fourth and sixth metal conductors are each electrically connected to the second metal conductor, but the third metal conductor is electrically insulated from the fourth metal conductor and the fifth metal conductor is electrically insulated from the sixth metal conductor to form the open circuit; and wherein the seventh metal conductor is electrically insulated from each of the first metal conductor and the second metal conductor. [8] The memory device of claim 7, wherein the third to sixth metal lines each have a first width along the first lateral direction and the seventh metal line has a second width along the first lateral direction, and wherein the first width is substantially greater than the second width. [9] The memory device of claim 1, wherein the memory cells each comprise an antifuse memory cell. [10] The memory device of claim 9, wherein the first memory cell comprises a read transistor and a program transistor connected in series with each other, the read transistor having a first threshold voltage and the program transistor having a second threshold voltage, and the second threshold voltage being substantially lower than the first threshold voltage to form the short circuit. [11] The memory device of claim 9, wherein the second memory cell comprises a read transistor and a program transistor connected in series with each other, the read transistor having a first threshold voltage and the program transistor having a second threshold voltage, and the second threshold voltage being substantially higher than the first threshold voltage to form the open circuit. [12] The memory device of claim 1, wherein respective positions of the first memory cell and the second memory cell in the memory array are preconfigured. [13] Storage device comprising: a memory matrix having a plurality of OTP memory cells; wherein a first subset of the OTP memory cells is configured to permanently represent a first logic state based on a short circuit; and wherein a second subset of the OTP memory cells is configured to permanently present a second logic state opposite to the first logic state based on an open circuit. [14] The memory device of claim 13, wherein the first subset of OTP memory cells each comprises: a transistor connected to the short circuit; a first metal trace disposed over the transistor and extending along a first lateral direction; a second metal trace disposed over the transistor, extending along the first lateral direction, and spaced from the first metal trace along a second lateral direction perpendicular to the first lateral direction; a third metal trace disposed over the first and second metal traces and extending along the second lateral direction; a fourth metal conductor arranged over the first and second metal conductors and extending along the second lateral direction; and a fifth metal trace disposed over the first and second metal traces, extending along the second lateral direction, and located between the third and fourth metal traces; wherein the third and fourth metal traces each electrically connect the first metal trace to the second metal trace to form the short circuit; and wherein the fifth metal conductor track is electrically insulated from each of the first metal conductor track and the second metal conductor track. [15] The memory device of claim 14, wherein the third and fourth metal lines each have a first width along the first lateral direction, and the fifth metal line has a second width along the first lateral direction, and wherein the first width is substantially greater than the second width. [16] The memory device of claim 13, wherein the second subset of OTP memory cells each comprises: a transistor connected to the open circuit; a first metal conductive line disposed over the main surface and extending along a first lateral direction; a second metal trace disposed over the main surface, extending along the first lateral direction, and spaced from the first metal trace along a second lateral direction perpendicular to the first lateral direction; a third metal trace disposed over the first metal trace and extending along the second lateral direction; a fourth metal trace disposed over the second metal trace and extending along the second lateral direction; a fifth metal trace disposed over the first metal trace, extending along the second lateral direction, and spaced from the third metal trace along the first lateral direction; a sixth metal trace disposed over the second metal trace, extending along the second lateral direction, and spaced from the fourth metal trace along the first lateral direction; and a seventh metal trace disposed over the first and second metal traces, extending along the second lateral direction, and located between the third and fifth metal traces and between the fourth and sixth metal traces; wherein the third and fifth metal conductors are each electrically connected to the first metal conductor, and the fourth and sixth metal conductors are each electrically connected to the second metal conductor, but the third metal conductor is electrically insulated from the fourth metal conductor and the fifth metal conductor is electrically insulated from the sixth metal conductor to form the open circuit; and wherein the seventh metal conductor track is electrically insulated from each of the first metal conductor track and the second metal conductor track. [17] The memory device of claim 16, wherein the third to sixth metal lines each have a first width along the first lateral direction and the seventh metal line has a second width along the first lateral direction, and wherein the first width is substantially greater than the second width. [18] The memory device of any one of claims 13 to 17, wherein respective positions of the first subset of memory cells and the second subset of memory cells in the memory matrix and respective numbers of the first subset of memory cells and the second subset of memory cells are preconfigured. [19] Procedure with the following steps: fabricating a plurality of transistors along a major surface of a substrate; and forming a plurality of metal conductive lines over the plurality of transistors; wherein a first of the transistors together with at least a first of the plurality of metal traces collectively forms a first memory cell in which the first metal trace forms a short circuit connected to the first transistor; and wherein a second of the transistors together with at least a third and a fourth of the plurality of metal lines collectively form a second memory cell in which the third and fourth metal lines form an open circuit connected to the second transistor. [20] The method of claim 19, wherein the first memory cell defaults to a first logic state based on the short circuit, and the second memory cell defaults to a second logic state based on the open circuit.

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