Method of forming a wide band gap semiconductor device

Abstract

A method for forming a wide bandgap semiconductor device (100) is proposed. The method comprises forming a trench (102) extending from a first surface (1041) of the wide bandgap semiconductor body (104) into a wide bandgap semiconductor body (104). The method further comprises forming a shielding region (106) comprising introducing dopants of a first conductivity type into the wide bandgap semiconductor body (104) through a bottom and / or a sidewall of the trench (102) by ion implantation. Thereafter, the method further comprises extending the trench (102), comprising an extension process for forming a sacrificial oxide (122) lining sidewalls and a bottom of the trench (102) by thermal oxidation and removing the sacrificial oxide (122).

Description

TECHNICAL FIELDThe present disclosure relates to a method of forming a semiconductor device, and more particularly, to a method of forming a semiconductor device including a wide band gap semiconductor body.BACKGROUNDTechnology development of new generations of wide band gap semiconductor devices, e.g., insulated gate field effect transistors (IGFETs), such as metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs), aims to improve electrical device characteristics and reduce costs by shrinking device geometries. Although cost can be reduced by shrinking device geometries, a variety of tradeoffs and challenges must be met as device functionalities per unit area are increased. For example, reducing the area specific on-state resistance, R on xA, may pose a challenge with process related variations in arranging trenches relative to doped regions or doped regions relative to each other. Such process related variations may be caused by process technology comprising different lithographic levels. For example, the formation of contacts, e.g., contact plugs or vias, on mesa regions may pose a challenge in shrinking the width of the mesa to reduce the area specific on-state resistance, R on xA.There is a need to improve formation methods of wide band gap semiconductor devices.SUMMARYAn example of the present disclosure relates to a method of forming a wide band gap semiconductor device. The method includes forming a trench extending from a first surface of the wide bandgap semiconductor body into a wide bandgap semiconductor body. The method further includes forming a shielding region including introducing dopants of a first conductivity type into the wide band gap semiconductor body through a bottom side and / or a sidewall of the trench by ion implantation. Thereafter, the method further includes expanding the trench including an expansion process for forming a sacrificial oxide lining sidewalls and a bottom of the trench by thermal oxidation and removing the sacrificial oxide.Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments for forming wide band gap semiconductor devices and, together with the description, serve to explain principles of the embodiments. Other embodiments are described in the following detailed description and claims. FIG. 1 schematically and exemplarily illustrates process features for forming a wide band gap semiconductor device. FIGS. 2A to 2C are cross-sectional views illustrating example process features for forming a wide band gap semiconductor device. FIGS. 3A to 3H are schematic cross-sectional views for illustrating process features for forming a SiC semiconductor device including a channel region on a sidewall of a gate trench. FIGS. 4A to 4G are schematic cross-sectional views for illustrating process features for forming a SiC semiconductor device including a channel region on opposing first and second sidewalls of a gate trench. FIGS. 5A and 5B are schematic cross-sectional views illustrating example process features for forming a pillar-shaped region and a connection region. FIGS. 6A to 6C are schematic cross-sectional views for illustrating example process features for forming a current spread layer. FIGS. 7A and 7B are schematic cross-sectional views illustrating example process features for forming an interconnect region.DETAILED DESCRIPTIONIn the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific examples in which semiconductor substrates may be processed. It should be understood that other examples may be used and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one example may be used in or in conjunction with other examples to provide yet another example. It is intended that the present disclosure encompass such modifications and variations. The examples are described using a specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Corresponding elements are denoted by the same reference numerals throughout the several drawings unless otherwise indicated.The terms "have", "contain", "comprise", "have" and the like are open-ended, and the terms indicate the presence of the stated structures, elements or features, but do not exclude the presence of additional elements or features. The articles "a", "an", and "the / s" are intended to include both the plural and the singular, unless the context clearly indicates otherwise.The term "electrically connected" may describe a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the relevant elements or a low-ohmic connection via a metal and / or heavily doped semiconductor material. The term "electrically coupled" may include that one or more intermediate element(s) configured for signal and / or power transmission may / may be connected between the electrically coupled elements, for example elements controllable to temporarily provide a low impedance connection in a first state and a high impedance electrical decoupling in a second state.When two elements A and B are combined using an "or", it is to be understood that all possible combinations are disclosed, i.e., only A, only B, and A and B, unless expressly or implicitly defined otherwise. An alternative formulation for the same combinations is "at least one of A and B" or "A and / or B". The same applies mutatismutatally to combinations of more than two elements.Ranges indicated for physical dimensions include the limits. For example, a range for a parameter y reads from a to b as a≤y≤b. The same applies to ranges having a limit value such as "at most" and "at least.".The main components of a layer or structure of a chemical compound or alloy are those elements whose atoms form the chemical compound or alloy. For example, silicon (Si) and carbon (C) are the main constituent elements of a silicon carbide (SiC) layer.The term "on" should not be construed to mean only "directly on". Rather, when an element is positioned "on" another element (e.g., a layer "on" another layer or "on" a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate when the layer is "on" the substrate).The specification and drawings merely illustrate the principles of the disclosure. Further, all examples listed herein are intended primarily for illustrative purposes only to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventors to further developing the prior art. All statements herein reflecting principles, aspects, and examples of the disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof.It is to be understood that the disclosure of multiple steps, processes, operations, steps, or functions disclosed in the specification or claims should not be construed as being in the specific order unless expressly or implicitly stated otherwise, e.g., by terms such as "thereafter", for example, for technical reasons. Therefore, the disclosure of multiple steps or functions does not limit them to a particular order unless these steps or functions are not interchangeable for technical reasons. Further, in some examples, a single step, function, process, operation, or step may include or be broken into multiple substeps, functions, processes, operations, or steps. Such substeps may be included and form part of the disclosure of this single step unless explicitly excluded.A configuration example of a method of forming a wide band gap semiconductor device may include forming a trench extending from a first surface of the wide band gap semiconductor body into a wide band gap semiconductor body. The method may further include forming a shielding region including introducing dopants of a first conductivity type into the wide band gap semiconductor body through a bottom side and / or a sidewall of the trench by ion implantation. Thereafter, the method may further include expanding the trench including an expansion process of forming a sacrificial oxide lining sidewalls and a bottom of the trench by thermal oxidation and removing the sacrificial oxide.The wide band gap semiconductor device may be part of an integrated circuit, for example, or may be a discrete semiconductor device or a semiconductor module. The wide band gap semiconductor device may be, for example, or may include an insulated gate field effect transistor (IGFET) such as a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). The wide band gap semiconductor device may be a vertical semiconductor device having a load current flow between the first surface and a second surface opposite to the first surface. The vertical power semiconductor device may be configured to conduct currents of more than 1 A or more than 10 A or more than 30 A or more than 50 A or more than 75 A or even more than 100 A, and may be further configured to block voltages between load electrodes, e.g. between collector and emitter on an IGBT or between drain and source of a MOSFET, in the range of several hundred to several thousand volts, e.g. 400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV, 10 kV. The blocking voltage may correspond to, for example, a voltage class specified in a data sheet of the power semiconductor device.The wide band gap semiconductor device may be based on a wide band gap semiconductor body made of a wide band gap crystalline semiconductor material having a band gap larger than the band gap of silicon, i.e., larger than 1.12 eV. The wide band gap semiconductor material may have a hexagonal crystal lattice and may be, for example, silicon carbide (SiC). For example, the semiconductor material may be 2H-SiC (2H-polytype SiC), 6H-SiC, or 15R-SiC. According to an example, the semiconductor material is silicon carbide of the 4H polytype (4H-SiC). The semiconductor body may comprise or consist of a semiconductor substrate having no, one or more than one semiconductor layer, e.g. epitaxially grown layers, thereon. One of the semiconductor layers may be, for example, a doped semiconductor layer of a current spreading layer.The first surface may be a front surface or an upper surface of the wide bandgap semiconductor body, and the wide bandgap semiconductor body may further include a second surface, which may be, for example, a back surface or a back surface of the wide bandgap semiconductor body. The wide bandgap semiconductor body may be attached to a lead frame via the second surface, for example. For example, bond pads may be disposed over the first surface of the wide bandgap semiconductor body and bond wires may be bonded to the bond pads.For example, the trench may be stripe-shaped and may define the dimensions of a trench gate structure formed in the trench.To realize a desired current carrying capacity, the wide band gap semiconductor device may be configured by a plurality of wide band gap semiconductor device cells connected in parallel. The parallel-connected wide band gap semiconductor device cells may be, for example, wide band gap semiconductor device cells formed in the form of a stripe or a stripe segment. Of course, the wide band gap semiconductor device cells may also have any other shape, e.g., circular, elliptical, polygonal, such as hexagonal or octahedral. The wide band gap semiconductor device cells may be disposed in the transistor cell region of the wide band gap semiconductor body. The transistor cell region may be a region in which an emitter region of an IGBT (or a source region of a MOSFET) and a collector region of an IGBT (or a drain region of a MOSFET) are disposed opposite to each other along the vertical direction. In the transistor cell region, a load current may enter or leave the wide band gap semiconductor body of the semiconductor device, e.g., via contact plugs on the first surface of the wide band gap semiconductor body. The wide band gap semiconductor device may further include an edge termination region that may include a termination structure. In a blocking mode or in a reverse biased mode of the wide band gap semiconductor device, the blocking voltage between the transistor cell region and a field free region falls laterally across the termination structure. The termination structure may have a higher or a slightly lower voltage blocking capability than the transistor cell region. The termination structure may include, for example, a junction termination extension (JTE) with or without variation of lateral doping (VLD), one or more laterally separated guard rings, or any combination thereof.The first mask pattern may be formed as a first hard mask pattern, e.g., an oxide hard mask pattern. The first mask pattern may be defined by a photolithography process, for example. Dimensions and arrangement of opening(s) in the first mask pattern may define, for example, a layout of a trench / trenches for forming the trench gate structure of the semiconductor device. The trench or trenches may be formed by an etching process, for example. Before forming the first mask pattern, the method may further comprise introducing dopants into the wide band gap semiconductor body, e.g. by ion implantation, to define semiconductor layers in the wide band gap semiconductor body, e.g. a current spreading layer and / or a body layer and / or a source layer.The ion implantation of dopants for the shielding region may be based on non-tilted and / or tilted ion implantation(s). By varying the tilt angle, dopants may also be implanted into the wide band gap semiconductor body through a lower part of the sidewall of the trench, for example. Prior to performing ion implantation process(s) through the bottom and / or sidewall of the trench, a shield dielectric, e.g., a shield oxide having a thickness of, for example, 20 nm to 200 nm, may be formed on the bottom and / or sidewalls of the trench. This may allow reducing or avoiding channelization effects and absorbing ions scattered at the trench sidewalls. The shielding dielectric can also be formed, for example, from materials other than oxide, e.g. polycrystalline silicon or silicon nitride or aluminum oxide.The expansion process is initiated by forming the sacrificial oxide lining sidewalls and the bottom of the trench by thermal oxidation. Lateral and vertical extension of the trench may be accurately controlled by, for example, oxidation time, temperature, and oxygen partial pressure. Optionally, a hydrogen treatment may be performed prior to the formation of the sacrificial oxide.The methods described herein may enable a self-aligned arrangement of a shielding region with respect to a trench gate structure. Critical alignment parameters of the shielding region, such as lateral distance to the sidewall of the trench gate structure or vertical extension from a bottom of the trench gate structure and a width of the trench gate structure, may be well controlled by ion implantation parameters, e.g., energy, of the ion implantation process for the shielding region, as well as oxidation parameters, e.g., temperature, time and oxygen partial pressure, of the sacrificial oxide. This may simplify the shrinkage of the width of the mesa including the source / body regions to reduce the area specific on-state resistance.For example, the expansion process may be repeated a plurality of times. Thus, the formation of the sacrificial oxide by thermal oxidation and removal of the sacrificial oxide may be repeated a plurality of times. A thickness of the sacrificial oxides formed subsequently may be different from each other or may be the same, e.g., by controlling the thermal oxidation times for each sacrificial oxide. Repetition of sacrificial oxide formation and removal may allow to counteract thickness limitations of a single sacrificial oxide, which may be caused, for example, by a decreasing oxide growth rate with increasing oxide thickness.For example, a width of the trench may be extended by 10% to 80% at a first horizontal reference level. In other words, each sidewall of opposing sidewalls of the trench may be laterally offset outward by 5% to 40% of the original trench width compared to the trench width prior to the expansion process. The first horizontal reference level may have the same vertical distance to the first surface as to a bottom of the trench prior to the extension process. For example, the trench widening may be in the range of one or more tens of nanometers to one or more hundreds of nanometers.For example, forming the wide band gap semiconductor device may further include forming a trench gate dielectric in the trench after the extension process. Between the expansion process and the trench gate dielectric or directly before the trench gate dielectric, one or more cleaning processes for surface conditioning may be performed. The trench gate dielectric may be formed by an oxidation process or may include an oxidation process, e.g., a thermal oxidation process and / or an oxide deposition process. Other dielectric materials may be used in addition to or as an alternative to the oxide. For example, high-k materials may be used. For example, the trench gate dielectric layer may include a high-k dielectric layer including at least one of Al 2 O 3, ZrO 2, HfO 2, AlN, aluminosilicate AlSiOx, silicon La- or Si-doped HfO 2, TiO 2, Y 2 O 3 or Si 3 N 4. For example, the trench gate dielectric may include at least a first dielectric sublayer and a second dielectric sublayer. The first dielectric sublayer adjoining a channel region may have a dielectric constant that is less than the dielectric constant of the high-k dielectric sublayer, e.g. equal to or greater than the dielectric constant of SiO 2. For example, the first dielectric layer may include at least one of SiO 2, AlN, or Si 3 N 4. The trench gate electrode may comprise one or more conductive material(s) e.g. metal, metal alloys e.g. Cu, Au, AlCu, Ag or alloys thereof, metal compounds e.g. TiN, highly doped semiconductor material such as highly doped polycrystalline silicon. The one or more conductive materials may form a layer stack, for example. The trench gate electrode may be electrically connected to a gate pad via a gate interconnect structure, such as a gate runner. The gate pad / the interconnection structure and, for example, a first load electrode pad, e.g., a source pad of a MOSFET or an emitter pad of an IGBT, may be part of a wiring region over the wide band gap semiconductor body. Forming the wiring region may comprise forming one or more than one, e.g. two, three, four or even more wiring levels. Each wiring level may be formed by a single or a stack of conductive layers, e.g. metal layer(s). The wiring levels may be lithographically patterned, for example. An interlayer dielectric structure may be disposed between stacked wiring levels. Contact plug(s) and / or contact line(s) may be formed in openings of the interlayer dielectric structure to electrically connect portions, e.g., metal lines or contact regions, of different wiring levels to each other.For example, the method may further include, before forming the trench, forming a first mask pattern over the first wide band gap surface of the semiconductor body. The first mask pattern may have an opening exposing a transistor cell region of the wide band gap semiconductor body. The method may further include forming a source layer including introducing dopants of a second conductivity type into the transistor cell region of the wide band gap semiconductor body through the first surface by ion implantation. The ion implantation may be a blanket ion implantation in the transistor cell region. In other words, the source layer may be formed in an entire area of the transistor cell area. The method may further include forming a body layer including introducing dopants of the first conductivity type into the transistor cell region of the wide band gap semiconductor body through the first surface by ion implantation. Similar to the source layer, the body layer may be formed by blanket ion implantation in the transistor cell region. The method may further include forming a current spreading layer including dopants of the second conductivity type. Similar to the source layer and the body layer, forming the current spreading layer may include introducing dopants of the second conductivity type into the transistor cell region of the wide band gap semiconductor body through the first surface by blanket ion implantation in the transistor cell region. In addition to or as an alternative, at least a portion of the current spread layer may also be formed by an epitaxial layer deposition process. The layer deposition process may be part of a layer deposition on a wide band gap semiconductor substrate. The layer deposition may form the uppermost region of the wide band gap semiconductor body in which the mesa regions bounded by gate trenches are formed. Doping the current spread layer with dopants of the second conductivity type may be performed, for example, in situ or by blanket ion implantation after the epitaxial layer deposition process. A bottom side of the current spread layer may be below a bottom side of the trench. In other words, a bottom side of the current spread layer may have a greater vertical distance to the first surface than a bottom side of the trench.For example, a bottom side of the shielding region may be positioned at a smaller vertical distance to the first surface than a bottom side of the current spreading layer. Thereby, a pn junction between the shielding region and the current spreading layer may be defined at least at the bottom of the shielding region.For example, the method may further include, before forming the trench, forming a second mask pattern over the first wide band gap surface of the semiconductor body. The second mask pattern may have an opening exposing a part of the transistor cell region of the wide band gap semiconductor body. The method may further include forming a pillar-shaped region including introducing dopants of the first conductivity type through the opening at the first surface into the transistor cell region of the wide band gap semiconductor body by ion implantation. The pillar-shaped region may contribute to electrically connecting the shielding region to an electrode pad over the first surface, for example.For example, a bottom side of the pillar-shaped region may be positioned between a bottom side of the body region and a bottom side of the current spreading layer. In some examples, the bottom side of the pillar-shaped region may also be positioned between a bottom side of the body region and a bottom side of the trench or between a bottom side of the source layer and a bottom side of the body layer.For example, after forming the trench, the method may further include forming a connection region including introducing dopants of the first conductivity type into the wide band gap semiconductor body through a sidewall of the trench by ion implantation. A bottom surface of the connection region may be adjusted by an inclination angle of ion implantation and by considering a thickness of an ion implantation mask. The connection region may provide an electrical coupling between the shielding region and the pillar-shaped region.For example, the dopants of the first conductivity type of the connection region may be further introduced into the wide band gap semiconductor body through a bottom side of the trench by ion implantation. For example, the dopants may be implanted simultaneously through the bottom and the sidewall by adjusting the angle of inclination of the ion implantation. As an alternative or in addition to implanting the dopants through the sidewall and optionally the bottom side, a further ion implantation process, e.g. not tilted or with a smaller tilt angle, may be performed to introduce the dopants through the bottom side of the trench.For example, the method may further include forming a third mask pattern over the first surface of the wide band gap semiconductor body. The third mask pattern may have an opening exposing a trench gate region of the transistor cell region of the wide band gap semiconductor body. The method may further include etching the trench into the wide band gap semiconductor body via the opening in the third mask pattern. The third mask pattern may serve as an ion implantation mask for forming the shield region.For example, before etching the trench, a connection region may be formed by introducing dopants of the first conductivity type into the wide band gap semiconductor body through the opening in the third mask pattern by ion implantation, e.g., tilted ion implantation.For example, removing the sacrificial oxide may include wet etching. The wet etching may be based on, for example, a hydrofluoric acid, HF, etching solution.For example, after forming the trench and before forming the shielding region, the method may further include forming an auxiliary dielectric lining sidewalls and a bottom of the trench. For example, the auxiliary dielectric may be an oxide and may be formed by thermal oxidation and / or deposition. The auxiliary dielectric may serve as a shielding dielectric at a bottom and / or sidewall of the trench for the ion implantation process of the shielding region, for example. The auxiliary dielectric can also be formed, for example, from materials other than oxide, e.g. polycrystalline silicon or silicon nitride or aluminum oxide.For example, after forming the shielding region and before expanding the trench, the method may further include removing the auxiliary oxide. The auxiliary region may be removed by wet etching. The wet etching may be based on, for example, a hydrofluoric acid, HF, etching solution.Details regarding the structure or function or technical utility of features described above regarding a wide band gap semiconductor device such as an FET or IGBT apply equally to the example methods further described below. Processing the wide band gap semiconductor body may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below.Some of the above and following examples are described in connection with a silicon carbide substrate. Alternatively, a wide band gap semiconductor substrate, e.g., a wide band gap wafer, may be processed, e.g., comprising a wide band gap semiconductor material different from silicon carbide. The wide bandgap semiconductor wafer may have a bandgap larger than the bandgap of silicon (1.12 eV). For example, the wide band gap semiconductor wafer may be a silicon carbide (SiC) wafer or gallium arsenide (GaAs) wafer.Functional and structural details described with respect to the above examples apply equally to the example embodiments illustrated in the figures and further described below. In the illustrated examples, n-channel FETs or IGBTs are illustrated. However, the examples described herein may also be applied to p-channel devices, e.g. p-channel MOSFETs or p-channel IGBTs.The process illustration of FIG. 1 relates to process features for forming a wide band gap semiconductor device. An example and more detailed illustration of the process features of FIG. 1 is shown in the cross-sectional views of FIGS. 2A through 2C. The first conductivity type may be, for example, an n-type and the second conductivity type may be, for example, a p-type for an n-channel FET. The first conductivity type may also be a p-type, for example, and the second conductivity type may be an n-type for a p-channel FET, for example.Referring to the process feature S 100 of FIG. 1 and the example cross-sectional view of FIG. 2A, the process feature S 100 includes forming a trench (e.g., the trench 102 in FIG. 2A ) extending from a first surface (e.g., the first surface 1041 in FIG. 2A ) of the wide band gap semiconductor body into a wide band gap semiconductor body (e.g., the wide band gap semiconductor body 104 in FIG. 2A ).Referring to the process feature S 110 of FIG. 1 and the example cross-sectional view of FIG. 2B, the process feature S 110 includes forming a shielding region (e.g., the shielding region 106 in FIG. 2B ) including introducing dopants of a first conductivity type into the wide band gap semiconductor body through a bottom side and / or a sidewall of the trench by ion implantation.Referring to the process feature S 120 of FIG. 1 and the example cross-sectional view of FIG. 2C, the process feature S 120 includes expanding the trench including an expansion process to form a sacrificial oxide lining sidewalls and a bottom of the trench by thermal oxidation and removal of the sacrificial oxide.Referring to FIG. 2C, a width of the trench 102 is extended at a first horizontal reference level href 1 by 10% to 80%. The first horizontal reference level href 1 has the same vertical distance to the first surface 1041 as to a bottom 1021 of the trench 102 before the extension process.The schematic cross-sectional views of FIGS. 3A to 3H illustrate process features for forming a configuration example of a wide band gap semiconductor device 100 comprising a channel region on one of opposing sidewalls of a trench gate structure.Referring to FIG. 3A, an n +- doped source layer 110 is formed in a transistor cell region TCA of an SiC semiconductor body 1043 by ion implantation of n-type dopants through the first surface 1041. The ion implantation process is bare or non-masked with respect to the transistor cell region TCA. However, masked regions may be formed outside the transistor cell region TCA (not illustrated in FIG. 3A ). A p-doped body layer 112 is formed in the transistor cell region TCA of the SiC semiconductor body 1043 by ion implantation of p-type dopants through the first surface 1041. An optional n-doped current spreading layer 114 is formed in the transistor cell region TCA of the SiC semiconductor body 1043 by ion implantation of n-type dopants through the first surface 1041. The ion implantation process is blanket / blanket or unmasked with respect to the transistor cell region TCA. The ion implantation process of the n-doped current spread layer 114 may also be masked to later have a minimum overlap with the p-type shielding structure (patterned current spread as illustrated in FIGS. 6A, 6B ). This may be advantageous, for example, for avoiding leakage currents in the blocking mode. Instead of or in addition to implanting n-type dopants to form the n-doped current spread layer 114, the current spread layer 114 may be formed on a SiC base substrate by an epitaxial deposition process when defining a semiconductor layer stack on the SiC base substrate. In this case, the formation of the current spread layer 114 may be partially or completely completed before the source and / or body layers 110, 112 are formed.A p-doped pillar-shaped region 116 is formed in the transistor cell region TCA of the SiC semiconductor body 1043 by a masked ion implantation process of p-type dopants through the first surface 1041 (ion implantation mask, not illustrated in FIG. 3A ). A bottom side of the p-doped columnar region 116 is positioned between a bottom side of the p-doped body region 112 and a bottom side of the n-doped current spreading layer 114.Referring to FIG. 3B, a mask pattern 120 is formed over the first surface 1041 of the SiC semiconductor body 1043. The mask pattern 120 has an opening exposing a trench gate region of the transistor cell region TCA of the SiC semiconductor body 1043. A trench 102 is etched into the SiC semiconductor body 1043 via the opening in the mask pattern 120. The etching of the trench 102 structures the source layer 110 into source regions 1101and further structures the body layer 112 into body regions 1121. On a first sidewall of the trench 102, a portion of the source region 1101, the body region 1121and the current spreading layer 114 is exposed, respectively. On a second sidewall of the trench 102 opposite the first sidewall, a portion of the pillar-shaped region 116 and the current spreading layer 114 is exposed, respectively.Referring to FIG. 3C, p-type dopants are introduced into the SiC semiconductor body 1043 by ion implantation through at least one of a bottom side or a sidewall of the trench 102, e.g., not tilted or slightly tilted (tilt angles may also differ with respect to opposing sidewalls) ion implantation, as illustrated in FIG. 3C for the non-tilted case. Thereby, a p-doped shielding region 106 is formed. For the ion implantation process of the p-type dopants for the shielding region 106, the mask pattern 120 may be used as an ion implantation mask.Referring to FIG. 3D, p-type dopants are introduced into the SiC semiconductor body 1043 through a sidewall and / or bottom of the trench 102 by ion implantation, e.g., tilted ion implantation, as illustrated in FIG. 3D (tilt angle may be larger than in FIG. 3C, for example). A p-doped connection region 118 is thereby formed. For the ion implantation process of the p-type dopants for the connection region 118, the mask pattern 120 may be used as an ion implantation mask. The connection region 118 electrically connects the shielding region 106 and the pillar-shaped region 116. After forming the connection region 118, the mask pattern 120 is removed, e.g. by wet etching using, for example, an HF solution. A high temperature annealing (HTA) may follow.Referring to FIG. 3E, an expansion process of the trench 102 is initiated by forming a sacrificial oxide 122 lining sidewalls and a bottom of the trench 102 through thermal oxidation. Lateral and vertical extension of the trench 102 may be accurately controlled by, for example, oxidation time, temperature, and oxygen partial pressure. Optionally, a hydrogen treatment may be performed before or after the formation of the sacrificial oxide 122.Referring to FIG. 3F, the sacrificial oxide 122 in the transistor cell region TCA is removed, e.g., by wet etching using, for example, an HF solution. The extension process of the trench 102 illustrated in FIGS. 3E and 3F may be repeated one or more times. The sacrificial oxide may be held in portions of the SiC semiconductor body 1043 outside the transistor cell region TCA, e.g. in inactive chip regions by a resist mask protecting the sacrificial oxide 122 from the etching process.Referring to FIG. 3G, a trench gate structure 124 is formed in the trench 102. Forming the trench gate structure 124 includes forming a trench gate dielectric 1241 in the trench 102, e.g., by thermal oxidation or deposition. Forming the trench gate structure 124 further includes forming a trench gate electrode 1242 on the trench gate dielectric 1241. Forming the trench gate structure 124 may further include post-oxidation annealing in a nitrogen-containing atmosphere, for example. The trench gate electrode 1242 may include one or a stack of conductive materials, e.g., highly doped polycrystalline silicon.Referring to FIG. 3H, an interlayer dielectric 126 is formed over the SiC semiconductor body 1043. A first load electrode 128, e.g., source or emitter electrode, is formed over the interlayer dielectric 126. The interlayer dielectric 126 electrically isolates the trench gate electrode 1242 from the first load electrode 128. Contact openings in the interlayer dielectric 126 enable electrical contact between the first load electrode 128 and the SiC semiconductor body 1043, e.g. the source and body regions 1101, 1121. A second load electrode 130, e.g., drain or collector electrode, is formed over a second surface 1042 of the SiC semiconductor body 1043. In some examples, not illustrated in FIG. 3H, the interlayer dielectric 126 may be formed in an upper or upper portion of the trench 102.The schematic cross-sectional views of FIGS. 4A to 4G illustrate process features for forming a configuration example of a wide band gap semiconductor device 100 including a channel region on both of opposing sidewalls of a trench gate structure.Referring to FIG. 4A, an n +- doped source layer 110 is formed in a transistor cell region TCA of an SiC semiconductor body 1043 by ion implantation of n-type dopants through the first surface 1041. The ion implantation process is blanket / blanket or unmasked with respect to the transistor cell region TCA. A p-doped body layer 112 is formed in the transistor cell region TCA of the SiC semiconductor body 1043 by ion implantation of p-type dopants through the first surface 1041. An n-type current spreading layer 114 is formed in the transistor cell region TCA of the SiC semiconductor body 1043 by ion implantation of n-type dopants through the first surface 1041. The ion implantation process is blanket / blanket or unmasked with respect to the transistor cell region TCA. Instead of or in addition to implanting n-type dopants to form the n-doped current spread layer 114, the current spread layer 114 may be formed by an epitaxial deposition process on a SiC base substrate when defining the semiconductor layer stack of the SiC semiconductor body 1043. In this case, the formation of the current spread layer 114 may be partially or completely completed before the source and / or body layers 110, 112 are formed. A mask pattern 120 is formed over the first surface 1041 of the SiC semiconductor body 1043. The mask pattern 120 has an opening exposing a trench gate region in the transistor cell region TCA of the SiC semiconductor body 1043. A trench 102 is etched into the SiC semiconductor body 1043 via the opening in the mask pattern 120. The etching of the trench 102 structures the source layer 110 into source regions 1101and further structures the body layer 112 into body regions 1121. On a first sidewall of the trench 102, a portion of the source region 1101, the body region 1121and the current spreading layer 114 is exposed, respectively. Similarly, on a second sidewall of the trench 102 opposite the first sidewall, a portion of the source region 1101, the body region 1121and the current spreading layer 114 is exposed, respectively.Referring to FIG. 4B, p-type dopants are introduced into the SiC semiconductor body 1043 by at least one of a bottom side or a sidewall of the trench 102 by ion implantation, e.g., non-tilted ion implantation, as illustrated in FIG. 4B. Prior to performing the ion implantation, an optional auxiliary or shielding dielectric, e.g., an oxide, may be formed and line sidewalls and a bottom of the trench 102. The auxiliary dielectric may be formed by thermal oxidation and / or deposition, for example.Thereby, a p-doped shielding region 106 is formed. For the ion implantation process of the p-type dopants for the shielding region 106, the mask pattern 120 may be used as an ion implantation mask.Referring to FIG. 4C, an expansion process of the trench 102 is initiated by forming a sacrificial oxide 122 lining sidewalls and a bottom of the trench 102 through thermal oxidation. Lateral and vertical extension of the trench 102 may be accurately controlled by, for example, oxidation time, temperature, and oxygen partial pressure. Optionally, a hydrogen treatment may be performed before or after the formation of the sacrificial oxide 122.Referring to FIG. 4D, the sacrificial oxide 122 in the transistor cell region TCA is removed, e.g., by wet etching using, for example, an HF solution. The extension process of the trench 102 illustrated in FIGS. 4C and 4D may be repeated one or more times. The sacrificial oxide 122 may be held in portions of the SiC semiconductor body 1043 outside the transistor cell region TCA, e.g. in inactive chip regions by a resist mask protecting the sacrificial oxide 122 from the etching process.Referring to FIG. 4E, a trench gate structure 124 is formed in the trench 102. Forming the trench gate structure 124 includes forming a trench gate dielectric 1241 in the trench 102, e.g., by thermal oxidation. Forming the trench gate structure 124 further includes forming a trench gate electrode 1242 on the trench gate dielectric 1241. Forming the trench gate structure 124 may further include post-oxidation annealing in a nitrogen-containing atmosphere, for example.Referring to FIG. 4F, an interlayer dielectric 126 is formed over the SiC semiconductor body 1043. A first load electrode 128, e.g., source or emitter electrode, is formed over the interlayer dielectric 126. The interlayer dielectric 126 electrically isolates the trench gate electrode 1242 from the first load electrode 128. Contact openings in the interlayer dielectric 126 enable electrical contact between the first load electrode 128 and the SiC semiconductor body 1043, e.g. the source and body regions 1101, 1121. A second load electrode 130, e.g., drain or collector electrode, is formed over a second surface 1042 of the SiC semiconductor body 1043. In some examples, not illustrated in FIG. 4F, the interlayer dielectric 126 may be formed in an upper or upper portion of the trench 102. For example, the interlayer dielectric may be formed entirely in the trench 102.The schematic cross-sectional view of FIG. 4G illustrates an example of connecting the p-doped shielding region 106 formed in the method illustrated in FIGS. 4A to 4F. For example, a p-doped pillar-shaped region 116 similar to the pillar-shaped region illustrated in FIG. 3A is formed in the process stage of forming the source layer 110, the body layer 112, and the current spreading layer 114. The pillar-shaped region 116 is formed by a masked ion implantation process and extends deeper into the SiC semiconductor body 1043 than a bottom of the trench 102.The schematic cross-sectional view of FIG. 5A illustrates another example process feature based on FIG. 3A, but differs from the example illustrated in FIG. 3A by a vertical extension of the p-doped pillar region 116. The p-doped pillar region 116 is formed in the transistor cell region TCA of the SiC semiconductor body 1043 by a masked ion implantation process of p-type dopants through the first surface 1041 (ion implantation mask, not illustrated in FIG. 5A ). A bottom side of the p-doped pillar-shaped region 116 in the example of FIG. 5A is positioned between a bottom side of the n +- doped source layer 110 and a bottom side of the p-doped body region 112. Process features similar to FIGS. 3B and 3C may follow.Referring to FIG. 5B (based on FIG. 3D ), p-type dopants are introduced into the SiC semiconductor body 1043 through a sidewall and / or bottom of the trench 102 by ion implantation, e.g., tilted ion implantation, as illustrated in FIG. 5D. A p-doped connection region 118 is thereby formed. For the ion implantation process of the p-type dopants for the connection region 118, the mask pattern 120 may be used as an ion implantation mask. The connection region 118 electrically connects the shielding region 106 and the pillar-shaped region 116. After forming the connection region 118, the mask pattern 120 is removed, e.g. by wet etching using, for example, an HF solution. A high temperature annealing (HTA) may follow. Further process features may follow, e.g., as illustrated in FIGS. 3E to 3H.The process features illustrated in FIGS. 3A, 4A, and 5A are based on an ion implantation process of the n-doped current spread layer 114 that is blanketed or un-masked with respect to the transistor cell region TCA. The following example process features may likewise be used to form the current spread layer 114. Referring to FIG. 6A, the ion implantation process of n-type dopants for forming the n-doped current spread layer 114 may also be masked. For example, a mask pattern 1201 may be used which is inverse with respect to the mask pattern 120 illustrated in FIGS. 3B, 4B, 5B. Referring to FIG. 6B, the n-type dopants for forming the n-doped current spread layer 114 may also be introduced through a sidewall of the trench 102 by an inclined ion implantation process. In addition to process features for forming the current spread layer 114, as illustrated in FIGS. 3A, 4A, 5A, 6A, 6B, a sub-region 1141 of the current spread layer 114 under the shielding region 106 may be formed by an ion implantation process through a bottom of the trench 102.The schematic cross-sectional views of FIGS. 7A and 7B illustrate another configuration example for forming the connection region 118. The schematic cross-sectional view of FIG. 7A is based on FIG. 5A and illustrates the mask pattern 120 for forming the trench. Referring to the schematic cross-sectional view of FIG. 7B, a connection region 118 is formed by introducing dopants of the first conductivity type into the wide band gap semiconductor body 104 through the opening in the third mask pattern 120 by tilted ion implantation. It may follow the formation of the trench 102 by etching. The configuration example illustrated in FIG. 7B is different from the example illustrated in FIG. 5B in that the connection region 118 is formed before the etching of the trench 102, for example.The aspects and features mentioned and described together with one or more of the examples and figures described above may also be combined with one or more of the other examples in order to replace a similar feature of the other example or in order to additionally introduce the feature into the other example.Although specific embodiments have been illustrated and described herein, it will be understood by those of ordinary skill in the art that a variety of alternative and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims

A method of forming a wide bandgap semiconductor device (100), the method comprising: forming a trench (102) extending from a first surface (1041) of the wide bandgap semiconductor body (104) into a wide bandgap semiconductor body (104); forming a shielding region (106) comprising introducing dopants of a first conductivity type into the wide bandgap semiconductor body (104) through a bottom and / or a sidewall of the trench (102) by ion implantation; and thereafter expanding the trench (102) comprises an expansion process of forming a sacrificial oxide (122) lining sidewalls and a bottom of the trench (102) by thermal oxidation and removing the sacrificial oxide (122).The method of the preceding claim, wherein the expansion process is repeated a plurality of times.The method according to any of the preceding claims, wherein a width of the trench (102) is extended at a first horizontal reference level (href1) by 10% to 80%, wherein the first horizontal reference level (href1) prior to the extension process has the same vertical distance to the first surface (1041) as to a bottom side (1021) of the trench (102).The method of any preceding claim, further comprising forming a trench gate dielectric (1241) in the trench (102) after the expansion process.The method of any preceding claim, further comprising, prior to forming the trench (102): forming a first mask pattern over the first surface (1041) of the wide bandgap semiconductor body (104), the first mask pattern having an opening exposing a transistor cell region (TCA) of the wide bandgap semiconductor body (104); forming a source layer (110) comprising introducing dopants of a second conductivity type into the transistor cell region (TCA) of the wide bandgap semiconductor body (104) through the first surface (1041) by ion implantation; forming a body layer (112) comprising introducing dopants of the first conductivity type into the transistor cell region (TCA) of the wide bandgap semiconductor body (104) through the first surface (1041) by ion implantation; forming a current spreading layer (114) comprising dopants of the second conductivity type.The method of the preceding claim, wherein a bottom side of the shielding region (106) is positioned at a smaller vertical distance to the first surface (1041) than a bottom side of the current spreading layer (114).The method of the preceding claim, further comprising, prior to forming the trench (102): forming a second mask pattern over the first surface (1041) of the wide bandgap semiconductor body (104), the second mask pattern having an opening exposing a portion of the transistor cell region (TCA) of the wide bandgap semiconductor body (104); and forming a columnar region (116) comprising introducing dopants of the first conductivity type through the opening at the first surface (1041) into the transistor cell region (TCA) of the wide bandgap semiconductor body (104) by ion implantation.The method of the preceding claim, wherein a bottom side of the columnar region (116) is positioned between a bottom side of the body layer (112) and a bottom side of the current spreading layer (114), or is positioned between a bottom side of the source layer (110) and a bottom side of the body layer (112).The method of any of the two preceding claims, further comprising, after forming the trench (102): forming a connection region (118) comprising introducing dopants of the first conductivity type into the wide band gap semiconductor body (104) through a sidewall of the trench (102) by ion implantation.The method of the preceding claim, wherein the dopants of the first conductivity type of the connection region (118) are further introduced into the wide band gap semiconductor body (104) through a bottom side of the trench (102) by ion implantation.The method of any preceding claim, further comprising: forming a third mask pattern (120) over the first surface (1041) of the wide bandgap semiconductor body (104), wherein the third mask pattern (120) comprises an opening exposing a trench gate region of the transistor cell region (TCA) of the wide bandgap semiconductor body (104); and etching the trench (102) into the wide bandgap semiconductor body (104) via the opening in the third mask pattern (120); and wherein the third mask pattern (120) serves as an ion implantation mask for forming the shielding region (106).The method of the preceding claim, further comprising, prior to the etching of the trench (102): forming a connection region (118) comprising introducing dopants of the first conductivity type into the wide band gap semiconductor body (104) through the opening in the third mask pattern (120) by ion implantation.The method of any preceding claim, wherein removing the sacrificial oxide (122) comprises wet etching.The method of any of the preceding claims, further comprising, after forming the trench (102) and before forming the shielding region (106): forming an auxiliary dielectric lining sidewalls and a bottom of the trench (102).The method of the preceding claim, further comprising: removing the auxiliary dielectric after forming the shielding region (106) and before expanding the trench (102).

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