Semiconductor devices with source / drain epitaxy area with a lower dielectic and manufacturing process

Abstract

Embodiments of the present disclosure provide a gate-all-around FET device having a structured or recessed lower dielectric layer. The lower dielectric layer prevents volume loss in the subsequently formed source / drain epitaxy region and induces a compressive stress in the channel region to prevent strain losses and a deterioration of the channel resistance.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] This application claims priority over U.S. Preliminary Patent Application No. 63 / 536 604, filed on September 5, 2023, and U.S. Preliminary Patent Application No. 63 / 610 117, filed on December 14, 2023, which are incorporated in their entirety by reference. BACKGROUND

[0002] Due to the continuous improvement in the integration density of various electronic components, the semiconductor industry is experiencing sustained, rapid growth. This improvement in integration density is largely attributable to repeated reductions in the minimum feature size, which allows more components to be integrated into a given chip area. However, reducing the minimum feature size can lead to side effects such as leakage current, parasitic elements, and reduced resistance. Therefore, there is a need to address these problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. In fact, the dimensions of the various elements may have been enlarged or reduced as appropriate for clarity of description. The Fig. Figures 1A to 1K schematically show a semiconductor device according to embodiments of the present disclosure. Fig. Figure 2 is a flowchart of a process for producing a semiconductor substrate according to embodiments of the present disclosure. The Fig. Figures 3A to 3R schematically show different stages of the manufacture of a semiconductor device according to embodiments of the present disclosure. The Fig. Figures 4A to 4L schematically show structural details of semiconductor devices according to embodiments of the present disclosure. The Fig. Figures 5A to 5L schematically show structural details of semiconductor devices according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For instance, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various described embodiments and / or configurations.

[0005] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "higher," "top," "upper," and similar, can be used here for the sake of simplicity to describe the relationship of an element or section with one or more other elements or sections, as shown in the figures. These spatially relative terms are intended to cover various orientations of the device used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here can be interpreted accordingly.

[0006] The foregoing broadly outlines some aspects of embodiments described in this disclosure. While some of the embodiments described herein are described in the context of nanosheet channel FETs, implementations of some aspects of this disclosure may be used in other processes and / or in other devices, such as planar FETs, fin FETs, horizontal gate all-around FETs (HGAA-FETs), vertical gate all-around FETs (VGAA-FETs), and other suitable devices. Those skilled in the art will readily understand that further modifications that may be made are considered within the scope of this disclosure. Furthermore, although process embodiments may be described in a particular sequence, various other process embodiments may be carried out in any logical order and may include fewer or more steps than described herein.In the present disclosure, a source / drain region denotes a source and / or a drain. Source and drain are used interchangeably.

[0007] The fins can be structured by any suitable method. For example, the fins can be structured using one or more photolithography processes, such as dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-alignment processes, allowing the creation of structures with, for example, center-to-center distances smaller than those obtainable with a single, direct photolithography process.

[0008] Embodiments of the present disclosure relate to a semiconductor device comprising a nanosheet channel region with reduced channel resistance (R). ch). In particular, embodiments of the present disclosure provide a GAA semiconductor device with reduced channel resistance for the source / drain epitaxy region in a p-FET. Specifically, embodiments of the present disclosure provide a GAA device formed from a semiconductor stack having a lower dielectric film on a lower surface of a source / drain region to prevent leakage currents through parasitic elements. In some embodiments, the lower dielectric film can be structured or otherwise formed to allow the growth of the source / drain region beneath a bottommost layer of the semiconductor stack. Embodiments of the present disclosure improve AC performance and avoid significant DC power losses due to R ch-Deterioration. For example, by structuring or shaping the lower dielectric layer, the subsequently formed source / drain epitaxy region does not experience any volume loss and can induce compressive stresses in the channel region to counteract strain losses and R ch -to prevent deterioration.

[0009] The Fig. Figures 1A to 1E schematically show a semiconductor device 10 according to embodiments of the present disclosure. Fig. Figures 1A to 1C are cross-sectional views of the semiconductor device 10 according to the present disclosure. Fig. Figure 1A is a cross-sectional view of the semiconductor device 10 along line 1A-1A in Fig. 1B. Fig. Figure 1B is a cross-sectional view of the semiconductor device 10 along line 1B-1B in Fig. 1A. Fig. Figure 1C is a partial cross-sectional view of the semiconductor device 10 along the line 1C-1C in Fig. 1A.

[0010] The semiconductor device 10 is a GAA device comprising semiconductor channels 16 formed between source / drain epitaxy regions 40. Gate structures 50 are formed over and surrounding the semiconductor channels 16. The semiconductor device 10 is formed by structuring a semiconductor stack 18 on a substrate 12 into semiconductor fins 20, forming sacrificial gate structures over the semiconductor fins 20, recessing the semiconductor fins 20 outside the sacrificial gate structures to form the source / drain epitaxy regions 40, and replacing the sacrificial gate structures with the gate structures 50.

[0011] In some embodiments, the semiconductor device 10 has a lower dielectric layer 38 arranged between the source / drain epitaxy regions 40 and a lower epitaxy layer 36. The lower dielectric layer 38 provides insulation between the source / drain epitaxy region 40 and a mesa region 12M of the semiconductor substrate 12. The lower epitaxy layer 36 can be formed by an epitaxial semiconductor layer located in the depression in the semiconductor substrate 12 between the mesa region 12M. The lower epitaxy layer 36 is formed in the space of the semiconductor fins 20. As shown in Fig. As shown in Figure 1B, the lower epitaxial layer 36 contacts a shallow trench insulation layer 22 and / or sidewall spacers 30. In some embodiments, the lower epitaxial layer 36 consists of an epitaxial semiconductor material formed by the semiconductor substrate 12. The lower epitaxial layer 36 can be a transition layer between the crystal structures of the semiconductor substrate 12 and the source / drain epitaxial region 40. In some embodiments, the lower epitaxial layer 36 can be used as an alignment element to form back-side source / drain contacts.

[0012] The lower dielectric layer 38 is formed on the lower epitaxial layer 36 and partially covers it. In some embodiments, an opening 39 is formed through the lower dielectric layer 38, exposing part of the lower epitaxial layer 36. Consequently, the lower epitaxial layer 36, together with the semiconductor channel layers 16, acts as a seed layer in the growth of the source / drain epitaxial regions 40. As shown in Fig. As shown in Figure 1A, the semiconductor stack 18 is formed on an upper surface 12f of the semiconductor substrate 12. The upper surface 12f can also be referred to as the underside of the sheet. Since the source / drain epitaxy regions 40 are formed by a section of the lower epitaxy layer 36, the source / drain epitaxy regions 40 extend beneath the upper surface 12f, or the underside of the sheet. In some embodiments, the lower epitaxy layer 36 can be omitted, and the lower dielectric layer 38 is formed directly in the depression on the semiconductor substrate 12.

[0013] The source / drain epitaxy regions 40 are formed in physical contact with the semiconductor channel layers 16. Using a portion of the lower semiconductor layer 36 as a seed layer to grow the source / drain epitaxy region 40 increases its volume. This increased volume amplifies the pressure force F on the semiconductor channel layers 16. The increased pressure force F induces a compressive stress in the semiconductor channel layers 16, thereby increasing the mobility of the channel region. The semiconductor channels 16 are separated by internal spacers 32 and surrounded by the substitute gate 50. The substitute gate 50 can consist of a gate stack comprising an interface layer, a gate dielectric layer, and a gate electrode layer. The gate electrode layer can also include one or more exit work layers and one or more metal filler layers.The side wall spacers 30 are arranged between the source / drain epitaxy areas 40 and the gate structure 50.

[0014] The semiconductor device 10 can further comprise source / drain contacts 52 arranged on the source / drain epitaxy regions 40. A silicide layer 54 can be formed between the source / drain contacts 52 and the source / drain epitaxy regions 40 to facilitate electrical contact between them. A contact etch stop layer (CESL) 42 is deposited over the source / drain epitaxy regions 40 to protect them during formation processes. An interlayer dielectric (ILD) 44 is deposited over the CESL 42 to provide electrical insulation between the S / D contacts 52 and the source / drain epitaxy regions 40.

[0015] If a gate bias higher than a threshold voltage is applied to the gate structure 50 during operation, a conductive channel forms in the semiconductor channel layers 16. If a suitable bias is applied to the source / drain epitaxy regions 40 via the source / drain contacts 52, current flows between the source / drain epitaxy regions 40 through the channels that have formed in the semiconductor channel layers 16. During the aforementioned operating condition, a portion of the gate structure 50 closest to the mesa region 12M can form a parasitic FET. If the source / drain epitaxy regions 40 were in physical contact with the mesa region 12M, an unwanted leakage current could flow between the source / drain epitaxy regions 40 across the mesa region 12M.The lower dielectric layer 38 in the semiconductor device 10 provides sufficient electrical insulation of the source / drain epitaxy regions 40 and suppression of leakage current.

[0016] In some embodiments, the semiconductor device 10 is formed on a bulk semiconductor substrate 12, e.g., as opposed to an SOI substrate. In some embodiments, the semiconductor substrate 12 contains crystalline silicon (Si) or another elemental semiconductor such as germanium (Ge). Alternatively, the semiconductor substrate 12 (i) may be a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (ii) an alloy semiconductor such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminium indium arsenide (AlInAs), aluminium gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP) and / or gallium indium arsenide phosphide (GaInAsP); or (iv) combinations thereof.

[0017] The semiconductor stack 18 can comprise semiconductor channel layers 16 arranged alternately with sacrificial semiconductor layers (not shown). In some embodiments, the number of channel layers 16 is between 1 and 6. The semiconductor channel layers 16 can be formed by a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the semiconductor channel layers 16 can contain the same material as the substrate 12. In some embodiments, the semiconductor channel layers 16 can contain materials different from the substrate 12. In some embodiments, the semiconductor channel layers 16 and the sacrificial semiconductor layers are made of materials with different lattice constants.In some embodiments, the sacrificial semiconductor layers include epitaxially grown silicon-germanium layers (SiGe layers), and the semiconductor channel layers 16 include epitaxially grown silicon layers (Si layers). Alternatively, in some embodiments, the semiconductor channel layers 16 and / or the sacrificial layers may contain other materials such as Ge, a compound semiconductor such as SiC, GeAs, GaP, InP, InAs and / or InSb, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP, or combinations thereof.

[0018] In some embodiments, each of the semiconductor channel layers 16 has a channel height H 16 along the z-direction in a range between approximately 5 nm and approximately 15 nm. In some embodiments, the semiconductor channel layers 16 in the semiconductor stack 18 have a uniform channel height H. 16In some embodiments, the semiconductor channel layers 16 in the semiconductor stack 18 exhibit variations in the channel height H. 16 In some embodiments, the semiconductor channel layers 16 have a channel width W 16 along the y-direction in a range between approximately 6 nm and approximately 80 nm. In some embodiments, the fins 20 or the source / drain epitaxy regions 40 have a spacing S 16 along the y-direction in a range between approximately 6 nm and approximately 115 nm.

[0019] In some embodiments, the source / drain epitaxy regions 40 for a p-type device may contain boron-doped (B-doped) silicon germanium (SiGe), B-doped germanium (Ge), B-doped germanium tin (GeSn), or combinations thereof. In some embodiments, the source / drain epitaxy regions 40 for an n-type device may contain arsenic-doped (As-doped) or phosphorus-doped (P-doped) silicon (Si), carbon-doped silicon (Si:C), or combinations thereof. In some embodiments, the source / drain epitaxy regions 40 may include two or more epitaxially grown layers, which will be described later, but for simplicity are referred to in the following. Fig. Figures 1A to 1C are not shown. In some embodiments, the source / drain epitaxy regions 40 are grown from exposed sidewall surfaces of the semiconductor channel layers 16 and the exposed section of the lower epitaxy layer 36.

[0020] In some embodiments, the source / drain epitaxy regions 40 have a width W 40 along the x-direction in a range between approximately 9 nm and approximately 32 nm. In some embodiments, the source / drain epitaxy regions 40 have a height H 40 along the z-direction in a range between approximately 20 nm and approximately 105 nm. The height H 40 is enlarged because lower sections of the source / drain epitaxy regions 40 grow from the lower epitaxy layer 36, which lies below the upper surface 12f of the mesa section 12M or the underside of the semiconductor stack 18. In some embodiments, there is a depression spacing D 40 the source / drain epitaxy region 40, which is defined by the distance between the upper surface 12f of the mesa section 12M and a lower surface 40b of the source / drain epitaxy region 40, in a range between 0 nm and about 80 nm.

[0021] In some embodiments, the lower epitaxial layer 36 is an undoped semiconductor layer. For example, the lower epitaxial layer 36 can be Si x Ge 1-x contained, where x lies in a range between 0.1 and 1. In some embodiments, the lower epitaxial layer 36 has a height H 36 along the z-direction in a range between approximately 0 nm and approximately 50 nm. In some embodiments, a depth of D is present. 36 the lower epitaxial layer 36, which is defined by the distance between the upper surface 12f of the mesa section 12M and a lower surface 36b of the lower epitaxial layer 36 along the z-direction, in a range between about 3 nm and about 50 nm.

[0022] In some embodiments, the lower dielectric layer 38 can contain any suitable dielectric, for example, oxides such as silicon oxide, germanium oxide, nitrides such as silicon nitride, a carbide, or other suitable dielectrics. In some embodiments, the lower dielectric layer 38 can contain one or more dielectrics with a resistivity greater than about 1 × 10⁻⁶ 10 Ohm·m contained. In some embodiments, the lower dielectric layer 38 has a thickness H 38 in the z-direction in a range between 0 nm and about 30 nm, for example the lower dielectric layer 38 can have a thickness H 38 exhibit wavelengths between approximately 10 nm and approximately 20 nm.

[0023] The lower dielectric layer 38 can be formed at a height close to the upper surface 12f of the mesa section 12M. Depending on the design, an upper surface 38f of the lower dielectric layer 38 can be formed below or above the upper surface 12f of the mesa section 12M. In some embodiments, a depression spacing D is present. 38 of the lower dielectric layer 38, which is defined by the distance between the upper surface 12f of the mesa section 12M and a lowest point of the lower dielectric layer 38, in a range between -15 nm and about 15 nm. A positive depression spacing D 38 indicates that the entire lower dielectric layer 38 is located above the upper surface 12f of the mesa section 12M. A negative depression spacing D 38 indicates that the lower surface 38b of the lower dielectric layer 38 lies below the upper surface 12f of the mesa section 12M, as shown in the Fig. Shown 1A to 1B.

[0024] In the embodiment of Fig. 1A and Fig. 1B the lower dielectric layer 38 has a negative depression spacing D 38 This results in the mesa section 12M not being exposed relative to the source / drain epitaxy regions 40. The source / drain epitaxy regions 40 in the semiconductor device 10 are partially electrically separated from the lower epitaxy layer 36 and the mesa section 12M.

[0025] The opening 39 is formed by the lower dielectric layer 38 such that a section of the lower epitaxial layer 36 is exposed, allowing the source / drain epitaxial region 40 to grow from a region below the upper surface 12f of the mesa section 12M. In some embodiments, the opening 39 is formed by structuring. The position and dimensions of the opening 39 can be determined according to the circuit design.

[0026] For example, the dimensions and location of the opening 39 can be designed to achieve the desired shape and volume for the initial growth of the source / drain epitaxy areas 40.

[0027] Fig. Figure 1C schematically shows the shape and position of the opening 39 according to one embodiment of the present disclosure. Fig. In 1C, the opening 39 is formed near the central region of the lower dielectric layer 38. In some embodiments, the opening 39 can have a width W. 39 in the x-direction in a range between 0 nm and approximately 30 nm and a length L 39 in the y-direction in a range between 0 nm and approximately 30 nm. In some embodiments, the opening 39 can be essentially circular. In other embodiments, the opening 39 can have a square shape and be symmetrical along the x- and y-directions.

[0028] Alternatively, the opening 39 can have a different shape, for example, be rectangular or asymmetrical. Fig. 1D and Fig. Figure 1E schematically shows two alternative embodiments. Fig. 1D is a rectangular opening 39' formed by a lower dielectric layer 38'. In Fig. 1D still forms the lower dielectric layer 38' as a continuous film. In Fig. 1E is formed by a slot 39" through a lower dielectric layer 38". The slot 39" divides the lower dielectric layer 38" into two separate sections. In Fig. 1E does not form a continuous film in the lower dielectric layer 38".

[0029] As described above, the space between and above the semiconductor channel layers 16 is occupied by the gate structure 50. The gate structure 50 can extend by a height H 50extend over the uppermost semiconductor channel layer 16tm. The gate structure 50 can include an interface layer, a gate dielectric layer and a gate electrode layer.

[0030] In some embodiments, the gate structure 50 occupies a central section of the semiconductor channel layers 16. Edge sections of the semiconductor channel layers 16 are covered by the inner spacers 32. The gate sidewall spacers 30 are arranged on both sides of the gate structures 50, except between the semiconductor channel layers 16. In some embodiments, the height H 50 The gate structure 50 has a width along the y-direction between approximately 5 nm and approximately 50 nm. In some embodiments, the sidewall spacers 30 and the inner spacers 32 can contain a nitride such as silicon nitride (Si3N4 or "SiN"), silicon carbon nitride (SiCN), and silicon carbon oxynitride (SiCON). In some embodiments, a width W is present. 30The side wall spacer 30 has a width W along the x-direction between approximately 3 nm and approximately 8 nm. In some embodiments, this width W is specified. 32 The inner spacers 32 extend along the x-direction between approximately 5 nm and approximately 10 nm. The inner spacers 32 are inserted between the gate structure 50 and the source / drain epitaxy regions 40 to electrically isolate the gate structure 50 from the source / drain epitaxy regions 40.

[0031] The silicide layers 54, arranged between the source / drain contacts 52 and the source / drain epitaxy region 40, can contain titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), platinum silicide (PtSi), or a suitable silicide material. For example, and without limitation, each silicide layer 54 can have a thickness between approximately 4 nm and approximately 8 nm. In some embodiments, the silicide layer reduces the contact resistance between the source / drain contact 53 and the source / drain epitaxy region 40.

[0032] In some embodiments, the ILD layer 44 contains one or more layers of dielectric material. In some embodiments, the ILD layer 44 consists of a silicon oxide-based dielectric containing nitrogen, hydrogen, carbon, or combinations thereof. According to some embodiments, the ILD layer 44 provides electrical insulation and structural support for the gate structure 50, the source / drain contacts 52, and the source / drain epitaxy regions 40.

[0033] The Fig. Figures 1F to 1G schematically show a semiconductor device 10' according to embodiments of the present disclosure. Fig. Figures 1F to 1G are cross-sectional views of the semiconductor device 10' according to the present disclosure. Fig. 1F is a cross-sectional view of the semiconductor device 10' along the line 1F-1F in Fig. 1G. Fig. 1G is a cross-sectional view of the semiconductor device 10' along the line 1G-1G in Fig. 1F.

[0034] The semiconductor device 10' is similar to the semiconductor device 10, except that the semiconductor device 10' has a lower dielectric layer 38a formed below the upper surface 12f of the mesa section 12M. In some embodiments, the lower dielectric layer 38a is a continuous film deposited on a lower epitaxial layer 36a. In some embodiments, the lower dielectric layer 38a covers an upper surface of the lower epitaxial layer 36a. A mesa sidewall 12s of the mesa section 12M is not covered by the lower dielectric layer 36a. This means that the lower dielectric layer 38a partially covers the semiconductor surfaces in the recess 34 below the upper surface 12f, which include the upper surface 36t of the lower epitaxial layer 36a and the sidewalls 12s of the mesa section 12M.Consequently, the mesa side wall 12s also functions as a nucleation layer during the formation of a source / drain epitaxy region 40a. In some embodiments, there is a depression spacing D. 40a The source / drain epitaxy region 40a, defined by the distance between the upper surface 12f of the mesa section 12M and a lower surface 40b of the source / drain epitaxy region 40a, is in a range between 0 nm and approximately 50 nm. The lower dielectric layer 38a has a negative depression spacing D 38 As a result, the mesa section 12M is exposed relative to the source / drain epitaxy regions 40. The source / drain epitaxy regions 40a in the semiconductor device 10' are partially electrically separated from the lower epitaxy layer 36a and the mesa section 12M.

[0035] The Fig. Figures 1H to 1K schematically show a semiconductor device 10" according to embodiments of the present disclosure. Fig. 1H is a cross-sectional view of the semiconductor device 10". Fig. 1I is a partial cross-sectional view of the semiconductor device 10" along line 1I-1I in Fig. 1H.

[0036] The semiconductor device 10" is similar to the semiconductor device 10, except that the semiconductor device 10" has an air gap 60 arranged between the lower dielectric layer 38 and the source / drain epitaxy region 40. In some embodiments, the air gap 60 may be open to the inner spacers 32. The air gaps 60 may be the result of a fusion of an epitaxial section grown from the semiconductor channel layer 16 and an epitaxial section grown from the lower epitaxy layer 36. In some embodiments, the air gaps 60 may be designed to increase the insulation around the source / drain epitaxy region 40. As shown in Fig. As shown in Figure 1, the air gaps 60 can extend along the y-direction.

[0037] The Fig. 1 year and Fig. Figure 1K schematically shows two alternative embodiments with rectangular openings and slotted openings. Fig. 1J the air gaps 60 near the rectangular opening 39' are formed by the lower dielectric layer 38'. In Fig. 1K the air gaps 60 are formed near the slot 39" which runs through the lower dielectric layer 38".

[0038] Fig. Figure 2 is a flowchart of a method 100 for manufacturing a semiconductor device according to embodiments of the present disclosure. Fig. Figures 3A to 3R schematically show different stages of the fabrication of a semiconductor device 200 according to embodiments of the present disclosure. The semiconductor device 200 is similar to the semiconductor devices 10 and 10'. In other words, the semiconductor devices 10 and 10' can be fabricated using the method 100.

[0039] The process 100 begins with process 102, in which several semiconductor fins 220 are formed over a substrate 210, as shown in Fig. Figure 3A shows the substrate 210, which is provided to form the semiconductor device 200. The substrate 210 can contain, but is not limited to, a single-crystal semiconductor material, such as Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. The substrate 210 can have different doping configurations depending on the circuit design. For example, different doping profiles, such as n-wells and p-wells, can be formed in the substrate 210 in regions designed for different device types, such as n-field-effect transistors (NFETs) and p-field-effect transistors (PFETs). In some embodiments, the substrate 210 is a silicon-on-insulator (SOI) substrate that incorporates an insulator structure (not shown) for improvement.

[0040] The substrate 210 has a front face 210f. Subsequently, a semiconductor stack 218 is formed over the front face 210f of the substrate 210. The semiconductor stack has alternating semiconductor layers of different materials to enable the formation of nanosheet channels in a multi-gate device such as a nanosheet channel FET. In some embodiments, the semiconductor stack has first semiconductor layers 214, between which second semiconductor layers 216 are inserted. The first semiconductor layers 214 and the second semiconductor layers 216 have different oxidation rates and / or etch selectivities. In some embodiments, the front face 210f of the substrate 210 can have a (100) orientation or a (110) orientation.The orientation of the front face 210f determines the orientation of the layers in the semiconductor stack 218 and of epitaxial elements such as source / drain epitaxial regions formed by the semiconductor channel layers in the semiconductor stack 218.

[0041] In later manufacturing phases, sections of the second semiconductor layers 216 form nanosheet channels in a multi-gate device. Three first semiconductor layers 214 and three second semiconductor layers 216 are arranged alternately, as shown in Fig. Figure 3A shows an example. Depending on the desired number of channels in the semiconductor device to be formed, more or fewer semiconductor layers 214 and 216 can be provided in the semiconductor stack. In some embodiments, the number of semiconductor layers 216 is between 1 and 6.

[0042] The semiconductor layers 214 and 216 can be formed by a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the semiconductor layers 216 consist of the same material as the substrate 210. In some embodiments, the semiconductor layers 214 and 216 contain different materials than the substrate 210. In some embodiments, the semiconductor layers 214 and 216 consist of materials with different lattice constants. In some embodiments, the first semiconductor layers 214 comprise epitaxially grown silicon-germanium layers (SiGe layers), and the second semiconductor layers 216 comprise epitaxially grown silicon layers (Si layers).Alternatively, in some embodiments, each of the semiconductor layers 214 and 216 may contain other materials such as Ge, a compound semiconductor such as SiC, GeAs, GaP, InP, InAs and / or InSb, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP or combinations thereof.

[0043] The first semiconductor layers 214 in the channel regions can ultimately be removed and serve to define a vertical distance between adjacent channels for a subsequently formed multi-gate device. In some embodiments, the thickness of the first semiconductor layer 214 is greater than or equal to the thickness of the second semiconductor layer 216. In some embodiments, each semiconductor layer 214 has a thickness in the range of approximately 3 nm to approximately 15 nm. In some embodiments, each second semiconductor layer 216 has a thickness in the range of approximately 3 nm to approximately 15 nm. In some embodiments, the second semiconductor layers 216 in the semiconductor stack have a uniform thickness.

[0044] The semiconductor fins 220 are formed from the semiconductor stack and a portion of the substrate 210. The semiconductor fins 220 can be formed by structuring a hard mask (not shown) formed on the semiconductor stack and one or more etching processes. Each semiconductor fin 220 has a channel section 218 formed by the semiconductor layers 214 and 216, and a trough section 212 formed by the substrate 210. The semiconductor fins 220 are formed along the x-direction.

[0045] An insulating layer (not shown, but similar to insulating layer 22 in Fig. 1B) is formed in the grooves between the semiconductor fins 220. The insulating layer is formed over the substrate 210 such that it covers the well section 212 of the semiconductor fins 220. The insulating layer can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or another suitable deposition process. In some embodiments, the insulating layer 222 can contain silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, or combinations thereof. In some embodiments, the insulating layer is formed by a suitable deposition process, such as atomic layer deposition (ALD), such that it covers the semiconductor fins 220, and then etched to a depth using a suitable anisotropic etching process to expose the channel sections 218 of the semiconductor fins 220.

[0046] In process 104, sacrificial gate structures 228 and spacer layers 230 are formed over the semiconductor fins 220, as shown in Fig. Figure 3A shows a sacrificial gated dielectric layer 224 deposited over the exposed surfaces of the semiconductor device 200. The sacrificial gated dielectric layer 224 can be conformally formed over the semiconductor fins 220 and the insulating layer 222. In some embodiments, the sacrificial gated dielectric layer 224 can be deposited by a CVD process, a subatmospheric CVD process (SACVD process), an FCVD process, an ALD process, a PVD process, or another suitable process. The sacrificial gated dielectric layer 224 can comprise one or more layers of a dielectric, such as SiO2, SiN, a high-k dielectric, and / or another suitable dielectric.

[0047] A sacrificial gate electrode layer 226 is deposited on the sacrificial gate dielectric layer 224. The sacrificial gate electrode layer 226 can be deposited completely on the sacrificial gate dielectric layer 224. The sacrificial gate electrode layer 226 contains silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the sacrificial gate electrode layer 226 is subjected to a planarization process. The sacrificial gate electrode layer 226 can be deposited using CVD such as LPCVD and PECVD, PVD, ALD, or other suitable processes. A structuring process is performed over the sacrificial gate dielectric layer 224 and the sacrificial gate electrode layer 226 to form the sacrificial gate structures 228, which cover portions of the semiconductor fins 220 configured as channel regions.

[0048] Gate sidewall spacers 230 are subsequently formed on the sidewalls of each sacrificial gate structure 228. After the sacrificial gate structures 228 are formed, the gate sidewall spacers 230 can be formed by depositing an insulating material, followed by anisotropic etching to remove the insulating material from horizontal surfaces. The gate sidewall spacers 230 can have a thickness in the range of about 3 nm to about 8 nm. In some embodiments, the insulating material of the gate sidewall spacers 230 is a silicon nitride-based material, for example, SiN, SiON, SiOCN, or SiCN and combinations thereof. Fig. In 3A, the gate sidewall spacers 230 have two layers. In further embodiments, the gate sidewall spacers 230 can be formed from fewer or more layers of dielectrics.

[0049] In process 106, the semiconductor fins 220 are deep-etched on opposite sides of the sacrificial gate structure 228, forming source / drain depressions 234 between the adjacent sacrificial gate structures 228, as shown in Fig. Figure 3B shows that the first semiconductor layers 214 and the second semiconductor layers 216 in the semiconductor fins 220 are deeply etched on both sides of the sacrificial gate structures 228 by means of etching processes. In some embodiments, all layers in the semiconductor stack of the semiconductor fins 220 and a portion of the well sections 212 of the semiconductor fins 220 are etched. In some embodiments, suitable dry etching and / or wet etching can be used to remove the first semiconductor layers 214, the second semiconductor layers 216, and the substrate 210.

[0050] In some embodiments, the source / drain depressions 234 form deep trenches below the upper surface 210f of the substrate 210. In some embodiments, the source / drain depression 234 has a depression spacing D. 234 on, which is defined by the distance between the upper surface 210f of the substrate 210 or a leaf underside and a lower surface 234b of the source / drain recesses 234. In some embodiments, the recess spacing D is 234 in a range between about 3 nm and about 50 nm.

[0051] In process 108, internal spacers 232 are formed at exposed ends of the first semiconductor layers 214 below the sacrificial gate structures 228, as shown in the Fig. 3C to 3E are shown. The first semiconductor layers 214, which are exposed opposite the source / drain depressions 234, are initially etched horizontally along the X-direction to form spacer cavities, as shown in Fig. Figure 3C shows that in some embodiments, the first semiconductor layers 214 can be selectively etched by using a wet etching agent such as, but not limited to, solutions of ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediaminepyrocatechol (EDP), or potassium hydroxide (KOH). In some embodiments, the etch dimension of the first semiconductor layer 214 along the X-direction is in a range between about 5 nm and about 10 nm.

[0052] After forming the spacer cavities at opposite ends of the first semiconductor layers 214, the inner spacers 232 can be formed in the spacer cavities by conformally depositing an insulating layer, as shown in Fig. shown in 3D. The insulating layer is then partially removed so that the inner spacers 232 are formed, as shown in Fig. Figure 3E shows that the insulating layer can be formed by ALD or another suitable method. The subsequent etching process removes most of the insulating layer except for the cavities, creating the internal spacers 232. The internal spacers 232 comprise two or more sections stacked alternately with the second semiconductor layers 216.

[0053] The internal spacers 232 can be formed from a single layer or multiple layers of a dielectric. In some embodiments, the internal spacers 232 can contain either silicon nitride (SiN) and silicon oxide (SiO2) or SiONC, or a combination thereof. The internal spacer 232 can have a thickness in the range of approximately 5 nm to approximately 10 nm along the X-direction.

[0054] In process 110, a lower epitaxial layer 236 is formed in the lower sections of the source / drain depressions 234, as shown in Fig. 3F shown. In some embodiments, the lower epitaxial layer 236 fills the lower portions of the source / drain depressions 234 to a level below the lowest semiconductor layer 216L or the lowest channel region. In some embodiments, the lower epitaxial layer 236 fills the source / drain depressions 234 to a level below the lowest inner spacers 232L. In some embodiments, a front surface 236f may lie at a level below the lowest inner spacers 232L. In some embodiments, the front surface 236f lies below the upper surface 210f of the substrate 210, and a portion of the mesa sidewall 212s is exposed after the formation of the lower epitaxial layer 236 of the source / drain depression 234.

[0055] The material and shape of the lower epitaxial layer 236 can be selected according to the achievement of one or more purposes. For example, the lower epitaxial layer 236 can provide a crystalline transition from the substrate 210 to the subsequently formed source / drain region with improved adhesion. The lower epitaxial layer 236 can define a base profile and crystal orientation of the subsequently formed source / drain region. In some embodiments, the lower epitaxial layer 236 can also function as an alignment element for back-side source / drain contacts.

[0056] In some embodiments, the lower epitaxial layer 236 can be formed from a material exhibiting etch selectivity with respect to the substrate material 210, such as the material in the well section 212 of the semiconductor fin 220. In some embodiments, the lower epitaxial layer 236 can also exhibit etch selectivity with respect to the insulating material in the insulating layer. In some embodiments, the lower epitaxial layer 236 is formed from a semiconductor material with high etch selectivity with respect to Si. For example, the lower epitaxial layer 236 can be formed from SiGe.

[0057] The lower epitaxial layer 236 can be formed by any suitable method, such as CVD, CVD epitaxy, molecular beam epitaxy (MBE), or any suitable deposition technique. In some embodiments, the lower epitaxial layer 236 is formed from undoped SiGe. In some embodiments, the lower epitaxial layer 236 is formed from undoped SiGe having an atomic concentration of Ge in the range of about 10% to about 100%. Alternatively, the lower epitaxial layer 236 can contain other materials, such as Ge, a compound semiconductor such as SiC, GeAs, GaP, InP, InAs, and / or InSb, an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof.

[0058] In process 112, a lower dielectric layer 238 is formed above the lower epitaxial layer 236, as shown in the Fig. Figures 3G to 3H are shown. The lower dielectric layer 238 is formed on the front face 236t of the lower epitaxial layer 236. The lower dielectric layer 238 can also cover exposed surfaces of the insulating layer. The lower dielectric layer 238 can include one or more layers of dielectrics. During operation, the lower dielectric layer 238 can provide electrical insulation between the trough section 212 of the substrate 210 and the source / drain regions.

[0059] The lower dielectric layer 238 can be formed by a directional deposition process with selectivity in its bottom-to-top growth relative to the sidewalls. For example, the lower dielectric layer 238 can be formed by a directional PECVD process. In some embodiments, the lower dielectric layer 238 can be formed by depositing a conformal dielectric layer over the exposed surface, as in Fig. 3G shown, and then the conformal dielectric layer is removed from vertical surfaces and outer surfaces, leaving a portion on the bottom of the source / drain depression 234, as shown in Fig. 3H shown. In some embodiments, the lower dielectric layer 238 can be formed from any suitable dielectric, such as a silicon nitride-containing material like SiN, SiON, SiOCN, SiOC, SiCN, a metal oxide like AlOx, HfOx or a combination thereof.

[0060] In some embodiments, the lower dielectric layer 238 covers the upper surface 236t of the lower epitaxial layer 236. The vertical orientation of the lower dielectric layer 238 depends on the shape and position of the lower epitaxial layer 236. The lower dielectric layer 238 can have a thickness greater than that of the lower epitaxial layer 236. In some embodiments, the thickness is in a range between approximately 0 nm and approximately 30 nm. In some embodiments, an upper surface 238t of the lower dielectric layer 238 can intersect the lowest inner spacer 232L, such that the lower dielectric layer 238 covers the trough section 212 of the substrate 210, while the lowest semiconductor layer 216 remains exposed. As shown in Fig. As shown in Figure 3I, in further embodiments the upper surface 238t of the lower dielectric layer 238 lies below the upper surface 210f of the substrate 210, so that part of the side wall 212s is exposed opposite the source / drain recesses 234. The shape and position of the lower dielectric layer 238 can vary depending on the design.

[0061] In process 114, an opening 239 is formed through the lower dielectric layer 238 such that part of the lower epitaxial layer 236 is exposed, as shown in the Fig. Figures 3I to 3J are shown. Depending on the device design, step 114 may be omitted. The opening 239 is designed such that a section of the lower epitaxial layer 236 can be used as a nucleating layer during the epitaxial growth of the source / drain region.

[0062] In some embodiments, the opening 239 can be formed by creating a structure using a photolithography technique and etching through the structure using a suitable etching process. In other embodiments, the opening 239 can be formed by directional etching.

[0063] Fig. 3J is a partially enlarged view of the 3J area in Fig. 3H. As in Fig. As shown in Figure 3, the opening 239 exposes part of the upper surface 236t of the lower epitaxial layer 236 to the source / drain depression 234. During subsequent epitaxial growth, an epitaxial layer can grow from the upper surface 236t and fill the opening 239. In the example of Fig. In step 3H, two sidewall sections of sidewall 212s opposite the source / drain depression 234 are also exposed, and epitaxial elements can also grow from sidewalls 212s. After step 114, the lower dielectric layer 238 partially covers the semiconductor surface below the upper surface 210f.

[0064] In process 116, an optional channel shortening process is performed to re-etch edge regions of the semiconductor layers 216 and the side walls 212s of the well section 212, as shown in the Fig. 3K to 3L are shown. In some embodiments, the semiconductor layers 216 exposed opposite the source / drain recesses 234 are etched horizontally along the X-direction, forming truncation cavities 216C. In some embodiments, the semiconductor layers 216 can be selectively etched by using a wet etching agent such as, but not limited to, solutions of ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediaminepyrocatechol (EDP), or potassium hydroxide (KOH). The truncation cavities 216C are formed below the sidewall spacers 230 and between the inner spacers 232. In some embodiments, the etch dimension of the semiconductor layers 216 along the x-direction is in a range between about 1 nm and about 6 nm.In some embodiments, the semiconductor layers 216 are etched back to a certain extent, which does not expose the first semiconductor layers 216 behind the inner spacers 232.

[0065] If side walls 212s of the trough section 212 are exposed towards the source / drain recess 234, in some embodiments a portion of the trough section 212 can also be etched back during the channel shortening process, thereby forming trough cavities 212C. The trough cavities 212C lie below the lowest inner spacers 232L and above the upper surface 238t of the lower dielectric layer 238.

[0066] Fig. 3L is a partially enlarged view of the 3L area in Fig. 3K. As in Fig. As shown in Figure 3L, after the channel shortening process, side walls 232s, upper surfaces 232t, and lower surfaces 232b are exposed opposite the source / drain recess 234. As shown in Fig. As shown in Figure 3L, the cavities 216C can have a width W along the x-direction. 216C exhibit the width W 216C can be defined by the distance between a side wall 216s of the semiconductor layer 216 and the side wall 232s of the inner spacers 232. In some embodiments, the width W is 216C in a range between about 1 nm and about 6 nm.

[0067] The channel shortening process enlarges the source / drain depressions 234, thus providing a larger volume for the subsequently formed source / drain area. Alternatively, the channel shortening process can be omitted.

[0068] In process 118, a first source / drain epitaxy layer 241 is formed in the source / drain depression 234, as shown in Fig. 3M shown. In some embodiments, a pre-cleaning process can be performed prior to the epitaxial growth of the first source / drain epitaxial layer 241. The first source / drain epitaxial layer 241 is formed by an epitaxial growth process using CVD, ALD, or molecular beam epitaxy (MBE). The first epitaxial layer 241 grows from exposed semiconductor surfaces, i.e., the side wall 216s of the semiconductor layer 216 and the upper surface 236t of the lower epitaxial layer 236. The first source / drain epitaxial layer 241 begins as separate sections of the exposed semiconductor surfaces. For example, the first source / drain epitaxy layer 241 includes channel sections 241C that have grown from the side wall 216s of the semiconductor layer 216, side wall sections 241S that have grown from exposed side walls, and a bottom section 241B that has grown through the opening 239 from the lower epitaxy layer 236.The channel sections 241C, side wall sections 241S and the bottom section 241B are collectively referred to as the first source / drain epitaxy layer 241.

[0069] The first source / drain epitaxial layer 241 is grown to a desired thickness to enable high-quality crystal growth during subsequent epitaxial bulk growth. After process 118, the channel sections 241C, the sidewall sections 241S, and the bottom section 241B may remain separate or be fused. For example, in Fig. The 3M adjacent channel sections 241C may be fused, or the bottom channel section 241C may be fused with the side wall section 241S. Alternatively, the bottom section 241B may be fused with the side wall sections 241S.

[0070] The channel sections 241C, the side wall sections 241S and the bottom section 241B may have different physical properties such as thickness, shape or surface orientation due to the different surface orientation, the different material and / or the different location of the corresponding nucleation layers.

[0071] In some embodiments, the channel sections 241C can have a channel thickness t c exhibiting a distance from the thickest section of the channel segment 241C to the side wall 232s of the inner spacer 232. In some embodiments, the channel thickness t is c in a range between approximately 1 nm and approximately 8 nm. When the channel shortening process is performed, in some embodiments the channel section 241C further exhibits a shortening thickness t PHon, which is defined by the distance between the side wall 232s of the inner spacer 232 and the side wall 216s of the semiconductor layer 216. In some embodiments, the reduction thickness t PH in a range between approximately 1 nm and approximately 6 nm. In some embodiments, an upper surface 241Ct of the channel section 241C can be oriented at an angle θs to a horizontal plane. The angle θs reflects a surface orientation resulting from the surface orientation of the nucleation layer and the process parameters. In some embodiments, the angle θs lies in a range between approximately 10° and approximately 80°.

[0072] In some embodiments, the lower sections 241B can have a soil thickness t B exhibiting a distance from the thickest section of the lower section 241B to the upper surface 236t of the lower epitaxial layer 236. In some embodiments, the soil thickness t Bin a range between approximately 1 nm and approximately 12 nm. In some embodiments, an upper surface 241Bt of the lower section 241B can be at an angle θ B relative to a horizontal plane. The angle θ B This reflects a surface orientation that results from the surface orientation of the nucleation layer and the process parameters. In some embodiments, the angle θ B in a range between approximately 10° and approximately 80°.

[0073] The first source / drain epitaxy layer 241 can contain one or more layers of Si, SiP, SiC, and SiCP for NFETs or Si, SiGe, and Ge for PFETs. For PFETs, the first source / drain epitaxy layer 241 can also contain p-type dopants such as boron (B). For NFETs, the first source / drain epitaxy layer 241 can also contain n-type dopants such as arsenic (As), phosphorus (P), or carbon (C), or combinations thereof.

[0074] In some embodiments, the semiconductor device 200 is a p-type device, and the first source / drain epitaxy layer 241 contains Si or SiGe with a p-type dopant such as B or Ga. In some embodiments, the first source / drain epitaxy layer 241 can consist of a SiGe layer with a Ge atomic concentration in the range of about 0% to about 40%. In some embodiments, the first source / drain epitaxy layer 241 contains p-type dopants in a concentration between about 1E20 and about 2E21.

[0075] In some embodiments, the first source / drain epitaxy layer 241 can be formed by an epitaxial growth process using CVD, ALD, or molecular beam epitaxy (MBE). In some embodiments, the epitaxial deposition process can be carried out in a temperature range between about 400 °C and about 750 °C, for example, between about 520 °C and about 620 °C. In some embodiments, the epitaxial deposition process can be carried out at a pressure in a range between about 10 Torr and about 300 Torr, for example, between about 20 Torr and about 100 Torr. In some embodiments, the epitaxial deposition process can use a precursor such as H₂SiCl₂ (DCS), SiH₄, Si₂H₆, GeH₄, GeCl₄, HCl, or Cl₂. In some embodiments, a p-doping precursor such as B2H6, BCl3 and Ga(CH3)3 can be used during deposition.

[0076] In process 120, a source / drain volume epitaxy layer 243 is formed above the first source / drain epitaxy layer 241, as shown in Fig. 3N shown. The source / drain volume epitaxy layer 243 fills the source / drain depression 234. The first source / drain epitaxy layer 241 and the source / drain volume epitaxy layer 243 form the source / drain epitaxy areas 240. Although in Fig. 3N shows only one layer, but the source / drain volume epitaxy layer 243 may contain two or more layers.

[0077] The source / drain volume epitaxy layer 243 is epitaxially grown from the first source / drain epitaxy layer 241. The source / drain volume epitaxy layer 243 has a higher concentration of dopants than the first source / drain epitaxy layer 241. In some embodiments, the composition of the source / drain volume epitaxy layer 243 also differs from that of the first source / drain epitaxy layer 241. The source / drain volume epitaxy layer 243 and the first source / drain epitaxy layer 241 have different crystal structures. The source / drain volume epitaxy layer 243 can include one or more layers of Si, SiP, SiC, and SiCP for NFETs or Si, SiGe, and Ge for PFETs. For PFETs, p-doping materials such as boron (B) are also included in the source / drain volume epitaxy layer 243.For NFETs, the source / drain volume epitaxy layer contains 243 n dopants such as arsenic (As), phosphorus (P) or carbon (C) or combinations thereof.

[0078] In some embodiments, the semiconductor device 200 is a p-type device, and the source / drain volume epitaxy layer 243 contains Si or SiGe with a p-type dopant such as B or Ga. In some embodiments, the source / drain volume epitaxy layer 243 can consist of a SiGe layer with a Ge atomic concentration in the range of about 20% to about 70%. In some embodiments, the source / drain volume epitaxy layer 243 contains p-type dopants in a concentration between about 1E20 and about 3E21.

[0079] In some embodiments, the source / drain volume epitaxy layer 243 can be formed by an epitaxial growth process using CVD, ALD, or molecular beam epitaxy (MBE). In some embodiments, the epitaxial deposition process can be carried out in a temperature range between about 400 °C and about 750 °C, for example, between about 520 °C and about 620 °C. In some embodiments, the epitaxial deposition process can be carried out at a pressure in a range between about 10 Torr and about 300 Torr, for example, between about 20 Torr and about 100 Torr. In some embodiments, the epitaxial deposition process can use a precursor such as H₂SiCl₂ (DCS), SiH₄, Si₂H₆, GeH₄, GeCl₄, HCl, or Cl₂. In some embodiments, a p-doping precursor such as B2H6, BCl3 and Ga(CH3)3 can be used during deposition.

[0080] As in Fig. As shown in Figure 3N, the source / drain epitaxy regions 240 are grown beyond the uppermost semiconductor channel, i.e., the second semiconductor layer 216 below the sacrificial gate structure 228, so that they touch the gate sidewall spacers 230. The first semiconductor layers 214 below the sacrificial gate structure 228 are separated from the source / drain epitaxy regions 240 by the inner spacers 232.

[0081] The source / drain epitaxy regions 240 extend below the upper surface 210f of the substrate 210 or beyond the bottom layer in the semiconductor stack 218, since the source / drain epitaxy regions 240 are grown from the side wall 212s of the well section 212 and / or the lower epitaxy layer 236. The source / drain epitaxy region 240 contacts the lower dielectric layer 238, which in turn provides insulation between the source / drain epitaxy region 240 and the well section 212.

[0082] In process 122, a contact etch stop layer (CESL) 242 and an interdielectric layer (ILD layer) 244 are formed over the exposed surfaces, as shown in Fig. Figure 3O shows the CESL 242 being formed on the source / drain epitaxy regions 240 and the gate sidewall spacers 230. In some embodiments, the CESL 242 has a thickness in the range of about 1 nm to about 15 nm. The CESL 242 can contain Si3N4, SiON, SiCN, or any other suitable material and can be formed by CVD, PVD, or ALD.

[0083] The intermediate dielectric layer (ILD layer) 244 is formed over the etch stop layer (CESL) 242. Materials for the ILD layer 244 include compounds containing Si, O, C, and / or H, such as silicon dioxide, SiCOH, and SiOC. Organic materials such as polymers can also be used for the ILD layer 244. After the ILD layer 244 has formed, a planarization process, such as CMP, is performed to expose the sacrificial gate electrode layer 226 for subsequent removal of the sacrificial gate structures 228. The ILD layer 244 protects the source / drain epitaxy regions 240 during the removal of the sacrificial gate structures 228.

[0084] In process 124, replacement gate structures 250 are formed instead of the victim gate structures 228, as in the Fig. 3P, Fig. 3Q and Fig. Figure 3R shows the process. First, the sacrificial gate structures 228 are removed. Specifically, the sacrificial gate electrode layer 226 and the sacrificial gate dielectric layer 224 are removed successively, exposing the channel section 218. The first semiconductor layers 214 and the second semiconductor layers 216 are exposed. The first semiconductor layers 214 are then selectively removed using an etchant that has a higher etch rate with respect to the first semiconductor layers 214 than with respect to the second semiconductor layers 216. After the first semiconductor layers 214 have been removed, the second semiconductor layers 216 are exposed, creating a semiconductor channel region that includes the second semiconductor layers 216, which are associated with the source / drain epitaxy regions 240.

[0085] The replacement gate structures 250 are then formed around the channel region. A gate dielectric layer 246 is formed around each of the second semiconductor layers 216, and a gate electrode layer 248 is formed on the gate dielectric layer 246. The gate dielectric layer 246 and the gate electrode layer 248 can be referred to as the replacement gate structure 250.

[0086] The gate dielectric layer 246 can be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 246 is formed using a highly conformal deposition process such as ALD to ensure the formation of a gate dielectric layer 246 with a uniform thickness around each of the second semiconductor layers 216. In some embodiments, the thickness of the gate dielectric layer 246 is in a range between about 1 nm and about 6 nm.

[0087] The gate dielectric layer 246 comprises one or more layers of a dielectric, such as silicon oxide, silicon nitride, or a high-k dielectric, another suitable dielectric, and / or combinations thereof. Examples of high-k dielectrics include HfO₂, HfSiO₂, HfSiON₄, HfTaO, HfTiO₂, HfZrO₂, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide alloy (HfO₂-Al₂O₃), other suitable high-k dielectrics, and / or combinations thereof. In some embodiments, an interface layer (not shown) is formed between the second semiconductor layer 216 and the gate dielectric layer 246. In some embodiments, one or more work function setting layers (not shown) are inserted between the gate dielectric layer 246 and the gate electrode layer 248.

[0088] The gate electrode layer 248 is formed on the gate dielectric layer 246 such that it surrounds each of the second semiconductor layers 216 (i.e., each channel) and the gate dielectric layer 246. The gate electrode layer 248 comprises one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 248 can be formed by CVD, ALD, electroplating, or other suitable methods.

[0089] After the formation of the gate electrode layer 248, a planarization process, such as a CMP process, is performed to remove excess deposited gate electrode material and expose the top surface of the ILD layer 244. In some embodiments, source / drain contacts 252 are formed in the ILD layer 244. Prior to the formation of the front-side source / drain contacts 252, contact holes are formed in the ILD layer 244, the CESL 242, and a portion of the source / drain epitaxy regions 240.

[0090] Following the formation of the front-side source / drain contacts 252, a front-side interconnect structure (not shown) is formed by a middle-end-of-line process. The front-side interconnect structure comprises multiple dielectric layers with metal conductors and vias formed therein. The metal conductors and vias in the front-side interconnect structure can be formed from copper or copper alloys using one or more Damascene processes. The front-side interconnect structure can include multiple sets of interlayer dielectric (ILD) layers and intermetal dielectric (IMD) layers.

[0091] Fig. 3Q is a partially enlarged view of Fig. 3P in which in Fig. 3P with 3Q marked area. Fig. 3R is a partial cross-sectional view of the semiconductor device 200 along the 3R-3R line in Fig. 3P. As in the Fig. 3Q and Fig. As shown in Figure 3P, the inner spacers 232 touch the channel sections 241C of the first epitaxy layer 241 at the upper surface 232t and the lower surface 232b. The side wall 232s of the inner spacer 232 touches the source / drain epitaxy area 240, which may be channel sections 241C or the source / drain volume epitaxy layer 243.

[0092] The lower dielectric layer according to the present disclosure, for example the lower dielectric layer 238, can vary in shape and / or position to achieve different design effects. The lower dielectric layer can be formed at different locations relative to the channel layers and / or have different shapes. Fig. 4A to 4L contain different arrangements of the lower dielectric layer according to embodiments of the present disclosure.

[0093] The Fig. Figures 4A to 4B schematically show a semiconductor device 10a according to the present disclosure. Fig. Figure 4A is a schematic cross-sectional view of the semiconductor device 10a according to procedure 114. Fig. Figure 4B is a corresponding top view of the semiconductor device 10a. Fig. 4A The lower epitaxial layer 36 has a substantially flat upper surface 36t, resulting in a substantially flat lower dielectric layer 38. The lower dielectric layer 38 can have a thickness t DF in a range between approximately 1 nm and approximately 10 nm. The lower dielectric layer 38 can be located essentially near the underside of the leaf or the upper surface 12f of the substrate 12. The relative position of the lower dielectric layer 38 with respect to the upper surface 12f can be determined by a depression spacing h. DFThe indentation spacing h is displayed, defined by the distance between the lower surface 38b of the lower dielectric layer 38 and the underside or upper surface 12f of the sheet. In some embodiments, the indentation spacing h DF in a range between approximately -15 nm and approximately 15 nm. A positive indentation spacing h DF indicates that the lower surface 38b of the lower dielectric layer 38 lies above the underside of the sheet or the upper surface 12f, while a negative depression spacing h DF indicates that the lower surface 38b of the lower dielectric layer 38 lies below the underside of the leaf or the upper surface 12f. In Fig. 4A is the depth spacing h DF negative.

[0094] The opening 39 through the lower dielectric layer 38 is wide enough to allow the source / drain epitaxy region to grow from the lower epitaxy layer 36 through the opening 39. As shown in Fig. As shown in Figure 4B, the opening 39 extends along the y-direction through the lower dielectric layer 38 and divides the lower dielectric layer 38 into two separate sections. In some embodiments, a width S is present. DF the aperture 39 in a range between about 1 nm and about 30 nm.

[0095] The Fig. Figures 4C to 4D schematically show a semiconductor device 10b according to the present disclosure. The semiconductor device 10b is similar to the semiconductor device 10a, except that the opening 39 is arranged asymmetrically with respect to the inner spacers 32.

[0096] Fig. Figure 4E schematically shows a semiconductor device 10c according to the present disclosure. The semiconductor device 10c is similar to the semiconductor device 10a, except that the lower dielectric layer 38 in the semiconductor device 10c is lower along the z-direction, i.e., has a larger negative indentation spacing h.DF exhibits the larger negative indentation distance h DF This results in a section of the side wall 12s of the mesa section 12M being exposed opposite the source / drain depression 34. The exposed side wall 12s acts as a nucleation layer during the subsequent growth of the source / drain region 40 to achieve a specific structure within the source / drain region. Furthermore, the lowering of the dielectric layer 38 increases the volume of the source / drain region 40.

[0097] Fig. Figure 4F schematically shows a semiconductor device 10d according to the present disclosure. The semiconductor device 10f is similar to the semiconductor device 10a, except that the side walls 38s of the opening 38 are inclined. The side wall 38s and the upper surface 38t form an angle θ. DF In some embodiments, the angle θ DFin a range between approximately 10° and approximately 150°. To achieve the desired crystal structure, a suitable angle θ can be used. DF be selected.

[0098] Fig. Figure 4G schematically shows a semiconductor device 10e according to the present disclosure. The semiconductor device 10f is similar to the semiconductor device 10a, except that the lower dielectric layer 38 in the semiconductor device 10f is higher along the z-direction, i.e., has a positive indentation spacing h. DF exhibits the positive indentation distance h. DF leads to improved insulation between the mesa section 12M and the source / drain epitaxy region 40, which is to be formed above the lower dielectric layer 38.

[0099] Fig. Figure 4H schematically shows a semiconductor device 10f according to the present disclosure. The semiconductor device 10f is similar to the semiconductor device 10a, except that the lower epitaxial layer 36 has a curved upper surface 36t, resulting in a substantially curved lower dielectric layer 38. The lower dielectric layer 38 can have a vertical extent V DC exhibiting a distance between the highest point of the upper surface 38t and the lowest point of the lower surface 38b along the z-direction. In some embodiments, the vertical extent V DC in a range between approximately 1 nm and approximately 30 nm. The lower dielectric layer 38 can have a horizontal extent L DCexhibiting a distance defined by the distance between the side wall 32s of the inner spacer 32 and the side wall 38s of the opening 39 along the x-direction. In some embodiments, the horizontal extent of the L DC in a range between approximately 1 nm and approximately 20 nm. In some embodiments, the lower dielectric layer 38 and an xy-plane can form an angle θ. DC form. In some embodiments, the angle θ DC in a range between approximately 5° and approximately 90°. The relative position of the lower dielectric layer 38 with respect to the upper surface 12f can be determined by a depression spacing h. DC The distance h is defined by the distance between the lowest point of the lower dielectric layer 38 and the underside of the sheet or the upper surface 12f along the z-direction. In some embodiments, the depression spacing h is DCin a range between approximately -15 nm and approximately 15 nm. Fig. 4H is the depth spacing h DC negative. In Fig. 4H are the upper surface 36t of the lower epitaxial layer 36 and the lower dielectric layer 38, both concave.

[0100] The opening 39 through the lower dielectric layer 38 is wide enough to allow the source / drain epitaxy region to grow from the lower epitaxy layer 36 through the opening 39. The opening 39 extends along the y-direction through the lower dielectric layer 38 and divides the lower dielectric layer 38 into two separate sections. In some embodiments, a width S is present. DC the aperture 39 in a range between about 1 nm and about 30 nm.

[0101] Fig. Figure 4I schematically shows a semiconductor device 10g according to the present disclosure. The semiconductor device 10g is similar to the one in Fig. 4H semiconductor device 10f shown, except that the upper surface 36t of the lower epitaxial layer 36 and the lower dielectric layer 38 are both convex and the depression spacing h DC is positive.

[0102] Fig. Figure 4J schematically shows a semiconductor device 10h according to the present disclosure. The semiconductor device 10h is similar to the one in Fig. 4E semiconductor device 10c shown, except that the lower dielectric layer 36 is a continuous layer without openings. The exposed sidewall 12s acts as a seed layer in the formation of the source / drain epitaxy region 40. The lower dielectric layer 38 can have a thickness t CFin a range between approximately 1 nm and approximately 10 nm. The lower dielectric layer 38 can be located essentially near the underside of the leaf or the upper surface 12f of the substrate 12. The relative position between the lower dielectric layer 38 and the upper surface 12f can be determined by a depression spacing h. CF The distance h is defined by the distance between the lower surface 38b of the lower dielectric layer 38 and the underside or upper surface 12f of the sheet. In some embodiments, the depression spacing h is CF in a range between approximately -20 nm and approximately 20 nm.

[0103] Fig. Figure 4K schematically shows a semiconductor device 10i according to the present disclosure. The semiconductor device 10i is similar to the semiconductor device 10h from Fig. 4J, except that the lower epitaxial layer 36 has a curved upper surface 36t, resulting in an essentially curved lower dielectric layer 38. The lower dielectric layer 38 forms a continuous curved film.

[0104] The lower dielectric layer 38 can have a vertical extent V CC exhibiting a distance between the highest point of the upper surface 38t and the lowest point of the lower surface 38b along the z-direction. In some embodiments, the vertical extent V CC in a range between approximately 1 nm and approximately 30 nm. In some embodiments, the lower dielectric layer 38 and an xy-plane can form an angle θ. CC form. In some embodiments, the angle θ CCin a range between approximately 5° and approximately 90°. The relative position between the lower dielectric layer 38 and the upper surface 12f can be determined by a depression spacing h. CC The indentation spacing h is defined by the distance between the lowest point of the lower dielectric layer 38 and the underside of the sheet or the upper surface 12f along the z-direction. In some embodiments, the indentation spacing h is CC in a range between approximately -20 nm and approximately 20 nm.

[0105] Fig. Figure 4L schematically shows a semiconductor device 10j according to the present disclosure. The semiconductor device 10j is similar to the one in Fig. 4K shown semiconductor device 10i, except that the upper surface 36t of the lower epitaxial layer 36 and the lower dielectric layer 38 are both convex.

[0106] According to embodiments of the present disclosure, source / drain regions can be designed to achieve different shapes and / or layer compositions of the source / drain region. This is done, for example, by modifying the shape and / or position of the lower dielectric layer, forming or omitting openings through the lower dielectric layer, selecting the shape and position of the opening, including or omitting the channel shortening process, etc. Fig. Figures 5A to 5L schematically show different designs of the source / drain areas according to embodiments of the present disclosure.

[0107] Fig. Figure 5A schematically shows a semiconductor device 200a according to embodiments of the present disclosure. Fig. Figure 5A schematically shows the semiconductor device 200a after the formation of the source / drain epitaxy regions 240, for example, after process 120. The semiconductor device 200a is similar to the semiconductor device 200 described above, except that the channel shortening process 116 is omitted in the fabrication of the semiconductor device 200a. Furthermore, the lower dielectric layer 238 contacts the lowermost inner spacers 232, and the side wall 212s of the well section 212 does not contact the source / drain epitaxy region 240. In other words, the lower dielectric layer 238 insulates the source / drain epitaxy region 240 and the well section 212 of the substrate 210, or the mesa region.

[0108] In the semiconductor device 200a, the first source / drain epitaxy layer 241 has several separate sections, namely the channel sections 241C and the bottom section 241B, which are not fused together. The channel sections 241C extend from the side wall 232s of the inner spacer 232 by a distance t. S along the x-direction. In some embodiments, the distance t is S between approximately 1 nm and approximately 8 nm. The lower section 241B extends from the upper surface 236t by a distance t. B along the z-direction. In some embodiments, the distance t is B between approximately 1 nm and approximately 12 nm. The source / drain volume epitaxy layer 243 contacts at least a portion of the side walls 232s of the inner spacer 232. The source / drain volume epitaxy layer 243 also contacts the lower dielectric layer 238.

[0109] Fig. Figure 5B schematically shows a semiconductor device 200b according to embodiments of the present disclosure. The semiconductor device 200b is similar to the semiconductor device 200a described above, except that some channel sections 241C of the first source / drain epitaxy layer 241 are fused together, while other channel sections 241 are not fused. The source / drain epitaxy region 240 has an EPI height M, which can be defined as the distance between an upper surface 240t and a lower surface 240b of the source / drain epitaxy region 240 along the z-direction. In some embodiments, the EPI height is in a range between about 20 nm and about 105 nm. In some embodiments, the channel sections 241C can be fused at a fusion height h. Mmerge, which can be defined as the distance between the upper surface 240t of the source / drain epitaxy region 240 and a merge point along the z-direction. In some embodiments, the merge height h is M in a range between 0 and the EPI height M. As in Fig. As shown in Figure 5B, in the semiconductor device 200b, the source / drain volume epitaxy layer 243 touches some of the inner spacers 232, but part of the inner spacers 232 may be covered by the first source / drain epitaxy layer 241. The source / drain volume epitaxy layer 243 also touches the lower dielectric layer 238.

[0110] Fig. Figure 5C schematically shows a semiconductor device 200c according to embodiments of the present disclosure. The semiconductor device 200c is similar to the semiconductor device 200a described above, except that the lowest channel section 241C and the lower section 241B of the first source / drain epitaxy layer 241 are fused together, while the upper channel sections 241 are not fused. As shown in Figure 5C, the semiconductor device 200c is a semiconductor device 200c. Fig. As shown in Figure 5C, in the semiconductor device 200c the source / drain volume epitaxy layer 243 touches the upper inner spacers 232, but the lower inner spacers 232 and the lower dielectric layer 238 are covered by the first source / drain epitaxy layer 241.

[0111] Fig. Figure 5D schematically shows a semiconductor device 200d according to embodiments of the present disclosure. The semiconductor device 200d is similar to the semiconductor device 200c described above, except that some of the upper channel sections 241 are fused together. As shown in Fig. As shown in Figure 5D, in the semiconductor device 200d the source / drain volume epitaxy layer 243 touches some of the upper inner spacers 232, but the lower inner spacers 232 and the lower dielectric layer 238 are covered by the first source / drain epitaxy layer 241.

[0112] Fig. Figure 5E schematically shows a semiconductor device 200e according to embodiments of the present disclosure. The semiconductor device 200e is similar to the semiconductor device 200a described above, except that a channel shortening process was performed during the fabrication of the semiconductor device 200e. As a result, the source / drain epitaxy region 240 extends beyond the side walls 232s of the inner spacers 232 into the semiconductor layers 216 and the channel layers, respectively. The first source / drain epitaxy layer 241 can extend over a length t PH extend from the side wall 232s of the inner spacer 232. In some embodiments, the length t PH in a range between approximately 1 nm and approximately 6 nm. As described above, the channel section 241C of the first source / drain epitaxy layer 241 can be positioned a distance t from the side wall 232s of the inner spacers 232. Sextend. In some embodiments, the total thickness t S + t PH of channel section 241C of the first source / drain epitaxy layer 241 in a range between about 1 nm and about 14 nm.

[0113] In these embodiments, the lower epitaxial layer 236 is also etched back during the channel shortening process. As a result, the source / drain epitaxial region 240 extends through the lower dielectric layer 238 and into the lower epitaxial layer 236. In some embodiments, the source / drain epitaxial region 240 can extend over a length t PV extend from the upper surface 236t into the lower epitaxial layer 236. In some embodiments, the length t PV in a range between approximately 1 nm and approximately 10 nm. As described above, the lower section 241B of the first source / drain epitaxic layer 241 can be positioned a distance t from the upper surface 236t. Bextend. In some embodiments, the total thickness t B + t PV of the lower section 241B of the first source / drain epitaxy layer 241 in a range between about 1 nm and about 22 nm.

[0114] Fig. Figure 5F schematically shows a semiconductor device 200f according to embodiments of the present disclosure. The semiconductor device 200f is similar to the semiconductor device 200 described above, except that the channel shortening process 116 is omitted in the fabrication of the semiconductor device 200f. Furthermore, the lower dielectric layer 238 is a continuous layer without the opening 239. In some embodiments, the side wall 212s of the well section 212 contacts the source / drain epitaxy region 240 over a vertical length K. In some embodiments, the vertical length K is in a range between about 0 nm and about 50 nm. In the semiconductor device 200f, the first source / drain epitaxy layer 241 has several separate sections, i.e., the channel sections 241C and the side wall section 241S, which are not fused together. The side wall section 241S is grown from the exposed side walls 212s.In some embodiments, an upper surface 241St of the side wall section 241S and an xy-plane form an angle θ. DB In some embodiments, the angle θ DB in a range between approximately 10° and approximately 80°. The source / drain volume epitaxy layer 243 contacts at least a portion of the side walls 232s of the inner spacer 232. The source / drain volume epitaxy layer 243 also contacts the lower dielectric layer 238.

[0115] Fig. Figure 5G schematically shows a semiconductor device 200g according to embodiments of the present disclosure. The semiconductor device 200g is similar to the semiconductor device 200 described above, except that the channel shortening process 116 is omitted in the fabrication of the semiconductor device 200g. Furthermore, the lower dielectric layer 238 is a continuous layer without the opening 239. The first source / drain epitaxy layer 241 covers the side walls 232s of some of the inner spacers 232. The source / drain volume epitaxy layer 243 contacts at least a portion of the side walls 232s of the inner spacer 232. The source / drain volume epitaxy layer 243 also contacts the lower dielectric layer 238.

[0116] Fig. Figure 5H schematically shows a semiconductor device 200h according to embodiments of the present disclosure. The semiconductor device 200h is similar to the semiconductor device 200g described above, except that the sidewall sections 241S of the first source / drain epitaxy layer 241 are fused together, while the channel sections 241C remain unconnected. As shown in Fig. As shown in Figure 5H, in the semiconductor device 200h the source / drain volume epitaxy layer 243 touches the inner spacers 232, but the lower dielectric layer 238 is covered by the first source / drain epitaxy layer 241.

[0117] Fig. Figure 5I schematically shows a semiconductor device 200i according to embodiments of the present disclosure. The semiconductor device 200i is similar to the semiconductor device 200h described above, except that the sidewall sections 241S of the first source / drain epitaxy layer 241 are fused to each other and to the lowest channel sections 241C. Some of the upper channel sections 241 remain unconnected. As shown in Fig. As shown in Figure 5I, in the semiconductor device 200i the source / drain volume epitaxy layer 243 touches some of the upper inner spacers 232, but the lower inner spacers 232 and the lower dielectric layer 238 are covered by the first source / drain epitaxy layer 241.

[0118] Fig. Figure 5J schematically shows a semiconductor device 200j according to embodiments of the present disclosure. The semiconductor device 200j resembles the one shown above in Fig. The semiconductor device 200f described in Section 5F is identical, except that a channel shortening process is performed during the fabrication of the semiconductor device 200j. As a result, the source / drain epitaxy region 240 extends beyond the side walls 232s of the inner spacers 232 into the semiconductor layers 216 and the channel layers, respectively. The first source / drain epitaxy layer 241 can extend over a length t PH extend from the side wall 232s of the inner spacer 232. In some embodiments, the length t PH in a range between approximately 1 nm and approximately 6 nm. As described above, the channel section 241C of the first source / drain epitaxy layer 241 can be positioned a distance t from the side wall 232s of the inner spacers 232. S extend. In some embodiments, the total thickness t S + t PHof the channel section 241C of the first source / drain epitaxy layer 241 in a range between approximately 1 nm and approximately 14 nm. In the embodiments, the trough section 212 is also etched back during the channel shortening process. This results in the side wall section 241S of the first source / drain epitaxy layer 241 projecting beyond the side wall 232s of the inner spacers 232.

[0119] Fig. Figure 5K schematically shows different profiles of the interface between the source / drain epitaxy region 240 and the semiconductor layer 216 or the channel layer. The profile can be convex, flat, concave, or inclined. The different profiles can be achieved by controlling the etching process during the channel shortening process, for example, process 116. The interface and the yz-plane form an angle θ. C In some embodiments, the angle θ C in a range between approximately -80° and approximately 80°.

[0120] Fig. Figure 5L schematically shows different profiles of the interface between the source / drain epitaxy region 240 and the internal spacers 232. The profile can be convex, flat, or concave. The different profiles can be achieved by controlling the etching process during the formation of the internal spacers 232. The interface and the yz-plane form an angle θ. SP In some embodiments, the angle θ SP in a range between approximately -80° and approximately 80°.

[0121] Several embodiments or examples described herein offer several advantages over current technology. The semiconductor device according to the present disclosure has a reduced channel resistance (R). ch ) with improved AC performance and minimized DC power loss through R ch -Deterioration.

[0122] It is understood that not all advantages have necessarily been described herein; no particular advantage is required in all embodiments or examples, and other embodiments or examples may offer other advantages.

[0123] Some embodiments of the present invention provide a semiconductor device. The semiconductor device comprises a semiconductor channel arranged above an upper surface of a semiconductor substrate; a source / drain epitaxy region connected to the semiconductor channel, the source / drain epitaxy region having a side wall connected to the semiconductor channel and a lower surface extending below the upper surface of the semiconductor substrate; and a lower dielectric layer in contact with the lower surface of the source / drain epitaxy region, the lower dielectric layer partially covering the lower surface extending below the semiconductor substrate.

[0124] Some embodiments of the present invention provide for a semiconductor device. The semiconductor device comprises a semiconductor substrate; two or more semiconductor channel layers stacked vertically above a top surface of the semiconductor substrate; two or more internal spacers stacked alternately with the two or more semiconductor channel layers; and a source / drain epitaxy region comprising: a first source / drain epitaxy layer grown from the two or more semiconductor channel layers and a semiconductor surface located below the top surface of the semiconductor substrate; and a source / drain volume epitaxy layer grown from the first source / drain epitaxy layer.

[0125] Some embodiments provide a method for forming a semiconductor device. The method comprises forming a semiconductor fin on an upper surface of a semiconductor substrate, wherein the semiconductor fin has alternating first and second semiconductor layers; forming a depression through the semiconductor fin and into the semiconductor substrate; forming a lower dielectric layer in the depression, wherein the lower dielectric layer partially covers a semiconductor surface below the upper surface of the semiconductor substrate; and growing a source / drain epitaxy region over the lower dielectric layer, wherein the source / drain epitaxy region contacts a portion of the semiconductor surface below the upper surface of the semiconductor substrate.

[0126] The foregoing describes features of various embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should recognize that they can easily use the present disclosure as a basis for designing or modifying further processes and structures to achieve the same objectives and / or realize the same advantages of the embodiments introduced herein. They should also recognize that such equivalent designs do not deviate from the spirit and scope of the present disclosure and that they can make various changes, substitutions, and modifications here without deviating from the spirit and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 536 604

[0001] US 63 / 610 117

[0001]

Claims

[1] A semiconductor device comprising: a semiconductor channel disposed over a top surface of a semiconductor substrate; a source / drain epitaxial region connected to the semiconductor channel, the source / drain epitaxial region having a sidewall connected to the semiconductor channel and a bottom surface extending below the top surface of the semiconductor substrate; and a lower dielectric layer in contact with the lower surface of the source / drain epitaxial region, the lower dielectric layer partially covering the lower surface extending beneath the semiconductor substrate. [2] The semiconductor device according to claim 1, wherein the semiconductor channel comprises two or more semiconductor channel layers stacked over the top surface of the semiconductor substrate. [3] The semiconductor device according to claim 2, further comprising a lower epitaxial layer disposed below the lower dielectric layer, and wherein a lower portion of the source / drain epitaxial region is formed above the lower epitaxial layer. [4] The semiconductor device according to claim 3, wherein the lower dielectric layer has an opening, and a lower portion of the source / drain epitaxial region extends under the lower dielectric layer through the opening to contact the lower epitaxial layer. [5] A semiconductor device according to claim 4, wherein the lower dielectric layer is a continuous layer through which an opening is formed. [6] The semiconductor device according to claim 4, wherein the lower dielectric layer is a discontinuous layer and the opening is a slit formed through the lower dielectric layer. [7] A semiconductor device according to any one of claims 4 to 6, wherein the lower portion of the source / drain epitaxial region extends into the lower epitaxial layer. [8] A semiconductor device according to any one of claims 3 to 6, wherein the lower dielectric layer is disposed below the upper surface of the semiconductor substrate, and the source / drain epitaxial region contacts the semiconductor substrate at a sidewall below the upper surface of the semiconductor substrate and above the lower dielectric layer. [9] The semiconductor device according to any one of claims 2 to 8, further comprising an inner spacer disposed between the two or more semiconductor channel layers, wherein a top surface, a bottom surface and a sidewall of the inner spacer contact the source / drain epitaxial region. [10] A semiconductor device comprising: a semiconductor substrate; two or more semiconductor channel layers stacked vertically above a top surface of the semiconductor substrate; two or more inner spacers arranged alternately stacked with the two or more semiconductor channel layers; and a source / drain epitaxial region comprising: a first source / drain epitaxial layer grown from the two or more semiconductor channel layers and a semiconductor surface disposed below the top surface of the semiconductor substrate; and a source / drain bulk epitaxial layer grown from the first source / drain epitaxial layer. [11] A semiconductor device according to claim 10, wherein the first source / drain epitaxial layer comprises: two or more channel sections grown from the two or more semiconductor channel layers; and a lower portion grown from the semiconductor surface located below the upper surface of the semiconductor substrate. [12] The semiconductor device of claim 11, further comprising a lower dielectric layer disposed between the semiconductor surface and the source / drain epitaxial region, the lower dielectric layer partially covering the semiconductor surface. [13] The semiconductor device of claim 12, wherein the lower dielectric layer has an opening, and the lower portion is grown from the semiconductor surface through the opening. [14] The semiconductor device of claim 13, wherein the lower portion extends below the lower dielectric layer and into the semiconductor surface. [15] A semiconductor device according to any one of claims 12 to 14, wherein the lower dielectric layer is disposed below the upper surface of the semiconductor substrate, and the lower portion is grown from a sidewall of the semiconductor substrate below the upper surface and above the lower dielectric layer. [16] A method comprising: Forming a semiconductor fin on an upper surface of a semiconductor substrate, the semiconductor fin having alternately arranged first semiconductor layers and second semiconductor layers; Forming a recess through the semiconductor fin and into the semiconductor substrate; Forming a lower dielectric layer in the recess, wherein the lower dielectric layer partially covers a semiconductor surface below the upper surface of the semiconductor substrate; and Growing a source / drain epitaxial region over the lower dielectric layer, wherein the source / drain epitaxial region contacts a portion of the semiconductor surface below the top surface of the semiconductor substrate. [17] The method of claim 16, further comprising: Growing a lower epitaxial layer in the recess, wherein the lower dielectric layer is formed on the lower epitaxial layer. [18] The method of claim 16 or 17, wherein forming the lower dielectric layer comprises: depositing a continuous dielectric layer; and Forming an opening through the continuous dielectric layer such that a portion of the lower epitaxial layer is exposed, wherein a portion of the source / drain epitaxial region is grown from the lower epitaxial layer through the opening. [19] The method of claim 18, further comprising: selectively etching back the first semiconductor layers to form internal spacers between the second semiconductor layers; and Before forming the source / drain epitaxial region, etching back the second semiconductor layers from the inner spacers. [20] The method of any one of claims 17 to 19, wherein an upper surface of the lower epitaxial layer is below the upper surface of the semiconductor substrate, and sidewalls of the recess are exposed between the lower dielectric layer and the upper surface of the semiconductor substrate, and wherein growing a source / drain epitaxial region comprises: Growing a first source / drain layer from the sidewalls of the recess.

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