SIDE-DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSITOR (LDMOS TRANSITOR) AND MANUFACTURING METHOD THERE FOR IT

Abstract

A side-diffused metal-oxide-semiconductor transistor (LDMOS transistor) has a first gate. The LDMOS transistor further has a first source region on a first side of the first gate. The LDMOS transistor further has a drain region on a second side of the first gate, the second side being opposite the first side. The LDMOS transistor further has a first spacer that surrounds the first gate. The first spacer has a first section on the first side of the first gate, the first section having a top surface that is substantially coplanar with a top surface of the first gate. The first spacer further has a second section on the second side of the first gate, the second section having a first horn structure that extends over the top surface of the first gate.

Description

background

[0001] With technological advances in the field of semiconductor integrated circuits (ICs), materials, designs, and manufacturing processes have enabled a continuous reduction in IC device size. This reduction in IC device size, in turn, leads to an increase in the portability of systems containing IC devices. Portable systems often use batteries as a basis for providing power to the IC device. Furthermore, IC devices have improved speed performance.

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) transistors can be used in radio frequency (RF) and microwave applications. LDMOS transistors are sometimes used in power amplification circuits. Therefore, LDMOS transistors are sometimes included in portable IC devices such as mobile phones.

[0003] Document US 2022 / 0 384 642 A1 discloses a method for fabricating an integrated circuit structure. The method comprises: forming a gate dielectric layer over a semiconductor substrate; depositing a first gate electrode layer over the gate dielectric layer; etching the first gate electrode layer to form a gate electrode over the gate dielectric layer; creating a drift region in the semiconductor substrate; depositing a dielectric layer over the gate dielectric layer and the gate electrode, the dielectric layer having a first portion along a first sidewall of the gate electrode; depositing a second gate electrode layer over the dielectric layer; etching the second gate electrode layer to form a field plate electrode along the first portion of the dielectric layer; and forming source / drain elements in the semiconductor substrate. Short description of the drawings

[0004] Aspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Rather, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 is a cross-sectional view of an LDMOS transistor according to some embodiments. Fig. 2 is a graph of drain voltage (Vd) versus gate-to-drain capacitance (Cgd) according to some embodiments, comparing an LDMOS transistor without a horn to an LDMOS transistor with a horn, each at a voltage of 6 V and a drain-to-gate capacitance (Cgd). Fig. 3 is a graph of total gate charge (Qg) versus gate voltage (Vg) comparing an LDMOS transistor without a horn to an LDMOS transistor with a horn, each at a voltage of 6 V and a drain-gate capacitance (Cgd), according to some embodiments. Fig. 4 is a flow diagram of a method of manufacturing an LDMOS transistor according to some embodiments. Fig. 5 is a cross-sectional view of an LDMOS transistor during an intermediate stage of fabrication, according to some embodiments. The Fig. 6A to 6E are cross-sectional views of an LDMOS transistor during various intermediate stages of fabrication, according to some embodiments. The Fig. 7A to 7E are cross-sectional views of an LDMOS transistor during various intermediate stages of fabrication according to some embodiments. The Fig. 8A to 8E are cross-sectional views of an LDMOS transistor during various intermediate stages of fabrication, according to some embodiments. The Fig. 9A to 9E are cross-sectional views of an LDMOS transistor during various intermediate stages of fabrication according to some embodiments. The Fig. 10A to 10E are cross-sectional views of an LDMOS transistor during various intermediate stages of fabrication, according to some embodiments. Fig. 11 is a schematic diagram of a buck converter including an LDMOS transistor according to some embodiments. Detailed description

[0005] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structural element to one or more other elements or structural elements illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90° or in another orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0006] As IC device sizes decrease, more IC devices are being integrated into portable systems, such as mobile phones, smartwatches, and other Internet of Things (IoT) systems. Portable systems sometimes rely on batteries to power IC devices. To extend the useful life of portable devices, IC devices with lower power consumption are desirable. And as the functionality of portable systems increases, customers expect better performance.

[0007] The present description relates to an LDMOS transistor having a horn structure on a drain-side spacer. The horn structure extends upward beyond a top surface of a gate enclosed by the spacer. Compared to other LDMOS transistors that do not have the horn structure, the LDMOS transistor with the horn structure can form a silicide layer across an entire top surface of the gate. By forming the silicide layer across the entire top surface of the gate, the resistance between the gate and a contact structure is reduced compared to other approaches. The reduced resistance contributes to reducing power consumption by the LDMOS transistor with the horn structure compared to other approaches. For example, an LDMOS transistor has a resist protection oxide (RPO) that partially overlaps the gate structure.Partially overlapping the gate with the RPO reduces a portion of the gate that can be covered by a silicide layer.

[0008] Overlapping the gate with the RPO also reduces the ability to reduce gate size, as there is an increased risk of device failure if the RPO compresses a smaller gate. Maintaining a larger gate size to support the RPO sometimes results in higher gate-drain capacitance (Cgd) or higher total gate charge (Qg). Total gate charge Qg is the amount of charge injected into a gate to cause the transistor to switch between a non-conductive (off) state and a conductive (on) state. Gate-drain capacitance Cgd affects the delay between applying a voltage to the gate to change the transistor's on / off state and changing the current at the transistor's drain. Reducing total gate charge Qg helps conserve battery power in portable systems.By minimizing the gate-drain capacitance Cgd, a speed of the transistor in fully switching between on / off states is improved.

[0009] In some cases, the use of an RPO in an LDMOS transistor also reduces the size of a silicide layer over a drain. Similar to the reduced silicide layer over the gate, the reduced silicide layer over the drain increases the resistance between the drain and a contact electrically connected to the drain. Due to the increased resistance between the contacts and the gate and / or drain of the LDMOS transistor, heat generation by the LDMOS transistor also increases. This also exacerbates heat dissipation problems in LDMOS transistors with an RPO compared to an LDMOS transistor with the horn structure of the present disclosure.

[0010] Fig. 1 is a cross-sectional view of an LDMOS transistor 100 according to some embodiments. The LDMOS transistor 100 includes multiple gates 150a and 150b. The LDMOS transistor 100 includes a common drain 170 between the gates 150a and 150b. While an LDMOS transistor 100 with a multi-gate structure is described in detail below, one of ordinary skill in the art will recognize that the description also applies to an LDMOS transistor with a single-gate structure.

[0011] The LDMOS transistor 100 has a substrate 110. A deep well 120 is arranged in the substrate 110. A plurality of first doped regions 130a and 130b are arranged above the deep well 120 and extend to a top surface of the substrate 110. A second doped region 135 is arranged between the first and second doped regions 130a and 130b. The second doped region 135 also extends to the top surface of the substrate 110.

[0012] A first source region 140a is disposed in an upper part or section of the first doped region 130a. A second source region 140b is disposed in an upper part of the first doped region 130b. The first source region 140a and the second source region 140b are each a split source region. For clarity of the drawings, different parts of the split source region are only labeled in the first source region 140a. The first source region 140a includes a first region 142a and a second region 144a. The second region 144a is located between the first region 142a and an adjacent gate 150a. A first source silicide layer 145a is disposed over the first source region 140a, and a second source silicide layer 145b is disposed over the second source region 140b.

[0013] The first gate 150a is adjacent to the first source region 140a and disposed above an interface of the first doped region 130a and the second doped region 135. A first gate silicide layer 155a is disposed above the first gate 150a. A first spacer encloses the first gate 150a. The first spacer includes a first spacer portion 160a adjacent to the first source 140a. A top surface of the first spacer portion 160a is approximately coplanar with a top surface of the first gate 150a. The first spacer further includes a second spacer portion 165a between the first gate 150a and the drain 170. The second spacer portion 165a has a lower region 167a extending from the top surface of the substrate 110 to be approximately coplanar with the top surface of the first gate 150a.A portion or section of the lower region 167a farthest from the first gate 150a has a substantially planar top surface. A portion of the lower region 167a closest to the first gate 150a has a curved top surface. The second spacer portion 165a further includes an upper region 169a, also referred to as a horn structure. The upper region 169a extends over the top surface of the first gate 150a to a point above the first gate 150a.

[0014] The drain region 170 is located in the second doped region 135 between the first gate 150a and the second gate 150b. A drain silicide layer 175 is disposed above the drain region 170.

[0015] The second gate 150b is similar to the first gate 150a. In some embodiments, dimensions Lg1, Lg2, and Ld for the second gate 150b also apply to the first gate 150a. A second silicide layer 155b is similar to the first silicide layer 155a. A second spacer surrounds the second gate 150b. The second spacer portion includes a third spacer portion 160b similar to the first spacer portion 160a. The second spacer further includes a fourth spacer portion 165b similar to the second spacer portion 165a. In some embodiments, dimensions L1 and L2 for the second spacer portion 165a also apply to the fourth spacer portion 165b.

[0016] The substrate 110 contains a semiconductor material. In some embodiments, the substrate 110 is lightly doped or self-doped. In some embodiments, the substrate 110 is undoped. In some embodiments, the substrate 110 contains silicon. In some embodiments, the substrate 110 is a silicon-on-insulator (SOI) substrate. In some embodiments, the substrate 110 has a top surface that directly contacts the first gate 150a and the second gate 150b. In some embodiments, the substrate 110 has a top surface that directly contacts the deep well 120, and the deep well 120 and other components are grown on the substrate 110, e.g., using an epitaxial process.

[0017] The deep well 120 contains a first dopant species. The deep well 120 provides electrical insulation for the substrate 110. In some embodiments, the first dopant species is p-type, such as boron (B) or boron difluoride (BF2 ). In some embodiments, the first dopant species is n-type, such as phosphorus (P) or arsenic (Ar). In some embodiments, the deep well 120 is created by implanting dopants having the first dopant species into the substrate 110. In some embodiments, an annealing process follows the implantation process to more evenly distribute the dopants in the deep well 120. In some embodiments, the deep well 120 is created by growing a doped epi layer over the substrate. In some embodiments, the epi layer is grown and doped after epitaxial growth. In some embodiments, the epi layer is doped in situ during epitaxial growth. In some embodiments, a doping concentration of the deep well 120 is about 10 15 Dopants / cm 3 up to 10 17 Dopants / cm 3If the doping concentration is too high, the risk of current leakage increases in some cases. Conversely, if the doping concentration is too low, the risk that the substrate 110 will not be electrically insulated increases in some cases. In some embodiments, a thickness of the deep well 120 is about 2 µm to about 3 µm. If the thickness of the deep well 120 is too small, there is a risk in some cases that the substrate 110 will not be sufficiently insulated. Conversely, if the thickness of the deep well 120 is too large, a size of the LDMOS transistor 100 increases in some cases without noticeably improving performance.

[0018] The deep well 120 extends continuously below the first gate 150a and the second gate 150b. In some embodiments, the deep well 120 is discontinuous at a location below the second doped region 135, which is offset from the first gate 150a and the second gate 150b in a top view.

[0019] The first doped regions 130a and 130b are arranged above the deep well 120. The first doped regions 130a and 130b each have the first dopant species. In some embodiments, the first doped regions 130a and 130b are created by implanting dopants having the first dopant species into the substrate 110. In some embodiments, an annealing process follows the implantation process to more evenly distribute the dopants in the first doped regions 130a and 130b. In some embodiments, the first doped regions 130a and 130b are created by growing a doped epi layer over the substrate 110 or the deep well 120. In some embodiments, the epi layer is grown and doped after epitaxial growth. In some embodiments, the epi layer is doped in situ during epitaxial growth.In some embodiments, a doping concentration of the first doped regions 130a and 130b is about 10. 17 Dopants / cm 3 up to 10 18 Dopants / cm 3If the doping concentration is too high, the risk of current leakage increases in some cases. Conversely, if the doping concentration is too low, the risk that undesired interactions with a bipolar transistor (BJT) are not sufficiently suppressed increases in some cases. In some embodiments, a thickness of the first doped regions 130a and 130b is about 1 µm to about 2 µm. If the thickness of the first doped regions 130a and 130b is too small, there is a risk in some cases that undesired BJT interactions are not sufficiently suppressed. Conversely, if the thickness of the first doped regions 130a and 130b is too large, the size of the LDMOS transistor 100 increases in some cases without noticeably improving performance.

[0020] In some embodiments, the first doped region 130a corresponds to the first doped region 130b. In some embodiments, the first doped region 130a differs from the first doped region 130b in doping concentration, thickness, dopant species, and / or another suitable parameter.

[0021] The second doped region 135 is disposed above the deep well 120. The second doped region 135 has a second dopant species that is opposite to the first dopant species. In some embodiments, the second doped region 135 is created by implanting dopants having the second dopant species into the substrate 110. In some embodiments, an annealing process follows the implantation process to more evenly distribute the dopants in the second doped region 135. In some embodiments, the second doped region 135 is created by growing a doped epi layer over the substrate 110 or the deep well 120. In some embodiments, the epi layer is grown and doped after epitaxial growth. In some embodiments, the epi layer is doped in situ during epitaxial growth.In some embodiments, a doping concentration of the second doped region 135 is about 10. 17 Dopants / cm 3 up to 10 18 Dopants / cm 3 . If the doping concentration is too high, the risk of current loss increases in some cases. Conversely, if the doping concentration is too low, the risk that undesired BJT interactions are not sufficiently suppressed increases in some cases. In some embodiments, a thickness of the second doped region 135 is about 1 µm to about 2 µm. If the thickness of the second doped region 135 is too small, there is a risk that undesired BJT interactions are not sufficiently suppressed in some cases. Conversely, if the thickness of the second doped region 135 is too large, the size of the LDMOS transistor 100 increases in some cases without noticeably improving performance.

[0022] In some embodiments, the thickness of the second doped region 135 corresponds to the thickness of the first doped regions 130a and 130b. In some embodiments, the thickness of the second doped region 135 is different from the thickness of the first doped region 130a and / or the first doped region 130b.

[0023] Source regions 140a and 140b are arranged in respective first doped regions 130a and 130b. Source regions 140a and 140b are each a split source region. In some embodiments, source region 140a and / or source region 140b are not split source regions. Source region 140a includes a first dopant type region 142a and a second dopant type region 144a. First dopant type region 144a has the first dopant type, and second dopant type region 144a has the second dopant type. In some embodiments, a thickness of source regions 140a and 140b is about 0.2 µm to about 0.3 µm. If the thickness of source regions 140a and 140b is too large, the risk of current leakage may increase in some cases. Conversely, if the thickness of source regions 140a and 140b is too small, the resistance in source regions 140a and 140b may increase beyond the design specification in some cases.In some embodiments, the source regions 140a and 140b are formed by ion implantation. In some embodiments, an annealing process is performed after the ion implantation. In some embodiments, a doping concentration of the source regions 140a and 140b is approximately 10. 20 Dopants / cm 3 up to 10 21 Dopants / cm 3 If the doping concentration is too high, the risk of current leakage may increase in some cases. Conversely, if the doping concentration is too low, the resistance in source regions 140a and 140b may increase beyond the design specification.

[0024] Silicide layers 145a and 145b are disposed over respective source regions 140a and 140b. Silicide layers 145a and 145b contribute to reducing the resistance between the respective source regions 140a and 140b and a contact structure in an IC device including LDMOS transistor 100. Silicide layers 145a and 145b include silicon and at least one metal. In some embodiments, the at least one metal is titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), and / or a combination thereof (e.g., an alloy of two or more metals). In some embodiments, silicide layers 145a and 145b also include germanium. In some embodiments, the silicide layers 145a and 145b are self-aligned silicide layers (salicide layers).In some embodiments, the silicide layers 145a and 145b are formed by depositing a layer comprising the aforementioned at least one metal and then performing an annealing process. In some embodiments, the layer comprising the at least one metal is deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plating, or another suitable deposition method.

[0025] Gates 150a and 150b are disposed over a top surface of first doped regions 130a and 130b and over a top surface of second doped region 135. In some embodiments, gates 150a and 150b include an electrode layer and a gate dielectric layer between the electrode layer and substrate 110. In some embodiments, gates 150a and 150b further include a work function layer, an interface layer, a diffusion barrier layer, and / or another suitable layer. In some embodiments, the gate dielectric layer is disposed between sidewalls of the electrode layer and the corresponding spacer enclosing gate 150a or gate 150b. In some embodiments, sidewalls of the electrode layer directly contact the corresponding spacer enclosing gate 150a or gate 150b.

[0026] In some embodiments, the electrode layer includes titanium, aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. A metallic fill layer may include, for example, aluminum, tungsten, cobalt, copper, and / or other suitable materials. In some embodiments, the electrode layer is formed by CVD, PVD, plating, and / or other suitable processes. In some embodiments, the gate dielectric layer includes a high-k dielectric material such as HfO 2, HfSiO, HfSiO 4 , HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x , ZrO, ZrO 2 , ZrSiO 2 , AlO, AlSiO, Al 2 O 3 , TiO, TiO 2 , LaO, LaSiO, Ta 2 O 3 , Ta 2 O 5 , Y 2 O 3 , SrTiO 3 , BaZrO, BaTiO 3 (BTO), (Ba,Sr)TiO 3 (BST), Si3 N 4 , a hafnium dioxide-aluminum oxide alloy (HfO 2 -Al 2 O 3 alloy), other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials are generally dielectric materials with a high dielectric constant, for example, higher than that of silicon oxide (k ≈ 3.9). In some embodiments, the gate dielectric layer is formed by chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods. In some embodiments, gate 150a and / or gate 150b are a dummy (non-functional) gate.

[0027] The gates 150a and 150b overlap an interface between the second doped region 135 and a corresponding one of the first doped regions 130a and 130b. In some embodiments, an overlap distance Lg1 of the gate 150b with the first doped region 130b is about 0.1 µm to about 0.5 µm. If the distance Lg1 is too large, in some cases an overall size of the LDMOS transistor 100 increases without a noticeable increase in performance. Conversely, if the distance Lg1 is too small, in some cases the risk of a short circuit between the source 140b and the drain 170 increases. In some embodiments, an overlap distance Lg2 of the gate 150b with the second doped region 135 is about 0.1 µm to about 0.5 µm. If the distance Lg2 is too large, in some cases the overall size of the LDMOS transistor 100 increases without a noticeable increase in performance.If the distance Lg2 is too small, however, the risk of a short circuit between the source 140b and the drain 170 increases in some cases. In some embodiments, the gate 150b is located entirely above the first doped region 130b or the second doped region 135. As explained above, the distances Lg1 and Lg2 for the gate 150b also apply to the gate 150a. In some embodiments, the distances Lg1 and Lg2 for the gate 150a have the same size as the distances Lg1 and Lg2 for the gate 150b. In some embodiments, the distances Lg1 and / or Lg2 for the gate 150a have a different size than the distance Lg1 or Lg2 for the gate 150b.

[0028] The first spacer portion 160a is located between the gate 150a and the source 140a. The first spacer portion 160a provides electrical isolation for the gate 150a. In some embodiments, the first spacer portion 160a includes only one dielectric material. In some embodiments, the first spacer portion 160a includes multiple dielectric layers. For example, in some embodiments, the first spacer portion 160a has a silicon oxide-silicon nitride-silicon oxide (ONO) structure. A top surface of the first spacer portion 160a is substantially coplanar with the top surface of the gate 150a. In some embodiments, the first spacer portion 160a is formed by depositing one or more dielectric material layers and subsequently etching them to define a shape of the first spacer portion 160a.In some embodiments, the one or more dielectric material layers are deposited by CVD, oxidation, or another suitable deposition method. In some embodiments, the etching process is an anisotropic etching process. In some embodiments, the etching process is a wet etching process or a dry etching process.

[0029] The second spacer portion 165a is located between the gate 150a and the drain 170. The second spacer portion 165a provides electrical isolation for the gate 150a. In some embodiments, the second spacer portion 165a includes only one dielectric material. In some embodiments, the second spacer portion 165a includes multiple dielectric layers. For example, in some embodiments, the second spacer portion 165a has an ONO structure. A top surface of the second spacer portion 165a extends above the top surface of the gate 150a. In some embodiments, the second spacer portion 165a is formed by depositing one or more dielectric material layers and subsequently etching them to define a shape of the second spacer portion 165a.In some embodiments, the one or more dielectric material layers are deposited by CVD, oxidation, or another suitable deposition method. In some embodiments, the etching process is an anisotropic etching process. In some embodiments, the etching process is a wet etching process or a dry etching process.

[0030] The second spacer portion 165a includes the lower region 167a and the upper region 169a. A top surface of the lower region 167a is substantially coplanar with the top surface of the gate 150a. In some embodiments, a portion of the lower region 167a farthest from the gate 150a has a substantially planar top surface. In some embodiments, a portion of the lower region 167a closest to the gate 150a has a curved top surface. In some embodiments, a distance L2 of the lower region 167a (which is also the thickness of the gate 150b) from a surface of the first doped region 130a or the second doped region 135a is about 0.1 µm to about 0.3 µm. If the distance L2 is too large, in some cases the size of the LDMOS transistor 100 increases without a noticeable increase in performance.On the other hand, if the distance L2 is too small, in some cases a distance between the silicide layer 155a and a channel under the gate 150a decreases, and the risk of a short circuit increases.

[0031] The upper region 169a extends beyond the top of the gate 150a. In some embodiments, the upper region 169a has a conical profile. In some embodiments, the conical profile is a uniform conical profile. In some embodiments, the conical profile is a curved conical profile. In some embodiments, the upper region 169a approaches a point at a position farthest from the substrate 110. A material of the upper region 169a is the same material as at least a portion of the lower region 167a. In some embodiments where the lower region 167a has multiple dielectric material layers, the upper region 169a includes only a material of a topmost layer of the lower region 167a.In some embodiments where the lower region 167a includes multiple dielectric material layers, the upper region 169a includes a material of the topmost layer as well as a material of at least one underlying layer of the lower region 167a. In some embodiments, a thickness L1 of the upper region 169a above the top surface of the gate 150a is greater than zero to about two-thirds (2 / 3) of L2. If the thickness L1 is too large, in some cases the size of the LDMOS transistor 100 increases without any noticeable improvement in performance.

[0032] The upper region 169a provides greater electrical isolation between the gate 150a and other structures in the LDMOS transistor 100 without requiring the use of separate insulating material outside the second spacer portion 165a. Not requiring the use of separate insulating materials outside the second spacer portion 165a helps reduce manufacturing costs and improve the efficiency of manufacturing the LDMOS transistor 100 compared to other approaches. Additionally, compared to other approaches that do not utilize the upper region 169a (such as approaches that utilize an RPO), the LDMOS transistor 100 may include the silicide layer 155a extending across the entire top surface of the gate 150a to reduce the resistance of the gate 150a.A reduced mass of a structure, such as an RPO, also allows for a greater reduction in the size of gate 150a to support a reduction in the size of LDMOS transistor 100. Furthermore, the ability to reduce the size of gate 150a through the presence of top region 169a helps improve the performance of LDMOS transistor 100 compared to other approaches. For example, the Cgd and Qg of LDMOS transistor 100 are reduced compared to other approaches that do not utilize top region 169a.

[0033] Fig. 1 is a cross-sectional view of LDMOS transistor 100. One of ordinary skill in the art will appreciate that in some embodiments, first spacer portion 160a and second spacer portion 165a are part of a contiguous first spacer that encloses gate 150a. For example, in some embodiments, in a top view, second spacer portion 165a extends along an entire length of gate 150a between gate 150a and drain 170, and first spacer portion 160a extends around a remaining portion of gate 150a. In some embodiments, in a top view, the second spacer portion 165a extends around approximately one half of the gate 150a, i.e., a half closest to the drain 170, while the first spacer portion 160a extends around the other half of the gate 150a, i.e., the half closest to the source 140a.

[0034] The above description for the first spacer portion 160a also applies to the third spacer portion 160b, which is adjacent to the gate 150b. In some embodiments, the first spacer portion 160a has the same dimension, shape, and material as the third spacer portion 160b. In some embodiments, the first spacer portion 160a has a different dimension, shape, and / or material than the third spacer portion 160b.

[0035] The above description for the second spacer portion 165a also applies to the fourth spacer portion 165b, which is adjacent to the gate 150b. In some embodiments, the second spacer portion 165a has the same dimension, shape, and material as the fourth spacer portion 165b. In some embodiments, the second spacer portion 165a has a different dimension, shape, and / or material than the fourth spacer portion 165b.

[0036] The drain region 170 is arranged in the second doped region 135. The drain region 170 has a second dopant type. In some embodiments, a thickness of the drain region 170 is about 0.2 µm to about 0.3 µm. If the thickness of the drain region 170 is too large, the risk of current leakage increases in some cases. Conversely, if the thickness of the drain region 170 is too small, the resistance in the drain region 170 increases beyond the design specification in some cases. In some embodiments, the drain region 170 is created by ion implantation. In some embodiments, an annealing process is performed after the ion implantation. In some embodiments, a doping concentration of the drain region 170 is about 10 20 Dopants / cm 3 up to 10 21 Dopants / cm 3If the doping concentration is too high, the risk of current leakage increases in some cases. Conversely, if the doping concentration is too low, the resistance in the drain region 170 may increase beyond the design specification in some cases.

[0037] In some embodiments, a distance Ld between the drain region 170 and the gate 150b is about 0.2 µm to about 6 µm. If the distance Ld is too small, the risk of a short circuit between the gate 150b and the drain 170 increases in some cases. Conversely, if the distance Ld is too large, an operating speed of the LDMOS transistor 100 decreases in some cases. A size of the distance Ld is determined in part depending on a specified operating voltage of the LDMOS transistor 100. In some embodiments, the specified operating voltage of the LDMOS transistor 100 is about 6 V to about 60 V. If the operating voltage of the LDMOS transistor 100 is too high, the risk of damage to the LDMOS transistor 100 and other components in the IC device increases in some embodiments.However, if the operating voltage of the LDMOS transistor 100 is too low, the risk of insufficient power supply to the components in the IC device increases in some cases. In some embodiments, an electric breakdown field strength for the distance Ld is approximately 0.9 × 10 . 5 V / cm to about 1.1 × 10 5 V / cm, where V is the unit of operating voltage of LDMOS transistor 100. If the breakdown electric field strength of LDMOS transistor 100 is set too high, the speed of LDMOS transistor 100 decreases in some embodiments. Conversely, if the breakdown electric field strength of LDMOS transistor 100 is set too low, the risk of a short circuit between drain 170 and gate 150b increases in some cases.

[0038] The above description for the distance between drain 170 and gate 150b also applies to a distance between drain 170 and gate 150a. In some embodiments, the distance between drain 170 and gate 150b is equal to the distance between drain 170 and gate 150a. In some embodiments, the distance between drain 170 and gate 150b is different from the distance between drain 170 and gate 150a.

[0039] The silicide layer 175 is disposed over the drain region 170. The silicide layer 175 helps reduce the resistance between the drain region 170 and a contact structure in an IC device including the LDMOS transistor 100. The silicide layer 175 includes silicon and at least one metal. In some embodiments, the at least one metal is titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), and / or a combination thereof (e.g., an alloy of two or more metals). In some embodiments, the silicide layer 175 also includes germanium. In some embodiments, the silicide layer 175 is a self-aligned silicide layer (salicide layer). In some embodiments, the silicide layer 175 is formed by depositing a layer including the aforementioned at least one metal and then performing an annealing process.In some embodiments, the layer comprising the at least one metal is deposited by CVD, PVD, ALD, plating, or other suitable deposition method.

[0040] Fig. 2 is a graph 200 of a drain voltage (Vd) versus a gate-drain capacitance (Cgd) according to some embodiments. The graph 200 is based on the LDMOS transistor being designed to have an operating voltage of 6 V. The graph 200 includes a first curve 210 indicating the performance of an LDMOS transistor that does not have a horn, e.g., an LDMOS transistor that has an RPO layer that partially overlaps a gate. The graph 200 also includes a second curve 220 indicating the performance of an LDMOS transistor that has a horn, e.g., the LDMOS transistor 100 ( Fig. 1). Graph 200 shows that the Cgd for the second curve 220 is significantly lower than the Cgd for the first curve 210. As the drain voltage Vd increases to the operating voltage of 6 V, curve 220 indicates a Cgd that is approximately 10% to approximately 40% lower than that of curve 210. This decrease in Cgd for curve 220 indicates that the LDMOS transistor with the horn would have a lower delay when switching between on / off states.

[0041] Fig. 3 is a graph 300 of total gate charge (Qg) versus gate voltage (Vg) according to some embodiments. The graph 300 is based on the LDMOS transistor being designed to have an operating voltage of 6 V. The graph 300 includes a first curve 310 indicating the performance of an LDMOS transistor that does not have a horn, e.g., an LDMOS transistor that has an RPO layer that partially overlaps a gate. The graph 300 also includes a second curve 320 indicating the performance of an LDMOS transistor that has a horn, e.g., the LDMOS transistor 100 ( Fig. 1). Graph 300 shows that the Qg for the second curve 320 is significantly lower than the Qg for the first curve 310. As the gate voltage Vg increases to the operating voltage of 6 V, curve 320 indicates a Qg that is approximately 20% to approximately 30% lower than that of curve 310. This decrease in Qg for curve 320 indicates that the LDMOS transistor with the horn would have a lower delay when switching between on / off states.

[0042] Fig. 4 is a flowchart of a method 400 for manufacturing an LDMOS transistor according to some embodiments. In some embodiments, the method 400 for manufacturing the LDMOS transistor 100 ( Fig. 1). In some embodiments, the method 400 may also be used to fabricate an LDMOS transistor other than the LDMOS transistor 100 of Fig. 1. For the sake of clarity, the method 400 is first described together with the sectional views of the Fig. 5 and 6A to 6E. The discussion of some other LDMOS transistors that can be manufactured using the method 400 is based on the Fig. 7A to 10E after the initial description, which refers to some embodiments based on the Fig. 6A to 6E concentrated.

[0043] The method 400 includes an operation 405 in which wells are implanted into a substrate. In some embodiments, multiple wells with different depths, doping concentrations, or dopant species are implanted into the substrate. In some embodiments, the implantation process is an ion implantation of dopant species. An energy for the implantation process is determined based on a particular depth of the well in the substrate. A doping concentration is set based on a particular power of a corresponding well. A dopant species is set based on a design of the LDMOS transistor. In some embodiments, operation 405 is replaced by an operation comprising epitaxially growing one or more layers over the substrate. The one or more epitaxial layers are doped either in situ or after the epitaxial process to define the wells.

[0044] In an operation 410, a gate is formed over a substrate. In some embodiments, the gate is a dummy gate. In some embodiments, the dummy gate undergoes a later replacement gate process. In some embodiments, the gate is an active gate. In some embodiments where the gate is a dummy gate, forming the gate includes depositing a layer of polysilicon and patterning the layer of polysilicon to define the gate. In some embodiments where the gate is an active gate, forming the gate includes depositing a gate dielectric layer over the substrate and depositing an electrode layer over the gate dielectric layer. The electrode layer and the gate dielectric layer are then patterned to define the gate. In some embodiments, patterning includes a combination of photolithography and etching processes.

[0045] In some embodiments, the gate dielectric layer is deposited by CVD, oxidation, or other suitable methods. In some embodiments, the electrode layer is deposited by CVD, PVD, plating, ALD, or other suitable methods. In some embodiments, the gate dielectric layer includes silicon oxide. In some embodiments, the gate dielectric layer includes a high-k dielectric material. In some embodiments, the electrode layer is a metal layer. In some embodiments, forming the gate includes forming further layers, such as at least one work function layer, an interface layer, a diffusion barrier layer, or another suitable layer.

[0046] Fig. 5 is a cross-sectional view of an LDMOS transistor 500 at an intermediate stage of fabrication according to some embodiments. In some embodiments, fabrication of LDMOS transistor 500 corresponds to fabrication of LDMOS transistor 100 ( Fig. 1) after surgery 410 ( Fig. 4) of method 400. The LDMOS transistor 500 includes the substrate 110, the deep well 120, the first doped regions 130a and 130b, the second doped region 135, and the gates 150a and 150b. In some embodiments, the deep well 120, the first doped regions 130a and 130b, and the second doped region 135 are formed using operation 405 of method 400 ( Fig. 4. In some embodiments, gates 150a and 150b are fabricated using operation 410 of method 400 ( Fig. 4) manufactured.

[0047] Returning to method 400, in an operation 415, a spacer material is deposited over the gate and the substrate. The spacer material includes at least one dielectric material. In some embodiments, the spacer material is deposited over the entire substrate. In some embodiments, the spacer material is deposited over less than the entire substrate. In some embodiments, depositing the spacer material includes performing CVD, oxidation, or other suitable processes.

[0048] In some embodiments, depositing the spacer material comprises depositing a single layer of a dielectric material. In some embodiments, depositing the spacer material comprises depositing multiple layers of a single dielectric material. In some embodiments, depositing the spacer material comprises depositing layers of different dielectric materials. For example, in some embodiments, depositing the spacer material comprises depositing silicon oxide or silicon nitride. In some embodiments, depositing the spacer material comprises depositing a combination of silicon oxide and silicon nitride, e.g., an ONO structure.

[0049] Fig. 6A is a cross-sectional view of an LDMOS transistor 600A at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 600A corresponds to a structure after operation 415 ( Fig. 4). Compared to the LDMOS transistor 500 ( Fig. 5) The LDMOS transistor 600A includes a spacer material 610 over the substrate 110 and the gates 150a and 150b. The spacer material 610 is a single layer of silicon oxide. In some embodiments, a thickness of the spacer material 610 is about 1000 Å to about 2000 Å. If the thickness of the spacer material 610 is too large, in some cases the size of the LDMOS transistor 600A increases without a noticeable improvement in performance. Conversely, if the thickness of the spacer material 610 is too small, in some cases the spacer material 610 does not provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, the spacer material 610 is deposited by CVD, oxidation, or other suitable methods. In some embodiments, the spacer material 610 is a conformal layer.In some embodiments, the spacer material 610 is a non-conformal layer.

[0050] Let us return to Fig. 4. In an operation 420, a photoresist is formed over the spacer material. In some embodiments, the photoresist is formed by spin coating or other suitable methods. In some embodiments, a curing process is performed after the photoresist is formed on the spacer material. In some embodiments, the photoresist is a positive photoresist. In some embodiments, the photoresist is a negative photoresist. In some embodiments, the photoresist is a resin, a polymer, or other suitable material. A maximum thickness of the photoresist is sufficient to cover a top surface of the spacer material. If the maximum thickness of the photoresist is too small, in some cases the photoresist remaining after patterning is insufficient to form a horn structure in the spacer material.In some embodiments, the maximum thickness of the photoresist is less than about 1.5 times a thickness of the gate fabricated in operation 410. If the maximum thickness of the photoresist is too large, in some cases, photoresist material is wasted without any noticeable improvement in performance.

[0051] Fig. 6B is a cross-sectional view of an LDMOS transistor 600B at an intermediate stage of fabrication, according to some embodiments. In some embodiments, the LDMOS transistor 600B corresponds to a structure after operation 420 ( Fig. 4). In contrast to the LDMOS transistor 600A ( Fig. 6A), the LDMOS transistor 600B includes a photoresist 620 over the spacer material 610. In some embodiments, the photoresist 620 is a resin, a polymer, or other suitable material. The photoresist 620 extends over a top surface of the spacer material 610. In some embodiments, a thickness t1 of the photoresist 620 is less than 1.5 times a thickness t2 of the gate 150b (or gate 150a). If the thickness t1 of the photoresist 620 is too large, in some cases, photoresist material is wasted without a noticeable increase in performance. In some embodiments, the thickness t1 of the photoresist 620 is measured at a position between the gates 150a and 150b. In some embodiments, the photoresist 620 is deposited by spin coating or other suitable methods.

[0052] Let us return to Fig. 4. In an operation 425, the photoresist is patterned. The photoresist is patterned using a combination of photolithography and etching. In some embodiments, the etching is a wet etch. In some embodiments, the etching is a dry etch. The photoresist is patterned to remove portions of the photoresist except for a portion of the photoresist along a sidewall of the spacer material closest to the drain region of the LDMOS transistor. In some embodiments, a top surface of the remaining photoresist is substantially coplanar with a top surface of the spacer material. In some embodiments where the LDMOS transistor has multiple gates, the remaining photoresist defines a discontinuous structure where a portion of the spacer material above the drain region does not include the photoresist.

[0053] Fig. 6C is a cross-sectional view of an LDMOS transistor 600C at an intermediate stage of fabrication, according to some embodiments. In some embodiments, the LDMOS transistor 600C corresponds to a structure after operation 425 ( Fig. 4). In contrast to the LDMOS transistor 600B ( Fig. 6B), the LDMOS transistor 600C has a remaining photoresist 620a and 620b over sidewalls of the spacer material 610 closest to a position where a drain region, e.g., the drain region 170 ( Fig. 1), is generated in the second doped region 135. Other parts of the photoresist 620 ( Fig. 6B) except for the remaining photoresist 620a and 620b are removed using a combination of photolithography and etching. The remaining photoresist 620a and 620b defines a discontinuous structure with an opening between the remaining photoresist 620a and the remaining photoresist 620b, in which the underlying spacer material 610 is exposed. In some embodiments, a top surface of the remaining photoresist 620a and 620b is substantially coplanar with a top surface of the spacer material 610.

[0054] Let us return to Fig. 4. In an operation 430, the spacer material is patterned using the patterned photoresist as a mask. An etchant used to etch the spacer material is based on a material of the spacer material. In some embodiments, the etch is a wet etch. In some embodiments, the etch is a dry etch. In some embodiments, the etchant is hydrofluoric acid (HF acid), a sulfur peroxide mixture (SPM), an ammonium peroxide mixture (APM), and / or another suitable etchant. Because the patterned photoresist protects a sidewall of the spacer material closest to a drain region of the LDMOS transistor, less spacer material closest to the drain region is removed during the etching process. As a result, the spacer material forms a horn structure on a side of the gate closest to the drain region.In some embodiments, the thickness of the horn structure is greater than zero to about two-thirds of the thickness of the gate structure. If the thickness of the horn structure is too large, in some cases the horn structure may hinder the formation of contact structures and impair the performance of the LDMOS transistor.

[0055] Fig. 6D is a cross-sectional view of an LDMOS transistor 600D at an intermediate stage of fabrication, according to some embodiments. In some embodiments, the LDMOS transistor 600D corresponds to a structure after operation 430 ( Fig. 4). In contrast to the LDMOS transistor 600C ( Fig. 6C), the LDMOS transistor 600D has a horn structure in the spacer material 610 that is closest to a position where a drain region, e.g., the drain region 170 ( Fig. 1), is generated in the second doped region 135. The etching process removes portions of the spacer material 610 ( Fig. 6C) to define a first spacer portion 635a, a second spacer portion 630a, a third spacer portion 635b, and a fourth spacer portion 630b. The second spacer portion 630a and the fourth spacer portion 630b include horn structures. The first spacer portion 635a and the third spacer portion 635b do not include horn structures. A thickness L2 of the gate 150b is about 0.1 µm to about 0.3 µm. If the thickness L2 is too large, in some cases the size of the LDMOS transistor 600D increases without noticeably improving performance. Conversely, if the thickness L2 is too small, in some cases a distance between a silicide layer, e.g., the silicide layer 155a ( Fig. 1), and a channel under the gate 150b, increasing the risk of a short circuit. In some embodiments, the thickness of the horn structure is greater than zero to about 2 / 3 of the thickness of the gate structure. If the thickness of the horn structure is too large, in some cases the horn structure hinders the formation of contact structures and impairs the performance of the LDMOS transistor.

[0056] Let us return to Fig. 4. In an operation 435, source / drain (S / D) regions are created. In some embodiments, the S / D regions are created by removing portions of an underlying substrate to define recesses; and growing S / D regions in the recesses. In some embodiments, the S / D regions are created in the recesses by epitaxy. In some embodiments, the S / D regions are doped after growth. In some embodiments, the S / D regions are doped in situ during their growth. In some embodiments, an annealing process is performed after doping or ion implantation.

[0057] In an operation 440, silicide structures are formed on the S / D regions and the gates. The silicide structures are formed by depositing a metal layer over the S / D regions and the gates; and then annealing the LDMOS transistor to induce a reaction to form the silicide. In some embodiments where the electrode layer of the gates includes a metal, a layer of silicon is deposited over the gates to provide silicon to react with the metal layer to form the silicide. The silicide structures over the gates formed in operation 440 extend an entire length of the gates. This helps reduce the resistance between the gates and a contact structure to improve device performance and reduce power consumption.In some embodiments, the metal layer includes titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), and / or a combination thereof (e.g., an alloy of two or more metals). In some embodiments, the silicide structures also include germanium. In some embodiments, the silicide structures are self-aligned silicide (salicide) layers. In some embodiments, the metal layer is deposited by CVD, PVD, ALD, plating, or another suitable deposition technique.

[0058] In an operation 445, an interlayer dielectric (ILD) is deposited over the substrate. The ILD covers the gates as well as the spacer material comprising the horn structure. In some embodiments, a top surface of the ILD is located above a top surface of the horn structure. In some embodiments, the top surface of the ILD is substantially coplanar with the top surface of the horn structure. In some embodiments, the ILD includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. In some embodiments, the ILD is deposited by CVD, ALD, or other suitable deposition techniques. In some embodiments, a CMP (chemical mechanical polishing) process is performed after the ILD is deposited.

[0059] In an operation 450, contact structures for electrically connecting to the S / D regions are formed. The contact structures are conductive elements that extend through the ILD. The contact structures are deposited on silicide layers of corresponding S / D regions to establish electrical connection with the corresponding S / D regions. The contact structures are formed by etching the ILD to define openings therein; and then depositing a conductive material in the openings. In some embodiments, etching the ILD comprises a combination of photolithography and etching processes. In some embodiments, the etching is a wet etch, and in some embodiments, the etching is a dry etch. In some embodiments, the conductive material is deposited in the openings by CVD, PVD, ALD, plating, or other suitable deposition techniques.In some embodiments, additional layers, such as barrier layers, are deposited in the opening between the conductive material and the ILD. In some embodiments, a CMP process is performed after forming the contact structures.

[0060] Fig. 6E is a cross-sectional view of an LDMOS transistor 600E at an intermediate stage of fabrication, according to some embodiments. In some embodiments, the LDMOS transistor 600E corresponds to a structure after operation 450 ( Fig. 4). In contrast to the LDMOS transistor 600D ( Fig. 6D), the LDMOS transistor 600E comprises S / D regions, silicide layers, an ILD, and contact structures. For clarity of the drawings, the split source regions 140a and 140b are shown in Fig. 6B not designated.

[0061] The source region 140a is arranged in the first doped region 130a. The source region 140b is arranged in the first doped region 130b. The silicide layer 145b is arranged over the source region 140b. The drain region 170 is arranged in the second doped region 135. The silicide layer 175 is arranged over the drain region 170. Details of these structural elements are described above for the LDMOS transistor 100 ( Fig. 1) has been described.

[0062] An ILD 640 is disposed over the gates 150a and 150b and over the spacer structures surrounding the gates 150a and 150b. The ILD 640 has a top surface above a highest point of the horn structure in the second spacer portion 630a and the fourth spacer portion 630b. In some embodiments, the top surface of the ILD 640 is substantially coplanar with the highest point of the horn structure in the second spacer portion 630a and the fourth spacer portion 630b. In some embodiments, the ILD 640 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0063] A first source contact 650a extends through the ILD 640 for electrically connecting to the silicide layer 145a to establish an electrical connection with the source region 140a. A second source contact 650b extends through the ILD 640 for electrically connecting to the silicide layer 145b to establish an electrical connection with the source region 140b. A drain contact 660 extends through the ILD 640 for electrically connecting to the silicide layer 175 to establish an electrical connection with the drain region 170. For brevity, the first source contact 650a, the second source contact 650b, and the drain contact 660 are collectively referred to as contacts in some cases.

[0064] Each of the contacts has sidewalls that are substantially perpendicular to the top surface of the substrate 110. In some embodiments, at least one of the contacts has a conical profile. In some embodiments, the contacts independently include copper, aluminum, tungsten, cobalt, alloys thereof, and / or other suitable conductive materials. In some embodiments, the contacts each include the same conductive material. In some embodiments, at least one contact includes a different conductive material than at least one other contact. In some embodiments, at least one of the contacts further includes a barrier layer to help prevent diffusion of the conductive material into the ILD 640.

[0065] Let us return to Fig. 4. One of ordinary skill in the art will recognize that modifications to method 400 are within the scope of the present disclosure. In some embodiments, method 400 includes at least one further operation. For example, in some embodiments, method 400 further includes epitaxially growing a semiconductor material over the substrate to implant wells into the epitaxial layer. In some embodiments, at least one operation of method 400 is omitted. For example, in some embodiments, operations 435 and 440, in which the gates are dummy gates and are intended to remain dummy gates in a final product, are omitted. For example, in some embodiments, operation 435 is performed before operation 415.

[0066] Fig. 7A is a cross-sectional view of an LDMOS transistor 700A at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 700A corresponds to a structure after operation 415 ( Fig. 4). In contrast to the LDMOS transistor 500 ( Fig. 5) The LDMOS transistor 700A includes a spacer material 710 over the substrate 110 and the gates 150a and 150b. The spacer material 710 has an ONO structure. The spacer material 710 includes a first silicon oxide layer 712, a silicon nitride layer 714 over the first silicon oxide layer 712, and a second silicon oxide layer 716 over the silicon nitride layer 714. In some embodiments, a total thickness of the spacer material 710 is about 700 Å to about 2800 Å. If the thickness of the spacer material 710 is too large, in some cases the size of the LDMOS transistor 700A increases without a noticeable increase in performance. On the other hand, if the thickness of the spacer material 710 is too small, the spacer material 710 may not provide sufficient electrical insulation for the gates 150a and 150b in some cases.In some embodiments, a thickness of the first silicon oxide layer 712 is about 100 Å to about 300 Å. If the thickness of the first silicon oxide layer 712 is too large, in some cases the size of the LDMOS transistor 700A increases without a noticeable increase in performance. Conversely, if the thickness of the first silicon oxide layer 712 is too small, in some cases the spacer material 710 does not provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, a thickness of the silicon nitride layer 714 is about 200 Å to about 500 Å. If the thickness of the silicon nitride layer 714 is too large, in some cases the size of the LDMOS transistor 700A increases without a noticeable increase in performance. On the other hand, if the thickness of the silicon nitride layer 714 is too small, the spacer material 710 may not provide sufficient electrical insulation for the gates 150a and 150b in some cases.In some embodiments, a thickness of the second silicon oxide layer 716 is about 500 Å to about 2000 Å. If the thickness of the second silicon oxide layer 716 is too large, in some cases the size of the LDMOS transistor 700A increases without a noticeable increase in performance. Conversely, if the thickness of the second silicon oxide layer 716 is too small, in some cases the spacer material 710 does not provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, the spacer material 710 is deposited by CVD, oxidation, or other suitable methods. In some embodiments, the spacer material 710 includes conformal layers. In some embodiments, the spacer material 710 includes non-conformal layers.

[0067] Fig. 7B is a cross-sectional view of an LDMOS transistor 700B at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 700B corresponds to a structure after operation 420 ( Fig. 4). In contrast to the LDMOS transistor 700A ( Fig. 7A), the LDMOS transistor 700B includes a photoresist 720 over the spacer material 710. In some embodiments, the photoresist 720 is a resin, a polymer, or other suitable material. The photoresist 720 extends over a top surface of the spacer material 710. In some embodiments, a thickness t1 of the photoresist 720 is less than 1.5 times a thickness t2 of the gate 150b (or gate 150a). If the thickness t1 of the photoresist 720 is too large, in some cases, photoresist material is wasted without a noticeable increase in performance. In some embodiments, the thickness t1 of the photoresist 720 is measured at a position between the gates 150a and 150b. In some embodiments, the photoresist 720 is deposited by spin coating or other suitable methods.

[0068] Fig. 7C is a cross-sectional view of an LDMOS transistor 700C at an intermediate stage of fabrication, according to some embodiments. In some embodiments, the LDMOS transistor 700C corresponds to a structure after operation 425 ( Fig. 4). In contrast to the LDMOS transistor 700B ( Fig. 7B), the LDMOS transistor 700C has a remaining photoresist 720a and 720b over sidewalls of the spacer material 710 closest to a position where a drain region, e.g., the drain region 170 ( Fig. 1), is generated in the second doped region 135. Other parts of the photoresist 720 ( Fig. 7B) except for the remaining photoresist 720a and 720b are removed using a combination of photolithography and etching. The remaining photoresist 720a and 720b defines a discontinuous structure with an opening between the remaining photoresist 720a and the remaining photoresist 720b, in which the underlying spacer material 710 is exposed. In some embodiments, a top surface of the remaining photoresist 720a and 720b is substantially coplanar with a top surface of the spacer material 710.

[0069] Fig. 7D is a cross-sectional view of an LDMOS transistor 700D at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 700D corresponds to a structure after operation 430 ( Fig. 4). In contrast to the LDMOS transistor 700C ( Fig. 7C), the LDMOS transistor 700D has a horn structure in the spacer material 710 that is closest to a position where a drain region, e.g., the drain region 170 ( Fig. 1), is generated in the second doped region 135. The etching process removes portions of the spacer material 710 ( Fig. 7C) to define a first spacer portion 735a, a second spacer portion 730a, a third spacer portion 735b, and a fourth spacer portion 730b. The second spacer portion 730a and the fourth spacer portion 730b include horn structures. The first spacer portion 735a and the third spacer portion 735b do not include horn structures. A thickness L2 of the gate 150b is about 0.1 µm to about 0.3 µm. If the thickness L2 is too large, in some cases the size of the LDMOS transistor 700D increases without noticeably improving performance. Conversely, if the thickness L2 is too small, in some cases a distance between a silicide layer, e.g., the silicide layer 155a ( Fig. 1), and a channel under the gate 150b, thus increasing the risk of a short circuit. In some embodiments, a thickness of the horn structure is more than zero to about 2 / 3 of a thickness of the gate structure. If the thickness of the horn structure is too large, in some cases the horn structure hinders the formation of contact structures and impairs the performance of the LDMOS transistor. The LDMOS transistor 700D has a horn structure that includes only the second silicon oxide layer 716. In some embodiments, the horn structure further includes a portion of the silicon nitride layer 714 and / or a portion of the first silicon oxide layer 712.

[0070] Fig. 7E is a cross-sectional view of an LDMOS transistor 700E at an intermediate stage of fabrication, according to some embodiments. In some embodiments, the LDMOS transistor 700E corresponds to a structure after operation 450 ( Fig. 4). In contrast to the LDMOS transistor 700D ( Fig. 7D), the LDMOS transistor 700E comprises S / D regions, silicide layers, an ILD, and contact structures. For clarity of the drawings, the split source regions 140a and 140b are shown in Fig. 7E. For the sake of brevity, details of the S / D regions and the silicide layers are not described with reference to Fig. 7E discussed.

[0071] An ILD 740 is disposed over the gates 150a and 150b and over the spacer structures surrounding the gates 150a and 150b. The ILD 740 has a top surface above a highest point of the horn structure in the second spacer portion 730a and the fourth spacer portion 730b. In some embodiments, the top surface of the ILD 740 is substantially coplanar with the highest point of the horn structure in the second spacer portion 730a and the fourth spacer portion 730b. In some embodiments, the ILD 740 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0072] A first source contact 750a extends through the ILD 740 for electrically connecting to the silicide layer 145a to establish an electrical connection with the source region 140a. A second source contact 750b extends through the ILD 740 for electrically connecting to the silicide layer 145b to establish an electrical connection with the source region 140b. A drain contact 760 extends through the ILD 740 for electrically connecting to the silicide layer 175 to establish an electrical connection with the drain region 170. For brevity, the first source contact 750a, the second source contact 750b, and the drain contact 760 are collectively referred to as contacts in some cases.

[0073] Each of the contacts has sidewalls that are substantially perpendicular to the top surface of the substrate 110. In some embodiments, at least one of the contacts has a conical profile. In some embodiments, the contacts independently include copper, aluminum, tungsten, cobalt, alloys thereof, and / or other suitable conductive materials. In some embodiments, the contacts each include the same conductive material. In some embodiments, at least one contact includes a different conductive material than at least one other contact. In some embodiments, at least one of the contacts further includes a barrier layer to help prevent diffusion of the conductive material into the ILD 740.

[0074] Fig. 8A is a cross-sectional view of an LDMOS transistor 800A at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 800A corresponds to a structure after operation 415 ( Fig. 4). In contrast to the LDMOS transistor 500 ( Fig. 5) The LDMOS transistor 800A includes a spacer material 810 over the substrate 110 and the gates 150a and 150b. The spacer material 810 includes a single layer of silicon nitride. In some embodiments, a thickness of the spacer material 810 is about 1000 Å to about 2000 Å. If the thickness of the spacer material 810 is too large, in some cases the size of the LDMOS transistor 800A increases without a noticeable increase in performance. Conversely, if the thickness of the spacer material 810 is too small, in some cases the spacer material 810 does not provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, the spacer material 810 is deposited by CVD, oxidation, or other suitable methods. In some embodiments, the spacer material 810 is a conformal layer.In some embodiments, the spacer material 810 is a non-conformal layer.

[0075] Fig. 8B is a cross-sectional view of an LDMOS transistor 800B at an intermediate stage of fabrication, according to some embodiments. In some embodiments, the LDMOS transistor 800B corresponds to a structure after operation 420 ( Fig. 4). In contrast to the LDMOS transistor 800A ( Fig. 8A), the LDMOS transistor 800B includes a photoresist 820 over the spacer material 810. In some embodiments, the photoresist 820 is a resin, a polymer, or other suitable material. The photoresist 820 extends over a top surface of the spacer material 810. In some embodiments, a thickness t1 of the photoresist 820 is less than 1.5 times a thickness t2 of the gate 150b (or gate 150a). If the thickness t1 of the photoresist 820 is too large, in some cases, photoresist material is wasted without a noticeable increase in performance. In some embodiments, the thickness t1 of the photoresist 820 is measured at a position between the gates 150a and 150b. In some embodiments, the photoresist 820 is deposited by spin coating or other suitable methods.

[0076] Fig. 8C is a cross-sectional view of an LDMOS transistor 800C at an intermediate stage of fabrication, according to some embodiments. In some embodiments, the LDMOS transistor 800C corresponds to a structure after operation 425 ( Fig. 4). In contrast to the LDMOS transistor 800B ( Fig. 8B), the LDMOS transistor 800C has a remaining photoresist 820a and 820b over sidewalls of the spacer material 810 closest to a position where a drain region, e.g., the drain region 170 ( Fig. 1), is generated in the second doped region 135. Other parts of the photoresist 820 ( Fig. 8B) except for the remaining photoresist 820a and 820b are removed using a combination of photolithography and etching. The remaining photoresist 820a and 820b defines a discontinuous structure with an opening between the remaining photoresist 820a and the remaining photoresist 820b, in which the underlying spacer material 810 is exposed. In some embodiments, a top surface of the remaining photoresist 820a and 820b is substantially coplanar with a top surface of the spacer material 810.

[0077] Fig. 8D is a cross-sectional view of an LDMOS transistor 800D at an intermediate stage of fabrication, according to some embodiments. In some embodiments, the LDMOS transistor 800D corresponds to a structure after operation 430 ( Fig. 4). In contrast to the LDMOS transistor 800C ( Fig. 8C), the LDMOS transistor 800D has a horn structure in the spacer material 810 that is closest to a position where a drain region, e.g., the drain region 170 ( Fig. 1), is generated in the second doped region 135. The etching process removes portions of the spacer material 810 ( Fig. 8C) to define a first spacer portion 835a, a second spacer portion 830a, a third spacer portion 835b, and a fourth spacer portion 830b. The second spacer portion 830a and the fourth spacer portion 830b include horn structures. The first spacer portion 835a and the third spacer portion 835b do not include horn structures. A thickness L2 of the gate 150b is about 0.1 µm to about 0.3 µm. If the thickness L2 is too large, in some cases the size of the LDMOS transistor 800D increases without a noticeable increase in performance. Conversely, if the thickness L2 is too small, in some cases a distance between a silicide layer, e.g., the silicide layer 155a ( Fig. 1), and a channel under the gate 150b, increasing the risk of a short circuit. In some embodiments, the thickness of the horn structure is greater than zero to about 2 / 3 of the thickness of the gate structure. If the thickness of the horn structure is too large, in some cases the horn structure hinders the formation of contact structures and impairs the performance of the LDMOS transistor.

[0078] Fig. 8E is a cross-sectional view of an LDMOS transistor 800E at an intermediate stage of fabrication, according to some embodiments. In some embodiments, the LDMOS transistor 800E corresponds to a structure after operation 450 ( Fig. 4). In contrast to the LDMOS transistor 800D ( Fig. 8D), the LDMOS transistor 800E comprises S / D regions, silicide layers, an ILD, and contact structures. For clarity of the drawings, the split source regions 140a and 140b are shown in Fig. 8E. For the sake of brevity, details of the S / D regions and silicide layers are not described with reference to Fig. 8E discussed.

[0079] An ILD 840 is disposed over the gates 150a and 150b and over the spacer structures surrounding the gates 150a and 150b. The ILD 840 has a top surface above a highest point of the horn structure in the second spacer portion 830a and the fourth spacer portion 830b. In some embodiments, the top surface of the ILD 840 is substantially coplanar with the highest point of the horn structure in the second spacer portion 830a and the fourth spacer portion 830b. In some embodiments, the ILD 840 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0080] A first source contact 850a extends through the ILD 840 for electrically connecting to the silicide layer 145a to establish an electrical connection with the source region 140a. A second source contact 850b extends through the ILD 840 for electrically connecting to the silicide layer 145b to establish an electrical connection with the source region 140b. A drain contact 860 extends through the ILD 840 for electrically connecting to the silicide layer 175 to establish an electrical connection with the drain region 170. For brevity, the first source contact 850a, the second source contact 850b, and the drain contact 860 are collectively referred to as contacts in some cases.

[0081] Each of the contacts has sidewalls that are substantially perpendicular to the top surface of the substrate 110. In some embodiments, at least one of the contacts has a conical profile. In some embodiments, the contacts independently include copper, aluminum, tungsten, cobalt, alloys thereof, and / or other suitable conductive materials. In some embodiments, the contacts each include the same conductive material. In some embodiments, at least one contact includes a different conductive material than at least one other contact. In some embodiments, at least one of the contacts further includes a barrier layer to help prevent diffusion of the conductive material into the ILD 840.

[0082] Fig. 9A is a cross-sectional view of an LDMOS transistor 900A at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 900A corresponds to a structure after operation 415 ( Fig. 4). In contrast to the LDMOS transistor 500 ( Fig. 5) The LDMOS transistor 900A includes a spacer material 910 over the substrate 110 and the gates 150a and 150b. The spacer material 910 includes a silicon oxide layer 912 and a silicon nitride layer 914 over the silicon oxide layer 912. In some embodiments, a total thickness of the spacer material 910 is about 1000 Å to about 2000 Å. If the thickness of the spacer material 910 is too large, in some cases the size of the LDMOS transistor 900A increases without a noticeable increase in performance. Conversely, if the thickness of the spacer material 910 is too small, in some cases the spacer material 910 does not provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, a thickness of the silicon oxide layer 912 is about 500 Å to about 1000 Å.If the thickness of the silicon oxide layer 912 is too large, in some cases the size of the LDMOS transistor 900A increases without a noticeable increase in performance. Conversely, if the thickness of the silicon oxide layer 912 is too small, in some cases the spacer material 910 does not provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, a thickness of the silicon nitride layer 914 is also about 500 Å to about 1000 Å. If the thickness of the silicon nitride layer 914 is too large, in some cases the size of the LDMOS transistor 900A increases without a noticeable increase in performance. Conversely, if the thickness of the silicon nitride layer 914 is too small, in some cases the spacer material 910 does not provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, the spacer material 910 is deposited by CVD, oxidation, or other suitable methods.In some embodiments, the spacer material 910 includes conformal layers. In some embodiments, the spacer material 910 includes non-conformal layers.

[0083] Fig. 9B is a cross-sectional view of an LDMOS transistor 900B at an intermediate stage of fabrication, according to some embodiments. In some embodiments, the LDMOS transistor 900B corresponds to a structure after operation 420 ( Fig. 4). In contrast to the LDMOS transistor 900A ( Fig. 9A), the LDMOS transistor 900B includes a photoresist 920 over the spacer material 910. In some embodiments, the photoresist 920 is a resin, a polymer, or other suitable material. The photoresist 920 extends over a top surface of the spacer material 910. In some embodiments, a thickness t1 of the photoresist 920 is less than 1.5 times a thickness t2 of the gate 150b (or gate 150a). If the thickness t1 of the photoresist 920 is too large, in some cases, photoresist material is wasted without a noticeable increase in performance. In some embodiments, the thickness t1 of the photoresist 920 is measured at a position between the gates 150a and 150b. In some embodiments, the photoresist 920 is deposited by spin coating or other suitable methods.

[0084] Fig. 9C is a cross-sectional view of an LDMOS transistor 900C at an intermediate stage of fabrication, according to some embodiments. In some embodiments, the LDMOS transistor 900C corresponds to a structure after operation 425 ( Fig. 4). In contrast to the LDMOS transistor 900B ( Fig. 9B), the LDMOS transistor 900C has a remaining photoresist 920a and 920b over sidewalls of the spacer material 910 closest to a position where a drain region, e.g., the drain region 170 ( Fig. 1), is generated in the second doped region 135. Other parts of the photoresist 920 ( Fig. 9B) except for the remaining photoresist 920a and 920b are removed using a combination of photolithography and etching. The remaining photoresist 920a and 920b defines a discontinuous structure with an opening between the remaining photoresist 920a and the remaining photoresist 920b, in which the underlying spacer material 910 is exposed. In some embodiments, a top surface of the remaining photoresist 920a and 920b is substantially coplanar with a top surface of the spacer material 910.

[0085] Fig. 9D is a cross-sectional view of an LDMOS transistor 900D at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 900D corresponds to a structure after operation 430 ( Fig. 4). In contrast to the LDMOS transistor 900C ( Fig. 9C), the LDMOS transistor 900D has a horn structure in the spacer material 910 that is closest to a position where a drain region, e.g., the drain region 170 ( Fig. 1), is generated in the second doped region 135. The etching process removes portions of the spacer material 910 ( Fig. 9C) to define a first spacer portion 935a, a second spacer portion 930a, a third spacer portion 935b, and a fourth spacer portion 930b. The second spacer portion 930a and the fourth spacer portion 930b include horn structures. The first spacer portion 935a and the third spacer portion 935b do not include horn structures. A thickness L2 of the gate 150b is about 0.1 µm to about 0.3 µm. If the thickness L2 is too large, in some cases the size of the LDMOS transistor 900D increases without a noticeable increase in performance. Conversely, if the thickness L2 is too small, in some cases a distance between a silicide layer, e.g., the silicide layer 155a ( Fig. 1), and a channel under the gate 150b, thus increasing the risk of a short circuit. In some embodiments, a thickness L1 of the horn structure is more than zero to about 2 / 3 of a thickness of the gate structure. If the thickness L1 of the horn structure is too large, in some cases the horn structure hinders the formation of contact structures and impairs the performance of the LDMOS transistor. The LDMOS transistor 900D has a horn structure that includes both the silicon oxide layer 912 and the silicon nitride layer 914. In some embodiments, the horn structure includes only a portion of the silicon nitride layer 914. In some embodiments, a thickness L3 of the silicon oxide layer 912 in the horn structure is more than 0 to about 1 / 2 of L1. If the thickness L3 is too large, in some cases the horn structure hinders the formation of contact structures and impairs the performance of the LDMOS transistor.

[0086] Fig. 9E is a cross-sectional view of an LDMOS transistor 900E at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 900E corresponds to a structure after operation 450 ( Fig. 4). In contrast to the LDMOS transistor 900D ( Fig. 9D), the LDMOS transistor 900E comprises S / D regions, silicide layers, an ILD, and contact structures. For clarity of the drawings, the split source regions 140a and 140b are shown in Fig. 9E. For the sake of brevity, details of the S / D regions and silicide layers are not described with reference to Fig. 9E discussed.

[0087] An ILD 940 is disposed over the gates 150a and 150b and over the spacer structures surrounding the gates 150a and 150b. The ILD 940 has a top surface above a highest point of the horn structure in the second spacer portion 930a and the fourth spacer portion 930b. In some embodiments, the top surface of the ILD 940 is substantially coplanar with the highest point of the horn structure in the second spacer portion 930a and the fourth spacer portion 930b. In some embodiments, the ILD 940 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0088] A first source contact 950a extends through the ILD 940 for electrically connecting to the silicide layer 145a to establish an electrical connection with the source region 140a. A second source contact 950b extends through the ILD 940 for electrically connecting to the silicide layer 145b to establish an electrical connection with the source region 140b. A drain contact 960 extends through the ILD 940 for electrically connecting to the silicide layer 175 to establish an electrical connection with the drain region 170. For brevity, the first source contact 950a, the second source contact 950b, and the drain contact 960 are collectively referred to as contacts in some cases.

[0089] Each of the contacts has sidewalls that are substantially perpendicular to the top surface of the substrate 110. In some embodiments, at least one of the contacts has a conical profile. In some embodiments, the contacts independently include copper, aluminum, tungsten, cobalt, alloys thereof, and / or other suitable conductive materials. In some embodiments, the contacts each include the same conductive material. In some embodiments, at least one contact includes a different conductive material than at least one other contact. In some embodiments, at least one of the contacts further includes a barrier layer to help prevent diffusion of the conductive material into the ILD 940.

[0090] Fig. 10A is a cross-sectional view of an LDMOS transistor 1000A at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 1000A corresponds to a structure after operation 415 ( Fig. 4). In contrast to the LDMOS transistor 500 ( Fig. 5) The LDMOS transistor 1000A includes a spacer material 1010 over the substrate 110 and the gates 150a and 150b. The spacer material 1010 has a multilayer structure. The spacer material 1010 includes a silicon nitride layer 1012 and a silicon oxide layer 1014 over the silicon nitride layer 1012. In some embodiments, a total thickness of the spacer material 1010 is about 1000 Å to about 2000 Å. If the thickness of the spacer material 1010 is too large, in some cases the size of the LDMOS transistor 1000A increases without a noticeable increase in performance. Conversely, if the thickness of the spacer material 1010 is too small, the spacer material 1010 may not provide sufficient electrical insulation for the gates 150a and 150b in some cases. In some embodiments, a thickness of the silicon nitride layer 1012 is about 500 Å to about 1000 Å.If the thickness of the silicon nitride layer 1012 is too large, in some cases the size of the LDMOS transistor 1000A increases without a noticeable increase in performance. Conversely, if the thickness of the silicon nitride layer 1012 is too small, in some cases the spacer material 1010 does not provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, a thickness of the silicon oxide layer 1014 is also about 500 Å to about 1000 Å. If the thickness of the silicon oxide layer 1014 is too large, in some cases the size of the LDMOS transistor 1000A increases without a noticeable increase in performance. Conversely, if the thickness of the silicon oxide layer 1014 is too small, in some cases the spacer material 1010 does not provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, the spacer material 1010 is deposited by CVD, oxidation, or other suitable methods.In some embodiments, the spacer material 1010 comprises conformal layers, and in some embodiments, the spacer material 1010 comprises non-conformal layers.

[0091] Fig. 10B is a cross-sectional view of an LDMOS transistor 1000B at an intermediate stage of fabrication, according to some embodiments. In some embodiments, the LDMOS transistor 1000B corresponds to a structure after operation 420 ( Fig. 4). In contrast to the LDMOS transistor 1000A ( Fig. 10A), the LDMOS transistor 1000B includes a photoresist 1020 over the spacer material 1010. In some embodiments, the photoresist 1020 is a resin, a polymer, or other suitable material. The photoresist 1020 extends over a top surface of the spacer material 1010. In some embodiments, a thickness t1 of the photoresist 1020 is less than 1.5 times a thickness t2 of the gate 150b (or gate 150a). If the thickness t1 of the photoresist 1020 is too large, in some cases, photoresist material is wasted without a noticeable increase in performance. In some embodiments, the thickness t1 of the photoresist 1020 is measured at a position between the gates 150a and 150b. In some embodiments, the photoresist 1020 is deposited by spin coating or other suitable methods.

[0092] Fig. 10C is a cross-sectional view of an LDMOS transistor 1000C at an intermediate stage of fabrication, according to some embodiments. In some embodiments, the LDMOS transistor 1000C corresponds to a structure after operation 425 ( Fig. 4). In contrast to the LDMOS transistor 1000B ( Fig. 10B), the LDMOS transistor 1000C has a remaining photoresist 1020a and 1020b over sidewalls of the spacer material 1010 closest to a position where a drain region, e.g., the drain region 170 ( Fig. 1), is generated in the second doped region 135. Other parts of the photoresist 1020 ( Fig. 10B) except for the remaining photoresist 1020a and 1020b are removed using a combination of photolithography and etching. The remaining photoresist 1020a and 1020b defines a discontinuous structure with an opening between the remaining photoresist 1020a and the remaining photoresist 1020b, in which the underlying spacer material 1010 is exposed. In some embodiments, a top surface of the remaining photoresist 1020a and 1020b is substantially coplanar with a top surface of the spacer material 1010.

[0093] Fig. 10D is a cross-sectional view of an LDMOS transistor 1000D at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 1000D corresponds to a structure after operation 430 ( Fig. 4). In contrast to the LDMOS transistor 1000C ( Fig. 10C), the LDMOS transistor 1000D has a horn structure in the spacer material 1010 that is closest to a position where a drain region, e.g., the drain region 170 ( Fig. 1), is generated in the second doped region 135. The etching process removes portions of the spacer material 1010 ( Fig. 10C) to define a first spacer portion 1035a, a second spacer portion 1030a, a third spacer portion 1035b, and a fourth spacer portion 1030b. The second spacer portion 1030a and the fourth spacer portion 1030b include horn structures. The first spacer portion 1035a and the third spacer portion 1035b do not include horn structures. A thickness L2 of the gate 150b is about 0.1 µm to about 0.3 µm. If the thickness L2 is too large, in some cases the size of the LDMOS transistor 1000D increases without a noticeable increase in performance. Conversely, if the thickness L2 is too small, in some cases a distance between a silicide layer, e.g., the silicide layer 155a ( Fig. 1), and a channel under the gate 150b, thus increasing the risk of a short circuit. In some embodiments, a thickness L1 of the horn structure is more than zero to about 2 / 3 of a thickness of the gate structure. If the thickness L1 of the horn structure is too large, in some cases the horn structure hinders the formation of contact structures and impairs the performance of the LDMOS transistor. The LDMOS transistor 1000D has a horn structure including only the silicon oxide layer 1014. In some embodiments, the horn structure of the LDMOS transistor 100D includes both the silicon nitride layer 1012 and the silicon oxide layer 1014.

[0094] Fig. 10E is a cross-sectional view of an LDMOS transistor 1000E at an intermediate stage of fabrication, according to some embodiments. In some embodiments, the LDMOS transistor 1000E corresponds to a structure after operation 450 ( Fig. 4). In contrast to the LDMOS transistor 1000D ( Fig. 10D), the LDMOS transistor 1000E comprises S / D regions, silicide layers, an ILD, and contact structures. For clarity of the drawings, the split source regions 140a and 140b are shown in Fig. 10E. For the sake of brevity, details of the S / D regions and silicide layers are not described with reference to Fig. 10E discussed.

[0095] An ILD 1040 is disposed over the gates 150a and 150b and over the spacer structures surrounding the gates 150a and 150b. The ILD 1040 has a top surface above a highest point of the horn structure in the second spacer portion 1030a and the fourth spacer portion 1030b. In some embodiments, the top surface of the ILD 1040 is substantially coplanar with the highest point of the horn structure in the second spacer portion 1030a and the fourth spacer portion 1030b. In some embodiments, the ILD 1040 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0096] A first source contact 1050a extends through the ILD 1040 for electrical connection with the silicide layer 145a to establish an electrical connection with the source region 140a. A second source contact 1050b extends through the ILD 1040 for electrical connection with the silicide layer 145b to establish an electrical connection with the source region 140b. A drain contact 1060 extends through the ILD 1040 for electrical connection with the silicide layer 175 to establish an electrical connection with the drain region 170. For the sake of brevity, the first source contact 1050a, the second source contact 1050b, and the drain contact 1060 are in some cases collectively referred to as contacts.

[0097] Each of the contacts has sidewalls that are substantially perpendicular to the top surface of the substrate 110. In some embodiments, at least one of the contacts has a conical profile. In some embodiments, the contacts independently include copper, aluminum, tungsten, cobalt, alloys thereof, and / or other suitable conductive materials. In some embodiments, the contacts each include the same conductive material. In some embodiments, at least one contact includes a different conductive material than at least one other contact. In some embodiments, at least one of the contacts further includes a barrier layer to help prevent diffusion of the conductive material into the ILD 1040.

[0098] Fig. 11 is a schematic diagram of a buck converter 1100 including an LDMOS transistor 1110 according to some embodiments. In some embodiments, the LDMOS transistor 1110 is similar to the LDMOS transistor 100 ( Fig. 1), the LDMOS transistor 600E ( Fig. 6E), the LDMOS transistor 700E ( Fig. 7E), the LDMOS transistor 800E ( Fig. 8E), the LDMOS transistor 900E ( Fig. 9E) or the LDMOS transistor 1000E ( Fig. 10E). Buck converter 1100 includes a sampling and switching circuit 1120, an inductor 1130, a capacitor 1140, and an output 1150 for providing an output voltage to a load. In some embodiments, buck converter 1100 includes gate drivers for providing a control voltage to the gates of LDMOS transistor 1100.

[0099] The sampling and switching circuit 1120 is configured to control a voltage provided to the gates of the LDMOS transistor 1110. A source of an upper device 1115a is connected to an input voltage V in connected. A source of a lower device 1115b is connected to a reference voltage, e.g., ground. The upper device 1115a and the lower device 1115b share a drain connected to the inductor 1130. The capacitor 1140 is connected between an output of the inductor 1130 and the source of the lower device 1115b. An output voltage (V out ) 1150 is connected to a load.

[0100] The LDMOS transistor 1110 includes the upper device 1115a and the lower device 1115b. In some embodiments, the upper device 1115a corresponds to the gate 150a ( Fig. 1), and the lower device 1115b corresponds to the gate 150b ( Fig.1). In some embodiments where V in 26.4 V, the buck converter 1100 includes an upper device 1115a with a hot carrier injection (HCI) rating of less than 26.4 V. The particular HCI rating of interest is a nominal operating range, a safe HCI 10-year operating range, a safe HCI 0.2-year operating range, and / or another suitable HCI rating. To assist in avoiding breakdown behavior, the upper device 1115a of some embodiments has a breakdown voltage (i.e., BV dss ) of greater than 26.4 V. To assist in achieving these operating characteristics, in some exemplary embodiments, the upper device 1115a of the LDMOS transistor has a smaller drift region length, ie, a smaller length Ld, than in other approaches.

[0101] Similar principles also apply to the lower device 1115b. In some embodiments where Vin 26.4 V, the buck converter 1100 includes a lower device 1115b with an HCI rating of less than 26.4 V. In some embodiments, the lower device 1115b of the LDMOS transistor has a smaller drift region length, ie, a smaller length Ld, than in other approaches.

[0102] One aspect of the present disclosure relates to a laterally diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS transistor has a first gate. The LDMOS transistor further has a first source region on a first side of the first gate. The LDMOS transistor further has a drain region on a second side of the first gate, the second side opposite the first side. The LDMOS transistor further has a first spacer enclosing the first gate. The first spacer has a first portion on the first side of the first gate, the first portion having a top surface substantially coplanar with a top surface of the first gate. The first spacer further has a second portion on the second side of the first gate, the second portion having a first horn structure extending above the top surface of the first gate.In some embodiments, the spacer comprises a single layer of silicon oxide. In some embodiments, the spacer comprises a single layer of silicon nitride. In some embodiments, the spacer comprises a first silicon oxide layer, a silicon nitride layer over the first silicon oxide layer, and a second silicon oxide layer over the silicon nitride layer. In some embodiments, the spacer comprises a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. In some embodiments, the spacer comprises a silicon nitride layer and a silicon oxide layer over the silicon nitride layer. In some embodiments, the first horn structure includes a single material.In some embodiments, the first gate has a first thickness measured in a direction perpendicular to the top surface of the first gate, and the first horn structure extends above the top surface of the first gate with a second thickness, the second thickness being less than about 2 / 3 of the first thickness. In some embodiments, the LDMOS transistor further comprises: a second gate, the drain being on a second side of the second gate; and a second spacer enclosing the second gate, the second spacer having a third portion on the second side of the second gate, the third portion comprising a second horn structure.In some embodiments, the second spacer further comprises a fourth portion on a first side of the second gate opposite the second side, the fourth portion having a top surface substantially coplanar with a top surface of the second gate.

[0103] One aspect of the present disclosure relates to a laterally diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS transistor has a first gate. The LDMOS transistor further has a second gate. The LDMOS transistor further has a drain region between the first gate and the second gate, wherein the first and second gates can each be used to control a voltage in the drain region. The LDMOS transistor further has a first spacer surrounding the first gate. The first spacer has a first portion on a side of the first gate closest to the drain region, the first portion comprising a first horn structure extending above a top surface of the first gate. The LDMOS transistor further has a second spacer surrounding the second gate.The second spacer has a second portion on a side of the second gate closest to the drain region, the second portion including a second horn structure extending above a top surface of the second gate. In some embodiments, the first and / or second horn structure have a conical shape. In some embodiments, the first gate has a first thickness measured in a direction perpendicular to the top surface of the first gate, and the first horn structure extends above the top surface of the first gate with a second thickness, the second thickness being less than about 2 / 3 of the first thickness. In some embodiments, the second gate has a third thickness measured in a direction perpendicular to the top surface of the second gate, and the second horn structure extends above the top surface of the second gate with a fourth thickness, the fourth thickness being less than about 2 / 3 of the third thickness.In some embodiments, the fourth thickness is equal to the second thickness. In some embodiments, the fourth thickness is different from the second thickness. In some embodiments, the LDMOS transistor further has a silicide layer over the top of the first gate, wherein the silicide layer extends completely across the top of the first gate.

[0104] One aspect of the present disclosure relates to a method of fabricating a laterally diffused metal oxide semiconductor (LDMOS) transistor. The method comprises forming a gate over a substrate. The method further comprises depositing a spacer material over the gate and the substrate. The method further comprises depositing a photoresist over the spacer material. The method further comprises patterning the photoresist. Patterning the photoresist comprises removing the photoresist from the spacer material on a first side of the gate and leaving the photoresist on the spacer material on a second side of the gate, the second side opposite the first side. The method further comprises etching the spacer material using the patterned photoresist as a mask.Etching the spacer material comprises depositing a first portion of the spacer material on the first side of the gate having a top surface substantially coplanar with a top surface of the gate; and forming a horn structure in a second portion of the spacer material on the second side of the gate, the horn structure extending above the top surface of the gate. In some embodiments, the method further comprises creating a drain region on the second side of the gate. In some embodiments, the method further comprises forming a silicide layer over an entire top surface of the gate.

Claims

[1] Laterally diffused metal oxide semiconductor transistor (LDMOS transistor) with: a first gate (150a); a first source region (140a) on a first side of the first gate (150a); a drain region (170) on a second side of the first gate (150a), the second side being opposite the first side; and a first spacer enclosing the first gate (150a), the first spacer comprising: a first portion on the first side of the first gate (150a), the first portion having a top surface that is substantially coplanar with a top surface of the first gate (150a), and a second portion on the second side of the first gate (150a), the second portion having a first horn structure extending above the top of the first gate (150a). [2] The LDMOS transistor according to claim 1, wherein the spacer has a single layer of silicon oxide. [3] The LDMOS transistor according to claim 1 or 2, wherein the spacer has a single layer of silicon nitride. [4] The LDMOS transistor according to claim 1 or 2, wherein the spacer has the following: a first silicon oxide layer (712); a silicon nitride layer (714, 914, 1012) over the first silicon oxide layer (712); and a second silicon oxide layer (716) over the silicon nitride layer (714, 914, 1012). [5] The LDMOS transistor according to claim 1 or 2, wherein the spacer has the following: a silicon oxide layer (712, 912, 1014); and a silicon nitride layer (714, 914, 1012) over the silicon oxide layer (712, 912, 1014). [6] The LDMOS transistor according to claim 1 or 2, wherein the spacer has the following: a silicon nitride layer (714, 914, 1012); and a silicon oxide layer (712, 912, 1014) over the silicon nitride layer (714, 914, 1012). [7] An LDMOS transistor according to any one of the preceding claims, wherein the first horn structure comprises a single material. [8] LDMOS transistor according to one of the preceding claims, wherein the first gate (150a) has a first thickness measured in a direction perpendicular to the top surface of the first gate (150a), and the first horn structure extends over the top of the first gate (150a) with a first thickness, the first thickness being less than about two-thirds (2 / 3) of the first thickness. [9] The LDMOS transistor of claim 2, further comprising: a second gate (150b), wherein the drain (170) is located on a second side of the second gate (150b); and a second spacer enclosing the second gate (150b), the second spacer comprising: a third portion on the second side of the second gate (150b), the third portion having a second horn structure. [10] The LDMOS transistor of claim 9, wherein the second spacer further comprises a fourth portion on a first side of the second gate (150b) opposite the second side, the fourth portion having a top surface substantially coplanar with a top surface of the second gate (150b). [11] An LDMOS transistor according to claim 1, further comprising: a second gate (150b); wherein the drain region (170) is located between the first gate (150a) and the second gate (150b), wherein the first gate (150a) and the second gate (150b) can each be used to control a voltage in the drain region (170); and a second spacer enclosing the second gate (150b), the second spacer comprising: a second portion on a side of the second gate (150b) closest to the drain region (170), the second portion having a second horn structure extending above a top surface of the second gate (150b). [12] The LDMOS transistor of claim 11, wherein the first and / or second horn structure has a conical shape. [13] LDMOS transistor according to claim 11, wherein the first gate (150a) has a first thickness measured in a direction perpendicular to the top surface of the first gate (150a), and the first horn structure extends over the top of the first gate (150a) with a second thickness, the second thickness being less than about two-thirds (2 / 3) of the first thickness. [14] LDMOS transistor according to claim 13, wherein the second gate (150b) has a third thickness measured in a direction perpendicular to the top of the second gate (150b), and the second horn structure extends over the top of the second gate (150b) with a fourth thickness, the fourth thickness being less than about 2 / 3 of the third thickness. [15] The LDMOS transistor of claim 14, wherein the fourth thickness is equal to the second thickness. [16] The LDMOS transistor of claim 14, wherein the fourth thickness is different from the second thickness. [17] The LDMOS transistor of claim 14, further comprising a silicide layer (155) over the top surface of the first gate (150a), the silicide layer (155) extending completely across the top surface of the first gate (150a). [18] A method of manufacturing a side-diffused metal oxide semiconductor (LDMOS) transistor, comprising: forming a gate (150) over a substrate (110); Depositing a spacer material (610, 710, 810, 910, 1010) over the gate (150) and the substrate (110); Depositing a photoresist (620, 720, 820, 920, 1020) over the spacer material (610, 710, 810, 910, 1010); Structuring the photoresist (620, 720, 820, 920, 1020), wherein the structuring of the photoresist (620, 720, 820, 920, 1020) comprises: Removing the photoresist (620, 720, 820, 920, 1020) from the spacer material (610, 710, 810, 910, 1010) on a first side of the gate (150), and Leaving the photoresist (620, 720, 820, 920, 1020) on the spacer material (610, 710, 810, 910, 1010) on a second side of the gate (150), the second side being opposite the first side; and Etching the spacer material (610, 710, 810, 910, 1010) using the patterned photoresist as a mask, wherein the etching of the spacer material (610, 710, 810, 910, 1010) comprises: Depositing a first portion of the spacer material (610, 710, 810, 910, 1010) on the first side of the gate (150) having a top surface that is substantially coplanar with a top surface of the gate (150), and Forming a horn structure in a second portion of the spacer material (610, 710, 810, 910, 1010) on the second side of the gate (150), the horn structure extending over the top of the gate (150). [19] The method of claim 18, further comprising forming a drain region (170) on the second side of the gate (150). [20] The method of claim 18, further comprising forming a silicide layer (155) over an entire top surface of the gate (150).

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