ONE-TIME PROGRAMMABLE STORAGE DEVICES AND METHODS FOR THEM TO BE MADE

Abstract

A memory device comprises: a matrix containing a plurality of once-programmable memory cells (OTP memory cells) fabricated over one side of a substrate; a plurality of word lines (WLs); a plurality of bit lines (BLs); and a plurality of control gate lines (CG lines). Each of the OTP memory cells contains a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first and second fuse resistors are connected to a corresponding BL. SThe first and second transistors are connected, while the first and second transistors are gated by the first and second CG lines, respectively. The first transistor, the second transistor, the first fuse resistor, and the second fuse resistor are manufactured in the first, second, third, and fourth of a plurality of metallization layers arranged on the substrate side.

Description

Cross-reference to related application

[0001] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 584,220, filed September 21, 2023, entitled “A PUF STRUCTURE ON METAL FUSE WITH BEOL TANANSISTOR,” which is incorporated by reference into this application. background

[0002] A one-time programmable memory (OTP) device is a type of non-volatile memory device used in integrated circuits to customize circuits after an integrated circuit has been manufactured. For example, the OTP memory device is used to provide repair information that controls the use of redundant cells when replacing defective cells in a memory array. Another use is to customize analog circuits by trimming a capacitive or resistive value of an analog circuit or by enabling and disabling parts of the system. A recent trend is for the same product to be manufactured in different manufacturing facilities using a common process technology. Despite best engineering efforts, it is likely that each facility uses a slightly different process.The use of OTP storage devices enables independent optimization of product functionality for each manufacturing facility. Short description of the drawings

[0003] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Rather, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 is a block diagram of an exemplary memory system including a memory array according to some embodiments of the present disclosure. Fig. 2 shows an exemplary circuit diagram of part of the memory matrix of Fig. 1 comprising a plurality of memory cells, according to some embodiments. Fig. 3 shows another exemplary circuit diagram of part of the memory matrix of Fig. 1 comprising a plurality of memory cells, according to some embodiments. The Fig. 4 and Fig. 5 show examples in which, according to some embodiments, two memory cells formed in Fig. 2 are shown, each of which can be programmed. Fig. Figure 6 shows an example in which, according to some embodiments, two memory cells formed in Fig. 2 are shown, are read out in each case. Fig. 7 is a flow diagram of an exemplary method for generating a PUF bit based on the memory array of Fig. 1, according to some embodiments. Fig. 8A shows an exemplary circuit diagram of a memory device with a memory cell arranged in Fig. 2, according to some embodiments. Fig. 8B shows a sectional view of a memory device based on the memory device shown in Fig. 8A, according to one embodiment. Fig. 8C shows a sectional view of a memory device based on the Fig. 8A, according to another embodiment. Fig. 8D shows a sectional view of a memory device based on the memory device shown in Fig. 8A, according to yet another embodiment. Fig. 9A shows an exemplary circuit diagram of a memory device with a memory cell arranged in Fig. 3, according to some embodiments. Fig. 9B shows a sectional view of a memory device based on the memory device shown in Fig. 9A, according to one embodiment. Fig. 9C shows a sectional view of a memory device based on the memory device shown in Fig. 9A, according to another embodiment. Fig. 10 shows a flow diagram of a method of manufacturing a semiconductor device according to some embodiments. Fig. 11 shows an exemplary diagram of a thin film transistor implemented as a CG (control gate) transistor according to some embodiments. Detailed description

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present disclosure, reference numbers and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structural element to one or more other elements or structural elements illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90° or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0006] A Physically Unclonable Function (PUF) is generally used for authentication and secret key storage without the need for secure electrically erasable programmable read-only memory (EEPROM) and / or other expensive hardware (e.g., battery-backed random access memory). Instead of storing secrets in digital memory, the PUF derives a secret from physical properties of an integrated circuit (IC). The PUF is based on the idea that even though an identical manufacturing process is used to produce multiple ICs, each IC may be slightly different from another due to manufacturing variability. PUFs exploit this variability to derive "secret" information specific to each of the ICs (e.g., a silicon biometric). This secret information is generally referred to as a "PUF signature" of the IC.Furthermore, due to the manufacturing variability that defines the PUF signature, even with full knowledge of the IC design, two identical ICs cannot be manufactured. Various types of IC variability can be used to define such a signature, for example, gate delay(s), power-up states of a memory device, and / or various physical properties of an IC.

[0007] In embodiments of the present disclosure, various systems and methods are provided for generating at least one bit of a PUF signature (referred to as a PUF bit) for / from a memory device having a plurality of memory cells. In one aspect of the present disclosure, the memory cells are each implemented as an eFuse cell including a plurality of transistors and two fuse resistors, referred to as an "mT2R structure." The two fuse resistors each have one end connected to a bit line across which a programming voltage is applied. Although the two fuse resistors are fabricated with the same dimensions and material, according to various embodiments, when programming simultaneously at the same programming voltage level, one of the fuse resistors may be blown by the programming voltage before the other.As such, one of the two fuse resistors can be randomly programmed (in advance) to create an equivalent open circuit, while the other remains intact as a short circuit. Depending on which of the fuse resistors fails first, the disclosed system (e.g., integrated with the memory device) can generate a PUF bit for / from a memory cell of the memory device. By applying this principle to all memory cells, the disclosed system can generate a specific PUF signature for / from the memory device.

[0008] In some embodiments, a memory device comprises: an array including a plurality of one-time programmable (OTP) memory cells fabricated over one side (e.g., a front side) of a substrate; a plurality of word lines (WLs); a plurality of bit lines (BLs); and a plurality of control gate (CG) lines. Each of the OTP memory cells includes a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first and second fuse resistors are commonly connected to a corresponding one of the BLs, while the first and second transistors are gated by first and second CG lines, respectively.The first transistor, the second transistor, the first fuse resistor, and the second fuse resistor are fabricated in a first, a second, a third, and a fourth of a plurality of metallization layers, each disposed over the side of the substrate, and thus are fabricated in the back end of line (BEOL), resulting in a smaller memory cell area and a higher memory cell density in the memory device.

[0009] Fig. 1 shows a block diagram of a storage system 100 according to various embodiments. In the illustrated embodiment of Fig. 1, the memory system 100 includes a memory array 102, a row decoder 104, a column decoder 106, an input / output (I / O) circuit 108, an authentication circuit 110, and a control logic circuit 112. Although Fig. 1, but all components of the memory system 100 can be connected to each other and to the control logic circuit 112. In the Fig. 1, each component is shown as a separate block for clarity, but in some other embodiments, some or all of the components shown in Fig. 1 can be integrated with each other. For example, the memory array 102 can include an embedded authentication circuit (e.g., 110).

[0010] The memory array 102 is a hardware component that stores data. In various embodiments, the memory array 102 is embodied as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or otherwise memory units) 103. The memory array 102 includes a plurality of rows R1, R2, R3, ... R M, each extending in a first direction (e.g., the x-direction), and a plurality of columns C1, C2, C3... C N , each extending in a second direction (e.g., the y-direction). The rows and columns may each include one or more conductive structures (e.g., metal structures) that function as access lines. Each memory cell 103 is arranged at an intersection of a corresponding row and a corresponding column and may be operated according to voltages or currents through the respective conductive structures of the row and column. For example, each of the rows may include a corresponding word line (WL), and each of the columns may include a corresponding bit line (BL) and a plurality of corresponding CG lines.

[0011] In some embodiments, each memory cell 103 is embodied as an eFuse memory cell, which may include first and second fuse resistors, first and second control / cascade gate selectors / transistors (CG selectors / transistors), and one or more WL selectors / transistors. The first fuse resistor, the first CG transistor, and at least one of the WL transistors are connected in series with each other, and the second fuse resistor, the second CG transistor, and at least one of the WL transistors are also connected in series with each other.In addition, a corresponding WL may be connected to one or more gates of the one or more WL transistors, a corresponding BL may be connected to respective ends of the first and second fuse resistors, a corresponding first CG line may be connected to a gate of the first CG transistor, and a corresponding second CG line may be connected to a gate of the second CG transistor, which may be described with reference to FIG. Fig. 2 and Fig. 3 is explained in more detail.

[0012] While in various embodiments of the present disclosure, the memory cell 103 is implemented as an eFuse memory cell including a plurality of fuse resistors, each formed as a metal trace in a corresponding metallization layer, the fuse resistors of the memory cell 103 may also be implemented based on other resistance-based memory configurations. For example, the memory cell 103 may be fabricated as an RRAM (resistive random access memory) configuration, a PCRAM or PRAM (phase-change random access memory) configuration, or an MRAM (magnetoresistive random access memory) configuration. In some further embodiments, the fuse resistors of the memory cell 103 may be implemented based on via structures or polysilicon structures.Furthermore, in some further embodiments, the memory cell 103 may be implemented as an eFuse memory cell including a plurality of fuse capacitors, where the fuse capacitors may each be fabricated as a metal-insulator-metal (MIM) capacitor or a metal-oxide-metal (MOM) capacitor.

[0013] In short, the one or more WL transistors and the first and second CG transistors may be turned on to program the respective first and second fuse resistors. For example, after turning on, these two fuse resistors may be programmed via the respective WL, first CG line, and second CG line simultaneously by applying the same programming voltage to the BL. Randomly, the first or second fuse resistor may be blown faster than the other, and thus, a logic state of the memory cell at which the respective fuse resistor has been blown may be determined. These randomly programmed logic states of the memory cells may form the basis for a PUF signature. Configurations and operations of the memory cell 103 and their use to generate a PUF signature will be described later with reference to the Fig. 4, Fig. 5 and Fig. 6 described in more detail.

[0014] The row decoder 104 is a hardware component that can receive a row address of the memory array 102 and activate a conductive structure (e.g., the WL) at that row address. The column decoder 106 is a hardware component that can receive a column address of the memory array 102 and activate multiple conductive structures (e.g., the BL and one or more of the CG lines) at that column address. The I / O circuit 108 is a hardware component that can access each of the memory cells 103 activated via the row decoder 104 and the column decoder 106. The authentication circuit 110 is a hardware component that can generate a PUF signature based on respective logic states of the memory cells read by the I / O circuit 108. The control logic circuit 112 is a hardware component that can control the connected components (e.g., 102 to 110).Configurations and operations of the storage system 100 are described later with reference to the flowchart of . Fig. 7 described in more detail.

[0015] The Fig. 2 and Fig. 3 show an example circuit diagram 200 or 300 of a portion of the memory device 100 (e.g., some of the memory cells 103) according to some embodiments. In the illustrated examples of Fig. 2 and Fig. 3 shows eFuse memory cells 103A, 103B, 103C, and 103D of memory array 102, each of eFuse memory cells 103A to 103D including at least two fuse resistors. While four eFuse memory cells 103A, 103B, 103C, and 103D are shown, it should be understood that memory array 102 may include any number of similar eFuse memory cells without departing from the scope of the present disclosure.

[0016] The memory cells 103 can be configured as a matrix (as described above in Fig. 1 is shown). In the Fig. 2 and Fig. 3, memory cells 103A and 103B may be arranged in the same row but in different columns, respectively, and memory cells 103C and 103D may also be arranged in the same row but in different columns, respectively. For example, memory cells 103A and 103B are arranged in a row R0 and in a column C0 and C1, respectively, and memory cells 103C and 103D are arranged in a row R1 and in the column C0 and C1, respectively. With such a configuration, each of the memory cells can be operatively connected to the access lines in the corresponding row or column, respectively. In various embodiments, along each row, a plurality of eFuse memory cells 103 are connected to a corresponding WL, and along each column, a plurality of eFuse memory cells 103 are connected to a corresponding BL and a plurality of corresponding CG lines.For example, the eFuse memory cells 103A and 103B are connected to a WL0 arranged in the row R0 and to a BL0, CG0, CG1 arranged in the column C0, and to a BL1, CG2, CG3 arranged in the column C1, respectively, and the eFuse memory cells 103C and 103D are connected to a WL1 arranged in the row R1 and to a BL0, CG0, CG1 arranged in the column C0, and to a BL1, CG2, CG3 arranged in the column C1, respectively.

[0017] In some embodiments, the eFuse memory cells 103 may include first and second fuse resistors, first and second CG transistors, and first and second WL transistors, wherein the first and second CG transistors have source / drain terminals connected to ground through the first and second WL transistors, respectively, as in the illustrative example of Fig. 2. In other embodiments, the eFuse memory cells 103 may include first and second fuse resistors, first and second CG transistors, and a common WL transistor, wherein the first and second CG transistors have source / drain terminals connected to ground through the common WL transistor, as in the illustrative example of Fig. 3 is shown.

[0018] In the circuit diagram 200 of Fig. 2, each of the eFuse memory cells 103A to 103D includes a first fuse resistor 210, a second fuse resistor 220, a first CG transistor 230, a second CG transistor 240, a first WL transistor 250, and a second WL transistor 260. This schematic design in Fig. 2 is referred to as a 4-transistor-2-resistor (4T2R) configuration. The first CG transistor 230, the second CG transistor 240, the first WL transistor 250, and the second WL transistor 260 can each be implemented as an n-type transistor. However, it should be understood that each of these transistors can also be implemented as a p-type transistor, which is also within the scope of the present disclosure. The first fuse resistor 210, the first CG transistor 230, and the first WL transistor 250 are connected in series with each other between BL0 and ground, and the second fuse resistor 220, the second CG transistor 240, and the second WL transistor 260 are also connected in series with each other between BL0 and ground.

[0019] In the eFuse memory cell 103A as a representative example, the first fuse resistor 210 has a first end (or first terminal) connected to the BL0 and a second end (or second terminal) connected to the first source / drain terminal of the first CG transistor 230; the second fuse resistor 220 has a first end (or first terminal) also connected to the BL0 and a second end (or second terminal) connected to the first source / drain terminal of the second CG transistor 240; the first CG transistor 230 has a second source / drain terminal connected to a first source / drain terminal of the first WL transistor 250, wherein a second source / drain terminal of the first WL transistor 250 is connected to ground;and the second CG transistor 240 has a second source / drain terminal connected to a first source / drain terminal of the second WL transistor 260, with a second source / drain terminal of the second WL transistor 260 connected to ground. Furthermore, the respective gate terminals of the first WL transistor 250 and the second WL transistor 260 are commonly connected to WL0 (i.e., commonly gated by WL0); the first CG transistor 230 has a gate terminal connected to CG0 (i.e., gated by CG0); and the second CG transistor 240 has a gate terminal connected to CG1 (i.e., gated by CG1).

[0020] Let us now turn to circuit diagram 300 of Fig. 3, in which the eFuse memory cells 103A to 103D each have a first fuse resistor 310, a second fuse resistor 320, a first CG transistor 330, a second CG transistor 340, and a common WL transistor 350. This schematic design in Fig. 3 is referred to as a 3-transistor-2-resistor (3T2R) configuration. The first CG transistor 330, the second CG transistor 340, and the WL transistor 350 can each be implemented as an n-type transistor. However, it should be understood that each of these transistors can also be implemented as a p-type transistor, which is also within the scope of the present disclosure. The first fuse resistor 310, the first CG transistor 330, and the WL transistor 350 are connected in series between BL0 and ground, and the second fuse resistor 320, the second CG transistor 340, and the WL transistor 350 are also connected in series between BL0 and ground.

[0021] In the eFuse memory cell 103A as a representative example, the first fuse resistor 310 has a first end (or first terminal) connected to the BL0 and a second end (or second terminal) connected to a first source / drain terminal of the first CG transistor 330; the second fuse resistor 320 has a first end (or first terminal) also connected to the BL0 and a second end (or second terminal) connected to a first source / drain terminal of the second CG transistor 340; and the first CG transistor 330 and the second CG transistor 340 each have a second source / drain terminal connected to a first source / drain terminal of the WL transistor 350, with a second source / drain terminal of the WL transistor 350 connected to ground. In addition, the gate terminal of the WL transistor 350 is connected to the WL0 (ie, gated by the WL0); the first CG transistor 330 has a gate terminal connected to the CG0 (i.e., gated by the CG0); and the second CG transistor 340 has a gate terminal connected to the CG1 (i.e., gated by the CG1).

[0022] To program the eFuse memory cell 103, first, the one or more corresponding WL transistors and the first and second CG transistors are activated. In the example where these transistors are each implemented as an n-type transistor, the one or more WL transistors and the first and second CG transistors are activated (e.g., turned on) by applying a logic high signal to the WL Sand the CG lines. Then, a programming signal (e.g., a voltage) is applied to the BL. When the WL transistor and the first and second CG transistors (and the one or more corresponding WL transistors) are turned on, the programming voltage can be applied across the first and second fuse resistors, respectively. In other words, two conduction paths are available through at least the first and second fuse resistors, respectively.

[0023] Although these two fuse resistors are manufactured from the same materials and with identical dimensions, due to processing variability, one of the two fuse resistors may blow faster than the other. For example, after one of the fuse resistors has blown (e.g., one of the fuse resistors has become an open circuit and the other remains a short circuit), a sudden voltage drop may occur on the BL, which may automatically interrupt the programming process on the eFuse memory cell 103. This allows the eFuse memory cell 103 to be "randomly" programmed to a first or second logic state.Whether the first or the second logic state is programmed into the memory cell may correspond to the circumstance which of the fuse resistors has been blown (earlier than the other), which can be determined (or detected) on the basis of a read process.

[0024] To read the eFuse memory cell 103, first the one or more corresponding WL transistors and only the first or second CG transistor are activated (e.g., turned on). In some embodiments, which of the CG transistors is selected for activation is fixed across the entire memory array. For example, across all columns of a memory array, one of the even-numbered CG lines (e.g., CG0) and the odd-numbered CG lines (e.g., CG1) is activated during the read process. Then, a read signal (e.g., a voltage) is applied to the BL. If one of the fuse resistors has been randomly programmed (blown), only one conduction path can be established from the BL through the fuse resistor that has not been blown, the selected (activated) CG transistor, and to ground.Otherwise, no conduction path can be established from the BL through the blown fuse resistor and the selected (activated) CG transistor and to ground. For example, if the selected CG transistor is connected to the blown fuse resistor, no conduction path is established; and if the selected CG transistor is connected to the unblown fuse resistor, a conduction path is established.

[0025] In some embodiments, if no conduction path is established (i.e., if the fuse resistor connected to the selected CG transistor has been blown), the eFuse memory cell 103 is determined to be in a first logic state (e.g., logic 1); and if conduction path is established (i.e., if the fuse resistor connected to the selected CG transistor has not been blown), the eFuse memory cell 103 is determined to be in a second logic state (e.g., logic 0). In other words, each of the eFuse memory cells 103 can be randomly programmed to logic 1 or 0. Based on such a randomly programmed logic state in each of the eFuse memory cells, a PUF signature (formed by respective PUF bits of the eFuse memory cells) can be generated.

[0026] The Fig. 4 and Fig. 5 illustrates an example in which the eFuse memory cells 103A and 103D are sequentially programmed, according to some embodiments. Following the principles discussed above, the eFuse memory cells 103A and 103D may each be randomly programmed to a first logic state (e.g., logic 1 for a blown fuse resistor) or to a second logic state (e.g., logic 0 for an intact fuse resistor). The numerical values ​​of signals discussed below are for illustrative purposes only, and therefore, other values ​​may be contemplated, which are also within the scope of the present disclosure.

[0027] Let us first come to Fig. 4, to program the eFuse memory cell 103A. WL0 is activated by applying a voltage signal corresponding to a logic high state (e.g., approximately 0.75 V), while other word lines (e.g., WL1) are each applied a voltage signal corresponding to a logic low state (e.g., approximately 0 V). Simultaneously or subsequently, CG0 and CG1 are also activated by applying a voltage signal, also approximately 0.75 V, while other control gate lines (e.g., CG2 and CG3) are each applied a voltage signal, approximately 0 V. This allows the WL transistors 250 and 260 and the CG transistors 230 and 240 of the eFuse memory cell 103A to be turned on, while the WL transistors and the CG transistors of other eFuse memory cells remain deactivated. Then a programming voltage (e.g. about 1.2 V to 1.5 V) is applied to BL0, while other bit lines (e.g.BL1) is each applied a voltage signal of approximately 0 V. Thus, two conduction paths, 401 and 403, are available for conducting current from BL0 to ground. As explained above, one of the fuse resistors (e.g., 210) will blow earlier than the other (e.g., 220). This can cause the voltage across BL0 to drop suddenly, interrupting the programming process (e.g., at the still intact fuse resistor 220).

[0028] In Fig. 5, to program the eFuse memory cell 103D, the WL1 is activated by applying a voltage signal corresponding to a logic high state (e.g., approximately 0.75 V), while other word lines (e.g., WL0) are each applied a voltage signal corresponding to a logic low state (e.g., approximately 0 V). Simultaneously or subsequently, the CG1 and the CG3 are also activated by applying a voltage signal, also approximately 0.75 V, while other control gate lines (e.g., CG0 and CG1) are each applied a voltage signal, approximately 0 V. This allows the WL transistors 250 and 260 and the CG transistors 230 and 240 of the eFuse memory cell 103A to be turned on, while the WL transistors and the CG transistors of other eFuse memory cells remain deactivated. Then a programming voltage (e.g. about 1.2 V to 1.5 V) is applied to BL1, while other bit lines (e.g.BL0) is each supplied with a voltage signal of approximately 0 V. Thus, two conduction paths, 501 and 503, are available for conducting current from BL1 to ground. As explained above, one of the fuse resistors (e.g., 220) will blow earlier than the other (e.g., 210). This can cause the voltage across BL1 to drop suddenly, interrupting the programming process (e.g., at the still intact fuse resistor 210).

[0029] Fig. 6 shows an example in which, according to some embodiments, the eFuse memory cells 103A and 103D (after being programmed) are read sequentially. In the example shown in FIGS. Fig. 4 and Fig. 5, the fuse resistor 210 of the eFuse memory cell 103A is blown, while the fuse resistor 220 of the eFuse memory cell 103D is blown, as shown in Fig. 6. The numerical values ​​of signals discussed below are for illustrative purposes only, and therefore other values ​​may be considered, which are also within the scope of the present disclosure.

[0030] To read the eFuse memory cell 103A, WL0 is activated by applying a voltage signal corresponding to a logic high state (e.g., approximately 0.75 V), while other word lines (e.g., WL1) are each applied a voltage signal corresponding to a logic low state (e.g., approximately 0 V). Simultaneously or subsequently, CG0 or CG1 (e.g., CG0) are also activated by applying a voltage signal, also approximately 0.75 V, while other control gate lines (e.g., CG1, CG2, and CG3) are each applied a voltage signal approximately 0 V. This allows the WL transistors 250 and 260 and the CG transistor 230 of the eFuse memory cell 103A to be turned on, while the CG transistor 240 of the eFuse memory cell 103A remains deactivated. Then, a read voltage (e.g., approximately 1.2 V to 1.5 V) is applied to BL0, while a voltage signal of approximately 0 V is applied to other bit lines (e.g., BL1).Only one conduction path 601 is provided for conducting current from BL0 via the fuse resistor 210, the CG transistor 230, and the WL transistor 250 to ground. Since the fuse resistor 210 has been blown (i.e., programmed as an open circuit), no current can flow through this conduction path 601. As a result, no current (or only a current level lower than a predefined threshold) is applied to BL0, and thus the eFuse memory cell 103A can be defined as an eFuse memory cell that is permanently programmed to logic 1 (e.g., has a blown fuse resistor connected to the activated CG transistor).

[0031] Similarly, to read the eFuse memory cell 103D, WL1 is activated by applying a voltage signal corresponding to a logic high state (e.g., approximately 0.75 V), while other word lines (e.g., WL0) are each applied a voltage signal corresponding to a logic low state (e.g., approximately 0 V). Simultaneously or subsequently, CG2 or CG3 (e.g., CG2) are also activated by applying a voltage signal, also approximately 0.75 V, while other control gate lines (e.g., CG3, CG0, and CG1) are each applied a voltage signal approximately 0 V. This allows the WL transistors 250 and 260 and the CG transistor 230 of the eFuse memory cell 103D to be turned on, while the CG transistor 240 of the eFuse memory cell 103D remains deactivated. Then, a read voltage (e.g., approximately 1.2 V to 1.5 V) is applied to BL1, while other bit lines (e.g.,BL0) is applied with a voltage signal of approximately 0 V. Only one conduction path 603 is provided for conducting current from BL1 through the fuse resistor 210, the CG transistor 230, and the WL transistor 250 to ground. Since the fuse resistor 210 has not been blown (i.e., programmed as an open circuit), a current can flow through this conduction path 603. As a result, a current (or a current level higher than a predefined threshold) is applied to BL1, and thus the eFuse memory cell 103D can be defined as an eFuse memory cell that is permanently programmed to logic 0 (e.g., has an intact fuse resistor connected to the activated CG transistor).

[0032] Fig. 7 shows a flow diagram of an exemplary method 700 for generating a PUF signature based on an eFuse memory cell that includes a pair of fuse resistors and multiple CG / WL transistors (i.e., has an "mT2R" configuration), according to various embodiments. Operations of the method 700 are performed by at least the components described in the Fig. 1 and Fig. 2. For discussion, the following embodiment of the method 700 is used in conjunction with the Fig. 1 and Fig. 2. The illustrated embodiment of method 700 is merely an example, so one of several operations may be omitted, performed in a different order, and / or added, all of which are also within the scope of the present disclosure.

[0033] The method 700 may begin with an operation 702 of a programming process. In some embodiments, operation 702 may include an operation 704 in which a column is selected; an operation 706 in which a row is selected; and an operation 708 in which a programming voltage is applied to a BL of the selected column. Note that the order of operations 704 to 708 may be changed, which is also within the scope of the present disclosure. For example, operations 704 and 706 may be swapped.

[0034] Let us first turn to operation 704, in which the control logic circuit 112 may provide a column address to the column decoder 106 to select one of the columns C; through C Nof the memory array 102. In some embodiments, the column address used during the programming process may not indicate which of the CG lines should be selected. In other words, the column decoder 106 may activate the CG lines and the BL of the selected column. After a column is selected, the I / O circuit 108 may provide a voltage (e.g., corresponding to a logic high state if the CG transistor is an n-type transistor) to each of the CG lines located in the selected column, e.g., CG0 and CG1 of Fig. 2. This allows the CG transistors 230 and 240 to be turned on.

[0035] Then, in operation 706, the control logic circuit 112 may provide a row address to the row decoder 104 to select one of the rows R1 through R M of the memory array 102. In some embodiments, the row address may indicate which of the WL Sis to be selected. After a row has been selected, the I / O circuit 108 may provide a voltage (e.g., corresponding to a logic high state if the WL transistor is an n-type transistor) to the WL located in the selected row, e.g., WL0 of Fig. 2. This allows the WL transistors 250 and 260 to be turned on. Thus, the memory cell located at the intersection of the selected column and the selected row (e.g., 103A) can be programmed.

[0036] Then, in operation 708, the programming voltage is applied to the BL of the selected column, e.g., BL0 of Fig. 2. By turning on CG transistors 230 and 240 and WL transistors 250 and 260, two conduction paths can be established, one extending from BL0 through fuse resistor 210, CG transistor 230, and WL transistor 250 to ground, and the other extending from BL0 through fuse resistor 220, CG transistor 240, and WL transistor 260 to ground. This allows the programming voltage applied to BL0 to accidentally blow fuse resistor 210 or fuse resistor 220.

[0037] Then, the method 700 may proceed to operation 710 to determine whether or not any of the fuse resistors of the selected memory cell have been blown (i.e., programmed). If so, the method 700 may proceed to operation 712, which includes one or more read processes. If not, the method 700 may return to operation 702 to perform the programming process again. In various embodiments, the I / O circuit 108 may determine whether any of the fuse resistors have been blown when it detects a voltage drop occurring at the selected BL (e.g., BL0), as set forth above.

[0038] In some embodiments, operation 712 may include: an operation 714 in which a column is selected; an operation 716 in which a row is selected; and an operation 718 in which a read voltage is applied to a BL of the selected column. Note that the order of operations 714 to 718 may be changed, which is also within the scope of the present disclosure. For example, operations 714 and 716 may be interchanged.

[0039] Let us first turn to operation 714, in which the control logic circuit 112 may provide a column address to the column decoder 106 to select one of the columns C1 through C Nof the memory array 102. In some embodiments, the column address used during the read process may not indicate which of the CG lines should be selected. In other words, the column decoder 106 may only activate one of the CG lines and the BL of the selected column. After a column is selected, the I / O circuit 108 may provide a voltage (e.g., corresponding to a logic high state if the CG transistor is an n-type transistor) to the CG line located in the selected column, e.g., CG0 of Fig. 2. This allows the CG transistor 230 to be turned on while the CG transistor 240 can be turned off.

[0040] Then, in operation 716, the control logic circuit 112 may provide a row address to the row decoder 104 to select one of the rows R1 through R Mof the memory array 102. In some embodiments, the row address may indicate which of the WL S is to be selected. After a row has been selected, the I / O circuit 108 may provide a voltage (e.g., corresponding to a logic high state if the WL transistor is an n-type transistor) to the WL located in the selected row, e.g., WL0 of Fig. 2. This allows the WL transistors 250 and 260 to be turned on. Thus, the memory cell located at the intersection of the selected column and the selected row (e.g., 103A) can be read.

[0041] Then, in operation 718, the read voltage is applied to the BL of the selected column, e.g., BL0 of Fig. 2. By turning on the CG transistor 230 and the WL transistors 250 and 260, depending on whether the fuse resistor 210 has accidentally blown, only one conduction path can be provided, extending from BL0 through the fuse resistor 210, the CG transistor 230, and the WL transistor 250 to ground. For example, the read voltage applied to BL0 can generate a current flowing through the conduction path if the fuse resistor 210 remains intact (not blown). In other words, a short circuit is created (or persists) from BL0 through the fuse resistor 210, the CG transistor 230, and the WL transistor 250 to ground. On the other hand, if the fuse resistor 210 has been blown, no current can be generated. In other words, an open circuit is created between BL0 and ground.

[0042] The method 700 may continue with an operation 720 in which a logic state programmed into the memory cell is determined and a bit of a PUF signature is generated based on the determined logic state. For example, the control logic circuit 112 may determine the logic state programmed into the memory cell 103A based on the read process, e.g., whether power is present at BL0. If current or a sufficiently high current level is detected (e.g., from the I / O circuit 108), the control logic circuit 112 may determine that the memory cell 103A (or, more specifically, the fuse resistor connected to the selected CG transistor) has not been blown, and may then determine that the programmed logic state is logic 0. If no current or a sufficiently low current level is detected (e.g.,from the I / O circuit 108), the control logic circuit 112 can determine that the memory cell 103A (or more specifically, the fuse resistor connected to the selected CG transistor) has been blown, and it can then determine that the programmed logic state is logic 1. The control logic circuit 112 can then provide the determined logic state to the authentication circuit 110 to generate a PUF bit. Since the logic state is randomly determined based on process variations of the pair of fuse resistors, the logic state (i.e., the PUF bit) can be randomly generated, thereby advantageously increasing the security of the memory system 100.

[0043] Fig. 8A shows an exemplary circuit diagram of a memory device 800A with a memory cell arranged in Fig. 2, according to some embodiments. In some embodiments, the memory cell 103 in the memory device 800A is implemented as an eFuse memory cell according to the schematic design 200 of Fig. 2 (e.g. as the 4T2R configuration), and therefore some reference symbols of Fig. 2 is reused. The memory cell 103 of Fig. 8A corresponds to the memory cell 103C of Fig. 2 and serves as a representative example, but the memory cell 103 of Fig. 8A, each of the memory cells 103A to 103D of Fig. 2 be.

[0044] As in Fig. 8A, the memory device 800A includes at least one memory cell 103 including a first fuse resistor 210, a second fuse resistor 220, a first CG transistor 230, a second CG transistor 240, a first WL transistor 250, and a second WL transistor 260. The first fuse resistor 210, the first CG transistor 230, and the first WL transistor 250 are connected in series between BL0 and ground. The second fuse resistor 220, the second CG transistor 240, and the second WL transistor 260 are also connected in series between BL0 and ground. The first WL transistor 250 and the second WL transistor 260 are commonly gated by a WL1 consisting of a plurality of WL S is selected. The first CG transistor 230 and the second CG transistor 240 are gated by a CG0 line and a CG1 line, respectively, which are selected from a plurality of CG lines.

[0045] In the programming process, the first WL transistor 250 and the second WL transistor 260 of the memory cell 103 are simultaneously activated by applying a voltage (e.g., about 0.75 V) to their gate terminals, and then a programming voltage (e.g., about 1.2 V to 1.5 V) is applied to the BL0. This blows either the first fuse resistor 210 or the second fuse resistor 220. The memory cell 103 is configured to randomly provide a first logic state (e.g., logic 1) when the first fuse resistor 210 is blown, or to randomly provide a second logic state (e.g., logic 0) when the second fuse resistor 220 is blown. As a result, either the first logic state or the second logic state functions as a bit (logic 1 or logical 0) of a PUF signature for the memory cell 103, and thus a bit of the PUF signature for the memory cell is generated.

[0046] In the read process, the first WL transistor 250 and the second WL transistor 260 of the memory cell 103 are simultaneously activated by applying a voltage (e.g., approximately 0.75 V) to their gate terminals, while only the first CG transistor 230 or the second CG transistor 240 is activated by applying a voltage (e.g., approximately 0.75 V) to its gate terminal. This reads or detects one bit (logical 1 or logical 0) of the PUF signature for the memory cell 103.

[0047] Further details on the implementations of the memory device 800A described as a 4T2R configuration described in Fig. 8A, are described with reference to sectional views of the Fig. 8B to 8D, and some reference symbols of Fig. 8A are reused. Fig. 8B shows a sectional view of a memory device 800B according to an embodiment. It should be understood that the Fig. 8B is simplified for illustrative purposes and therefore the sectional view 800B may include various other components, which is also within the scope of the present disclosure.

[0048] As in Fig. 8B, the memory device 800B includes: a substrate 801 having a front side 803 and a back side 805; an active region 802 formed along a main surface of the front side 803 and extending in a first lateral direction (e.g., x-direction); and a first gate structure 812 and a second WL gate structure 814 formed over the active region 802 and extending in parallel in a second lateral direction (e.g., y-direction).

[0049] In some embodiments, this active area and gate structures are referred to as part of a "front end of line" (FEOL) processing / network because they are formed along the main surface of the front side of the substrate. Directly above the front side of the substrate, multiple front-side metallization layers (referred to as part of a "middle end of line" (MEOL) processing / network) may be formed. Above and further away from the main surface of the front side of the substrate, multiple front-side metallization layers (referred to as part of a "back end of line" (BEOL) processing / network) may be formed. Multiple back-side metallization layers (e.g., BM0) may be formed above the backside 805 of the substrate 801.

[0050] In some embodiments, the active region 802 is formed by a stack structure (not shown) that protrudes from the main surface 803 of the substrate 801 in the FEOL network. The stack includes a plurality of semiconductor nanostructures (e.g., nanosheets) that extend along the x-direction and are vertically spaced from each other. Portions of the semiconductor nanostructures in the stack that are covered by the gate structures 812 and 814 remain, while other portions are replaced by a plurality of epitaxial structures. The remaining portions of the semiconductor structures may be configured as channels of a corresponding transistor; the epitaxial structures connected to both sides (or ends) of the remaining portions of the semiconductor structures may be configured as source / drain structures (or terminals) of the transistor; and a portion of the gate structure that covers the remaining portions of the semiconductor structures (e.g.,spanned), can be configured as a gate structure (or gate terminal) of the transistor.

[0051] As a representative example in Fig. 8B, in the FEOL network, a part of the active region 802 covered by the gate structure 812 may be used as a channel of the first WL transistor 250 of Fig. 8A. Portions of the active region 802 that are arranged on opposite sides of the gate structure 812 are replaced by epitaxial structures and can thereby each function as the source / drain terminals of the first WL transistor 250. The gate structure 812 can function as the gate terminal of the first WL transistor 250. Similarly, a portion of the active region 802 that is covered by the gate structure 814 can serve as a channel of the second WL transistor 260 of Fig. 8A. Parts of the active region 802 that are arranged on opposite sides of the gate structure 814 are replaced by epitaxial structures and can thereby each function as the source / drain terminals of the second WL transistor 260. The gate structure 814 can function as the gate terminal of the second WL transistor 260. In this way, the first WL transistor 250 and the second WL transistor 260 are Fig. 8A along the main surface of the front side of the substrate in the FEOL network.

[0052] As in Fig. 8B, in the MEOL network, a plurality of middle-end interconnect structures (such as 822, 824, and 826) are formed over respective source / drain terminals of the first WL transistor 250 and the second WL transistor 260. A middle-end interconnect structure (referred to as an MD) may connect a respective source / drain terminal to an upper interconnect structure through a middle-end via structure (referred to as a VD; such as VD1, VD2). A gate structure may be connected to an upper interconnect structure through another middle-end via structure (referred to as a VG; such as VG1, VG2). This may connect the gate structures 812 and 814 to one or more metal lines formed thereon.

[0053] Over these middle-end structures on the front side of the substrate, several metallization layers (e.g., M0, M1, M2, M3, M4) can be fabricated, each containing several metal traces or lines embedded in a corresponding dielectric material, e.g., an inter-metal dielectric (IMD) or an inter-layer dielectric (ILD). As described in Fig. 8B, the memory device 800B may include, for example, metal lines 832, 834, 836, and 838 in the M0 layer, metal lines 842 and 844 in the M1 layer, metal lines 852 and 854 in the M2 layer, a metal line 862 in the M3 layer, and metal lines 872, 874, 876, and 878 in the M4 layer.

[0054] For example, the gate structure 812 is connected to the M0 trace 834 by the VG1, and the gate structure 814 is connected to the M0 trace 836 by the VG2. The MD 822, together with at least the M0 trace 832 and the M1 trace 842, may connect one of the source / drain terminals (e.g., an epitaxial structure) of the WL transistor 250 to one end of the M4 trace 872; and the MD 826, together with at least the M0 trace 838 and the M1 trace 844, may connect one of the source / drain terminals (e.g., an epitaxial structure) of the WL transistor 260 to one end of the M4 trace 878. The other source / drain terminals of WL transistors 250 and 260 are commonly connected to MD 824. MD 824 is connected to a supply voltage (VSS) in some embodiments and to ground (GND) in other embodiments.

[0055] As in Fig. 8B, the memory device 800B further includes a metal trace 892 (hereinafter referred to as “BM0 trace 892”) in a first backside metallization layer, which is the lowest metallization layer with respect to the backside 805 of the substrate 801. For simplicity, in Fig. 8B only shows the BM0. However, multiple metallization layers (labeled BM0, BM1, BM2, BM3) can be fabricated on the backside of the substrate, each containing one or more metal traces or lines in a corresponding dielectric material (e.g., an IMD or an ILD).

[0056] In addition, the memory device 800B further includes: a first CG transistor 230 and a second CG transistor 240, both fabricated in one metallization layer (e.g., M4) of the plurality of metallization layers (e.g., M1, M2, M3, M4) in the BEOL network above the front side 803 of the substrate 801; and a first fuse resistor 210 and a second fuse resistor 220, both fabricated in another metallization layer (e.g., M2) of the plurality of metallization layers (e.g., M1, M2, M3, M4) in the BEOL network above the front side 803. As in Fig. 8B, in some embodiments, the first CG transistor 230 and the second CG transistor 240 fabricated in the BEOL network are vertically farther from the main surface of the front side 803 than the first fuse resistor 210 and the second fuse resistor 220 fabricated in the BEOL network.

[0057] In the Fig. 8A and Fig. 8B, the M2 traces 852 and 854 may function as the first fuse resistor 210 and the second fuse resistor 220. In some embodiments, the first fuse resistor 210 and the second fuse resistor 220 are commonly connected to a BL. As shown in Fig. As shown in Figure 8B, one end of the first fuse resistor 210 and one end of the second fuse resistor 220 are commonly connected to the M3 metal trace 862, which functions as a part of a BL0.

[0058] As in the Fig. 8A and Fig. 8B, a source / drain terminal of the first CG transistor 230 is connected to a source / drain terminal of the first WL transistor 250 at least through the MD 822, the M0 metal line 832, the M1 metal line 842, and the M4 metal line 872 and some vias, and another source / drain terminal of the first CG transistor 230 is connected to another end of the first fuse resistor 210 at least through the M4 metal line 874. Similarly, a source / drain terminal of the second CG transistor 240 is connected to a source / drain terminal of the second WL transistor 260 at least through the MD 826, the Mo metal trace 838, the M1 metal trace 844, and the M4 metal trace 878, and some vias, and another source / drain terminal of the second CG transistor 240 is connected to another end of the second fuse resistor 220 at least through the M4 metal trace 876.

[0059] In this way, by fabricating CG transistors and fuse resistors in one or more metallization layers in the BEOL network, the area and programming voltage for each memory cell of the memory device can be reduced, resulting in a higher density of memory cells in the memory device and better performance of the memory device.

[0060] Fig. 8C shows a sectional view of a memory device 800C based on the memory device shown in Fig. 8A, according to one embodiment. Memory device 800C is configured substantially similarly to memory device 800B, but has some differences. Memory device 800C includes: a memory cell 103 designed in a 4T2R configuration and fabricated over a front side 803 of a substrate 801; and a plurality of metallization layers (e.g., M0, M1, M2, M3, M4, M5), each disposed over the front side 803 of the substrate 801.

[0061] As in Fig. 8C, the memory cell 103 also includes: a first WL transistor 250 and a second WL transistor 260, both formed along a main surface of the front side 803 in the FEOL network; a first CG transistor 230 and a second CG transistor 240, both formed in a first metallization layer (e.g., M5) of the plurality of metallization layers in the BEOL network; and a first fuse resistor 210 and a second fuse resistor 220, respectively formed in a second metallization layer (e.g., M2) and a third metallization layer (e.g., M4) of the plurality of metallization layers in the BEOL network. In contrast to what is shown in Fig. As shown in Figure 8B, the first fuse resistor 210 and the second fuse resistor 220 are each fabricated in different metallization layers (e.g., M2 and M4) of the plurality of metallization layers in the BEOL network.

[0062] Similarly, as in Fig. 8C, the first WL transistor 250 and the second WL transistor 260 are gated in common with WL1. The first CG transistor 230 and the second CG transistor 240 are gated with CG0 and CG1, respectively. The first WL transistor 250, the first CG transistor 230, and the first fuse resistor 210 are connected in series between BL0 (implemented, for example, by the M3 metal trace 862) and a supply voltage (VSS) or ground (GND); and the second WL transistor 260, the second CG transistor 240, and the second fuse resistor 220 are connected in series between BL0 and the supply voltage (VSS) or ground (GND).

[0063] Fig. 8D shows a sectional view of a memory device 800D based on the memory device shown in Fig. 8A, according to one embodiment. Memory device 800D is configured substantially similarly to memory device 800B, but has some differences. Memory device 800D includes: a memory cell 103 designed in a 4T2R configuration and fabricated over a front side 803 of a substrate 801; and a plurality of metallization layers (e.g., M0, M1, M2, M3, M4), each disposed over front side 803.

[0064] As in Fig. 8D, the memory cell 103 includes: a first WL transistor 250 and a second WL transistor 260 formed along a main surface of the front side 803 in the FEOL network; a first CG transistor 230 and a second CG transistor 240 formed in a first metallization layer (e.g., M2) of the plurality of metallization layers in the BEOL network; and a first fuse resistor 210 and a second fuse resistor 220, both formed in a second metallization layer (e.g., M3) of the plurality of metallization layers in the BEOL network. In contrast to what is shown in Fig. However, as shown in Figure 8B, the first fuse resistor 210 and the second fuse resistor 220 fabricated in the BEOL network are vertically farther from the front side 803 than the first CG transistor 230 and the second CG transistor 240 fabricated in the BEOL network.

[0065] Fig. 9A shows an exemplary circuit diagram of a memory device 900A with a memory cell arranged in Fig. 3, according to some embodiments. The memory cell 103 of the memory device 900A is configured as an eFuse memory cell according to the schematic design 300 of Fig. 3 (the 3T2R configuration) is implemented, and some reference symbols of Fig. 3 are reused. The memory cell 103 of Fig. 9A (which corresponds to the memory cell 103C of Fig. 3) is used as a representative example and may be any of the memory cells 103A to 103D of Fig. 3 be.

[0066] The memory device 900A includes at least one memory cell 103, which includes a first fuse resistor 310, a second fuse resistor 320, a first CG transistor 330, a second CG transistor 340, and a single WL transistor 350. The first fuse resistor 310, the first CG transistor 330, and the single WL transistor 350 are connected in series between BL0 and VSS (or ground). The second fuse resistor 320, the second CG transistor 340, and the single WL transistor 350 are also connected in series between BL0 and VSS (or ground). The single WL transistor 350 is gated by a WL1 selected from a plurality of WLs. The first CG transistor 330 and the second CG transistor 340 are gated by a CG0 line and a CG1 line, respectively.

[0067] In the programming process, the single WL transistor 350 of the memory cell 103 is activated by applying a voltage (e.g., about 0.75 V) to its gate terminal, and then a programming voltage (e.g., about 1.2 V to 1.5 V) is applied to the BL0. This blows either the first fuse resistor 310 or the second fuse resistor 320. The memory cell 103 is configured to randomly provide a first logic state (e.g., logic 1) when the first fuse resistor 310 is blown, or to randomly provide a second logic state (e.g., logic 0) when the second fuse resistor 320 is blown. As a result, either the first logic state or the second logic state functions as a bit (logic 1 or logical 0) of a PUF signature for the memory cell 103, and thus a bit of the PUF signature for the memory cell 103 is generated.

[0068] In the read process, the single WL transistor 350 is activated by applying a voltage (e.g., approximately 0.75 V) to its gate terminal, and only the first CG transistor 330 or the second CG transistor 340 is activated by applying a voltage (e.g., approximately 0.75 V) to its gate terminal. This detects one bit (logic 1 or logical 0) of the PUF signature for memory cell 103.

[0069] Further details on the configurations and / or implementations of the memory device according to the circuit diagram 900A of Fig. 9A are discussed using various embodiments shown in sectional views of the Fig. 9B and Fig. 9C, and some reference symbols of Fig. 9A are in the Fig. 9B and Fig. 9C reused.

[0070] Fig. 9B shows a sectional view of a memory device 900B constructed based on the circuit diagram of Fig. 9A, according to one embodiment. It is understood that the Fig. 9B is simplified for illustrative purposes and therefore the sectional view 800B may include various other components, which is also within the scope of the present disclosure.

[0071] The memory device 900B includes: a memory cell 103 designed in a 3T2R configuration and fabricated over a front side 903 of a substrate 901; and a plurality of metallization layers (e.g., M1, M2, M3, M4), each disposed over the front side 903 of the substrate 901 in the BEOL network. The memory cell 103 includes: a single WL transistor 350 fabricated in an active region 902 along a major surface of the front side 903 in the FEOL network; a first CG transistor 330 and a second CG transistor 340, both fabricated in a first metallization layer (e.g., M4) of the plurality of metallization layers in the BEOL network; and a first fuse resistor 310 and a second fuse resistor 320, both fabricated in a second metallization layer (e.g., M2) of the plurality of metallization layers in the BEOL network.

[0072] As in the Fig. 9A and Fig. As shown in Figure 9B, in some embodiments, the single WL transistor 350 is gated to WL1. The first CG transistor 330 and the second CG transistor 340 are each gated to CG lines (e.g., CG0 and CG1). The single WL transistor 350, the first CG transistor 330, and the first fuse resistor 310 are connected in series between BL0 (formed, for example, by an M3 trace) and VSS; and the single WL transistor 350, the second CG transistor 340, and the second fuse resistor 320 are connected in series between BL0 and VSS.

[0073] As in Fig. 9B, in some embodiments, the first CG transistor 330 and the second CG transistor 340, which are formed in the first metal layer (e.g., M4) of the plurality of metallization layers in the BEOL network, are vertically farther from the front side 903 of the substrate 901 than the first fuse resistor 310 and the second fuse resistor 320, which are formed in the second metal layer (e.g., M2) of the plurality of metallization layers in the BEOL network.

[0074] Fig. 9C shows a sectional view of a memory device 900C based on the memory device shown in Fig. 9A, according to another embodiment. The memory device 900C is substantially similar to the circuit diagram shown in Fig. 9B, but it has some differences.

[0075] As in Fig. 9C, the memory device 900C includes a memory cell 103 designed in a 3T2R configuration and fabricated over a front side 903 of a substrate 901; and a plurality of metallization layers (e.g., M1, M2, M3, M4) each disposed over the front side 903 in the BEOL network. The memory cell 103 includes a single WL transistor 350 fabricated in an active region 902 and along a major surface of the front side 903 in the FEOL network; a first CG transistor 330 and a second CG transistor 340 fabricated in a first metallization layer (e.g., M2) of the plurality of metallization layers in the BEOL network; and and a first fuse resistor 310 and a second fuse resistor 320, both fabricated in a second metallization layer (e.g., M3) of the plurality of metallization layers in the BEOL network.

[0076] As in Fig. However, as shown in Figure 9C, in the memory device 900C, the first fuse resistor 310 and the second fuse resistor 320 fabricated in the BEOL network are vertically farther from the front side 903 than the first CG transistor 330 and the second CG transistor 340 fabricated in the BEOL network.

[0077] Fig. 10 shows a flow diagram of an exemplary method 1000 for manufacturing a semiconductor device according to some embodiments. It should be noted that the method 1000 is merely an example and is not intended to limit the present disclosure. It is therefore understood that further operations before, during, and after the method 1000 of Fig. 10 may be provided, and some other operations may only be described briefly here. The order of operations is interchangeable.

[0078] The method 1000 may be performed to, for example, store the memory device 800D of Fig. 8D, and therefore, some of the reference symbols used above may be reused in the following discussion of method 1000. As set forth above, memory device 800D includes: a memory cell 103 designed in a 4T2R configuration and fabricated over a front side 803 of a substrate 801; and a plurality of metallization layers (e.g., M0, M1, M2, M3, M4), each disposed over the front side 803 of the substrate 801. Memory cell 103 includes: a first WL transistor 250 and a second WL transistor 260 fabricated along a major surface of the front side 803 of the substrate 801 in the FEOL network; a first CG transistor 230 and a second CG transistor 240, both formed in a first metallization layer (e.g.M2) of the plurality of metallization layers in the BEOL network; and a first fuse resistor 210 and a second fuse resistor 220, both fabricated in a second metallization layer (e.g., M3) of the plurality of metallization layers in the BEOL network.

[0079] The method 1000 begins with an operation 1002 in which, according to various embodiments, a substrate is provided. The substrate is a semiconductor material substrate, for example, silicon. Alternatively, the substrate may include other elemental semiconductor materials, such as germanium. The substrate may also include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The substrate may also include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate includes an epitaxial layer. For example, the substrate may include an epitaxial layer over a bulk semiconductor. Furthermore, the substrate may be a semiconductor-on-insulator (SOI) structure.For example, the substrate may include a buried oxide (BOX) layer formed by a process such as SIMOX (separation by implantation of oxygen) or by another suitable process such as wafer bonding and grinding.

[0080] The method 1000 continues with an operation 1004 in which, according to various embodiments, a stack containing an alternating sequence of first and second nanostructures is fabricated. Such a stack may be fabricated based on one of the (active area) structures discussed above. The stack may be fabricated in a front side of the substrate. In some embodiments, the first nanostructures may be sacrificial SiGe nanostructures, and the second nanostructures may be Si channel structures. This stack may be referred to as a superlattice. In one non-limiting example, the sacrificial SiGe nanostructures may contain 25% SiGe. The phrase "25% SiGe" is used to indicate that 25% of the SiGe material is Ge.It is understood that the percentage of Ge in each of the sacrificial SiGe nanostructures can take any value between 0 and 100 (except 0 and 100), which is within the scope of the present disclosure. In some further embodiments, the second nanostructures may include a first semiconductor material other than Si, and the first nanostructures may include a second semiconductor material other than SiGe, as long as the first and second semiconductor materials are each characterized by different etching properties (e.g., etching rates).

[0081] The alternating sequence of nanostructures can be created by first growing one layer and then another epitaxially until the desired number and thickness of nanostructures are achieved. Epitaxial materials can be grown from gaseous or liquid precursors. Epitaxial materials can be grown by vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable techniques. Epitaxial silicon, silicon germanium, and / or carbon-doped silicon (Si:C silicon) can be doped during deposition (in situ) by adding n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor.

[0082] The method 1000 continues with an operation 1006 in which, according to various embodiments, a plurality of dummy gate structures are formed. Each dummy gate structure may be formed based on one of the gate structures discussed above. The dummy gate structure may extend along a direction perpendicular to a longitudinal direction of a dielectric fin structure (and the stack). Furthermore, in one of various embodiments, the dummy gate structure may be formed shorter than the dielectric fin structure, and thus the formed dummy gate structure is severed (or otherwise separated) by the dielectric fin structure.

[0083] The dummy gate structure can be formed by depositing amorphous silicon (a-Si) over the stack. Other materials suitable for forming dummy gates (e.g., polysilicon) can also be used, which is also within the scope of the present disclosure. The a-Si is then planarized to a desired level. A hard mask is deposited over the planarized a-Si, which is then patterned. The hard mask can be made of a nitride or an oxide layer. The a-Si is then subjected to an etching process, e.g., an RIE (reactive ion etching) process, to form the dummy gate structure. After forming the dummy gate structure, gate spacers can be formed to extend along sidewalls of the dummy gate structure. The gate spacers can be formed by conformally depositing a dielectric material (e.g.,silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC or a combination of these materials) and subsequent directed etching (e.g. by RIE).

[0084] The method 1000 proceeds to an operation 1008 in which, according to various embodiments, internal spacers are formed by replacing end portions of each of the sacrificial SiGe nanostructures with a dielectric material. After the dummy gate structure has been formed over certain portions of the stack (e.g., the portions of the stack separated by the dielectric fin structure), the uncovered portions of the stack are removed. Then, respective end portions of each sacrificial SiGe nanostructure of the covered stack are removed. The internal spacers are formed by filling these recesses of each sacrificial SiGe nanostructure with a dielectric material by chemical vapor deposition (CVD) or by monolayer doping (MLD) of nitride, followed by spacer RIE.The internal spacers may be made of the same material as or a different material than the gate spacers described above. For example, the internal spacers may be made of silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon carbon oxide nitride, or another type of dielectric material (e.g., a dielectric material with a dielectric constant k of less than about 5).

[0085] The method 1000 proceeds to an operation 1010 in which, according to various embodiments, a plurality of epitaxial structures are fabricated. After the internal spacers are fabricated, the epitaxial structures are fabricated using an epitaxial layer growth process on exposed ends of the Si nanostructures. To fabricate doped epitaxial structures, in-situ doping (ISD) can be used, thereby creating the required connections for a corresponding transistor (or sub-transistor). By implanting different types of dopants into selected regions of the device, n- and p-FETs are fabricated to create the required connections. N-type devices can be fabricated by implanting arsenic (As) or phosphorus (P), and p-type devices can be fabricated by implanting boron (B). After the epitaxial structures are fabricated, an interlayer dielectric (e.g.,Silicon dioxide) is deposited to cover the epitaxial structures.

[0086] The method 1000 proceeds to an operation 1012 in which, according to various embodiments, the dummy gate structures and the remaining sacrificial SiGe nanostructures are replaced with respective active gate structures. After deposition of the interlayer dielectric, the dummy gate structures are removed using an etching process, e.g., RIE or chemical oxide removal (COR). Then, the remaining sacrificial SiGe nanostructures are removed, leaving the Si channel nanostructure substantially intact by using a selective etch, e.g., with hydrochloric acid (HCl). After removal of the sacrificial SiGe nanostructures, top and bottom surfaces and sidewalls of each of the Si channel nanostructures may be exposed, except for the sidewall that is in contact with the dielectric fin structure.Then, multiple active gate structures can be fabricated to enclose each of the Si channel nanostructures, except for the sidewall that contacts the dielectric fin structure. The active gate structures each include at least one gate dielectric layer (e.g., a high-k dielectric layer) and one gate metal layer (e.g., a work function metal layer). After the active gate structures are fabricated, the transistors of the memory device can be fabricated. For example, in . Fig. 8D, a first WL transistor 250 and a second WL transistor 260 of the memory device 800D are formed along a main surface of the front side 803 of the substrate 801 in the FEOL network.

[0087] The method 1000 proceeds to an operation 1014 in which, according to various embodiments, a plurality of front-end interconnect structures are fabricated. After the WL transistors (e.g., 250 and 260) are fabricated, a plurality of middle-end interconnect structures (e.g., VGs, MDs) are fabricated over the transistors. In Fig. 8B, for example, several VG S(e.g., VG1 and VG2) can be fabricated to connect to gate terminals of the transistors, respectively, and multiple MDs (e.g., 822, 824, and 826) can be fabricated to connect to source / drain terminals of CG transistors 230 and 240. Furthermore, multiple back-end interconnect structures can be fabricated above the middle-end interconnect structures. These back-end interconnect structures include the aforementioned Mo traces (e.g., 832, 834, 836, 838) in the M0 layer and further metal traces (e.g., 852, 854, 872, 874, 876, 878) in upper metallization layers (e.g., M1, M2, M3, M4). At least the VG S Each of the WL transistors 250 and 260 can be gated. For example, the WL transistors 250 and 260 can be gated together with WL1, as shown in Fig. 8B is shown.

[0088] The front-side interconnect structure can be made of a metallic material. The metallic material can be selected from the group consisting of aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. Other metallic materials are also within the scope of the present disclosure. The front-side interconnect structures can be formed by covering the front side of the substrate with the aforementioned metallic materials, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating, electroplating, or combinations thereof.

[0089] The method 1000 proceeds to an operation 1016 in which a first and a second CG transistor are formed in a first of the plurality of metallization layers in the BEOL network over the first and second WL transistors. At least some of the aforementioned processes used to form the WL transistors may also be used to form the CG transistors. Fig. 8D, for example, in memory device 800D, the first CG transistor 230 and the second CG transistor 240 are formed in a metallization layer M2 in the BEOL network above the first WL transistor 250 and the second WL transistor 260 formed in the FEOL network. The front-side interconnect structures gate the first and second CG transistors 230 and 240, respectively, and connect them in series with the first and second WL transistors 250 and 260, respectively.

[0090] The method 1000 proceeds to an operation 1018 in which a first and a second fuse resistor are formed in a second of the plurality of metallization layers in the BEOL network over the first and second WL transistors. In Fig. 8D, a first and a second fuse resistor 210 and 220 are formed in the memory device 800D in a metallization layer M3. Through the front-side interconnect structures, the first fuse resistor 210 and the second fuse resistor 220 are commonly connected to a bit line BL0, the first fuse resistor 210 is connected between the first CG transistor 230 and BL0, and the second fuse resistor 220 is connected between the second CG transistor 240 and BL0. As shown in Fig. 8D, the M4 trace 862 may be implemented to be part of the bit line BL0.

[0091] The method 1000 proceeds to an operation 1020 in which, according to various embodiments, a plurality of back-side interconnect structures are formed. After forming the back-end metal traces, the substrate is flipped, and a plurality of back-side interconnect structures (e.g., BM0, BM1, BM3 traces) are formed over the backside of the substrate. After the substrate has been flipped, a polishing process may, for example, be performed on the backside of the substrate until a bottom side of the epitaxial structures (e.g., the source / drain terminals formed in operation 1010) is exposed. One or more dielectric layers are then formed over the polished backside, and subsequently, back-side via structures are formed, each of which may extend through the one or more dielectric layers to reach the bottom side of a corresponding epitaxial structure.Then the rear interconnect structures can be manufactured in respective rear metallization layers.

[0092] The backside interconnect structure is made of a metallic material. The metallic material can be selected from the group consisting of aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. Other metallic materials are also within the scope of the present disclosure. The backside interconnect structures can be formed by covering the backside of the substrate with the aforementioned metallic materials, for example, by CVD, PVD, electroless plating, electroplating, or combinations thereof.

[0093] Fig. 11 shows an exemplary representation of a thin film transistor 1100 according to some embodiments. In some embodiments, the Fig. 11 can be implemented as the CG transistors 230 and 240 shown in the Fig. 8A to 9C. As shown in Fig.11, the thin-film transistor 1100 includes a bottom gate 1116; a gate dielectric 1118 disposed over the bottom gate 1116; a channel structure 1120 disposed over the gate dielectric 1118; and a pair of source / drain structures 1122 and 1124 disposed over the channel structure 1120. The thin-film transistor 1100 may be referred to as a "two-dimensional back-gate transistor" or a "2D transistor." The term "two-dimensional back-gate transistor" may refer to a transistor whose gate is fabricated as a relatively planar or thinner structure and whose channel structure contacts a top surface of its gate. In some embodiments, the bottom gate 1116 includes TiN, the gate dielectric 1118 includes a high-k dielectric material (such as HfO2), the channel structure 1120 includes InGaZnO (IGZO), and the source / drain structures 322 and 324 include TiN.

[0094] In one aspect of the present disclosure, a memory device is disclosed. The memory device comprises: an array including a plurality of one-time programmable (OTP) memory cells fabricated over one side of a substrate; a plurality of word lines (WLs); a plurality of bit lines (BLs); and a plurality of control gate lines (CG lines). Each of the OTP memory cells includes a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first and second fuse resistors are connected to a corresponding one of the BL Sconnected, while the first and second transistors are gated by first and second CG lines, respectively. The first transistor, the second transistor, the first fuse resistor, and the second fuse resistor are fabricated in first, second, third, and fourth of a plurality of metallization layers disposed on the substrate side, respectively.

[0095] In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory cell fabricated over one side of a substrate. The memory cell includes: a first fuse resistor; a second fuse resistor; a first transistor connected in series with the first fuse resistor; and a second transistor connected in series with the second fuse resistor. The memory cell is configured to randomly provide a first logic state when the first fuse resistor is blown or randomly provide a second logic state when the second fuse resistor is blown.The first transistor, the second transistor, the first fuse resistor and the second fuse resistor are formed in a first, a second, a third and a fourth of a plurality of metallization layers, each disposed on the side of the substrate.

[0096] In yet another aspect of the present disclosure, a method of fabricating a memory device is disclosed. The method includes: forming first and second wordline transistors along a major surface on one side of a substrate; forming a first of a plurality of metallization layers disposed over the first and second wordline transistors; forming a second of the plurality of metallization layers over the first of the plurality of metallization layers; forming first and second control gate transistors in the second of the plurality of metallization layers; forming a third of the plurality of metallization layers over the first of the plurality of metallization layers; and forming first and second fuse resistors in the third of the plurality of metallization layers.The first and second word line transistors are gated together and are commonly connected to an operating voltage line. The first and second control gate transistors are each gated. The first fuse resistor is connected between the first control gate transistor and a bit line, and the second fuse resistor is connected between the second control gate transistor and the bit line.

[0097] The terms "about" and "approximately" as used herein generally indicate a value of a given quantity that may vary based on a particular technology node associated with the semiconductor device of the invention. Depending on the particular technology node, the term "about" may indicate a value of a given quantity that varies within a range of, for example, 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0098] Features of various embodiments have been described above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other methods and structures for achieving the same objectives and / or obtaining the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent interpretations do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 584,220

[0001] Cited non-patent literature

[0000] A PUF STRUCTURE ON METAL FUSE WITH BEOL TANANSISTOR“ (“PUF structure on a metal fuse with BEOL transistor

[0001]

Claims

[1] Storage device with: a matrix comprising a plurality of one-time programmable (OTP) memory cells fabricated over one side of a substrate; a plurality of word lines (WL S ; a plurality of bit lines (BL S ; and a plurality of control gate lines (CG lines), where each of the OTP memory cells has a first fuse resistor, a second fuse resistor, a first transistor and a second transistor, wherein the first and second fuse resistor with a corresponding BL S are connected, while the first and second transistors are gated by a first and a second of the CG lines, respectively, and the first transistor, the second transistor, the first fuse resistor and the second fuse resistor are fabricated in a first, a second, a third and a fourth of a plurality of metallization layers, each disposed on the side of the substrate. [2] The memory device of claim 1, wherein the first, second, third, and fourth of the plurality of metallization layers are formed over the side of the substrate, the first and second of the plurality of metallization layers being identical to each other. [3] The memory device of claim 1 or 2, wherein the first and second of the plurality of metallization layers are different from the third and fourth of the plurality of metallization layers. [4] A memory device according to any one of the preceding claims, wherein the OTP memory cells are arranged over a plurality of columns and a plurality of rows, each of the rows having a corresponding one of the WL S and each of the columns has a corresponding BL S and a corresponding pair of CG lines. [5] A memory device according to any preceding claim, wherein each of the OTP memory cells further comprises a third and a fourth transistor formed along a major surface of the side of the substrate, the third and fourth transistors being connected in common by a corresponding one of the WL S are gated. [6] A memory device according to claim 5, wherein the first fuse resistor, the first transistor and the third transistor are connected in series between the corresponding BL and an operating voltage line carrying a supply voltage, and the second fuse resistor, the second transistor and the fourth transistor are connected in series between the corresponding BL and the operating voltage line. [7] A memory device according to any preceding claim, wherein each of the OTP memory cells further comprises a third transistor formed along a major surface of the side of the substrate, the third transistor being formed by a corresponding one of the WL S is gated. [8] A memory device according to claim 7, wherein the first fuse resistor, the first transistor and the third transistor are connected in series between the corresponding BL and an operating voltage line carrying a supply voltage, and the second fuse resistor, the second transistor and the third transistor are connected in series between the corresponding BL and the operating voltage line. [9] A memory device according to any preceding claim, wherein each of the OTP memory cells is configured to permanently provide a logic state based on whether the first or second fuse resistor is randomly blown. [10] The memory device of claim 9, wherein the logic state is identified based on the activation of the first or second transistor. [11] Storage device comprising: a memory cell fabricated over one side of a substrate and comprising: a first fuse resistor; a second fuse resistor; a first transistor connected in series with the first fuse resistor; and a second transistor connected in series with the second fuse resistor, wherein the memory cell is configured to randomly provide a first logic state when the first fuse resistor is blown, or to randomly provide a second logic state when the second fuse resistor is blown, and the first transistor, the second transistor, the first fuse resistor and the second fuse resistor are fabricated in a first, a second, a third and a fourth of a plurality of metallization layers, each disposed on the side of the substrate. [12] A memory device according to claim 11, wherein the first, second, third and fourth of the plurality of metallization layers are formed over the side of the substrate, the first and second of the plurality of metallization layers being identical to each other, and either the first logical state or the second logical state functions as a bit of a PUF signature (PUF: Physically Unclonable Function) for the memory cell. [13] A memory device according to claim 11 or 12, wherein the memory cell further comprises: a third transistor connected in series with the first transistor; and a fourth transistor connected in series with the second transistor, wherein the third and fourth transistors are fabricated along a main surface of the side of the substrate. [14] The memory device of claim 13, wherein the third and fourth transistors are activated simultaneously and the first and second transistors are activated simultaneously when the memory cell is programmed to randomly blow the first or second fuse resistor. [15] The memory device of claim 13, wherein the third and fourth transistors are activated simultaneously and only the first or second transistor is activated when the memory cell is read to identify the first or second logic state. [16] The memory device of claim 11 or 12, wherein the memory cell further comprises: a third transistor connected in series with each of the first and second transistors, the third transistor being formed along a main surface of the side of the substrate. [17] The memory device of claim 16, wherein the third transistor is activated and the first and second transistors are activated simultaneously when the memory cell is programmed to randomly blow the first or second fuse resistor. [18] The memory device of claim 16, wherein the third transistor is activated and only the first or second transistor is activated when the memory cell is read to identify the first or second logic state. [19] A method of manufacturing a memory device, comprising: forming a first and a second word line transistor along a main surface on one side of a substrate; forming a first of a plurality of metallization layers disposed over the first and second wordline transistors, the first and second wordline transistors being gated together and commonly connected to an operating voltage line; forming a second of the plurality of metallization layers over the first of the plurality of metallization layers; forming a first and a second control gate transistor in the second of the plurality of metallization layers, wherein the first and second control gate transistors are each gated; forming a third of the plurality of metallization layers over the first of the plurality of metallization layers; and Forming a first and a second fuse resistor in the third of the plurality of metallization layers, wherein the first fuse resistor is connected between the first control gate transistor and a bit line and the second fuse resistor is connected between the second control gate transistor and the bit line. [20] The method of claim 19, wherein the third of the plurality of metallization layers is higher than the second of the plurality of metallization layers.

Images