Device for detecting an addressing current in a bus shunt configuration of a participant of a communication bus system in an address allocation phase

Abstract

The device for detecting an addressing current in a bus shunt configuration of a participant in a communication bus system during an address allocation phase allows the selection of the participant to be addressed according to one of two different bus shunt configurations as well as one of two addressing current supply variants. The two bus shunt configurations differ in that in one case the participant is only connected via an internal bus shunt (R int ), while in the second case it has a parallel connection from the internal bus shunt (R int ) and an external bus shunt (R ext ). When selecting the addressing current supply, a distinction is made between the supply to the bus connection (28) facing the respective bus master (16) or to the bus connection (24) facing away from the bus master (16).

Description

[0001] The invention relates to a device for detecting an addressing current in a bus shunt configuration of a subscriber of a communication bus system during an address allocation phase. The communication bus system has a bus master connected to a communication bus to which several subscribers are serially connected. The relative positions of the subscribers within the communication bus are defined below as "downstream" and / or "upstream". This definition is made "from the perspective of the bus master", meaning that all subscribers are arranged downstream of the bus master. Of the subscribers, one subscriber is the subscriber connected to the communication bus closest to the bus master downstream of the communication bus, and another subscriber is the subscriber connected to the communication bus furthest away from the bus master downstream of the communication bus.Additional participants are connected to the communication bus between these two participants. A participant that is connected to the communication bus adjacent to another participant towards the bus master is therefore located upstream of that other participant. Accordingly, a participant that is connected to the communication bus further away from the bus master than its neighbor is connected to the communication bus downstream of that neighbor. During the address assignment phase, in several consecutive address assignment cycles, one of the participants that has not yet been assigned an address is successively identified as the participant to which an address can be assigned by the bus master. After receiving its address, this participant no longer participates in subsequent address assignment cycles.The successive identification of the only device to be assigned an address by the bus master always concerns the device connected to the communication bus furthest downstream of the bus master from the group of devices not yet assigned an address. The "second-to-last device" in this respect is therefore a device connected to the communication bus upstream of this "last device," while the "last device" is the device connected to the communication bus downstream of the "second-to-last device" (and all other devices connected to the communication bus between the "second-to-last device" and the bus master).

[0002] In serial communication bus systems, the individual devices connected serially to a communication bus originating from a bus master are preferably addressed automatically. This occurs in several consecutive address assignment cycles within an address assignment phase, which typically occurs during the initialization of the communication bus system, for example, each time the communication bus system is started up. For each address assignment cycle, the device that is furthest downstream of the master from the communication bus is identified among the not yet addressed devices. The not yet addressed devices each feed an addressing stream into the communication bus.Each subscriber has an internal bus shunt, whereby in a first variant the addressing current supplied by the subscriber is fed directly into the communication bus so that it does not flow through its internal bus shunt. This means that the last subscriber connected to the communication bus, i.e. the one furthest from the bus master, essentially detects a voltage drop of 0 via its internal bus shunt (a quiescent current that may flow through this to stabilize the communication bus is not taken into account here), while the other subscribers connected upstream of said last subscriber, which have not yet been addressed, each detect a voltage drop greater than a predetermined threshold (close to 0 V) via their internal bus shunt resistors. Thus, the last subscriber connected to the communication bus furthest from the bus master identifies itself.If the bus master then places an address on the communication bus, only this last participant takes over this address as its address.

[0003] The participant addressed in this way no longer participates in subsequent address assignment cycles. An example of such a bus system with automatic participant addressing is described in DE 10 2018 104 852.

[0004] Typically, each address assignment cycle is preceded by a preselect phase in which a group of "last devices" is selected from the multitude of not yet addressed devices. This group includes the not yet addressed devices that are furthest from the bus master on the communication bus compared to the other not yet addressed devices. These preselect phases are generally known and serve to protect the communication bus from overload due to the injection of the addressing current by all not yet addressed devices. The specific features of this preselect phase will not be discussed further here, as they are generally known.

[0005] However, there are also configurations in which, in addition to the internal bus shunt per participant, an external bus shunt is connected to the communication bus. Thus, the bus shunt configuration per participant comprises a parallel connection of an external and internal bus shunt. The resistance value of the external bus shunt is typically smaller than that of the internal bus shunt, so that the series connection results in a total bus shunt with a value that is smaller than the smaller of the two bus shunts connected in parallel. An example of such a bus system with automatic addressing of the bus participants is known from DE 10 2018 104 488.

[0006] It is obvious that, depending on the bus shunt configuration, different thresholds must be provided for the detection of the addressing current in the last unaddressed device. Devices designed for both bus shunt configuration variants therefore require different circuit concepts. In particular, the gain factors of the amplifier that receives the voltage drop across the internal bus shunt alone or via the parallel connection of the internal and external bus shunt resistors must be selected differently.

[0007] Another variant for determining the "last" unaddressed station in a serial communications bus system during address assignment involves an addressing current source that feeds its addressing current into the communications bus via the internal bus shunt. The current source is regulated in such a way that the voltage drop between the terminals of the internal bus shunt has a predetermined value. If this voltage drop is reached by feeding in the addressing current, which is also a predetermined value, this is an indication that the station in question is the last unaddressed station, i.e., the unaddressed station furthest connected to the communications bus from the bus master.If, however, the voltage drop of the specified magnitude occurs with an addressing current that is smaller than the specified addressing current, this is a sign that an addressing current is also being fed into the communication bus from a station further downstream of the communication bus. Therefore, the station in question is not the last unaddressed station. Only the unaddressed station that measures the voltage drop of the specified magnitude when the specified addressing current is fed in is the last unaddressed station. Only this station then adopts as its address the address that the bus master subsequently places on the communication bus.

[0008] To cover all three bus shunt configuration and addressing current supply variants with one and the same hardware, multiple pairs of bond pads on the hardware IC would be required to connect to the communication bus. Furthermore, the voltage measurement signals within the device would have to be amplified to different levels to ensure that they can be amplified to the same level for further digital signal processing, despite their different magnitudes. For example, in an analog-to-digital converter (ADC), which requires an input voltage within a specified minimum voltage range for proper and reliable operation.

[0009] The object of the invention is to provide a device for detecting an addressing current in a subscriber of a communication system in an address allocation phase, which reliably covers the aforementioned cases and in particular the first two aforementioned cases and requires as little chip area as possible when integrated into an IC.

[0010] The above object is achieved according to the invention by a device for detecting an addressing current in a bus shunt configuration of a subscriber of a communication bus system in an address allocation phase, which has a bus master which is connected to a communication bus to which several subscribers are serially connected, of which one subscriber is the subscriber connected to the communication bus closest to the bus master upstream of the communication bus and of which another subscriber is the subscriber connected to the communication bus furthest away from the bus master downstream of the communication bus, wherein further subscribers are connected to the communication bus between these two subscribers, wherein in the address allocation phase in several consecutive address allocation cycles one of the subscribers not yet provided with an address is successively identified as the subscriberto which an address can be assigned by the bus master and this participant no longer participates in subsequent address allocation cycles after receiving its address. The device according to the invention is provided with, - a first bus connection and a second bus connection, wherein the first bus connection is connectable to the communication bus via a first external electrical conductor downstream of the communication bus at a first connection point, and the second bus connection is connectable to the communication bus via a second external electrical conductor upstream of the communication bus at a second connection point, - an internal bus shunt with a first connection and a second connection, - a first internal bonding wire between the first bus terminal and the first terminal of the internal bus shunt, - a second internal bonding wire between the second bus terminal and the second terminal of the internal bus shunt, - a first addressing current source connected to the second bus connection of the subscriber or to the second connection of the internal bus shunt of the subscriber for feeding an addressing current into the first bus connection and / or into the second bus connection, - an amplifier having a first input terminal and a second input terminal and having an output terminal, - wherein the first input terminal of the amplifier is connected to the first terminal of the internal bus shunt and the second input terminal of the amplifier is connected to the second terminal of the internal bus shunt, and the amplifier outputs a voltage measurement signal between its two input terminals amplified by a predetermined gain factor as an output signal at its output terminal, and - an electronic evaluation unit (with e.g. A / D and D / A converters, microcontroller, CPU, I / O interfaces, ROM, RAM) for evaluating the output signal of the amplifier and for determining, by comparing the size of the output signal with a selected one of several threshold values, which of the not yet addressed participants is the participant connected to the communication bus downstream of the communication bus and furthest away from the bus master, if necessary after an analogue-to-digital conversion, - wherein in the address allocation phase the evaluation in the evaluation unit is carried out depending on the choice of operation of the communication bus system according to one of several operating modes, wherein - in a first operating mode, the communication bus does not have an additional external bus shunt per participant and thus a first bus shunt configuration is provided in which the communication bus has the internal bus shunt per participant and the voltage difference between the two terminals of the internal bus shunt forms the measuring voltage signal, wherein in this first operating mode, the comparison of the output signal of the amplifier with a first threshold value takes place, wherein the output signal of the amplifier of only one of the participants feeding an addressing current into the communication bus is smaller than the first threshold value, and - in a second operating mode, the communication bus has an additional, external bus shunt for each subscriber, which is arranged in the communication bus between the two connection points of the communication bus for the two external electrical conductors of a bus subscriber, thus creating a second bus shunt configuration in which the communication bus has a parallel circuit comprising the external bus shunt and the internal bus shunt for each subscriber, and the voltage difference between the two terminals of the internal bus shunt forms the measuring voltage signal, wherein in this second operating mode the output signal of the amplifier is compared with a second threshold value which is different from the first threshold value, wherein the output signal of the amplifier of only one of the subscribers feeding an addressing current into the communication bus is smaller than the second threshold value.

[0011] A key feature of the invention is the ability to operate the amplifier amplifying the voltage measurement signal with the same gain factor for both possible bus shunt configurations. In this regard, a compromise was found regarding the different magnitudes of the voltage measurement signal, which, with the same addressing current in the communication bus, flows either through the internal bus shunt alone or through the parallel connection of the external and internal bus shunts.

[0012] An advantage of operating the amplifier with the same average gain for both cases is that the measurement time is essentially the same in both cases. The reason for this is that a voltage measurement with low gain is faster than a voltage measurement with high gain due to the reduced bandwidth at high gain. By selecting the same average gain, the measurements are equally fast in both operating modes—i.e., in communication bus systems with the first bus shunt configuration and in bus communication systems with the second bus shunt configuration.

[0013] The elimination of a pair of connection pads and the multiplexer (which is required in the state of the art to select the measurement voltage (voltage drop) assigned to the respective bus shunt configuration via only the internal bus shunt or via the parallel connection of internal and external bus shunt and to switch it to the amplifier) also results in the advantage of reduced chip area requirements.

[0014] In a further advantageous embodiment of the invention, it is provided that in an address allocation phase, all participants to which no address has yet been assigned, or that in an address allocation phase, a group of neighboring participants not yet having an address, which are arranged downstream of the communication bus and which include the not yet addressed participant furthest from the bus master connected to the communication bus, each feed an addressing current into the communication bus by means of their addressing current sources, and that by comparing the output signal of the amplifier with the first threshold value or with the second threshold value in each of these participants, the participant whose measurement signal is smaller than the first threshold value or smaller than the second threshold value is identified as the participant connected to the communication bus furthest from the bus master downstream of the communication bus.Identifies a participant that has not yet been assigned an address, allowing the bus master to assign an address to this participant.

[0015] As already described above, it is usual that in a preselect phase preceding the address allocation phase, all participants that have not yet been assigned an address feed a preselect current into the communication bus using their addressing current sources and that the evaluation unit of each participant in the preselect phase compares the output signal of the amplifier with a selected one of several further threshold values, whereby - in the first operating mode, the comparison of the output signal of the amplifier with a third threshold value different from the first threshold value, which is smaller or larger than the first threshold value, or with the first threshold value, and - in the second operating mode, the output signal of the amplifier is compared with a fourth threshold value which is different from the second threshold value and is smaller or larger than the second threshold value, or with the second threshold value.

[0016] It can further be advantageously provided that, by comparing the amplifier output signal with the third or first threshold value or with the fourth or second threshold value in each of these participants in the preselect phase, those participants are identified as belonging to a group of participants whose amplifier output signals are smaller than the third or first threshold value or smaller than the fourth or second threshold value, wherein, among the participants in this group, in the address allocation cycle following the preselect phase, in which only the participants in this group feed their addressing streams into the communication bus, an address can be assigned by the bus master to that participant which can be identified as the participant connected to the communication bus furthest downstream of the communication bus from the bus master.

[0017] In a further alternative for address allocation, there is a further addressing current source connected to the first bus connection of the subscriber or there is a connection switching unit for selectively connecting the first addressing current source to either the second bus connection of the subscriber or the first bus connection of the subscriber, wherein the electronic evaluation unit has an addressing current controller, wherein in a third operating mode downstream, ievia the first bus connection of the subscriber, an addressing current can be fed into the communication bus by the further addressing current source or by the first addressing current source connected to the first bus connection of the subscriber by means of the connection switching unit, the size of which addressing current is representative of the voltage measurement signal, wherein the addressing current regulator regulates the size of the addressing current to a value at which an output signal is set at the amplifier which is equal to a fifth threshold value, and wherein, of the subscribers not yet addressed, the subscriber whose further addressing current source or whose first addressing current source feeds an addressing current with a predetermined size into the communication bus (while the (first orfurther) addressing current sources of all other not yet addressed participants feed in less or no addressing current).

[0018] In the inventive concept, the amplifier operates with the same average gain factor in both operating mode 1 (hereinafter referred to as Type 1) and operating mode 2 (hereinafter referred to as Type 2). In principle, the gain factor in Type 2 would have to be higher than in Type 1 due to the smaller overall bus shunt value due to the parallel bus shunt connection compared to Type 1. However, it has been found within the scope of the invention that the voltage measurement signal can be sufficiently amplified in both operating modes with one and the same average gain factor so that it can then be pre-processed by the ADC of an electronic evaluation unit, which has, among other things, a microcontroller, CPU, I / O interfaces, ROM, RAM, with sufficient quality for further digital signal processing, for example to decide whether the respective threshold values have been exceeded or not.The “average gain” is considered to be a gain that lies between the “ideal” gains for each operating mode (e.g. arithmetic mean or weighted mean or within an arithmetic or weighted mean range).

[0019] The addressing current for operating modes 1 and 2, for example, is approximately 2 mA. The internal bus shunt, for example, is approximately 1 Ω. In contrast, the resistance of the external bus shunt is about an order of magnitude smaller. It is, for example, 0.2 Ω to 0.3 Ω. This means that the gain in the second operating mode would have to be about five times higher than the gain in the first operating mode. However, it has been shown that the ADC can always be operated within its (nominal) operating point or range if a medium gain is used in both cases.

[0020] In the third operating mode, it is also possible to work with the same gain factor. The addressing current fed in the third operating mode (hereinafter also referred to as Type 3) is approximately 10 mA. This is roughly five times the addressing current of approximately 2 mA in the first and second operating modes. The higher addressing current in Type 3 results in a larger, i.e. approximately five times larger, voltage drop across the parallel circuit of the two bus shunt resistors, so that it would in principle be possible to work with a smaller gain factor. As already mentioned, the invention provides for this third operating mode to also work with the same average gain factor used for operating modes 1 and 2, so that the ADC is again operated in its (nominal) operating point or range.

[0021] In the preselect phase, which applies to the first and second operating modes, an extremely low preselect addressing current, e.g., 300 µA, i.e., approximately 1 / 10 of the addressing current, is used. Those devices that internally detect a voltage measurement signal that, after amplification, has a value lower than a prescribed threshold, are preselected. From this group of last devices, the last device in this group of the last unaddressed devices is then selected using the address assignment cycle. As stated, this procedure is state of the art and will therefore not be discussed further.

[0022] The invention is explained in more detail below using an exemplary embodiment and with reference to the drawing. In detail: Fig. 1 and Fig. 2 Block diagrams of two state-of-the-art circuits of devices connected to a serial communication bus for address allocation in a bus shunt configuration according to operating mode 1 or operating mode 2 ( Fig. 1) or when addressing according to each of these two operating modes and according to the third operating mode ( Fig. 2), Fig. 3 the block diagram according to a first embodiment of the invention in operating mode 1, ie without external bus shunt, Fig. 4 the block diagram according to the first embodiment of the invention in operating mode 2, ie with internal and external bus shunt, Fig. 5 the block diagram according to the second embodiment of the invention for optionally one of the three operating modes 1 to 3, shown here for operating mode 1, ie without external bus shunt, Fig. 6 the block diagram according to the second embodiment of the invention, due to the now present external bus shunt optionally operable in operating mode 2 or 3, Fig. 7 a variant of the circuit according to Fig. 6 for one of the operating modes 1 to 3, shown here for operating mode 1, ie without external bus shunt, and Fig. 8 the variant of the circuit according to Fig. 7, can be operated either in operating mode 2 or 3 due to the now existing external bus shunt.

[0023] As already mentioned in the introduction to the description, it is generally known that in each participant 10 of a serial communication bus system, such as LIN, a device 12 is installed, which serves, among other things, to detect an addressing current flowing through the participant 10 during address assignment. The communication bus 14 has a plurality of participants 10 and, in addition, also a bus master 16. In Fig. 1 (as well as in all subsequent figures), it is indicated in the communication bus 14 above and below the participant 10 shown in detail with its device 12 that further participants are connected to the communication bus 14. In addition, the current source 18 symbolizes that the participant 10 shown with the detailed device 12 receives a current from downstream of the communication bus 14 (as seen from the bus master 16) during the address allocation phase. This current results from the addressing currents fed into the communication bus 14 by participants arranged further downstream of the communication bus.

[0024] The device 12 comprises an integrated circuit in an IC die 20, which in this exemplary embodiment has a plurality of connection pads. These connection pads are connected to bus connections of an IC package 22 via bond wires. A first bus connection 24 of the IC package 22 is connected to a first communication bus connection point 26, while a second bus connection 28 of the IC package 22 is connected to a second communication bus connection point 30. The first bus connection 24 is connected to a first connection pad 34 of the IC die 20 via a first bond wire line 32, while a second bond wire line 36 connects the second bus connection 28 of the IC package 22 to a second connection pad 38 of the IC die 20. These bond wire lines and all others are referred to below for short as bond wire or bond wires. The two connection pads 34, 38 form the connections for an internal bus shunt R int. The terminals 34, 38 are equal to the first and second terminals 34', 38' of the internal bus shunt R int .

[0025] The two bus terminals 24 and 28 are further connected to further connection pads 44, 46 of the IC die 20 by further bonding wires 40, 42. Finally, the IC die 20 has an additional connection pad 48, to which the output of an addressing current source 50 of the device 12 is connected and which, in turn, is connected to the second bus terminal 28 via a bonding wire 49.

[0026] The device 12 further comprises a connection switching unit 52 (hereinafter referred to as multiplexer) having two inputs 54, 56 and one output 58. One of the two inputs 54 is supplied by the two terminals 34, 38 of the internal bus shunt R intformed, while the other input 56 is formed by the two further connection pads 44, 46 of the IC die 20. At one input 54, the voltage drop is across the internal bus shunt R int while the other input 56 receives the voltage difference between the two other connection pads 44, 46. If the communication bus 14 per participant 10 is connected to an external bus shunt R ext , the voltage between the connection pads 44 and 46 is identical to the voltage between the bus connections 24 and 28, since no current flows through the bond wires 40, 42. Instead, a current flows through the bond wires 32, 36 via R int , whereby the voltage at the connection pads 34,38 is lower than at the connection pads 44,46, since the bond wires 32,36 each have a parasitic resistance across which the current flow causes a voltage drop.

[0027] The output 58 of the multiplexer 52 is connected to an amplifier 60, whose gain factor is variably adjustable. The amplified analog output signal of the multiplexer 52 is converted into digital form by an analog-to-digital converter 62 of an evaluation unit 63 for further processing.

[0028] The device 12 according to Fig. 1 allows the automatic addressing of device 10 in two different bus shunt configurations (Type 1, Type 2). In the case of Type 1, only the internal bus shunt R exists. int , while in type 2 of the address allocation procedure the external bus shunt R ext exists.

[0029] As described above, during the address allocation phase, the bus participants each feed an addressing current into the communication bus 14, which flows to the bus master 16. Since this addressing current is fed into the second bus connection 28 (see Fig. 1), the bus current of a participant does not influence the voltage drop across its internal bus shunt R int for type 1 or via the parallel connection of an internal and external bus shunt (for type 2). Therefore, if a voltage drop is detected at the connection pad pairs 34, 38 or 44, 46, this can only have been caused by a current flowing through the communication bus 14 from downstream of the respective device 10, i.e., from the "rear" part of the communication bus 14 (any quiescent current flowing in the communication bus 14 for stabilization purposes will be disregarded here for the sake of simplicity).

[0030] The voltage drop across the internal bus shunt R int in type 1, with the same addressing current flowing into the device 10 via the communication bus 14, the current is greater than in case of type 2, where the two bus shunts R int and R extare connected in parallel and thus their total resistance is due to the difference in comparison to R int by about a power of ten smaller external bus shunt R ext is smaller than R int . Accordingly, the gain factor in amplifier 60 changes (increases). Only the corresponding input is routed to output 58 via multiplexer 52. Both are controlled by a select signal 64.

[0031] The previously described circuit concept of the Fig. 1 is still known in a supplemented form according to the state of the art, which Fig. 2 shows. The additional option concerns the operating mode 3 already described above, in which an addressing current flows through the parallel circuit of internal and external bus shunts for each participant, and is then fed into the communication bus 14 in the direction of the bus master via the second bus connection 28. In Fig. 2, a further bond switching unit 66 (hereinafter referred to as multiplexer) is connected between the output of the addressing current source 50 and the additional connection pad 48 of the IC die 20, one output 68 of which (type 1 and type 2) is connected to the further connection pad 48 and the other output 70 of which (type 3) is connected to an additional connection pad 72 of the IC die 20, which is connected to the first bus connection 24 via a bond wire 74. In operating mode 3 (type 3), the input 76 of the multiplexer 66 is therefore connected to its output 70, whereby the addressing current is fed into the communication bus 14 via the first bus connection 24 and thus via the parallel connection of the two bus shunts. The multiplexer 66 is controlled via a further select signal 78 in order to feed the addressing current into the communication bus 14 either via the first bus connection 24 or via the second bus connection 28.

[0032] In the Fig. 1 and Fig. 2, A1, A2 and A3 indicate the respective amplification factor of the amplifier 60 in the three operating modes (Type 1, Type 2 and Type 3).

[0033] The gain factor depends, among other things, on the analog-to-digital converter 62 operating at its operating point or operating point range and thus reliably. A certain disadvantage of the circuit concepts of the Fig. 1 and Fig. 2 can be seen in the comparatively large chip area requirement, due to the large number of connection pads of the IC die 20 and due to the two multiplexers, in particular due to the multiplexer 52. Finally, the requirement to design the gain factor in a switchable manner is also a certain disadvantage, since the test time for series production is extended because tests must now be carried out for several gain factors.

[0034] The approach according to the invention eliminates all of the disadvantages and limitations mentioned above.

[0035] In the Fig. 3 to 8 show various embodiments of devices according to the invention for detecting the magnitude of addressing currents flowing through the participants of a serial communication bus system during the address allocation phase. As far as the elements of the participant 10 and the communication bus system according to each of the Fig. 3 to 8 those of Fig. 1 and Fig. 2 are the same or similar, they are in the Fig. 3 to 8 with the same reference numerals as in the Fig. 1 and Fig. 2 marked.

[0036] The Fig. 3 and Fig. 4 cover the operating modes 1 and 2, ie the two bus shunt configurations in which either only the internal bus shunt R intis present or in addition to this internal bus shunt also the external bus shunt R ext It can be seen that the multiplexer 52 is Fig. 1 and Fig. 2 can be dispensed with, which also means that the area on the IC die 20 for the two additional connection pads 44, 46 of the Fig. 1 and Fig. 2 can be dispensed with. The amplifier 60 is also simplified in that it operates in both operating modes 1 and 2 with the same average gain factor, which allows both the comparatively large voltage drop signal via the internal bus shunt R intin operating mode 1 (Type 1) so that the analog-to-digital converter 62 operates properly, as well as to sufficiently amplify the relatively small voltage drop signal in operating mode 2 (Type 2 with bus shunt configuration as a parallel circuit of internal and external bus shunt) so that the analog-to-digital converter 62 operates properly.

[0037] In the Fig. 5 and Fig. 6 shows a further embodiment of the device according to the invention, which can be used during the address assignment phase selectively according to one of the operating modes 1 to 3. Whether the addressing current is fed into the first bus connection 24 (type 3) or into the second bus connection 28 (types 1 and 2) is decided by the multiplexer 66, to which the select signal 64 is fed. In all three operating modes, the amplifier 60 can operate with one and the same average gain factor.

[0038] A variant of the circuit concept according to Fig. 5 and Fig. 6 is in the Fig. 7 and Fig. 8. The difference between the concept according to these last two figures and the concept according to the Fig. 5 and Fig. 6 is that for the supply of the addressing current on the IC die 20 the two additional connection pads 48 and 72 (as in the circuit according to Fig. 2) are provided. LIST OF REFERENCE SYMBOLS 10 participants 12 Device 14 Communication bus 16 bus masters 18 Power source 20 IC-Die 22 IC packages 24 first bus connection 26 first communication bus connection point 28 second bus connection 30 second communication bus connection point 32 first bond wire 34 first connection pad 34' first connection of the internal bus shunt 36 second bond wire 38 second connection pad 38' second connection of the internal bus shunt 40 additional bonding wires 42 additional bonding wires 44 additional connection pad 46 additional connection pad 48 additional connection pad 49 Bonding wire 50 Addressing current source 52 Multiplexer (connection switching unit) 54 Entrance 56 Entrance 58 Exit 60 amplifiers 62 analog-to-digital converters 63 Evaluation unit 64 Select signal 66 Multiplexer (connection switching unit) 68 Exit 70 Exit 72 additional connection pad 74 bonding wire 76 Entrance 78 additional select signal R int internal bus shunt R ext external bus shunt

Claims

[1] Device for detecting an addressing current in a bus shunt configuration of a subscriber of a communication bus system in an address allocation phase, which has a bus master (16) which is connected to a communication bus (14), to which a plurality of subscribers (10) are serially connected, of which one subscriber (10) is the subscriber (10) connected to the communication bus (14) closest to the bus master (16) downstream of the communication bus (14) and of which another subscriber (10) is the subscriber (10) connected to the communication bus (14) furthest away from the bus master (16) downstream of the communication bus (14), wherein further subscribers (10) are connected to the communication bus (14) between these two subscribers (10),wherein in the address allocation phase, in several consecutive address allocation cycles, one of the subscribers (10) not yet provided with an address is successively identified as the subscriber (10) to which an address can be assigned by the bus master (16), and said subscriber (10) no longer participates in subsequent address allocation cycles after receiving its address, and wherein the device (12) is provided with, - a first bus connection (24) and a second bus connection (28), wherein the first bus connection (24) is connectable to the communication bus (14) via a first external electrical conductor downstream of the communication bus (14) at a first connection point (26) and the second bus connection (28) is connectable to the communication bus (14) via a second external electrical conductor upstream of the communication bus (14) at a second connection point (30), - an internal bus shunt (R int) with a first connection (34') and with a second connection (38'), - a first internal bonding wire line (32) between the first bus terminal (28) and the first terminal (34') of the internal bus shunt (R int ), - a second internal bonding wire line (36) between the second bus terminal (28) and the second terminal (38') of the internal bus shunt (R int ), - one with the second bus connection (28) of the subscriber (10) or with the second connection (38') of the internal bus shunt (R int ) of the subscriber (10) for feeding an addressing current into the first bus connection (24) and / or into the second bus connection (28), - an amplifier (60) having a first input terminal and a second input terminal and having an output terminal, - wherein the first input terminal of the amplifier (60) is connected to the first terminal (34') of the internal bus shunt (R int ) and the second input terminal of the amplifier (60) with the second terminal (38') of the internal bus shunt (R int ) and the amplifier (60) outputs a voltage measurement signal between its two input terminals amplified by a predetermined gain factor at its output terminal as an output signal, and - an electronic evaluation unit (63) for evaluating the output signal of the amplifier (60) and for determining, on the basis of a comparison of the magnitude of the output signal with a selected one of several threshold values, if necessary after an analog-to-digital conversion, which of the not yet addressed subscribers (10) is the subscriber (10) connected to the communication bus (14) downstream of the communication bus (14) furthest away from the bus master (16), - wherein in the address allocation phase the evaluation in the evaluation unit is carried out depending on the choice of operation of the communication bus system according to one of several operating modes, wherein - in a first operating mode, the communication bus (14) does not have an additional external bus shunt (R ext ) per participant (10) and thus a first bus shunt configuration is given, in which the communication bus (14) per participant (10) has the internal bus shunt (R int ) and the voltage difference between the two terminals (34', 38') of the internal bus shunt (R int ) forms the measuring voltage signal, wherein in this first operating mode the comparison of the output signal of the amplifier (60) with a first threshold value takes place, wherein the output signal of the amplifier (60) of only one of the participants (10) feeding an addressing current into the communication bus (14) is smaller than the first threshold value, and - in a second operating mode, the communication bus (14) has an additional external bus shunt (R ext ), which is arranged in the communication bus (14) between the two connection points (26, 28) of the communication bus (14) for the two external electrical conductors of a subscriber (10), thus providing a second bus shunt configuration in which the communication bus (14) comprises a parallel circuit consisting of the external bus shunt (R ext ) and the internal bus shunt (R int ) and the voltage difference between the two terminals (34', 38') of the internal bus shunt (R int) forms the measuring voltage signal, wherein in this second operating mode the comparison of the output signal of the amplifier (60) with a second threshold value different from the first threshold value takes place, wherein the output signal of the amplifier (60) of only one of the participants (10) feeding an addressing current into the communication bus (14) is smaller than the second threshold value. [2] Device according to claim 1, characterized bythat in an address allocation phase, all participants (10) to which no address has yet been assigned or a group of neighboring participants (10) not yet having an address, which are arranged downstream of the communication bus (14) and which comprise the not yet addressed participant (10) connected furthest from the bus master (16) to the communication bus (14), each feed an addressing current into the communication bus (14) by means of their addressing current sources (50), and that by comparing the output signal of the amplifier (60) with the first threshold value or with the second threshold value in each of these participants (10), the participant (10) whose measurement signal is smaller than the first threshold value or smaller than the second threshold value is identified as the participant connected furthest from the bus master (16) to the communication bus (14) downstream of the communication bus (14).a subscriber (10) not yet provided with an address is identified, whereby the bus master (16) can assign an address to this subscriber (10). [3] Device according to claim 1 or 2, characterized by that in a preselect phase preceding the address allocation phase, all participants (10) to which no address has yet been assigned each feed a preselect current into the communication bus (14) by means of their addressing current sources (50), and that the evaluation unit (63) of each participant (10) compares the output signal of the amplifier (60) with a selected one of several further threshold values in the preselect phase, wherein - in the first operating mode, the comparison of the output signal of the amplifier (60) with the first threshold value or with a third threshold value different from the first threshold value and smaller or larger than the first threshold value is carried out, and - in the second operating mode, the output signal of the amplifier (60) is compared with the second threshold value or with a fourth threshold value which is different from the second threshold value and is smaller or larger than the second threshold value. [4] Device according to claim 3, characterized bythat by comparing the output signal of the amplifier (60) with the first or with the third threshold value or with the second or with the fourth threshold value in each of these participants (10) in the preselect phase, those participants (10) whose amplifier output signals are smaller than the first or third threshold value or smaller than the second or fourth threshold value are identified as belonging to a group of participants (10), wherein, in the address allocation cycle following the preselect phase, an address can be allocated by the bus master (16) to that participant (10) of the participants (10) of this group which can be identified as the participant (10) connected to the communication bus (14) furthest downstream of the communication bus (14) from the bus master (16). [5] Device according to one of claims 1 to 4, characterized by - a further addressing current source connected to the first bus connection (24) of the subscriber (10) or - a connection switching unit (66) for selectively connecting the first addressing current source (50) to either the second bus connection (28) of the subscriber (10) or the first bus connection (24) of the subscriber (10), - wherein the electronic evaluation unit (63) has an addressing current controller, - wherein in a third operating mode, in which the bus shunt configuration is the same as in the second operating mode, an addressing current can be fed downstream into the communication bus (14) by the further addressing current source or by the first addressing current source (50) connected to the first bus connection (24) of the subscriber (10) by means of the connection switching unit (66), for the magnitude of which addressing current the voltage measurement signal is representative, - wherein the addressing current controller regulates the magnitude of the addressing current to a value at which an output signal is set at the amplifier (60) which is equal to a fifth threshold value, and - wherein of the not yet addressed participants (10), the participant (10) connected to the communication bus (14) furthest downstream of the communication bus (14) from the bus master (16) and thus the only one of the not yet addressed participants (10) whose further addressing current source or whose first addressing current source (50) feeds an addressing current of a predetermined size into the communication bus (14) is identifiable.

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