COMPACT K-XOR SAT FILTERING WITH CAMS

Abstract

Examples of the technique disclosed herein provide CAM-based circuits specifically designed for implementing Boolean satisfiability problems involving k-XOR-SAT clauses. By strategically adding additional counting and logic circuits that evaluate the matching line voltage outputs of a CAM at k discrete time points to determine whether a counted number of matches returned by a matching line satisfies a predefined parity condition—where k is the number of literals of a k-XOR-SAT clause of a Boolean satisfiability problem—a circuit of the present technique can utilize a common CAM (i.e., the same CAM) to implement the k-XOR-SAT clause and k-SAT clauses.Accordingly, this extremely versatile circuit can be used to implement k-XOR-SAT and k-SAT-k-XOR-SAT hybrid problems in less time and with less hardware and power consumption than existing hardware accelerators.

Description

background

[0001] A Boolean satisfiability problem (i.e., a propositional satisfiability problem, abbreviated to satisfiability, SAT, or B-SAT) is a problem that seeks to determine whether an interpretation exists that satisfies a Boolean formula (sometimes referred to herein as a Boolean satisfiability formula). For example, a SAT problem attempts to determine whether the variables of a Boolean formula can be consistently replaced with the values ​​True or False, such that the Boolean formula evaluates to True. If so, the Boolean formula is said to be satisfiable. For example, the Boolean formula "a AND NOT b" is satisfiable because the values ​​a=True and b=False would make the Boolean formula "a AND NOT b" = True. On the other hand, if the variables of the Boolean formula cannot be consistently replaced with the values ​​True or False, such that the Boolean formula evaluates to True, the Boolean formula is unsatisfiable.For example, “a AND NOT a” is not satisfiable.

[0002] A content-addressable memory (“CAM”) is a type of computer memory in which stored data is searched for by its content rather than its location. When a “word” is input into a CAM, the CAM searches for that word in its content. If the ZAV finds the word (i.e., “provides a match”), the ZAV returns the address of the location where the found word is located. Individual cells of a ZAV (i.e., CAM cells) can be arranged in rows and columns. CAM cells in a common row can be connected along a common match line. Words can be stored in the rows of the CAM, and each CAM cell in a particular row can store one entry of a stored word. When the CAM receives an input word (e.g.,a series of voltage signals, each representing an entry of the input word and sometimes referred to herein as an input vector), the CAM can search for the input word entry by entry along the columns of the CAM (i.e., a first entry of the input word can be searched in a first column of the CAM, a second entry of the input word can be searched in a second column of the CAM, etc.). The ZAV can "find" the input word in a given row if all ZAV cells of the given row provide a match for their respective entries of the input word. Brief description of the drawings

[0003] The present disclosure will be described in detail in accordance with one or more various embodiments with reference to the following figures. The figures are for illustrative purposes only and show examples only. Fig. Figure 1 shows an example of a CAM cell as used in the technology presented here. Fig. shows an example of a CAM that matches the technology presented here. Fig. Figure 3A shows another example of a CAM consistent with the technology presented here. Fig. Figure 3B shows an example truth table for the evaluation of a k-SAT clause using the CAM of Fig. 3A, in accordance with examples of the presently disclosed technology. Fig. Figure 4A shows an example of a CAM-based circuit for implementing k-XOR SAT clauses according to examples of the presently disclosed technology. Fig. Figure 4B shows an example truth table for the evaluation of a k-XOR-SAT formula using the CAM-based circuit of Fig. 4A, in accordance with examples of the presently disclosed technology. Fig. 5 shows an example diagram illustrating comparisons between a threshold voltage and the output voltage of a match line connected to a row of CAM cells programmed to store a k-XOR SAT clause, in accordance with examples of the presently disclosed technology. Fig. 6 shows an exemplary flowchart for solving a Boolean satisfiability problem using a CAM-based circuit, in accordance with examples of the presently disclosed technology. Fig. 7 shows a block diagram of an example computer system in which various of the examples described herein may be implemented.

[0004] The figures are not exhaustive and do not limit the present disclosure to the precise form disclosed. Detailed description

[0005] A k-SAT problem is a type of SAT problem characterized by a number of variables V, a number of literals k, and a number of clauses C. A k-SAT clause generally comprises k literals. A literal of a k-SAT clause is either a variable or the negation of a variable. Conjunctive Normal Form (CNF)—particularly with k=3 literals per k-SAT clause—is often considered the canonical representation for k-SAT formulas. In CNF, a k-SAT clause is a disjunction (i.e., a logical OR operation) of literals, and a k-SAT formula is a conjunction (i.e., a logical AND operation) of k-SAT clauses. A k-SAT formula can also be transformed into disjunctive normal form (DNF), where a k-SAT clause is a conjunction (i.e., logical AND operation) of literals and the k-SAT formula is a disjunction (i.e., logical OR operation) of k-SAT clauses.k-SAT problems are nondeterministic polynomial-time (NP)-hard problems and are among the first problems proven to be NP-complete. All problems in the class of NP-hard complexity (which encompasses a wide range of natural decision and optimization problems) are at most as difficult to solve as k-SAT problems.

[0006] Since k-SAT problems form the backbone of many industrial and scientific problems, such as the automation of electronics design and cryptography, various hardware accelerators have been specifically developed for the implementation (i.e., representation and evaluation) of k-SAT problems. For example, certain QUBO-based (quadratic unconstrained binary optimization) solvers, Ising machines, and CAMs have been specifically developed for the implementation of k-SAT problems. In specially designed CAMs, the clauses of a k-SAT problem / formula can be programmed into the corresponding rows of a CAM, and each CAM cell of a particular row can be programmed to represent a literal of a corresponding k-SAT clause. An input vector (which, for example,represents a set of variables) can then be applied to the columns of the CAM to evaluate whether a set of variables represented by the input vector satisfies the k-SAT clauses programmed into the CAM.

[0007] While many industrial and scientific optimization problems can be formulated as k-SAT problems, certain optimization problems are better formulated differently. For example, some optimization problems, such as low-density parity checking (LDPC) in network systems, are best represented as k-exclusive-OR (k-XOR-SAT) satisfiability problems (i.e., Boolean satisfiability problems formulated with k-XOR-SAT clauses). In this context, certain optimization problems are best represented as "k-SAT-k-XOR-SAT hybrid problems," which contain a combination of k-SAT and k-XOR-SAT clauses.

[0008] Unlike a k-SAT clause, which (in CNF) contains logical OR operations between the constituent literals, a k-XOR SAT clause contains logical XOR operations between the constituent literals. This seemingly insignificant distinction has major implications for problem type / classification. For example, k-SAT problems (i.e., Boolean satisfiability problems formulated with k-SAT clauses) are NP-hard problems, whereas k-XOR SAT (i.e., Boolean satisfiability problems formulated with k-XOR SAT clauses) are polynomial (P) problems. P-problems can be solved in polynomial time and are generally easier to represent and solve than NP-hard problems. Accordingly, representing a native k-XOR-SAT optimization problem as a k-XOR-SAT problem instead of a k-SAT problem (or using k-XOR-SAT clauses instead of k-SAT clauses) can reduce the complexity of the optimization problem.

[0009] Unfortunately, the hardware accelerators described above, which were specifically designed for the implementation (i.e., representation and evaluation) of k-SAT problems, are generally not capable of implementing k-XOR-SAT clauses. Accordingly, implementing a k-XOR-SAT problem with these existing hardware accelerators usually requires reformulating the k-XOR-SAT problem as a k-SAT problem, which generally increases the problem complexity (e.g., the number of variables involved) and shifts the evaluation of the k-XOR-SAT problem from polynomial time to non-polynomial time. Thus, reformulating the k-XOR-SAT problem into a k-SAT problem generally increases the time, hardware, and energy consumption required to implement the k-XOR-SAT problem. Implementing a k-SAT-k-XOR-SAT hybrid problem (i.e.,Computation of a problem formulated using a combination of k-SAT and k-XOR-SAT clauses using these existing hardware accelerators typically involves reformulating the k-XOR-SAT clauses as k-SAT clauses. Again, such reformulation can increase problem complexity—and thus the time, hardware, and power consumption required to implement the k-SAT-k-XOR-SAT hybrid problem.

[0010] With this in mind, examples of the presently disclosed technology provide CAM-based circuits specifically designed to implement Boolean satisfiability problems with k-XOR-SAT clauses. By strategically adding additional counting and logic circuitry that evaluates the voltage outputs of a CAM line at k discrete times to determine whether a counted number of matches returned by a match line satisfies a predetermined parity condition—where k represents a number of literals of a k-XOR-SAT clause of a Boolean satisfiability problem—a circuit of the present technology can utilize a common CAM (i.e., the same CAM) to implement the k-XOR-SAT clause and k-SAT clauses.Accordingly, this highly versatile circuit can be used to implement k-XOR-SAT and k-SAT-k-XOR-SAT hybrid problems in less time and with less hardware and power consumption than existing hardware accelerators.

[0011] A circuit of the presently disclosed technology may include: (1) a row of CAM cells programmed to store a k-XOR-SAT clause of a Boolean satisfiability problem; (2) a sense amplifier that, in response to an input vector applied to the row of CAM cells, compares at k discrete times the voltage output of a match line associated with the row of CAM cells to a threshold voltage, where k represents a number of times of the k-XOR-SAT clause; (3) a counter circuit that counts a number of matches returned by the match line based on the k voltage comparisons of the sense amplifier (e.g.,the counted number of matches may correspond to a number of the k voltage comparisons where the voltage output of the match line exceeded the threshold voltage); and (4) a logic circuit that outputs a signal indicating that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches that satisfy a predetermined parity condition (e.g., where the counted number of matches includes an odd number of matches). The row of CAM cells may include at least k literal-representing CAM cells. A literal-representing CAM cell among the k literal-representing CAM cells may be programmed to store a literal of the k-XOR-SAT clause.

[0012] In various examples, the CAM cell representing the literal may be programmed to store: (a) a first value when the literal is negated in the k-XOR-SAT clause; and (b) a second value when the literal is not negated in the k-XOR-SAT clause. As described in more detail below, programming the literal-representing CAM cell to store the literal of the k-XOR-SAT clause may involve programming the conductivity of one or more memristors included in the literal-representing CAM cell. As already indicated, the circuit may also be used to represent / evaluate a k-SAT clause of the Boolean satisfiability problem. In other words, the Boolean satisfiability problem may comprise a k-SAT-k-XOR-SAT hybrid problem.For example, the circuit may further comprise: (1) a second row of CAM cells programmed to store the k-SAT clause of the Boolean satisfiability problem; and (2) a processor that determines that the input vector satisfies the Boolean satisfiability problem in response to receiving: (a) the signal indicating that the input vector satisfies the k-XOR SAT clause; and (b) a second signal indicating that the input vector satisfies the k-SAT clause (such a signal may be based on a comparison between a threshold voltage and the voltage of a match line connected to the second row of CAM cells).

[0013] As already indicated, the CAM-based circuits of the present technology offer numerous advantages over existing hardware accelerators used to implement Boolean satisfiability problems.

[0014] For example, existing CAMs for implementing k-SAT problems generally require reformulating k-XOR-SAT clauses into k-SAT clauses to implement k-XOR-SAT problems and / or k-SAT-k-XOR-SAT hybrid problems. Such reformulation can increase problem complexity and thus increase the time, hardware, and power consumption required to represent and evaluate such problems.In contrast, a CAM-based circuit of the present technology can leverage a common CAM to implement the k-XOR-SAT clause and k-SAT clauses through the strategic addition of additional counting circuits and logic circuits that evaluate the voltage outputs of a CAM at k discrete times to determine whether a counted number of matches returned by a match line satisfies a predetermined parity condition—where k represents a number of literals of a k-XOR-SAT clause of a Boolean satisfiability problem. Accordingly, this highly versatile circuit can be used to implement k-XOR-SAT and k-SAT-k-XOR-SAT hybrid problems in less time and with less hardware and power consumption than existing CAMs.

[0015] Using a CAM-based circuit to implement k-XOR-SAT problems and / or k-SAT-k-XOR-SAT hybrid problems can also be faster / more efficient than using other types of hardware accelerators (e.g., QUBO-based solvers and Ising machines). For example, by exploiting the unique parallel search capabilities of CAMs, the circuits presented here can evaluate an input vector against all (of the potentially many) clauses of a Boolean satisfiability problem in a single search operation. In other words, for the CAM-based circuits of the currently disclosed technology, the time required to evaluate a Boolean satisfiability problem generally remains constant, even as the number of clauses (e.g., k-XOR-SAT clauses and / or k-SAT clauses) used to formulate the Boolean satisfiability problem increases.Accordingly, CAM-based circuits of the present technology can evaluate large / complex Boolean satisfiability problems (i.e., Boolean satisfiability problems formulated with a large number of k-XOR-SAT clauses and / or k-SAT clauses) faster than other types of hardware accelerators (e.g., QUBO-based solvers and Ising machines) that lack this unique parallel search capability.

[0016] Examples of the currently disclosed technology are further described in the following figures.

[0017] Fig. Figure 1 shows an example of a CAM cell 100 in accordance with examples of the presently disclosed technology. The CAM cell 100 may be an example of a 4-transistor, 2-memristors (4T2M) CAM cell that may be used in a CAM-based circuit of the technology described herein. For example, the CAM cell 100 may be programmed to represent a literal of a k-XOR SAT clause or a k-SAT clause.

[0018] As shown, the CAM cell 100 includes a switching transistor T1 connected to a data line SL, and a switching transistor T2 connected to an inverted data line SL. As indicated above, the voltages on the data line SL and the inverted data line SL may correspond to a value / entry (e.g., a voltage signal) of an input vector applied to a CAM of which the CAM cell 100 is a part. For example, the voltage on the data line SL may correspond to the value / entry of the input vector (e.g., a logical one), while the voltage on the inverted data line SL may correspond to a negated version of the value / entry of the input vector (e.g., a logical zero). A memristor M2 is connected to the switching transistor T1, and a memristor M1 is connected to the switching transistor T2.As shown, the gate terminals of the switching transistors T1 and T2 are connected to a word line WL, which biases the switching transistors T1 and T2. Immediately before and during a search / match operation, the voltage of the word line WL can be increased above a threshold, thereby activating the switching transistors T1 and T2. When the switching transistor T1 is activated, the switching transistor T1 can establish an electrical connection between the data line SL and the memristor M2. Conversely, when the switching transistor T1 is not activated (i.e., when the voltage on the word line WL is below the threshold), the data line SL and the memristor M2 can be electrically isolated. When the switching transistor T2 is activated, the switching transistor T2 can establish an electrical connection between the inverted data line SL and the memristor M1. Conversely, when the switching transistor T2 is not activated (i.e.,When the voltage on the word line WL is lower than the threshold, the inverted data line SL and the memristor M1 can be electrically isolated from each other. Accordingly, the inclusion of the switching transistors T1 and T2 can ensure that the memristors M1 and M2 are disconnected from the data lines of the CAM cell 100 when no search / match operations are performed, which can reduce the overall power consumption of the CAM cell 100.

[0019] As shown in the figure, memristors M1 and M2 are connected in series to form a resistive divider 102. The output voltage of resistive divider 102 (i.e., the voltage at common node G) is applied to a gate of a match line transistor T4 to control the activation of the match line transistor T4. When the match line transistor T4 is activated, it can discharge (i.e., "pull down") the voltage of the match line ML. For example, if the voltage applied to the gate of the match line transistor T4 exceeds a threshold, the match line transistor T4 is activated and discharges (i.e., "pull down") the voltage on the match line ML, resulting in a mismatch.Conversely, if the voltage applied to the gate of match line transistor T4 is less than or equal to the threshold, match line transistor T4 may not be activated. Accordingly, match line transistor T4 will not discharge (i.e., "pull down") the voltage on match line ML, thus establishing a match. While in the specific example of . Fig. 1 describes a “pull-down” logic, in other examples the CAM cell 100 may instead implement a “pull-up” logic.

[0020] As already indicated, the CAM cell 100 can be programmed to store a literal of a k-XOR-SAT clause or a k-SAT clause by programming the conductances of memristors M1 and M2. While the programmed conductances of memristors M1 and M2 generally remain the same unless reprogrammed, the output voltage of the resistive divider 102 (i.e., the voltage at the common node G) changes based on the value of the voltages that memristors M2 and M1 receive from the data line SL and the inverted data line SL, respectively. For example, the memristors M1 and M2 can be programmed to a first conduction state (e.g., a logic zero conduction state—which can correspond to a negated literal) that causes the output voltage of the resistive divider to be high (e.g.,exceeds a threshold value) when the voltages received from the data line SL and the inverted data line SL represent a logical one - thus activating the match line transistor T4 and returning a mismatch when the voltages on the data line SL and the inverted data line SL represent a logical one. In contrast, the memristors M1 and M2 can be programmed to a second conduction state (e.g., a logical conduction state of one - which can correspond to a non-negated literal), which causes the output voltage of the resistive divider to be high (e.g.,exceeds a threshold) when the voltages received from the data line SL and the inverted data line SL represent a logic zero - thus activating the match line transistor T4 and returning a mismatch when the voltages on the data line SL and the inverted data line SL represent a logic zero. As described in more detail below, in various examples, the memristors M1 and M2 can be programmed to a third conductance state (e.g., a wildcard conductance state - which can correspond to a variable not included in a k-XOR-SAT or k-SAT clause) that causes the output voltage of the resistive divider to remain low (e.g.,below a threshold), regardless of whether the voltages received from the data line SL and the inverted data line SL represent a logic zero or a logic one - thus ensuring that the match line transistor T4 does not remain activated and returns a match when the voltages across the data line SL and the inverted data line SL represent a logic zero or a logic one.

[0021] As shown, a service line transistor T3 can cooperate with the switching transistor T1 and / or the switching transistor T2 to program the conductances of the memristors M1 and M2 via a service line SX.

[0022] It should be understood that CAM cell 100 is only one example of a CAM cell that may be included in a CAM-based circuit of the present technology. In general, any type of CAM cell that can be programmed to represent a literal k-XOR-SAT or k-SAT clause may be used. For example, six-transistor two-memristor (6T2M) CAM cells, three-terminal CAM cells, 16-transistor (16T) ternary CAM (TCAM) cells, etc., may be used in the present technology.

[0023] Fig. Figure 2 shows an example of a CAM 200 according to examples of the presently disclosed technology. The CAM 200 can be programmed to represent a Boolean satisfiability problem such as a k-SAT problem, a k-XOR-SAT problem, or a k-SAT-k-XOR-SAT hybrid problem.

[0024] As described above, a content-addressable memory (“CAM”) is a type of computer memory in which the stored data is searched for by its content rather than its location. When a “word” is input into a CAM, the CAM searches for the word in its content. If the ZAV finds the word (i.e., “provides a match”), the ZAV returns the address of the location where the found word is located. Individual cells of a ZAV (i.e., CAM cells) can be arranged in rows and columns. CAM cells in a common row can be connected along a common match line. Words can be stored in the rows of the CAM, and each CAM cell in a particular row can store one entry of a stored word. When the CAM receives an input word (e.g.,a series of voltage signals, each representing an entry of the input word and sometimes referred to herein as an input vector), the CAM can search for the input word entry by entry along the columns of the CAM (i.e., a first entry of the input word can be searched in a first column of the CAM, a second entry of the input word can be searched in a second column of the CAM, etc.). The ZAV can "find" the input word in a given row if all ZAV cells of the given row provide a match for their respective entries of the input word.

[0025] Since k-SAT problems form the backbone of many industrial and scientific problems, such as the automation of electronics design and cryptography, various hardware accelerators have been specifically designed for the implementation (i.e., representation and evaluation) of k-SAT problems. For example, certain CAMs (e.g., CAM 200) have been specifically designed to implement k-SAT problems. For example, clauses of a k-SAT problem / formula can be programmed into corresponding rows of the CAM 200, and each CAM cell of a particular row can be programmed to represent a literal of a corresponding k-SAT clause. An input vector (e.g., representing a set of variables) can then be applied to the columns of the CAM 200 to evaluate whether a set of variables represented by the input vector satisfies the k-SAT clauses programmed into the CAM 200.

[0026] As described above, while many industrial and scientific optimization problems can be formulated as k-SAT problems, certain optimization problems are better formulated in other ways. For example, some optimization problems, such as low-density parity checking (LDPC) in network systems, are best represented as k-k-XOR-SAT problems (i.e., Boolean satisfiability problems formulated with k-XOR-SAT clauses). Certain optimization problems are best represented as "k-SAT-k-XOR-SAT hybrid problems," which contain a combination of k-SAT and k-XOR-SAT clauses.

[0027] Unlike a k-SAT clause, which (in CNF) contains logical OR operations between the constituent literals, a k-XOR SAT clause contains logical XOR operations between the constituent literals. This seemingly insignificant distinction has major implications for problem type / classification. For example, k-SAT problems (i.e., Boolean satisfiability problems formulated with k-SAT clauses) are NP-hard problems, whereas k-XOR SAT (i.e., Boolean satisfiability problems formulated with k-XOR SAT clauses) are polynomial (P) problems. P-problems can be solved in polynomial time and are generally easier to represent and solve than NP-hard problems. Accordingly, representing a native k-XOR-SAT optimization problem as a k-XOR-SAT problem instead of a k-SAT problem (or using k-XOR-SAT clauses instead of k-SAT clauses) can reduce the complexity of the optimization problem.

[0028] Unfortunately, many hardware accelerators specifically designed for the implementation (i.e., representation and evaluation) of k-SAT problems (e.g., CAM 200) are generally incapable of implementing k-XOR-SAT clauses. Accordingly, implementing a k-XOR-SAT problem on the CAM 200 using conventional techniques would typically require reformulating the k-XOR-SAT problem as a k-SAT problem, which generally increases problem complexity (e.g., the number of variables involved) and shifts the evaluation of the k-XOR-SAT problem from polynomial time to non-polynomial time. Thus, reformulating the k-XOR-SAT problem as a k-SAT problem generally increases the time, hardware, and energy required to implement the k-XOR-SAT problem. In this context, the implementation of a k-SAT-k-XOR-SAT hybrid problem (i.e.Implementing a problem formulated using a combination of k-SAT and k-XOR-SAT clauses on CAM 200 using conventional techniques typically involves reformulating the constituent k-XOR-SAT clauses as k-SAT clauses. Again, such a reformulation can increase problem complexity—and thus the time, hardware, and power consumption required to implement the k-SAT-k-XOR-SAT hybrid problem.

[0029] To address the above-described disadvantages of conventional techniques / technologies, examples of the presently disclosed technology provide CAM-based circuits specifically designed to implement Boolean satisfiability problems with k-XOR-SAT clauses. Through the strategic addition of additional counting and logic circuitry that evaluates the voltage outputs of a CAM line at k discrete times to determine whether a counted number of matches returned by a match line satisfies a predetermined parity condition—where k represents a number of literals of a k-XOR-SAT clause of a Boolean satisfiability problem—a circuit of the present technology can utilize a common CAM (i.e., the same CAM) to implement the k-XOR-SAT clause and k-SAT clauses.Accordingly, this highly versatile circuit can be used to implement k-XOR-SAT and k-SAT-k-XOR-SAT hybrid problems in less time, with less hardware, and lower power consumption than existing hardware accelerators.

[0030] A circuit of the presently disclosed technology may include: (1) a row of CAM cells programmed to store a k-XOR-SAT clause of a Boolean satisfiability problem (e.g., a row of CAM 200); (2) a sense amplifier (in Fig. 2 not shown, but in Fig. 4A) which, in response to an input vector applied to the row of CAM cells, compares the voltage output of a match line associated with the row of CAM cells with a threshold voltage at k discrete times, where k represents a number of literals of the k-XOR-SAT clause; (3) a counter circuit (in FIG. (3) a counter circuit (in Fig. 2 not shown, but in Fig. 4A) that counts a number of matches returned by the match line based on the k voltage comparisons of the sense amplifier (e.g., the counted number of matches may correspond to a number of the k voltage comparisons where the voltage output of the match line has exceeded the threshold voltage); and (4) a logic circuit (in Fig. 2 not shown, but in Fig. 4A) that outputs a signal indicating that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches that satisfy a predetermined parity condition (e.g., the counted number of matches includes an odd number of matches). The row of CAM cells may comprise at least k literal-representing CAM cells. A literal-representing CAM cell (e.g., CAM cell 100 of Fig. 2) the k literal-representing CAM cells can be programmed to store a literal of the k-XOR-SAT clause.

[0031] In various examples, the CAM cell representing the literal may be programmed to store: (a) a first value when the literal is negated in the k-XOR SAT clause (e.g., a logical zero); and (b) a second value when the literal is not negated in the k-XOR SAT clause (e.g., a logical one). As described in more detail below, programming the CAM cell representing the literal to store the literal of the k-XOR SAT clause may include programming the conductance of one or more memristors included in the CAM cell representing the literal (e.g., programming the conductances of memristors M1 and M2 of CAM cell 100). As already indicated, the circuit may also be used to implement a k-SAT clause of the Boolean satisfiability problem. In other words, the Boolean satisfiability problem can involve a k-SAT-k-XOR-SAT hybrid problem.For example, the circuit may further comprise: (1) a second row of CAM cells (e.g., a second row of CAM cells (e.g., a second row of CAM 200) programmed to store the k-SAT clause of the Boolean satisfiability problem; and (2) a processor (not shown) that determines that the input vector satisfies the Boolean satisfiability problem in response to receiving: (a) the signal indicating that the input vector satisfies the k-XOR SAT clause; and (b) a second signal indicating that the input vector satisfies the k-SAT clause (such a signal may be based on a comparison between a threshold voltage and the voltage of a match line connected to the second row of CAM cells).

[0032] Again referring to Fig. 2, certain CAMs (e.g., CAM 200) can be categorized as "ternary." A ternary CAM ("TCAM") can evaluate input vectors containing binary bits of zero, one, and / or placeholder values ​​against TCAM cells that store / represent bits of either zero, one, or a placeholder value (as indicated above, a placeholder value is sometimes referred to as a "don't care" or "always match" value). As previously mentioned, for example, one or more memristors of a TCAM cell can be programmed to a first conduction state (e.g., a logic zero) that provides a match when a voltage signal representing a logic zero or a placeholder value is applied to the TCAM cell. In contrast, the one or more memristors of the TCAM cell can be programmed to a second conduction state (e.g.,a logical one) that results in a match when a voltage signal representing a logical one or a wildcard value is applied to the TCAM cell. Additionally, the one or more memristors of the TCAM cell can be programmed to a third conduction state (e.g., a wildcard conduction state) that results in a match when a voltage signal representing a logical zero, a one, or a wildcard value is applied to the TCAM cell. In various implementations, CAM 200 may include a TCAM. However, in other embodiments, CAM 200 may also include higher-order CAMs (e.g., a quaternary CAM ("QCAM"), an analog CAM ("aCAM"), etc.).

[0033] As shown, CAM 200 comprises columns 202A, 202B,... 202L. The number of columns of CAM 200 can be equal to the number of variables V within a total set of variables x I , x2,..., x L, to which a Boolean satisfiability formula can be set, either identically or as a negative of it. Accordingly, the columns of CAM 200 can each be assigned to the variables x I , x2,..., x L are equivalent to.

[0034] CAM 200 also contains rows 204A, 204B, ... 204S. The number of rows of CAM 200 may be equal to the number of clauses S (e.g., k-XOR-SAT clauses and / or k-SAT clauses) that comprise the Boolean satisfiability formula. As illustrated, the CAM cells of each row may be connected to a common match line. For example, the CAM cells of row 204A are connected to match line 212A, the CAM cells of row 204B to match line 212B, the CAM cells of row 204S to match line 212S, and so on. As already indicated, CAM 200 may be an "AND" type CAM, which performs a logical AND operation between CAM cells of a common row.

[0035] As illustrated, the CAM cells of a common row may also be connected to a common word line. For example, the CAM cells of row 204A are connected to word line 213A, the CAM cells of row 204B are connected to word line 213B, the CAM cells of row 204S are connected to word line 213S, and so on. As indicated above, the word lines of CAM 200 may bias the switching transistors of the constituent CAM cells so that the memristors of the constituent CAM cells are electrically connected to the data lines / reverse data lines of CAM 200 only immediately before and during match / search operations, which may reduce the power consumption of CAM 200.

[0036] As shown, each column of the CAM 200 contains a data line (e.g., SL 206A for column 202A, SL 206B for column 202B, SL 206L for column 202L, etc.) and an inverted data line (e.g., SL 207A for column 202A, SL 207B for column 202B, SL 207L for column 202L, etc.). Each column may also contain a service line (e.g., SX 208A for column 202A, SX 208B for column 202B, SX 208L for column 202L, etc.) for programming CAM cells.

[0037] As previously mentioned, the CAM 200 can be programmed to implement (i.e., represent and evaluate) both k-SAT clauses and k-XOR-SAT clauses of a Boolean satisfiability problem. For illustration, an example implementation of a k-SAT formula 250 is described in the following sections, also in conjunction with the Fig. 3A-3B. As previously indicated, implementation of k-SAT clauses on CAM 200 may not require the additional counting and logic circuitry used in examples of the presently disclosed technology for implementing k-XOR SAT clauses on CAM-based circuits.

[0038] As described above, the canonical representation of the k-SAT formula 250 can be in conjunctive normal form (CNF). However, the k-SAT formula 250 can also be converted to disjunctive normal form (DNF), where: (1) a DNF k-SAT formula 252 (i.e., the k-SAT formula 250 converted to DNF) is a disjunction (i.e., a logical OR operation) of DNF k-SAT clauses; (2) each DNF k-SAT clause (i.e., the k-SAT clause converted to DNF) is a conjunction (i.e., a logical AND operation) of literals; and (3) the literals of a respective DNF k-SAT clause are negated versions of the literals of a corresponding k-SAT clause in CNF. For example, if the k-SAT formula 250 is represented as f = ( ¬ x V ¬ y) Λ (y V ¬ z) is represented in CNF, the DNF-k-SAT formula 252 can be represented as follows f = (x Λ y) V ( ¬y Λ z). As already indicated, DNF can be mapped naturally to a CAM of type AND (e.g., CAM 200), where the literals of a DNF-k-SAT clause are programmed to individual CAM cells of a corresponding row.

[0039] For example, a DNF-k-SAT clause of the DNF-k-SAT formula 252 can be programmed into row 204A by programming the CAM cells of row 204A to correspond to the variable assignments of the DNF-k-SAT clause. The DNF-k-SAT clause programmed in row 204A can include the first clause of the DNF-k-SAT formula 252. As already indicated, the columns of the CAM 200 can correspond to the total number of V variables of the DNF-k-SAT clause. For example, column 202B can correspond to the second variable x2 of the total set of V variables x1, x2,..., x V , and thus correspond to the variable assignment corresponding to the variable x2.

[0040] Each DNF-k-SAT clause of the DNF-k-SAT formula 252 can be programmed into a corresponding row of the CAM 200 according to an assignment sequence. In this way, the inherent AND properties of the CAM 200 can be used to solve the DNF-k-SAT formula 252—and thus also the k-SAT formula 250. For example, since (1) the DNF-k-SAT formula 252 contains a plurality of DNF-k-SAT clauses connected by logical ORs, and (2) each DNF-k-SAT clause contains a plurality of literals connected by logical ANDs, the DNF-k-SAT clauses of the DNF-k-SAT formula 252 can be partitioned into corresponding rows of the CAM 200 without disturbing the DNF-k-SAT formula 252. Once the DNF k-SAT formula 252 is mapped into rows, each variable within the row can be arranged in a column so that a guess (i.e., an input vector) can be applied to each variable across each column.

[0041] As in Fig. 3A, an example CAM 300 (which may have the same / similar structure as CAM 200) includes a plurality of columns 307 and rows 305. Each DNF-k-SAT clause of the DNF-k-SAT formula 252 may be mapped to a row 305 of the plurality of CAM cells 306 according to a mapping order. In one implementation, the mapping order includes programming a first DNF-k-SAT clause containing a plurality of literals into a first row 305A and programming a second DNF-k-SAT clause containing a plurality of literals into a second row 305B. Each of the plurality of literals may further include a first value assigned to each non-negated literal (e.g., z) and a second value assigned to each negated literal (e.g., ¬ z).

[0042] In the specific example of Fig. 3A, the k-SAT formula 250 (and by extension, the DNF k-SAT formula 252) comprises an exemplary 2-SAT formula that includes two literals (i.e., k=2), three variables (i.e., V=3), and two k-SAT clauses (i.e., C=2). In this example, CAM 300 consists of an array of CAM cells spanning two rows and three columns. Each DNF k-SAT clause of the DNF k-SAT formula 252 is mapped to a row of the CAM 300. For example, a first DNF k-SAT clause is mapped to the first row 305A and a second DNF k-SAT clause is mapped to the second row 305B. Furthermore, each column of CAM 300 contains a variable (e.g., 1, 0, or a placeholder value ("X")). Each DNF k-SAT clause has k literals selected from among the V variables. In this example, each DNF k-SAT clause contains two literals. Non-negated literals are programmed as 1 in the corresponding CAM cells, and negated literals are programmed as 0 in the corresponding CAM cells.Variables that do not appear in a DNF k-SAT clause are programmed as “X” (i.e., as placeholders) in the corresponding CAM cells.

[0043] As indicated above, the k-SAT formula 250 can be represented in CNF as follows: f = ( ¬ x V ¬ y) Λ (y V ¬ z). The k-SAT formula 250 can then be converted to DNF as follows: f = (x Λ y) V ( ¬ y Λ z). This DNF-k-SAT formula 252 can be programmed (i.e., mapped) onto CAM 300. In this example, the first DNF-k-SAT clause (x Λ y) is programmed into the first row 305A, and the second DNF k-SAT clause ( ¬y Λ z) is programmed in the second row 305B. Each literal within each DNF k-SAT clause is mapped to its own column 307A-C. For example, x is mapped to the first column 307A, y is mapped to the second column 307B, and z is mapped to the third column 307C. Furthermore, each literal is assigned a bit value (ternary 0 or 1 or "X") depending on whether the literal is a negated literal, a non-negated literal, or a missing literal in a corresponding DNF k-SAT clause. A negated literal can be assigned a bit value of 0, a non-negated literal a bit value of 1, and a missing literal a bit value of "X" (i.e., a placeholder value). For example, the first DNF k-SAT clause contains the literals x, y. The values ​​of x, y are programmed in CAM 300 so that x is represented as a 1 in cell 311, y is represented as a 1 in cell 312, and z is represented as an “X” in cell 313. As in Fig. 3A, the second DNF k-SAT clause ( ¬ y Λ z) is programmed into the second row 305 of the CAM 300, so that x is represented as “X” in cell 314, ¬ y is represented as a "0" in cell 315, and z is represented as a "1" in cell 316. Thus, the first DNF-k-SAT clause (x Λ y) of the DNF k-SAT expression f = (x Λ y) V ( ¬ y Λ z) in the first row as 1 1 X, and the second DNF k-SAT clause ( ¬ y Λ z) is represented in the second line as X 0 1.

[0044] As in Fig. As shown in Figure 3A, each row contains a matching line. For example, cells 311-313 in the first row 305A are connected to a first match line ML1, and cells 314-316 in the second row 305B are connected to a second match line ML2.

[0045] As indicated above, a circuit of the presently disclosed technology can apply each entry (representing a variable) of an input vector (representing a set of variables evaluated against a Boolean satisfiability problem) in parallel to each column of a CAM to determine which clauses of a Boolean satisfiability problem are satisfied. In the specific example of Fig. 3A, since k-SAT clauses in DNF are programmed into the CAM 300, a satisfied DNF k-SAT clause (e.g., corresponding to a matchline output of 1) can correspond to an unsatisfied CNF k-SAT clause (and vice versa). For example, if the first DNF k-SAT clause (x Λ y) of the DNF k-SAT formula 252 is satisfied, the corresponding first CNF k-SAT clause ( ¬ xv ¬ y) of the k-SAT formula 250 may not be met (and vice versa). As in Fig. For example, as shown in Figure 3A, if an input vector [1 1 0] is applied to CAM 300, the match line ML1 would return a high voltage value (e.g., a high-order bit value of 1). In this case, the match line ML1 would return a high voltage value because each variable of the input vector (i.e., the input values / entries) matches the values ​​stored in cells 311, 312, and 313, respectively. Furthermore, the match line ML2 would return a low voltage value (e.g., the bit value 0) because the input vector [1 1 0] does not match the values ​​stored in cells 314, 315, and 316. Thus, the first CNF-k-SAT clause (i.e., the original first k-SAT clause in CNF) is not satisfied because the corresponding first DNF-k-SAT clause is satisfied, while the second CNF-k-SAT clause (i.e.,the original second k-SAT clause in CNF) is satisfied because the corresponding second DNF k-SAT clause is not satisfied. On the other hand, if an input vector [0 0 0] is applied to CAM 300, ML1 and ML2 would return a low ML value (e.g., a low-order bit value of 0) because the input vector does not match the value stored in cells 311, 312, 313, 314, 315, and 316. Since both matching rows ML1 and ML2 return a low value, both original CNF k-SAT clauses (i.e., both k-SAT clauses of the Boolean satisfiability formula in CNF) are satisfied because the two DNF k-SAT clauses are not satisfied.

[0046] A truth table 370 for the k-SAT formula 250 is in Fig. 3B. The k-SAT formula 250 is solved when f = 0 (f = 1). Each row can be connected to an OR gate to check whether the k-SAT formula 250 is satisfied.

[0047] In an alternative embodiment, the analog values ​​of each match line can be passed through an analog adder. The analog adder can combine the analog values ​​(i.e., the non-binary signals) of each match line to calculate a sum value. The sum of the analog values ​​can be returned as an output, which can be used to solve the Boolean satisfiability formula.

[0048] Fig. 4A shows an exemplary CAM-based circuit 400 for implementing k-XOR SAT clauses in accordance with various examples of the presently disclosed technology. Before describing the CAM-based circuit 400 in more detail, some background information on k-XOR SAT problems / clauses is instructive. As previously mentioned, unlike a k-SAT clause, which (in CNF) contains logical OR operations between constituent literals, a k-XOR SAT clause contains logical XOR operations between its constituent literals. This seemingly minor distinction has major implications for the problem type / classification. For example, k-SAT problems (i.e., Boolean satisfiability problems formulated with k-SAT clauses) are NP-hard problems, whereas k-XOR-SAT (i.e., Boolean satisfiability problems formulated with k-XOR-SAT clauses) are polynomial (P) problems.P-problems can be solved in polynomial time and are generally easier to represent and solve than NP-hard problems. Accordingly, representing a native k-XOR-SAT optimization problem as a k-XOR-SAT problem instead of a k-SAT problem (or using k-XOR-SAT clauses instead of k-SAT clauses) can reduce the complexity of the optimization problem.

[0049] A k-XOR-SAT formula can be considered as a system of linear equations modulo 2 and can be solved in polynomial time (e.g., O(V 3 vice versa). In other words, if the k-XOR-SAT formula contains V variables, the solution of the k-XOR-SAT formula can be O(V 3 conversely require iterations.

[0050] A k-XOR-SAT example formula 450 may include f = (p ⊕ r ⊕ s) Λ (q ⊕ ¬ r ⊕ s). Here, the k-XOR-SAT formula 450 contains four variables (ie, p, q, r, s), two k-XOR-SAT clauses (ie, (p ⊕ r ⊕ s) and Λ (q ⊕¬r ⊕ s)), and three literals per k-XOR-SAT clause. Since the XOR operation effectively performs a reverse parity check, an input vector (or more precisely, the variable assignments represented by the input vector) may satisfy a corresponding k-XOR-SAT clause if a number of matches between the input vector and the literals of the k-XOR-SAT clause satisfy a predetermined parity condition. For example, if the input vector matches an odd number of literals of a k-XOR-SAT clause, the input vector may satisfy the k-XOR-SAT clause. Conversely, if the input vector matches an even number of literals of the k-XOR-SAT clause, the input vector may violate the k-XOR-SAT clause. As already mentioned, the k-XOR-SAT formula 450 is satisfied if both k-XOR-SAT clauses of which it is composed are satisfied.The k-XOR-SAT formula 450 is not satisfied if at least one of the k-XOR-SAT clauses of which it consists is not satisfied.

[0051] As in Fig. 4A, the CAM-based circuit 400 includes a CAM 410. In certain implementations, the constituent CAM cells of the CAM 410 may have the same / similar structure as the CAM cell 100 of Fig. 1 - although this is not required. In general, any CAM cell that can be programmed to two possible values ​​(e.g., a logical one or a logical zero) can be used in CAM 410.

[0052] As depicted, CAM 410 includes a lower row of CAM cells and an upper row of CAM cells. The lower row of CAM cells is connected to a first match row ML1, and the upper row of CAM cells is connected to a second match row ML2. As described in more detail below, the lower row of CAM cells is programmed to store the first k-XOR-SAT clause of the k-XOR-SAT formula 450 (i.e., (p ⊕ r ⊕ s)) and the upper row of CAM cells is programmed to store the second k-XOR-SAT clause of the k-XOR-SAT formula 450 (i.e., (q ⊕ ¬r ⊕ s)). While in the specific implementation of Fig. 4A, the CAM 410 comprises two rows (i.e., one row for each clause of the k-XOR-SAT formula 450), in other implementations, the CAM 410 may comprise a different number of rows. For example, when the CAM-based circuit 400 is used to implement any Boolean satisfiability problem (e.g., with one or more k-XOR-SAT clauses), the number of rows of the CAM 410 may correspond to the number of clauses of the Boolean satisfiability problem.

[0053] CAM 410 also contains four columns—and accordingly, each row of CAM 410 contains four CAM cells. As shown, the first column (i.e., the leftmost column) of CAM 410 is associated with the variable p of k-XOR-SAT formula 450. The second column of CAM 410 is associated with the variable q of k-XOR-SAT formula 450, the third column of CAM 410 is associated with the variable r of k-XOR-SAT formula 450, and the fourth column of CAM 410 is associated with the variable s of k-XOR-SAT formula 450. Accordingly, when an input vector is applied to CAM 410, a first entry (e.g., a first voltage signal) of the input vector associated with the variable p can be applied to the first column of CAM 410, a second entry (e.g., a second voltage signal) of the input vector associated with the variable q can be applied to the second column of CAM 410, a third entry (e.g.,a third voltage signal) of the input vector associated with the variable r can be applied to the third column of CAM 410, and a fourth entry (e.g., a fourth voltage signal) of the input vector associated with the variable s can be applied to the fourth column of CAM 410. While in the specific implementation of . Fig. 4A CAM 410 includes four columns (i.e., one column for each variable of the k-XOR-SAT formula 450), in other implementations, CAM 410 may include a different number of columns. For example, if the CAM-based circuit 400 is used to implement any Boolean satisfiability problem (e.g., including one or more k-XOR-SAT clauses), the number of columns of CAM 410 may correspond to the number of variables in the Boolean satisfiability problem.

[0054] As indicated above, the bottom row of CAM 410 is programmed to store the first k-XOR-SAT clause of the k-XOR-SAT formula 450 (i.e., (p ⊕ r ⊕ s)). In the specification example of Fig. 4A, a logical one is used to represent literals / variables that are not negated in a clause, a logical zero is used to represent literals / variables that are negated in a clause, and a placeholder value (i.e., "X") is used to represent variables that do not appear in a k-XOR-SAT clause. Therefore, since the variable q is not included in the first k-XOR-SAT clause of k-XOR-SAT formula 450, the second CAM cell of the bottom row is programmed to a placeholder value that always matches. This ensures that the second CAM cell of the bottom row does not interfere with the evaluation of the first k-XOR-SAT clause of k-XOR-SAT formula 450. The first, third, and fourth CAM cells of the bottom row can be called literal-representing CAM cells because they are programmed to store literals of the first k-XOR-SAT clause of the k-XOR-SAT formula 450.In contrast, the second CAM cell of the bottom row can be called a non-literal CAM cell because it is programmed to a placeholder value to account for the fact that the first k-XOR-SAT clause of the k-XOR-SAT formula 450 does not contain the variable q.

[0055] The top row of CAM 410 is programmed to store the second k-XOR-SAT clause of k-XOR-SAT formula 450 (i.e., (q ⊕ ¬r ⊕ s)) in the same / similar manner. As illustrated, the second through fourth CAM cells of the top row are literal-representing CAM cells, while the first CAM cell of the top row is a non-literal-representing CAM cell programmed to a placeholder value to account for the fact that the second k-XOR-SAT clause of k-XOR-SAT formula 450 does not contain the variable p.

[0056] The CAM-based circuit 400 also includes auxiliary circuits connected to the first match line ML1 and the second match line ML2, respectively. As indicated above (and described in more detail below), these auxiliary circuits enable the CAM-based circuit 400 to implement k-XOR SAT clauses using the same CAM hardware (e.g., CAM 410) used to implement k-SAT clauses.

[0057] As described above, unlike a k-SAT clause, which (in CNF) contains logical OR operations between constituent literals, a k-XOR-SAT clause contains logical XOR operations between the constituent literals. Because the XOR operation effectively performs a reverse parity check, an input vector (or more precisely, a set of variable assignments represented by the input vector) can satisfy a corresponding k-XOR-SAT clause if a number of matches between the input vector and the literals of the k-XOR-SAT clause satisfy a predetermined parity condition. For example, if the input vector matches an odd number of literals of a k-XOR-SAT clause, the input vector can satisfy the k-XOR-SAT clause.

[0058] As can be seen from the examples of the present technology, the voltage of a match line generally decreases at different rates depending on the number of mismatches returned by the CAM cells connected to the match line (in various implementations, this may correspond to a Hamming distance between an input vector and a stored word). The match line voltage generally decreases faster as the number of mismatches increases. In other words, the match line voltage will generally decrease more slowly as the number of matches increases relative to the number of mismatches.Based on this finding, examples of the technology presented here can count the number of matches (or conversely, the number of mismatches) returned by CAM cells connected to a match line based on the decay rate of the match line voltage. For example, examples can compare the match line voltage to a threshold voltage at multiple discrete times (e.g., at 0.25 second intervals) to count the number of matches returned by the match line. The number of matches returned by the match line can, for example, correspond to the number of comparisons described above where the match line voltage exceeded the threshold voltage.

[0059] Combining the insights described above with the programming of k-XOR-SAT clauses in rows of a CAM, examples can count the number of matches between an input vector and a k-XOR-SAT clause comprising k literals by (1) comparing a threshold voltage at k discrete times (e.g., at intervals of 0.25 seconds) with the voltage of a match line associated with a row of CAM cells programmed to store the k-XOR-SAT clause; and (2) counting the number of matches returned by the match line based on the k voltage comparisons (e.g., a number of comparisons where the voltage of the match line exceeded the threshold voltage). To illustrate the concept, Fig. 5 is an example graph 500 illustrating comparisons between a threshold voltage and the output voltage of a match line associated with a row of CAM cells programmed to store a k-XOR-SAT clause with k=3 literals. As shown, the threshold voltage is 0.9 wE volts, and the match line voltage is compared to the threshold voltage at three discrete times: t=10.00 wE seconds; t=10.25 wE seconds; and t=10.50 wE seconds. If the match line produces three matches (as shown in curve 502), the match line voltage exceeds the threshold voltage three times. If two matches result (as shown in curve 504), the match line voltage exceeds the threshold voltage twice.When the match line produces a match (as shown in curve 506), the match line voltage exceeds the threshold voltage once. When the match line produces zero matches (as shown in curve 508), the match line voltage exceeds the threshold voltage zero times. Here, the threshold voltage and sample / compare times can be strategically chosen to match such a relationship.

[0060] Referring again to Fig. 4A, CAM 400 includes auxiliary voltage comparison, counting, and logic circuits that implement the methodology described above. For example, sense amplifier 410 is electrically connected to the first match line ML1 associated with the bottom row of CAM 410. Accordingly, sense amplifier 410 can receive the output voltage of the first match line ML1 and compare the output voltage of the first match line ML1 to a threshold voltage at k=3 discrete times.

[0061] As shown, the counter circuit 420 is electrically connected to the sense amplifier 410 and accordingly receives outputs from the sense amplifier 410. Based on the outputs of the sense amplifier 410, the counter circuit 420 can count the number of matches returned by the first match line ML1 (e.g., count a number of comparisons where the voltage of the first match line ML1 has exceeded the threshold voltage).

[0062] As shown, logic circuit 430 is electrically connected to counter circuit 420 and receives outputs from counter circuit 420 accordingly. Based on the outputs from counter circuit 420, logic circuit 430 may determine whether the counted number of matches satisfies a predetermined parity condition (e.g., an odd number of matches) and output a signal indicating whether the input vector satisfies or violates the k-XOR-SAT clause programmed into the bottom row of CAM cells (i.e., (p ⊕ r ⊕ s)).

[0063] Similarly, sense amplifier 412 is electrically connected to the second match line ML2, which is connected to the upper row of CAM 410. Accordingly, sense amplifier 412 can receive the output voltage of the second match line ML2 and compare the output voltage of the second match line ML2 with the threshold voltage at k=3 discrete times.

[0064] As shown, the counter circuit 422 is electrically connected to the sense amplifier 412 and accordingly receives outputs from the sense amplifier 412. Based on the outputs of the sense amplifier 412, the counter circuit 422 can count the number of matches returned by the second match line ML2 (e.g., count a number of comparisons where the voltage of the second match line ML2 has exceeded the threshold voltage).

[0065] As shown, logic circuit 432 is electrically connected to counter circuit 422 and receives outputs from counter circuit 422 accordingly. Based on the outputs of counter circuit 422, logic circuit 432 may determine whether the counted number of matches satisfies the predetermined parity condition (e.g., an odd number of matches) and output a signal indicating whether the input vector satisfies or violates the k-XOR-SAT clause programmed into the top row of CAM cells (i.e., (q ⊕ ¬ r ⊕ s)).

[0066] In various implementations, logic circuits 430 and 432 may be coupled to a processor (or, in certain implementations, to additional logic circuitry) that determines whether the input vector satisfies the k-XOR-SAT formula 450. For example, if the processor receives signals from both logic circuits 430 and 432 indicating that the input vector satisfies their respective k-XOR-SAT clauses, the processor may determine that the input vector satisfies the k-XOR-SAT formula 450. A truth table 470 for evaluating the k-XOR-SAT formula 450 using the CAM-based circuit 400 is shown in Fig. 4B. As shown, the k-XOR-SAT formula 450 is solved when (f = 1).

[0067] As already indicated, the CAM-based circuit 400 can also be used to implement larger Boolean satisfiability problems. For example, the CAM-based circuit 400 can contain additional lines programmed to store additional clauses of a larger Boolean satisfiability problem. These additional lines can be programmed to store k-XOR SAT clauses, but also k-SAT clauses. If the CAM-based circuit 400 is also used to implement k-SAT clauses, the match lines associated with the k-SAT clauses can be used in conjunction with Fig. 4A. This is because the implementation of the k-SAT clauses may not include counting the number of matches returned by CAM cells of a common row. If the k-SAT clauses are implemented in DNF (as in conjunction with Fig. 2 and 3A-3B), the Match line outputs associated with the DNF k-SAT clauses—or alternatively, the Match line outputs associated with the k-XOR SAT clauses—may be connected to logic circuits and / or inverters to account for the fact that the original k-SAT clauses converted to DNF for CAM programming are satisfied by a mismatch, while the k-XOR SAT clauses implemented on the CAM-based circuit 400 are satisfied by a match.

[0068] Fig. 6 shows an exemplary flowchart for solving a Boolean satisfiability problem using a CAM-based circuit, in accordance with various examples of the presently disclosed technology.

[0069] Operation 606 includes comparing the output voltage of a match line associated with a row of CAM cells at k discrete times to a threshold voltage. The row of CAM cells may be programmed to store a k-XOR-SAT clause of a Boolean satisfiability problem. k may represent a number of literals of the k-XOR-SAT clause. Accordingly, the row of CAM cells may include at least k CAM cells representing literals. A literal-representing CAM cell of the k literal-representing CAM cells may be programmed to store a literal of the k-XOR-SAT clause. The CAM cell representing the literal may be programmed to store a first value (e.g., a logical zero or a logical one) when the literal in the k-XOR-SAT clause is negated. The CAM cell representing the literal can be programmed to store a second value (e.g.the other of the logical zeros and the logical one) if the literal is not negated in the k-XOR SAT clause. As indicated above, programming the CAM cell representing the literal may include programming the conductivity of one or more memristors of the CAM cell representing the literal. As described above, operation 606 may be performed by a sense amplifier electrically connected to the match line.

[0070] Operation 608 includes counting a number of matches returned by the match line based on the k voltage comparisons. As indicated above, counting the matches returned by the match line based on the k voltage comparisons may include counting a number of the k voltage comparisons where the voltage output of the match line exceeded the threshold voltage. As described above, operation 608 may be performed by a counting circuit electrically connected to the sense amplifier.

[0071] Operation 610 includes determining that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches that satisfy a predetermined parity condition. In certain implementations, the predetermined parity condition may include an odd number of matches. In other implementations, the predetermined parity condition may include an even number of matches. As described above, operation 610 may be performed by a processor receiving an output from logic circuitry electrically coupled to the counting circuitry. The output from the logic circuitry may be a signal indicating that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches that satisfy the predetermined parity condition.

[0072] As shown, in certain implementations, the flowchart may also include operations 612-616. Note that due to the parallel search capabilities of CAMs, operations 612-616 may be performed in parallel (i.e., approximately concurrently) with operations 606-610.

[0073] For example, operation 612 may include comparing the output voltage of a second match line associated with a second row of CAM cells to the threshold voltage at the k discrete times. The second row of CAM cells may be programmed to store a second k-XOR-SAT clause of the Boolean satisfiability problem. In certain implementations, the second k-XOR-SAT clause may include fewer than k literals. For example, the second k-XOR-SAT clause may include (k - n) literals. Accordingly, the second row of CAM cells may include (k - n) CAM cells representing literals and n CAM cells representing non-literals.As previously mentioned, the n non-literal CAM cells can be programmed to store placeholder values ​​that always result in a match, so that they do not interfere with the evaluation of the second k-XOR SAT clause programmed for the second row of CAM cells. As described above, operation 612 can be performed by a second sense amplifier electrically connected to the second match line.

[0074] Operation 614 includes counting a number of matches returned by the second match line based on the k voltage comparisons associated with the voltage output of the second match line. As indicated above, counting the number of matches returned by the second match line may include counting a number of the k voltage comparisons associated with the voltage output of the second match line when the voltage output of the second match line has exceeded the threshold voltage. As described above, operation 614 may be performed by a second counting circuit electrically connected to the second sense amplifier.

[0075] Operation 616A includes determining that the input vector satisfies the second k-XOR-SAT clause based on the counted number of matches that satisfy the predetermined parity condition. Alternatively, operation 616B includes determining that the input vector violates the second k-XOR-SAT clause based on the counted number of matches that violate the predetermined parity condition. As described above, operations 616A-B may be performed by a processor receiving an output from a second logic circuit electrically coupled to the second counting circuit. A first output (corresponding to operation 616A) from the second logic circuit may be a signal indicating that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches that satisfy the predetermined parity condition.A second output (corresponding to operation 616B) from the second logic circuit may be a signal indicating that the input vector violates the k-XOR-SAT clause based on the counted number of matches that violate the predetermined parity condition. In various implementations, a common (i.e., the same) processor may perform operations 616A-B and operation 610. In certain implementations, the processor may also determine whether the input vector satisfies or violates the Boolean satisfiability problem based on the outputs of the logic circuits of the CAM-based circuit. For example, if the processor receives an indication that the input vector satisfies all clauses programmed into the CAM-based circuit, the processor may determine that the input vector satisfies the Boolean satisfiability problem.

[0076] Fig.7 shows a block diagram of an example computer system 700 in which various of the examples described herein may be implemented.

[0077] Computer system 700 includes a bus 712 or other communication mechanism for conveying information, and one or more hardware processors 704 connected to bus 712 to process information. For example, hardware processor(s) 704 may be one or more general-purpose microprocessors.

[0078] Computer system 700 also includes main memory 706, such as random access memory (RAM), a cache, and / or other dynamic storage devices connected to bus 712, for storing information and instructions to be executed by processor 704. Main memory 706 may also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by processor 704. When such instructions are stored in storage media accessible to processor 704, computer system 700 becomes a special-purpose machine adapted to perform the operations specified in the instructions.

[0079] Computer system 700 also includes a read-only memory (ROM) 712 or other static storage device connected to bus 712 for storing static information and instructions for processor 704. A storage device 714, such as a magnetic disk, an optical disk, or a USB stick (flash drive), etc., is provided and connected to bus 712 for storing information and instructions.

[0080] Computer system 700 additionally includes a hardware accelerator 708. Hardware accelerator 708 may be configured to execute instructions (i.e., programming or software code) stored in main memory 706, read-only memory (ROM) 712, and / or storage device 714 to encode a set of logical rules contained in a Boolean satisfiability problem (e.g., a k-XOR-SAT problem) in a CAM-based circuit 710. In an example implementation, example hardware accelerator 708 may include multiple integrated circuits, which in turn may include application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other very large-scale integrated circuits (VLSIs).The integrated circuits of the exemplary hardware accelerator 708 may be specifically optimized to perform a discrete subset of computer processing operations or to execute a discrete subset of computer-executable instructions in an accelerated manner. For example, the hardware accelerator 708 may be configured or fabricated to implement a set of logical rules contained in a Boolean satisfiability problem (e.g., a k-XOR-SAT problem) into a CAM-based circuit 710.

[0081] The CAM-based circuit 710 may include non-volatile memory constructed using technologies including, for example, resistive switching memory (i.e., a memristor), phase-change memory, magnetoresistive memory, ferroelectric memory, another resistive random access memory (Re-RAM), or combinations of these technologies. More generally, the CAM-based circuit 710 may be implemented using technologies that allow the CAM-based circuit 710 to retain its contents even when power is interrupted or otherwise removed. Thus, the data in the CAM-based circuit 710 "persists," and the CAM-based circuit 710 may function as what is known as "non-volatile memory."

[0082] Computer system 700 may be connected via bus 712 to a display 716, e.g., a liquid crystal display (LCD) (or a touch screen), for displaying information to a computer user. An input device 718, including alphanumeric and other keys, is coupled to bus 712 to communicate information and command selections to processor 704. Another type of user input device is cursor control 720, e.g., a mouse, trackball, or cursor direction keys for communicating direction information and command selections to processor 704 and controlling cursor movement on display 716. In some embodiments, the same direction information and command selections as with cursor control may be implemented via receiving touches on a touchscreen without a cursor.

[0083] Computer system 700 may include a user interface module for implementing a graphical user interface, which may be stored on a mass storage device as executable software code executed by the computing device(s). This and other modules may include, for example, components such as software components, object-oriented software components, class components and task components, processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables.

[0084] In general, the term "component", "engine", "system", "database", "data store" and the like, as used herein, may refer to logic embodied in hardware or firmware, or to a collection of software instructions that may have entry and exit points and be written in a programming language such as Java, C, or C++. A software component may be compiled and linked into an executable program, installed in a dynamic link library, or written in an interpreted programming language such as BASIC, Perl, or Python. It is understood that software components may be callable by other components or by themselves, and / or may be called in response to detected events or interrupts. Software components configured to run on computing devices may be embodied on a computer-readable medium, such asa compact disc, digital video disc, flash drive, magnetic disk, or other tangible medium, or as a digital download (and may be originally stored in a compressed or installable format that requires installation, decompression, or decryption before execution). Such software code may be stored partially or entirely in a memory of the executing computing device so that it can be executed by the computing device. Software instructions may be embedded in firmware, such as an EPROM. In addition, the hardware components may consist of connected logic units such as gates and flip-flops and / or programmable units such as programmable gate arrays or processors.

[0085] Computer system 700 may implement the techniques described herein using custom hard-wired logic, one or more ASICs or FPGAs, firmware, and / or program logic that, in combination with the computer system, makes or programs computer system 700 into a special-purpose machine. According to one embodiment, the techniques described herein are performed by computer system 700 in response to processor(s) 704 executing one or more sequences of one or more instructions contained in main memory 706. Such instructions may be read into main memory 706 from another storage medium, such as storage device 714. Execution of the instruction sequences contained in main memory 706 causes processor(s) 704 to perform the process steps described herein.In alternative embodiments, hard-wired circuits may be used instead of or in combination with software instructions.

[0086] The term "non-volatile media" and similar terms as used herein refer to any media that stores data and / or instructions that cause a machine to operate in a particular manner. Such non-volatile media may include non-volatile media and / or volatile media. Non-volatile media includes, for example, optical or magnetic disks, such as storage device 714. Volatile media includes dynamic memory, such as main memory 706. Common forms of non-volatile media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tape or other magnetic data storage media, CD-ROMs, other optical data storage media, physical media with hole patterns, RAM, PROM and EPROM, FLASH EPROM, NVRAM, other memory chips or cartridges, and networked versions thereof.

[0087] Non-transitory media are distinct from transmission media but can be used in conjunction with them. Transmission media are involved in the transfer of information between non-transitory media. Transmission media include, for example, coaxial cables, copper and fiber optic cables, including the wires that make up bus 712. Transmission media can also take the form of sound or light waves, such as those generated in data communications via radio and infrared.

[0088] Computer system 700 also includes a communications / network interface 722 connected to bus 712. Network interface 722 establishes a two-way data communications connection to one or more network connections connected to one or more local area networks. For example, communications interface 722 may be an Integrated Services Digital Network (ISDN) card, a cable modem, a satellite modem, or a modem for establishing a data communications connection to a corresponding type of telephone line. As another example, network interface 722 may be a Local Area Network (LAN) card for establishing a data communications connection to a compatible LAN (or a WAN component for communicating with a WAN). Wireless connections may also be implemented.In each of these implementations, the network interface 718 sends and receives electrical, electromagnetic, or optical indicators that carry digital data streams containing various types of information.

[0089] A network connection typically enables data communication over one or more networks to other data devices. For example, a network connection may establish a connection over a local area network to a host computer or data devices operated by an Internet service provider (ISP). The ISP, in turn, provides data communication services over the worldwide packet data communication network, now commonly referred to as the "Internet." Both the local area network and the Internet use electrical, electromagnetic, or optical indicators that transmit digital data streams. The indicators in the various networks and the indicators in the network connection and in the communication interface 722 that transmit the digital data to and from the computer system 700 are examples of transmission media.

[0090] Computer system 700 can send messages and receive data, including program code, over the network(s), the network connection, and the communications interface 718. In the Internet example, a server could transmit requested code for an application program over the Internet, the ISP, the local network, and the communications interface 722.

[0091] The received code may be executed by processor 704 upon receipt and / or stored in storage device 714 or other non-volatile memory for later execution.

[0092] Each of the processes, methods, and algorithms described in the preceding sections may be embodied in, and fully or partially automated by, code components executed by one or more computer systems or computer processors comprising computer hardware. The one or more computer systems or computer processors may also operate to support the performance of the corresponding operations in a cloud computing environment or as software as a service (SaaS). The processes and algorithms may be partially or fully implemented in application-specific circuitry. The various features and methods described above may be used independently or combined in various ways.Various combinations and subcombinations are intended to be within the scope of this disclosure, and certain method or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular order, and the associated blocks or states may be performed in other suitable orders, in parallel, or otherwise. Blocks or states may be added to or removed from the disclosed examples. The execution of certain operations or processes may be distributed among computer systems or computer processors located not only in a single machine, but distributed across a number of machines.

[0093] A circuit may be implemented in any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, PALs, CPLDs, FPGAs, logic components, software routines, or other mechanisms may be implemented to form a circuit. In implementation, the various circuits described herein may be implemented as discrete circuits, or the described functions and features may be distributed, in part or in whole, among one or more circuits. Even though various features or functional elements are individually described or claimed as separate circuits, those features and functions may be shared by one or more common circuits, and such description is not intended to assume or imply that separate circuits are required to implement those features or functions.If a circuit is implemented in whole or in part with software, that software may be implemented to operate with a computer or processing system capable of performing the functionality described with respect to it, such as the computer system 700.

[0094] As used herein, the term "or" can be interpreted both inclusively and exclusively. Furthermore, descriptions of resources, acts, or structures in the singular should not be construed as excluding the plural. Conditional expressions such as "may," "could," "might," or "may," unless expressly stated otherwise or understood by context, are generally intended to convey that certain embodiments include certain features, elements, and / or steps, while other embodiments do not.

[0095] Unless expressly stated otherwise, the terms and expressions used in this document, as well as their variations, are not to be interpreted as limiting but as open-ended. Adjectives such as "conventional," "traditional," "normal," "standard," "known," and terms of similar import are not to be construed as limiting the subject matter described to a particular period of time or to a subject matter available at a particular time, but should be understood to include conventional, traditional, normal, or standard technologies that may be available or known now or at any time in the future.The presence of broader words and phrases such as “one or more,” “at least,” “but not limited to,” or similar phrases in some cases should not be construed as meaning that the narrower case is intended or required in the absence of such broader phrases.

Claims

[1] A circuit comprising: an array of content-addressable memory (CAM) cells programmed to store a k-exclusive-OR (k-XOR-SAT) clause of a Boolean satisfiability problem; a sense amplifier which, in response to an input vector being applied to the row of CAM cells: at k discrete times, compares the voltage output of a match line associated with the row of CAM cells with a threshold voltage, where k represents a number of literals of the k-XOR-SAT clause; a counter circuit that counts a number of matches returned by the match line based on the k voltage comparisons of the sense amplifier; and a logic circuit that outputs a signal indicating that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches that satisfy a predetermined parity condition. [2] The circuit of claim 1, wherein: the row of CAM cells comprises k literal-representing CAM cells; and one literal-representing CAM cell of the k literal-representing CAM cells is programmed to store a literal of the k-XOR-SAT clause. [3] The circuit of claim 1, wherein the counted number of matches corresponds to a number of k voltage comparisons at which the voltage output of the match line has exceeded the threshold voltage. [4] The circuit of claim 1, wherein the predetermined parity condition comprises an odd number of matches. [5] The circuit of claim 2, wherein programming the literal-representing CAM cell to store the literal of the k-XOR-SAT clause comprises: programming the literal-representing CAM cell to store a first value when the literal is negated in the k-XOR-SAT clause; and Program the literal-representing CAM cell to store a second value if the literal is not negated in the k-XOR-SAT clause. [6] A circuit according to claim 5, wherein: the row of CAM cells also includes a non-literal CAM cell programmed to store a placeholder value. [7] The circuit of claim 2, wherein programming the literal-representing CAM cell to store the literal of the k-XOR-SAT clause comprises: Programming the conductance of a memristor contained in the literal-representing CAM cell. [8] The circuit of claim 1, further comprising: a second row of CAM cells programmed to store a second k-XOR-SAT clause of the Boolean satisfiability problem; a second sense amplifier which, in response to the input vector being applied to the second row of CAM cells: at the k discrete times, comparing the voltage output of a second match line associated with the second row of aCAM cells with the threshold voltage; a second counter circuit that counts a number of matches returned by the second match line based on the k voltage comparisons of the second sense amplifier; and a second logic circuit that outputs a signal indicating that the input vector satisfies the second k-XOR-SAT clause based on the counted number of matches satisfying the predetermined parity condition. [9] The circuit of claim 8, further comprising a processor responsive to receiving the signal from the first logic circuit and the signal from the second logic circuit: determines that the input vector satisfies the Boolean satisfiability problem. [10] A method for solving a Boolean satisfiability problem using a CAM-based circuit, the method comprising: Comparing, at k discrete times, the voltage output of a match line associated with a row of CAM cells with a threshold voltage, where: the CAM-based circuit includes the row of CAM cells, the row of CAM cells is programmed to store a k-XOR-SAT clause of the Boolean satisfiability problem, and k represents a number of literals of the k-XOR-SAT clause; Counting a number of matches returned by the match line based on the k voltage comparisons; and Determine that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches that satisfy a predetermined parity condition. [11] The method of claim 10, further comprising: Comparing the voltage output of a second match line associated with a second row of CAM cells with the threshold voltage at the k discrete times, where: the CAM-based circuit comprises the second row of CAM cells, the second row of CAM cells is programmed to store a second k-XOR-SAT clause of the Boolean satisfiability problem, Counting a number of matches returned by the second match line based on the k voltage comparisons associated with the voltage output of the second match line; and Determining that the input vector satisfies the second k-XOR-SAT clause based on the counted number of matches returned by the second match row satisfying the predetermined parity condition. [12] The method of claim 10, further comprising: Comparing the voltage output of a second match line associated with a second row of CAM cells with the threshold voltage at the k discrete times, where: the CAM-based circuit comprises the second row of CAM cells, the second row of CAM cells is programmed to store a second k-XOR-SAT clause of the Boolean satisfiability problem, Counting a number of matches returned by the second match line based on the k voltage comparisons associated with the voltage output of the second match line; and Determining that the input vector violates the second k-XOR-SAT clause based on the counted number of matches returned by the second match row violating the predetermined parity constraint. [13] The method of claim 11, further comprising: Determine that the input vector satisfies the Boolean satisfiability problem. [14] The method of claim 12, further comprising: Determine that the input vector violates the Boolean satisfiability problem. [15] The method of claim 10, wherein: the row of CAM cells comprises k literal-representing CAM cells; and one literal-representing CAM cell of the k literal-representing CAM cells is programmed to store a literal of the k-XOR-SAT clause. [16] The method of claim 15, further comprising: programming the literal-representing CAM cell to store a first value when the literal is negated in the k-XOR-SAT clause; and Programming the CAM cell to store a second value if the literal in the k-XOR-SAT clause is not negated. [17] The method of claim 15, further comprising programming the literal-representing CAM cell to store the literal of the k-XOR-SAT clause by programming the conductivity of a memristor included in the literal-representing CAM cell. [18] CAM-based circuit comprising: a row of CAM cells programmed to store a k-XOR-SAT clause of a Boolean satisfiability problem, where: k stands for a number of literals of the k-XOR-SAT clause, the row of CAM cells comprises k literal-representing CAM cells and one literal-representing CAM cell of the k literal-representing CAM cells is programmed to store a literal of the k-XOR-SAT clause; a sense amplifier which, in response to an input vector being applied to the row of CAM cells: at k discrete times, compares the voltage output of a match line associated with the row of CAM cells with a threshold voltage; a counter circuit that counts a number of matches returned by the match line based on the k voltage comparisons of the sense amplifier; and a logic circuit that outputs a signal indicating that the input vector satisfies the k-XOR-SAT clause based on the counted number of matches satisfying a predetermined parity condition. [19] The CAM-based circuit of claim 18, wherein the counted number of matches corresponds to a number of the k voltage comparisons where the voltage output of the match line has exceeded the threshold voltage. [20] The CAM-based circuit of claim 18, wherein programming the literal-representing CAM cell to store the literal of the k-XOR-SAT clause comprises: programming the literal-representing CAM cell to store a first value when the literal is negated in the k-XOR-SAT clause; and Program the literal-representing CAM cell to store a second value if the literal is not negated in the k-XOR-SAT clause.

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