ARRAY SUBSTANT, METHOD FOR MAKING THE SAME AND DISPLAY PANEL

Abstract

The present application provides an array substrate, a method for its fabrication, and a display panel, wherein the array substrate comprises a substrate, a first transistor, and a photocell arranged on the substrate, the first transistor and the photocell being electrically connected. The first transistor comprises a first gate, a first active layer, a second gate, and a source and a drain arranged in a laminated form, the source and drain each being electrically connected to the first active layer. The photocell comprises a first electrode, a photosensitive layer, and a second electrode arranged in a laminated form, the first electrode being arranged in the same layer as the second gate and electrically connected to the source and the drain.By arranging the first electrode of the photocell in the same layer as the second gate of the first transistor, some foil layers of the photocell and some foil layers of the first transistor can be formed using the same mask, in order to reduce the number of masks and the cost, and to mitigate the problem that, in the prior art, a multiple of masks are required for the integration of a photocell and a transistor, thus causing high costs.

Description

Technical FieldThe present application relates to the field of display technology, and more particularly to an array substrate, a method of manufacturing the same, and a display panel.Prior ArtAs display technology is developed, it is desired that a display panel have characteristics such as high resolution, large viewing angle, and low power loss, and the like, and further demands are being made on the display panel. For example, it is desirable that the display panel further has the function of ambient light detection. As for the function of ambient light detection, the brightness of a screen may be automatically adjusted depending on the brightness of the external environment. Moreover, depending on the external environment, a flash lamp may be automatically turned on or lighted upon photographing. In order to achieve the ambient light detection of the display panel, it is necessary to provide a photovoltaic cell on the display panel, the photovoltaic cell itself having no reading and processing function for a signal, and usually implementing addressing and processing of a signal by integrating transistor technology. Rather, a dual gate oxide transistor is considered an optimal option for integration with the photovoltaic cell because it has advantages such as high mobility, low leakage current, adjustable electrical characteristics, good electrical stability and uniformity, as well as compatibility with a process for a flexible substrate, and the like. However, since the manufacturing process for a dual gate oxide thin film transistor usually requires 5 to 6 layouts and the usual process for a photovoltaic cell also requires 4 to 5 layouts, the number of masks required for integration of the two becomes as high as 9 to 11. too large a number of masks may result in very high manufacturing cost and too long a process flow, which is disadvantageous for actual production. Thus, it is of great importance how the integration of the two can be facilitated.Disclosure of the InventionThe present application provides an array substrate, a method of manufacturing the same, and a display panel to alleviate the technical problem that a plurality of masks are required for integration of a photovoltaic cell and a transistor in the related art, thereby causing high costs.In order to solve the above problems, the present application presents the following technical solutions:According to an embodiment of the present application, there is provided an array substrate comprising a substrate and a first transistor and a photo-element arranged on the same side of the substrate, wherein the first transistor and the photo-element are electrically connected to each other; wherein the first transistor comprises:a first gate disposed on a side of the substrate;a first active layer disposed on a side of the first gate opposite the substrate;a second gate disposed on a side of the first active layer opposite the first gate;a source and a drain disposed on a side of the second gate opposite the first active layer, the source and the drain being electrically connected to the first active layer, respectively;and wherein the photovoltaic cell comprises:a first electrode disposed in the same layer as the second gate and electrically connected to the source or the drain;a photosensitive layer disposed on a side of the first electrode opposite to the substrate;and a second electrode disposed on a side of the photosensitive layer opposite to the first electrode.In the array substrate according to an embodiment of the present application, it is provided that the photovoltaic cell further comprises a first input electrode, wherein the first input electrode is located on a side of the second electrode opposite to the photosensitive layer and is disposed in the same layer as the source and the drain, and wherein the first input electrode is electrically connected to the second electrode.In the array substrate according to an embodiment of the present application, it is provided that the first transistor further includes a second input electrode, the second input electrode is disposed in the same layer as the source and the drain, and the second input electrode is electrically connected to the second gate.In the array substrate according to an exemplary embodiment of the present application, it is provided that the array substrate further comprises a passivation layer, wherein the passivation layer covers the second gate, the first electrode and the second electrode, and wherein the source, the drain, the first input electrode and the second input electrode are arranged on a side of the passivation layer facing away from the second gate.In the array substrate according to an exemplary embodiment of the present application, it is provided that the passivation layer includes a first via, a second via, a third via, and a fourth via, wherein the source and the drain are each electrically connected to the first active layer through the corresponding first via, wherein the source or the drain is further electrically connected to the first electrode through the second via, wherein the first input electrode is electrically connected to the second electrode through the third via, and wherein the second input electrode is electrically connected to the second gate through the fourth via.In the array substrate according to an embodiment of the present application, it is provided that the first active layer includes a channel, and a source region and a drain region located on two sides of the channel, wherein the orthogonal projection of the second gate onto the substrate covers the orthogonal projection of the channel onto the substrate, wherein the source is electrically connected to the source region through the corresponding first via, and wherein the drain is electrically connected to the drain region through the corresponding first via.In the array substrate according to an embodiment of the present application, it is provided that the array substrate further comprises:a buffer layer disposed between the substrate and the first gate;a first gate insulating film covering the first gate and the buffer layer;a second gate insulating film covering the first active layer and the first gate insulating film, the second gate and the first electrode being disposed on a side of the second gate insulating film opposite to the first gate insulating film.According to an embodiment of the present application, there is provided a method of manufacturing an array substrate, the method comprising:forming a first metal layer on a substrate and patterning the first metal layer to form a first gate of a first transistor;forming a semiconductor layer on a side of the first gate facing away from the substrate and patterning the semiconductor layer to form a first active layer of the first transistor;forming a second metal layer on a side of the first active layer opposite the first gate and patterning the second metal layer to form a second gate of the first transistor and a first electrode of a photo-element;forming a second semiconductor layer on a side of the first electrode facing away from the substrate, forming a transparent electrode layer on the second semiconductor layer, patterning the transparent electrode layer to form a second electrode of the photovoltaic element, and patterning the second semiconductor layer to form a photosensitive layer of the photovoltaic element;and forming a third metal layer on a side of the second electrode opposite to the photosensitive layer, patterning the third metal layer to form a source and a drain of the first transistor, and electrically connecting the source and the drain to the first active layer, respectively.In the method for manufacturing an array substrate according to an embodiment of the present application, it is provided that the method includes: patterning the third metal layer to form a first input electrode and a second input electrode, electrically connecting the first input electrode to the first electrode, and electrically connecting the second input electrode to the second gate; and after forming the second electrode and the photosensitive layer of the photovoltaic element, and before forming the third metal layer, the method further includes:Forming a passivation layer on a side of the second electrode facing away from the photosensitive layer, overlaying the second gate, the first electrode and the second electrode with the passivation layer and patterning the passivation layer to form a first via, a second via, a third via and a fourth via, wherein the source and the drain are each electrically connected to the first active layer by the corresponding first via, wherein the source or the drain is further electrically connected to the first electrode by the second via, wherein the first input electrode is electrically connected to the first electrode by the third via, and wherein the second input electrode is electrically connected to the second gate by the fourth via.According to an embodiment of the present application, there is further provided a display panel including an array substrate according to any one of the above embodiments and an array substrate manufactured according to a method of manufacturing an array substrate according to any one of the above embodiments.The present application has advantages as follows: In an array substrate, a method for manufacturing the same, and a display panel according to the present application, it is provided that the array substrate includes a substrate, and a first transistor and a photo element disposed on the same side of the substrate, the first transistor and the photo element being electrically connected to each other. The first transistor includes a first gate, a first active layer, a second gate, and a source and a drain arranged in a laminated manner, the source and the drain being electrically connected to the first active layer, respectively. The photovoltaic cell includes a first electrode, a photosensitive layer and a second electrode disposed in a laminated manner, the first electrode being disposed in the same layer as the second gate and being electrically connected to the source and the drain. By disposing the first electrode of the photovoltaic cell in the same layer as the second gate of the first transistor, some film layers of the photovoltaic cell and some film layers of the first transistor can be formed using the same mask to reduce the number of masks and the cost, thereby solving the technical problem that a plurality of masks are required for integration of a photovoltaic cell and a transistor in the related art and thus cause high cost.Brief Description of the FiguresIn order to more clearly explain the technical solutions in the exemplary embodiments or in the prior art, the drawings required for describing the exemplary embodiments or the prior art are briefly presented below. Obviously, the drawings in the following description represent only some embodiments of the invention. The skilled person can also obtain further drawings based on these drawings without inventive activity. FIG. 1 is a structural schematic cross-sectional view of an array substrate according to an embodiment of the present application. FIG. 2 shows a schematic illustration of the functional principle of a first transistor and a photovoltaic cell from FIG. 1. FIG. 3 shows another structural schematic sectional view of the array substrate according to an embodiment of the present application. FIG. 4 is a structural schematic plan view of the array substrate according to an embodiment of the present application. FIG. 5 shows a schematic flow diagram of a method for producing an array substrate according to an exemplary embodiment of the present application. FIG. 6 shows a schematic illustration of the method for producing an array substrate according to an exemplary embodiment of the present application, wherein a first gate is produced on a substrate. FIG. 7 is a schematic diagram illustrating a first active layer formed on the structure of FIG. 6. FIG. 8 is a schematic diagram illustrating a second gate and a first electrode formed on the structure of FIG. 7. Fig. 9 is a schematic diagram showing a photosensitive layer and a second electrode formed on the structure of Fig. 8. FIG. 10 is a schematic diagram illustrating a passivation layer formed on the structure of FIG. 9. FIG. 11 is a schematic diagram illustrating a source, a drain, a first input electrode, and a second input electrode formed on the structure of FIG. 10.DETAILED EMBODIMENTSThe respective embodiments are described with reference to the accompanying drawings to exemplify specific embodiments that can be implemented by the present application. The directional terms such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "lateral" and the like mentioned in the present application refer only to the directions with reference to the attached drawings. Accordingly, the directional terms used are illustrative and understanding of the present application, and the present application is not limited thereto. In the figures, units having similar structures are represented by the same reference numerals. In the accompanying drawings, the thicknesses of some layers and regions are enlarged for the sake of clarity of understanding and simplified description. That is, the dimension and the thickness of each component illustrated in the accompanying drawings are arbitrarily illustrated, and the present application is not limited thereto, however.Referring to FIG. 1, FIG. 1 is a structural schematic sectional view of an array substrate according to an embodiment of the present application, and FIG. 2 is a schematic view of the operation principle of a first transistor and a photovoltaic cell of FIG. 1, the array substrate 100 includes a substrate 10 and a first transistor 20 and a photovoltaic cell 30 disposed on the same side of the substrate 10, the first transistor 20 and the photovoltaic cell 30 being electrically connected to each other. The photo-element 30 may be a photosensitive element for detecting visible light or invisible light such as infrared light and the like. After the photoelement 30 detects the visible light or the invisible light such as infrared light and the like, a light signal of the visible light or the invisible light such as infrared light and the like is converted into an electric signal, and then the electric signal is transmitted to the first transistor 20, and the first thin film transistor can take in the electric signal and output the electric signal. Thus, functions such as ambient light detection or fingerprint recognition and the like can be realized in cooperation of the photovoltaic cell 30 according to the present application and with the first thin film transistor.The first transistor 20 may be a thin film transistor. The first transistor 20 includes a first gate 21, a first active layer 22, a second gate 23, and a source 24 and a drain 25. The first active layer 22 is arranged on a side of the first gate 21 facing away from the substrate 10. The second gate 23 is arranged on a side of the first active layer 22 facing away from the first gate 21. The source 24 and the drain 25 are arranged on a side of the second gate 23 facing away from the first active layer 22, wherein the source 24 and the drain 25 are each electrically connected to the first active layer 22.The photovoltaic cell 30 includes a first electrode 31, a photosensitive layer 32, and a second electrode 33. the first electrode 31 is disposed in the same layer as the second gate 23 and electrically connected to the source 24 or the drain 25. The photosensitive layer 32 is arranged on a side of the first electrode 31 facing away from the substrate 10. The second electrode 33 is arranged on a side of the photosensitive layer 32 facing away from the first electrode 31.Optionally, it is provided that the photovoltaic cell 30 further comprises a first input electrode 34, wherein the first input electrode 34 is located on a side of the second electrode 33 facing away from the photosensitive layer 32 and is arranged in the same layer as the source 24 and the drain 25, and wherein the first input electrode 34 is electrically connected to the second electrode 33. The first transistor 20 further includes a second input electrode 26, wherein the second input electrode 26 is disposed in the same layer as the source 24 and the drain 25, and wherein the second input electrode 26 is electrically connected to the second gate 23.Of course, a plurality of insulating layers are also disposed between respective layers of the first transistor 20 and the photoelement 30. Specifically, the array substrate 100 further includes a buffer layer 11, a first gate insulating layer 12, a second gate insulating layer 13, and a passivation layer 14 disposed on the substrate 10.The substrate 10 may be a rigid substrate or a flexible substrate. When the substrate 10 is a rigid substrate, it may be a hard substrate such as glass substrate, quartz substrate, or silicon wafer, and the like. When the substrate 10 is a flexible substrate, it may be a flexible substrate such as polyimide film (PI film), ultra-thin glass film, and the like.The buffer layer 11 is disposed between the substrate 10 and the first gate 21. The buffer layer 11 can prevent the diffusion of undesired contaminants and contaminants, such as moisture, oxygen, or the like, from the substrate 10 into a agent that may be damaged by such contaminants or contaminants, while providing a flat surface. Optionally, the buffer layer 11 may be made of silicon nitride (SiNx), silicon oxide (SiOx), or a laminate of silicon nitride and silicon oxide. In addition, the buffer layer 11 may further be composed of multiple layers having different refractive indices to scatter the external light incident from the outside.The first gate 21 is arranged on a side of the buffer layer 11 facing away from the substrate 10. The first gate 21 may be made of an elemental metal such as molybdenum, copper, aluminum, titanium, niobium, nickel, or a molybdenum-titanium alloy, molybdenum-niobium alloy, or molybdenum-nickel alloy, or a combined laminate of some of the above metals or alloys.The first gate insulating film 12 covers the first gate 21 and the buffer layer 11. the first gate insulating film 12 may be a single layer of silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, scandium zirconium oxide, and the like, or a laminate of two or three thereof.The first active layer 22 is disposed on a side of the first gate insulating layer 12 facing away from the buffer layer 11. The first active layer 22 comprises a channel 221 as well as a source region 222 and a drain region 223 arranged on two sides of the channel 221. The orthogonal projection of the first gate 21 onto the substrate 10 covers at least the orthogonal projection of the channel 221 onto the substrate 10 to provide light shielding for the channel 221. Optionally, the orthogonal projection of the first gate 21 onto the substrate 10 covers at least the orthogonal projection of the first active layer 22 onto the substrate 10. For example, the metal oxide semiconductor material may be one of zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc tin oxide, aluminum tin oxide, indium tin oxide, indium gallium zinc oxide, indium tin zinc oxide, aluminum indium tin zinc oxide, zinc sulfide, barium titanate, strontium titanate, and lithium niobate.The second gate insulating film 13 covers the first active film 22 and the first gate insulating film 12, and the first gate 21 may be made of an elemental metal such as molybdenum, copper, aluminum, titanium, niobium, nickel, or a molybdenum-titanium alloy, molybdenum-niobium alloy, or molybdenum-nickel alloy, or a combined laminate of some of the above metals or alloys.The second gate 23 and the first electrode 31 are disposed on a side of the second gate insulating film 13 opposite to the first gate insulating film 12, and the second gate 23 is disposed in the same layer as the first electrode 31, so that the second gate 23 can be formed under the same process condition as the first electrode 31. For example, the second gate 23 and the first electrode 31 commonly use the same mask to reduce the number of masks and thus the cost. The second gate 23 is disposed corresponding to the channel 221 of the first active layer 22 to provide light shielding for the channel 221. Optionally, the orthogonal projection of the second gate 23 onto the substrate 10 covers the orthogonal projection of the channel 221 onto the substrate 10.It should be noted that the expression "arranged in the same layer" in the present application means that in a manufacturing process, at least two different structures are obtained by patterning the film layers of the same material, whereby the two different structures are arranged in the same layer. For example, the second gate 23 and the first electrode 31 according to this embodiment are obtained after patterning by the same conductive foil layer, whereby the second gate 23 is disposed in the same layer as the first electrode 31.Optionally, the second gate 23 and the first electrode 31 may be made of an elemental metal such as molybdenum, copper, aluminum, titanium, niobium, nickel, or a molybdenum-titanium alloy, molybdenum-niobium alloy, or molybdenum-nickel alloy, or a laminate of some of the above metals or alloys.The photosensitive layer 32 is disposed on a side of the first electrode 31 opposite to the second gate insulating layer 13, the photosensitive layer 32 being directly in contact with the first electrode 31. The arrangement area of the photosensitive layer 32 is smaller than the arrangement area of the first electrode 31; for example, the orthogonal projection of the photosensitive layer 32 onto the substrate 10 falls within the area of the orthogonal projection of the first electrode 31 onto the substrate 10, and the area of the orthogonal projection of the first electrode 31 onto the substrate 10 is larger than the area of the orthogonal projection of the photosensitive layer 32 onto the substrate 10, so that the arrangement area of the first electrode 31 exceeds the arrangement area of the photosensitive layer 32.The photosensitive layer 32 may be any one of undoped hydrogenated amorphous silicon, phosphorus-doped hydrogenated amorphous silicon, boron-doped hydrogenated amorphous silicon, or fluorine-doped amorphous silicon, or a laminate of two or three thereof. Optionally, the photosensitive layer 32 may comprise a plurality of semiconductor layers arranged in a laminated manner. For example, the photosensitive layer 32 may include an undoped semiconductor layer, as well as a P-type semiconductor layer and an N-type semiconductor layer located on two sides of the undoped semiconductor layer.The second electrode 33 is arranged on a side of the photosensitive layer 32 facing away from the first electrode 31, wherein the second electrode 33 is also directly in contact with the photosensitive layer 32. The arrangement area of the second electrode 33 is the same as the arrangement area of the photosensitive layer 32, so that the second electrode 33 can be formed under the same process condition as the photosensitive layer 32. For example, the second electrode 33 and the photosensitive layer 32 commonly use the same mask to further reduce the number of masks and hence further reduce the cost. The second electrode 33 is a transparent electrode, so that the light can pass through the second electrode 33 to the photosensitive layer 32. Optionally, the second electrode 33 may be a laminate of one or some of the following materials: tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc tin oxide, aluminum tin oxide, indium tin oxide, indium gallium zinc oxide, indium tin zinc oxide, and aluminum indium tin zinc oxide.The passivation layer 14 is arranged on a side of the second electrode 33 facing away from the photosensitive layer 32. Specifically, the passivation layer 14 covers the second gate 23, the first electrode 31, and the second electrode 33, and covers the sidewall of the second gate 23, the first electrode 31, the photosensitive layer 32, and the second electrode 33. the passivation layer 14 is used to protect the second gate 23, the first electrode 31, the photosensitive layer 32, and the second electrode 33, and flatten the surfaces of the structures such as the second gate 23, the first electrode 31, the photosensitive layer 32, and the second electrode 33, and the like. Optionally, the passivation layer 14 may be a single layer of silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, or a combined laminate of two or three thereof.The source 24, the drain 25, the first input electrode 34 and the second input electrode 26 are arranged on a side of the passivation layer 14 facing away from the second gate 23. The source 24, the drain 25, the first input electrode 34, and the second input electrode 26 are arranged in the same layer. The source 24, drain 25, first input electrode 34, and second input electrode 26 may be made of an elemental metal such as molybdenum, copper, aluminum, titanium, niobium, nickel, or a molybdenum-titanium alloy, molybdenum-niobium alloy, or molybdenum-nickel alloy, or a combined laminate of some of the above metals or alloys.The passivation layer 14 includes a first via 141, a second via 142, a third via 143, and a fourth via 144, wherein the source 24 and the drain 25 are electrically connected to the first active layer 22 through the corresponding first via 141, respectively, and wherein the source 24 or the drain 25 is further electrically connected to the first electrode 31 through the second via 142. The first input electrode 34 is electrically connected to the second electrode 33 through the third via 143, and the second input electrode 26 is electrically connected to the second gate 23 through the fourth via 144. Here, in this embodiment, it is described by way of example that the first electrode 31 is electrically connected to the source 24, so that the source 24 is electrically connected to the source region 222 of the first active layer 22 through the corresponding first via 141 and electrically connected to the first electrode 31 through the second via 142, and that the drain 25 is electrically connected to the drain region 223 of the first active layer 22 through the corresponding first via 141.Thus, the source 24, the drain 25, the first input electrode 34, and the second input electrode 26 are arranged in the same layer, so that the source 24, the drain 25, the first input electrode 34, and the second input electrode 26 can be formed under the same process condition. For example, the source 24, the drain 25, the first input electrode 34, and the second input electrode 26 commonly use the same mask to further reduce the number of masks and hence further reduce the cost.In this embodiment, by arranging the first electrode 31 of the photovoltaic cell 30 in the same layer as the second gate 23 of the first transistor 20, and arranging the first input electrode 34 of the photovoltaic cell 30 in the same layer as the second input electrode 26, the source 24, and the drain 25 of the first transistor 20, some film layers of the photovoltaic cell 30 and some film layers of the first transistor 20 can be formed using the same mask to reduce the number of masks and the cost, thereby solving the technical problem that a plurality of masks are required for integration of a photovoltaic cell 30 and a transistor in the related art and thus cause high cost.The functional principle of the photosensitive source 24 and the first transistor 20 will be explained in concrete terms below.Referring to FIG. 2, an input of the photovoltaic cell 30 is electrically connected to an input signal Vin. The input signal Vin supplies a voltage signal to the second electrode 33 via the first input electrode 34, and an output of the photo element 30 is electrically connected to an input of the first transistor 20. An output of the first transistor 20 is electrically connected to an output signal Vout. The input of the first transistor 20 is the source 24, and the output of the first transistor 20 is the drain 25, and the first gate 21 and the second gate 23 of the first transistor 20 may be electrically connected to one and the same scan signal Vsan. In this case, the electrodes, like the first gate 21 and the second gate 23, together form a dual-gate transistor. The second gate 23 may be used for modulating a threshold voltage of a transistor to increase the stability of the first transistor 20. With this, after the photovoltaic cell 30 detects the visible light or the invisible light such as infrared light and the like, a light signal of the visible light or the invisible light such as infrared light and the like is converted into an electric signal, and then the electric signal is transmitted to the first transistor 20, and the first thin film transistor can receive the electric signal and output the electric signal.An exemplary embodiment is provided here. See FIGS. 1 to 4, FIG. 3 shows another structural schematic sectional view of the array substrate 100 according to an embodiment of the present application, and FIG. 4 shows a structural schematic plan view of the array substrate 100 according to an embodiment of the present application. It differs from the above embodiment. Referring to FIG. 4, the array substrate 100 further includes a second transistor 40, the second transistor 40 being disposed in the same layer as the first transistor 20. Specifically, the second transistor 40 comprises a first gate 41, a second active layer 42, a second gate 43, a source 44 and a drain 45 and a third input electrode 46, wherein the first gate 41 of the second transistor 40 is arranged in the same layer as the first gate 21 of the first transistor 20, wherein the second active layer 42 of the second transistor 40 is arranged in the same layer as the first active layer 22 of the first transistor 20, wherein the second gate 43 of the second transistor 40 is arranged in the same layer as the second gate 23 of the first transistor 20, and wherein the source 44, the drain 45 and the third input electrode 46 of the second transistor 40 are arranged in the same layer as the source 24, the drain 25 and the second input electrode 26 of the first transistor 20.Referring to FIGS. 4 and 5, the array substrate 100 includes a display area AA and a photo area SA, the display area AA is used to achieve a display function, and the photo area SA is used to take in the light, convert a light signal into an electric signal, and realize functions such as ambient light detection or fingerprint recognition, or the like. The second transistor 40 is located in the display area AA, and the first transistor 20 and the photovoltaic cell 30 are located in the photo area SA. Optionally, the photo area SA is located on one side of the display area AA, that is, the photo area may be located in the display area AA outside the display area AA. Of course, the photo area SA may be located in the display area AA, for example, the photo area may be located in a gap between adjacent subpixels in the display area AA. The photo area SA may be provided in a number of at least one. When the photo area SA is provided in a plurality, some of the photo areas SA may be located on one side of the display area AA while the other of the photo areas SA are located in the display area AA. For the further description, reference can be made to the exemplary embodiments described above, and will not be discussed in more detail here.In an embodiment, the present application further provides a method of manufacturing an array substrate. Referring to FIGS. 1 to 11, FIG. 5 is a schematic flow chart of a method of manufacturing an array substrate according to an embodiment of the present application; FIG. 6 is a schematic diagram of the method of manufacturing an array substrate according to an embodiment of the present application, wherein a first gate 21 is manufactured on a substrate 10; FIG. 7 is a schematic diagram, wherein a first active layer 22 is manufactured on the structure of FIG. 6; FIG. 8 is a schematic diagram, wherein a second gate 23 and a first electrode 31 are manufactured on the structure of FIG. 7; FIG. 9 is a schematic diagram, wherein a photosensitive layer 32 and a second electrode 33 are manufactured on the structure of FIG. 8; FIG. 10 is a schematic diagram illustrating a passivation layer 14 formed on the structure of FIG. 9; and FIG. 11 is a schematic diagram illustrating a source 24, a drain 25, a first input electrode 34, and a second input electrode 26 formed on the structure of FIG. 10. Referring to FIG. 5, the method of manufacturing an array substrate includes the following steps:S 201: Production of a first metal layer on a substrate 10 and patterning of the first metal layer to form a first gate 21 of a first transistor 20.In particular, referring to FIG. 6, the substrate 10 is provided, wherein the substrate 10 may be a rigid substrate or a flexible substrate. When the substrate 10 is a rigid substrate, it may be a hard substrate such as glass substrate, quartz substrate, or silicon wafer, and the like. When the substrate 10 is a flexible substrate, it may be a flexible substrate such as polyimide film (PI film), ultra-thin glass film, and the like.A buffer layer 11 is deposited on the substrate 10. The buffer layer 11 can prevent the diffusion of undesired contaminants and contaminants, such as moisture, oxygen, or the like, from the substrate 10 into a agent that may be damaged by such contaminants or contaminants, while providing a flat surface. Optionally, the buffer layer 11 may be made of silicon nitride (SiNx), silicon oxide (SiOx), or a laminate of silicon nitride and silicon oxide. In addition, the buffer layer 11 may further be composed of multiple layers having different refractive indices to scatter the external light incident from the outside.A first metal layer is deposited on the buffer layer 11. The first metal layer may be made of an elemental metal such as molybdenum, copper, aluminum, titanium, niobium, nickel, or a molybdenum-titanium alloy, molybdenum-niobium alloy, or molybdenum-nickel alloy, or a combined laminate of some of the above metals or alloys.The first metal layer is patterned using a lithography process and an etching process to form the first gate 21 of the first transistor 20. The lithography process may be one of ultraviolet light, visible light, electron beam, and ion beam. The etching process may be a dry etching process, a wet etching process, or a combined process of the dry etching process and the wet etching process. The dry etching process can be carried out in a single gas component such as chlorine, boron trichloride, hydrogen hexasulfide, carbon tetrafluoride, carbon trifluoride, nitrogen trifluoride, oxygen, argon, nitrogen or a combination of the above gases. The wet etching process may be performed in solution such as ammonia, sodium hydroxide, potassium hydroxide, phosphoric acid, hydrofluoric acid, nitric acid, acetic acid, hydrochloric acid, sulfuric acid, hydrogen peroxide, aqua regia, or a mixed solution of two or three thereof.S 202: Production of a semiconductor layer on a side of the first gate 21 facing away from the substrate 10 and patterning of the semiconductor layer to form a first active layer 22 of the first transistor 20.Referring to FIG. 7, a first gate insulating film 12 is deposited on the first gate 21, in particular. The first gate insulating film 12 covers the first gate 21 and the buffer layer 11. the first gate insulating film 12 may be a single layer of silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, scandium zirconium oxide, and the like, or a laminate of two or three thereof.A semiconductor layer is deposited on the first gate insulating film 12. The material of the semiconductor layer is a metal oxide semiconductor material. For example, the metal oxide semiconductor material may be one of zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc tin oxide, aluminum tin oxide, indium tin oxide, indium gallium zinc oxide, indium tin zinc oxide, aluminum indium tin zinc oxide, zinc sulfide, barium titanate, strontium titanate, and lithium niobate.The semiconductor layer is patterned using the lithography process and the etching process to form the first active layer 22 of the first transistor 20.S 203: Production of a second metal layer on a side of the first active layer 22 facing away from the first gate 21 and patterning of the second metal layer to form a second gate 23 of the first transistor 20 and a first electrode 31 of a photovoltaic cell 30.Referring to FIG. 8, a second gate insulating film 13 is deposited on the first active layer 22. The second gate insulating film 13 covers the first active layer 22 and the first gate insulating film 12, and the second gate insulating film 13 may be a single layer of silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, scandium zirconium oxide, and the like, or a laminate of two or three thereof.After the deposition of the second gate insulating layer 13, an annealing treatment is performed, wherein the annealing treatment may be performed in vacuum, nitrogen, oxygen, argon, or air in the annealing process.A second metal layer is deposited on the second gate insulating film 13. The second metal layer may be made of an elemental metal such as molybdenum, copper, aluminum, titanium, niobium, nickel, or a molybdenum-titanium alloy, molybdenum-niobium alloy, or molybdenum-nickel alloy, or a combined laminate of some of the above metals or alloys.By means of the same mask, the second metal layer is patterned using the lithography process and the etching process to form the second gate 23 of the first transistor 20 and the first electrode 31 of the photo-element 30. Thus, the second gate 23 can be formed under the same process condition as the first electrode 31. For example, the second gate 23 and the first electrode 31 commonly use the same mask to reduce the number of masks and thus the cost.S204: Formation of a second semiconductor layer on a side of the first electrode 31 facing away from the substrate 10, formation of a transparent electrode layer on the second semiconductor layer, patterning of the transparent electrode layer to form a second electrode 33 of the photovoltaic cell 30, and patterning of the second semiconductor layer to form a photosensitive layer 32 of the photovoltaic cell 30.Specifically, referring to FIG. 9, a second semiconductor layer is formed on a side of the first electrode 31 opposite to the substrate 10, and a transparent electrode layer is formed on the second semiconductor layer. By means of the same mask, the transparent electrode layer and the second semiconductor layer are patterned using the lithography process and the etching process to realize the patterning of the transparent electrode layer to form a second electrode 33 of the photovoltaic cell 30 and the patterning of the second semiconductor layer to form a photosensitive layer 32 of the photovoltaic cell 30. Thus, the second electrode 33 can be formed under the same process condition as the photosensitive layer 32. For example, the second electrode 33 and the photosensitive layer 32 commonly use the same mask to further reduce the number of masks and hence further reduce the cost.The photosensitive layer 32 may optionally be one of undoped hydrogenated amorphous silicon, phosphorus-doped hydrogenated amorphous silicon, boron-doped hydrogenated amorphous silicon, or fluorine-doped amorphous silicon, or a laminate of two or three thereof. The second electrode 33 may be a laminate of one or some of the following materials: tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc tin oxide, aluminum tin oxide, indium tin oxide, indium gallium zinc oxide, indium tin zinc oxide, and aluminum indium tin zinc oxide.With reference to FIG. 10, a passivation layer 14 is furthermore deposited on a side of the second electrode 33 facing away from the photosensitive layer 32. And the passivation layer 14 is allowed to cover the second gate 23, the first electrode 31, and the second electrode 33, and to cover the sidewall of the second gate 23, the first electrode 31, the photosensitive layer 32, and the second electrode 33. Optionally, the passivation layer 14 may be a single layer of silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, or a combined laminate of two or three thereof.The passivation layer 14 is patterned using the lithography process and the etching process to form the first via 141, the second via 142, the third via 143, and the fourth via 144. The first via 141 penetrates the passivation layer 14 and the second gate insulating layer 13 to partially expose the first active layer 22. The second via penetrates the passivation layer 14 to partially expose the first electrode 31. The third via penetrates the passivation layer 14 to partially expose the second electrode 33. The fourth via penetrates the passivation layer 14 to partially expose the second gate 23.S 205: forming a third metal layer on a side of the second electrode 33 opposite to the photosensitive layer 32, patterning the third metal layer to form a source 24 and a drain 25 of the first transistor 20, and electrically connecting the source 24 and the drain 25 to the first active layer 22, respectively.Referring to FIG. 11, a third metal layer is deposited on the passivation layer 14, in particular. The third metal layer may be made of an elemental metal such as molybdenum, copper, aluminum, titanium, niobium, nickel, or a molybdenum-titanium alloy, molybdenum-niobium alloy, or molybdenum-nickel alloy, or a combined laminate of some of the above metals or alloys.The third metal layer is patterned using the lithography process and the etching process to form the source 24 and the drain 25 of the first transistor 20. At the same time, by patterning the third metal layer, a first input electrode 34 and a second input electrode 26 are further formed, the first input electrode 34 being electrically connected to the first electrode 31, and the second input electrode 26 being electrically connected to the second gate 23.The source 24 and the drain 25 of the first transistor 20 are each electrically connected to the first active layer 22 through the corresponding first via 141, and the source 24 or the drain 25 is further electrically connected to the first electrode 31 through the second via 142. The first input electrode 34 is electrically connected to the second electrode 33 through the third via 143, and the second input electrode 26 is electrically connected to the second gate 23 through the fourth via 144. Here, in this embodiment, it is described by way of example that the first electrode 31 is electrically connected to the source 24, so that the source 24 is electrically connected to the source region 222 of the first active layer 22 through the corresponding first via 141 and electrically connected to the first electrode 31 through the second via 142, and that the drain 25 is electrically connected to the drain region 223 of the first active layer 22 through the corresponding first via 141.Thus, the source 24, the drain 25, the first input electrode 34, and the second input electrode 26 are arranged in the same layer, so that the source 24, the drain 25, the first input electrode 34, and the second input electrode 26 can be formed under the same process condition. For example, the source 24, the drain 25, the first input electrode 34, and the second input electrode 26 commonly use the same mask to further reduce the number of masks and hence further reduce the cost.Based on one and the same concept of the invention, according to one exemplary embodiment of the present application, a display panel is furthermore provided, wherein the display panel comprises an array substrate 100 according to one of the preceding exemplary embodiments and an array substrate 100 which is produced according to a method for producing an array substrate according to one of the preceding exemplary embodiments. The display panel may be a liquid crystal display panel, an organic light emitting diode display panel, and the like. The display panel may be used in electronic devices having display functions, such as a cellular phone, a tablet computer, a laptop, a game console, a digital camera, a car navigator, an electronic advertising board, an automated teller machine, an e-books, e-newspapers, and wearable devices such as smart bracelets, smart watches, virtual reality (VR), and the like.According to the above embodiments, it is known that:In an array substrate, a method of manufacturing the same, and a display panel according to the present application, it is provided that the array substrate includes a substrate, and a first transistor and a photo element disposed on the same side of the substrate, the first transistor and the photo element being electrically connected to each other. The first transistor includes a first gate, a first active layer, a second gate, and a source and a drain arranged in a laminated manner, the source and the drain being electrically connected to the first active layer, respectively. The photovoltaic cell includes a first electrode, a photosensitive layer and a second electrode disposed in a laminated manner, the first electrode being disposed in the same layer as the second gate and being electrically connected to the source and the drain. By disposing the first electrode of the photovoltaic cell in the same layer as the second gate of the first transistor, some film layers of the photovoltaic cell and some film layers of the first transistor can be formed using the same mask to reduce the number of masks and the cost, thereby solving the technical problem that a plurality of masks are required for integration of a photovoltaic cell and a transistor in the related art and thus cause high cost.In the above embodiments, individual embodiments having different centers of gravity will be described. For parts not discussed in detail in a particular embodiment, reference may be made to the relevant description of other embodiments.The exemplary embodiments of the present application have been explained in detail up to now, wherein the concepts and embodiments of the present application have been discussed in more detail here on the basis of specific examples, and the exemplary embodiments serve only for better understanding of the technical solutions and the core ideas of the present application. Those skilled in the art should understand that they can modify the technical solutions described in the above embodiments or equivalently replace some of the technical features included therein; and that these modifications or substitutions do not, however, lead to the spirit of the respective technical solutions deviating from the scope of the technical solutions of the individual embodiments of the present application.

Claims

An array substrate, characterized in that the array substrate comprises a substrate, and a first transistor and a photovoltaic element disposed on the same side of the substrate, the first transistor and the photovoltaic element being electrically connected to each other; the first transistor comprising: a first gate disposed on a side of the substrate; a first active layer disposed on a side of the first gate opposite the substrate; a second gate disposed on a side of the first active layer opposite the first gate; a source and a drain disposed on a side of the second gate opposite the first active layer, the source and the drain being electrically connected to the first active layer, respectively; and wherein the photovoltaic cell comprises: a first electrode disposed in the same layer as the second gate and electrically connected to the source or the drain; a photosensitive layer disposed on a substrate opposite side of the first electrode; and a second electrode disposed on a first electrode opposite side of the photosensitive layer.The array substrate of claim 1, characterized in that the photovoltaic cell further comprises a first input electrode, wherein the first input electrode is located on a side of the second electrode opposite to the photosensitive layer and is disposed in the same layer as the source and the drain, and wherein the first input electrode is electrically connected to the second electrode.The array substrate of claim 2, characterized in that the first transistor further comprises a second input electrode, wherein the second input electrode is disposed in the same layer as the source and the drain, and wherein the second input electrode is electrically connected to the second gate.The array substrate of claim 3, characterized in that the array substrate further comprises a passivation layer, wherein the passivation layer covers the second gate, the first electrode and the second electrode, and wherein the source, the drain, the first input electrode and the second input electrode are arranged on a side of the passivation layer facing away from the second gate.The array substrate of claim 4, characterized in that the passivation layer comprises a first via, a second via, a third via, and a fourth via, wherein the source and the drain are each electrically connected to the first active layer through the corresponding first via, wherein the source or the drain is further electrically connected to the first electrode through the second via, wherein the first input electrode is electrically connected to the second electrode through the third via, and wherein the second input electrode is electrically connected to the second gate through the fourth via.The array substrate of claim 5, characterized in that the first active layer comprises a channel and a source region and a drain region located on two sides of the channel, wherein the orthogonal projection of the second gate onto the substrate covers the orthogonal projection of the channel onto the substrate, wherein the source is electrically connected to the source region through the corresponding first via, and wherein the drain is electrically connected to the drain region through the corresponding first via.The array substrate according to any one of claims 1 to 6, characterized in that the array substrate further comprises: a buffer layer disposed between the substrate and the first gate; a first gate insulating layer covering the first gate and the buffer layer; and a second gate insulating layer covering the first active layer and the first gate insulating layer, wherein the second gate and the first electrode are disposed on a side of the second gate insulating layer opposite to the first gate insulating layer.A method of manufacturing an array substrate, characterized in that the method comprises: forming a first metal layer on a substrate and patterning the first metal layer to form a first gate of a first transistor; forming a semiconductor layer on a side of the first gate facing away from the substrate and patterning the semiconductor layer to form a first active layer of the first transistor; forming a second metal layer on a side of the first active layer facing away from the first gate and patterning the second metal layer to form a second gate of the first transistor and a first electrode of a photoelement; forming a second semiconductor layer on a side of the first electrode facing away from the substrate, forming a transparent electrode layer on the second semiconductor layer, patterning the transparent electrode layer to form a second electrode of the photovoltaic element and patterning the second semiconductor layer to form a photosensitive layer of the photovoltaic element; and forming a third metal layer on a side of the second electrode facing away from the photosensitive layer, patterning the third metal layer to form a source and a drain of the first transistor and electrically connecting the source and the drain to the first active layer, respectively.A method of manufacturing an array substrate according to claim 8, characterized in that the method comprises: patterning the third metal layer to form further a first input electrode and a second input electrode, connecting the first input electrode electrically to the first electrode, and connecting the second input electrode electrically to the second gate; and that after forming the second electrode and the photosensitive layer of the photovoltaic element, and before forming the third metal layer, the method further comprises: forming a passivation layer on a side of the second electrode opposite the photosensitive layer, overlaying the second gate, the first electrode, and the second electrode with the passivation layer, and patterning the passivation layer to form a first via, a second via, a third via, and a fourth via, wherein the source and the drain are each electrically connected to the first active layer through the corresponding first via, wherein the source or the drain is further electrically connected to the first electrode through the second via, wherein the first input electrode is electrically connected to the first electrode through the third via, and wherein the second input electrode is electrically connected to the second gate through the fourth via.A display panel characterized by comprising an array substrate according to any one of claims 1 to 7 and an array substrate manufactured by a method of manufacturing an array substrate according to claim 8 or 9.

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