GRAPH CACHE

Abstract

A graph cache (200) comprising the following: a content-addressable memory array, CAM array, (202) comprising CAM rows (210) and matching lines corresponding to the CAM rows, wherein the CAM array is configured to receive an identifier of a target node of a graph structure (300), search for the identifier in the CAM rows and activate those of the matching lines that correspond to the CAM rows which store the identifier; a random access memory (RAM) array (208) comprising RAM lines (214) and word lines corresponding to the RAM lines; and a multiple match resolver (206) connected to the CAM array and the RAM array, wherein the multiple match resolver is configured to serially activate the word lines of the RAM array corresponding to the activated match lines of the CAM array.

Description

BACKGROUND

[0001] Graph neural networks (GNNs) are a class of machine learning algorithms designed for processing and analyzing data represented as graphs. They have gained importance in various fields, including traffic analysis, social networks, recommendation systems, and biology. GNNs work by summarizing information from neighboring nodes in a graph, enabling them to identify relationships and patterns in the data. A GNN comprises multiple layers, each refining the node embeddings of a graph through a combination of node features and information from neighboring nodes. GNNs are useful for tasks such as node classification, link prediction, and graph classification.

[0002] US 2022 / 0114103A1 relates to integrated circuits, software and graph databases, and in particular to a method, device and system for storing and retaining graphs in memory.

[0003] US 2023 / 0 245 210 A1 refers to the field of machine learning, including graph-based information recommendations.

[0004] US 6 493 790 B1 refers to a translation-lookaside buffer (TLB) with a reference current circuit that improves the processing efficiency of the TLB.

[0005] US 7 606 974 B2 refers to automatic cache generation for network applications.

[0006] The present invention is defined by independent claims 1, 11 and 17. Embodiments are the subject of the respective dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present revelation are best understood from the following detailed description when read together with the accompanying figures. Fig. Figure 1 is a block diagram of a computer system according to some implementations. Fig. Figure 2 is a block diagram of the graph cache according to some implementations. Fig. Figures 3A-3B show an example of storing a graph structure in a graph cache. Fig. Figure 4 is a flowchart of a graph search procedure according to some implementations. Fig. Figure 5 is a flowchart of a graph programming method according to some implementations. Fig. Figure 6 is a flowchart of a graph processing procedure according to some implementations.

[0008] The corresponding numbers and symbols in the various illustrations generally refer to the corresponding parts, unless otherwise indicated. The illustrations serve to clarify the relevant aspects of the disclosure and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0009] The following disclosure provides many different examples of the implementation of various features. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, only examples and are not intended as limitations.

[0010] A graph represents the relationships between a collection of entities. Specifically, a graph consists of nodes (corresponding to the entities) and edges (corresponding to the relationships between the entities). Each of these elements of a graph can contain an embedding. A node embedding contains one or more pieces of information about the node.

[0011] A graph neural network (GNN) consists of multiple layers. When processing a graph with a GNN, the network operates in several iterations, with each layer updating the embeddings of the nodes in the graph. In each layer, the GNN gathers information from neighboring nodes, updates the embedding of each node, and then moves on to the next layer. This process continues for a certain number of layers or until a convergence criterion is met.

[0012] The structure of a graph remains constant during processing with a GNN. In other words, the graph structure (represented by the edges connecting the nodes) does not change when the node embeddings are updated. One way to represent a graph structure for processing is an adjacency matrix. However, adjacency matrices can consume a large amount of memory and—especially with large graph structures—may be sparsely filled, leading to inefficient memory usage.

[0013] This disclosure describes a cache for efficiently storing a graph structure, also called a "graph structure cache" or simply a "graph cache." The graph structure cache can be used in a computer system to accelerate the processing of a graph by a GNN. The graph cache differs from the general-purpose memory of the computer system. Embeds for the nodes of a graph are stored in the computer system's memory, while the structure of the graph is stored in the graph cache. The graph cache can contain a content-addressable memory array (CAM), which can be suitable for the efficient representation of a graph structure. In particular, a graph structure can be represented more efficiently in a CAM array than in an adjacency matrix. This can reduce the memory space used by the computer system for processing a graph with a GNN.

[0014] In some implementations, the graph cache comprises a content-addressable memory array (CAM), used to store values ​​for the edges of a graph structure, and a random-access memory (RAM) array, used to store memory addresses for embeddings of neighboring nodes of the graph structure. These memory addresses are locations within the computer system's memory. During processing with a GNN, an identifier for a target node of a graph structure is passed to the CAM array. Corresponding word lines of the RAM array are activated by the CAM array, causing the graph cache to output the memory addresses for the embeddings of the target node's neighbors. The embeddings of the neighbor nodes can then be accessed directly via the memory addresses in the computer system's memory. The graph cache may also include a multiple-match resolver (MMR).If multiple matching lines of the CAM array are activated, the multiple matching resolver can serially activate the corresponding word lines of the RAM array, so that the corresponding memory addresses are serially output from the RAM array.

[0015] Fig. Figure 1 is a block diagram of a computer system 100, which can be used to process a graph with a GNN, according to some implementations. The computer system 100 can be implemented in an electronic device. Examples of electronic devices include servers, desktop computers, laptops, mobile devices, gaming systems, and the like.

[0016] The Computer System 100 can be used in any data processing scenario, including standalone hardware, mobile applications, or combinations thereof. Furthermore, the Computer System 100 can be used in a computer network, such as a public cloud network, a private cloud network, a hybrid cloud network, other types of networks, or combinations thereof. For example, the procedures provided by the Computer System 100 are delivered as a service over a network, for instance, by a third party. The Computer System 100 can be implemented on one or more hardware platforms, with the modules within the system running on one or more platforms. Such modules can run on various forms of cloud and hybrid cloud technologies or be offered as Software-as-a-Service (SaaS) that can be deployed in or outside of a cloud.

[0017] To achieve the desired functionality, the computer system comprises 100 different hardware components. These hardware components can include a processor 102, one or more interfaces 104, memory 106, and a graphics cache 200. The hardware components can be interconnected via a number of buses and / or network connections. For example, the processor 102, the interface(s) 104, the memory 106, and the graph cache 200 can be interconnected via a bus 108.

[0018] Processor 102 retrieves executable code from memory 106 and executes it. When executed by Processor 102, this executable code can cause Processor 102 to implement any functionality described herein. Processor 102 can be a microprocessor, an application-specific integrated circuit, a microcontroller, or similar device.

[0019] The interface(s) 104 enable the processor 102 to communicate with various other hardware components both inside and outside the computer system 100. The interface(s) 104 may include, for example, interfaces to input / output devices such as a display, mouse, keyboard, etc. Additionally or alternatively, the interface(s) 104 may include one or more interfaces to an external storage device or to a range of network devices such as servers, switches and routers, client devices, other types of computer equipment, and combinations thereof.

[0020] Memory 106 can comprise various memory types, including volatile and non-volatile memory. For example, memory 106 can include random-access memory (RAM), random-access memory (ROM), a hard disk drive (HDD), and / or similar storage media. Different memory types can be used for different data storage requirements. In certain examples, for instance, the processor 102 can boot from ROM, maintain non-volatile memory on a hard disk, execute program code stored in RAM, and store data to be processed in RAM. Memory 106 can include a non-transitory, computer-readable medium that stores instructions for execution by the processor 102. One or more modules within the computer system 100 can be implemented partially or entirely as software and / or hardware to perform the functions described herein.Memory 106 can contain a general-purpose memory used to store data for Processor 102.

[0021] The Graph Cache 200 is an accelerator for processing a graph using a GNN. The Graph Cache 200 differs from the Processor 102 and the Memory 106, specifically from the caches of the Processor 102 and Memory 106. Furthermore, the architecture of the Graph Cache 200 differs from that of Memory 106. In some implementations, the Graph Cache 200 comprises a content-addressable memory array (CAM) and a random-access memory array (RAM). The CAM array can be programmed with values ​​corresponding to the edges of a graph structure. In this way, a graph structure can be stored in the CAM array. A CAM array can store a graph structure more efficiently than general-purpose memory (e.g., Memory 106). Accordingly, the use of the Graph Cache 200 can improve the efficiency of the Computer System 100.

[0022] As described in more detail below, the graph cache 200 can be used by processor 102 to accelerate graph processing with a GNN. Processor 102 can store a graph structure in graph cache 200 and also store node embeddings of the graph in memory 106. During processing, processor 102 can update the embedding of a target node by aggregating the embeddings of neighboring nodes adjacent to the target node in the graph structure. Processor 102 can retrieve the embeddings of the neighboring nodes using graph cache 200. Specifically, processor 102 can send an identifier for the target node to graph cache 200. Graph cache 200 then returns the memory addresses for the embeddings of the neighboring nodes to processor 102. The memory addresses are memory locations of memory 106.Processor 102 can then directly access the embeddings of neighboring nodes (from memory 106) at the memory addresses provided by graph cache 200. In this way, graph cache 200 is used for a lookup operation where the memory addresses for the neighboring embeddings can be looked up in one go based on the target node identifier.

[0023] Fig. Figure 2 is a block diagram of a graph cache 200 according to several implementations. An example implementation of the graph cache 200 from the computer system 100 is shown. Fig.Figure 1 shows the graph cache 200. In this implementation, the graph cache 200 comprises a CAM array 202, a register 204, a multiple match resolver 206, and a RAM array 208. Additionally, the graph cache 200 may include peripheral circuits (not shown separately) for operating the various components of the graph cache 200. Examples of peripheral circuits include read / write circuits for the CAM array 202, read / write circuits for the RAM array 208, a clock circuit for timing operations in the graph cache 200, a control circuit for controlling the components of the graph cache 200, and the like.

[0024] As mentioned earlier, an edge is a connection between two adjacent nodes in a graph structure. The Graph Cache 200 stores a graph structure by storing values ​​that represent the edges of the graph structure. Specifically, the Graph Cache 200 stores a multitude of edge connections. Each edge connection is a mapping between an identifier of a first node and a memory address for a second node. Thus, each edge connection represents an edge between a first node and a second node. During operation, a target node is fed to the Graph Cache 200. In response to receiving the identifier of the target node, the Graph Cache 200 returns the memory addresses for the mapped nodes that are connected to the target node by edges in the graph structure.

[0025] The CAM array 202 contains CAM cells 210, search lines SL, and matching lines ML. The CAM cells 210 are arranged in rows and columns. The search lines SL are arranged along the columns of the CAM cells 210 and correspond to them. The matching lines ML are arranged along the rows of the CAM cells 210 and correspond to them. The CAM cells 210 can be ternary CAM cells (TCAM). A TCAM cell can store a low value (e.g., a binary 0), a high value (e.g., a binary 1), or a placeholder value. Examples of TCAM cells include SRAM-based TCAM cells, ReRAM-based TCAM cells, memristor-based TCAM cells, and the like.

[0026] A row of CAM cells 210 can be referred to as a CAM row 212. Each CAM row 212 stores a vector containing multiple values ​​(which are stored in the CAM cells 210 of CAM row 212). A match row ML corresponds to a CAM row 212. The search lines SL correspond to the CAM cells 210 of CAM rows 212.

[0027] During a write operation, a write vector of values ​​(e.g., voltages) is applied to the CAM cells 210 of a CAM line 212 via bit lines. Each CAM cell 210 of the CAM line 212 can be set to a low value, a high value, or (optionally) a placeholder value based on a corresponding value from the write vector. Thus, a vector of values ​​is stored in each CAM line 212.

[0028] During a read operation, a read vector of values ​​(e.g., voltages) is applied to the CAM lines 212 via the search lines SL. Each CAM cell 210 of a CAM line 212 compares its stored value with a corresponding value in the read vector. The CAM lines 212 with stored values ​​that match the corresponding values ​​in the read vector activate their corresponding matching lines ML. In other words, during a read operation, the CAM array 202 receives a read vector, searches for the read vector in the CAM lines 212, and activates the matching lines ML of the CAM lines 212 that store the read vector. The matching lines ML of the CAM lines 212 that store a vector other than the read vector are deactivated.

[0029] As described in more detail below, the identifiers for the nodes of a graph structure are stored in the CAM rows 212 of the CAM array 202. An identifier can be a vector of values ​​stored in the CAM cell 210 of a CAM row 212. The CAM array 202 is designed to receive (in the search lines SL) an identifier of a target node of the graph structure. Furthermore, the CAM array 202 is able to search the CAM rows 212 for the received identifier and activate those of the matching lines ML that correspond to the CAM rows 212 that store the identifier. Each of the CAM rows 212 in which the identifier of the target node is stored corresponds to an edge that connects the target node to neighboring nodes.

[0030] Register 204 is connected to the CAM array 202, specifically to the matching lines ML of CAM array 202. Register 204 can contain multiple buffers, for example, one buffer for each CAM line 212. Register 204 is configured to store a matching vector corresponding to the matching lines ML of CAM array 202. Each value in the matching vector corresponds to a matching line ML and can be a low value (e.g., a binary 0) or a high value (e.g., a binary 1). Thus, the matching vector contains high values ​​(corresponding to the enabled matching lines ML) and low values ​​(corresponding to the disabled matching lines ML). When a vector is searched for during a read operation in CAM array 202, register 204 is used to store the result of the read operation.Therefore, the match vector stored in register 204 (which reflects the result of the read operation) can persist even if the search lines SL are reset.

[0031] The multiple match resolver 206 is connected to register 204. The output of register 204 can be connected to the input of the multiple match resolver 206. The multiple match resolver 206 is designed to resolve conflicts that may arise when multiple match lines ML of the CAM array 202 are activated during a read operation. In some implementations, the multiple match resolver 206 is a match-token multiple match resolver. However, any suitable network of logic gates can be used to implement the multiple match resolver 206. To resolve conflicts during the read operation, the multiple match resolver 206 converts the match vector stored in register 204 into one or more output vectors.

[0032] The multiple matching resolver 206 is designed to serially generate output vectors corresponding to the high values ​​of the matching vector. For each high value in the matching vector, one output vector is generated. Each value of an output vector is a low value, except for the high value of the matching vector to which the output vector corresponds. For example, if the matching vector contains a first high value and a second high value (corresponding to two activated matching lines ML), two output vectors are generated: a first output vector with a high value corresponding to the first high value of the matching vector, and a second output vector with a high value corresponding to the second high value of the matching vector. The output vectors are fed (serially) to the RAM array 208.

[0033] The RAM array 208 comprises RAM cells 214, word lines WL, and bit lines BL. The RAM cells 214 are arranged in rows and columns. The word lines WL are arranged along the rows of the RAM cells 214 and correspond to them. The bit lines BL are arranged along the columns of the RAM cells 214 and correspond to them. The RAM cells 214 can be static random-access memory (SRAM) cells.

[0034] A series of RAM cells 214 can be referred to as a RAM row 216. Each RAM row 216 stores a vector containing multiple values ​​(which are stored in the RAM cells 214 of the RAM row 216). A word line WL corresponds to a RAM row 216. The bit lines BL correspond to the RAM cells 214 of the RAM rows 216.

[0035] During a write operation, a write vector of values ​​(e.g., voltages) is applied to RAM cells 214 of RAM row 216 via the bit lines BL and word lines WL. Each RAM cell 214 of RAM row 216 can be set to a low or high value based on a corresponding value of the write vector. Thus, a vector is stored in each RAM row 216.

[0036] During a read operation, a word line WL of a RAM row 216 is activated. The RAM cells 214 of this RAM row 216 output their stored vector on the bit lines BL.

[0037] The matching lines ML of the CAM array 202 are connected (via register 204 and the multiple matching resolver 206) to corresponding word lines WL of the RAM array 208. The multiple matching resolver 206 is designed to serially activate the word lines WL of the RAM array 208 according to the activated matching lines ML of the CAM array 202. In other words, when a matching line ML of a CAM line 212 is activated, a corresponding word line WL of a corresponding RAM line 216 is activated, causing that RAM line 216 to output its stored vector on the bit lines BL.

[0038] As described in more detail below, memory addresses are stored in RAM lines 216 of RAM array 208. Each memory address is a location in memory outside the graph cache 200 where a node embedding is stored. If identifiers for nodes of a graph structure are stored in CAM lines 212 of CAM array 202, the memory addresses stored in RAM lines 216 of RAM array 208 point to embeddings of the corresponding neighboring nodes. In particular, a CAM line 212 can store an identifier of a target node, and the corresponding RAM line 216 can store a memory address that points to an embedding of a neighboring node of the target node.Thus, when an identifier of a target node is fed to the CAM array 202, a CAM line 212 containing this identifier activates its matching line ML; this causes the word line WL of a corresponding RAM line 216 to be activated, which causes the RAM line 216 to output (on the bit lines BL) the memory address for a neighboring node of the target node.

[0039] The graph cache 200 can include connectors for external connections. In some implementations, the graph cache 200 also includes an input connector 218 and an output connector 220. The input connector 218 is connected to the search lines SL of the CAM array 202. The output connector 220 is connected to the bit lines BL of the RAM array 208.

[0040] The Fig. illustrates an example of storing a graph structure in a graph cache. Fig.3A is a diagram of an exemplary graph structure 300, while Fig. 3B is a diagram of the values ​​stored in graph cache 200 (representing graph structure 300). CAM array 202 stores identifiers for nodes of graph structure 300, while RAM array 208 stores memory addresses of embeddings of neighbors of the nodes.

[0041] An example of a reading process is also in Fig.Figure 3B illustrates this. In this example, the target node is node 1 of graph structure 300. An identifier of the target node (e.g., 1) is fed to CAM array 202. The rows containing this identifier activate their matching lines. The matching outputs of CAM array 202 are shown with dashed lines. As a result of these outputs being activated, the corresponding rows of RAM array 208 are serially activated (by the multiple matching resolver 206), causing RAM array 208 to serially output the memory address for neighboring nodes of the target node. In this example, where node 1 is connected to node 2 and node 3 in graph structure 300, providing the identifier for node 1 to CAM array 202 causes RAM array 208 to serially access the memory address for node 2 ADDR2. (k) and the memory address for node 3 ADDR3 (k)outputs. The embeddings for node 2 and node 3 are stored at these memory addresses.

[0042] Fig. Figure 4 is a flowchart of a graph search algorithm 400 according to some implementations. The graph search algorithm 400 is used in conjunction with the Fig. 1 and Fig. 2. The graph search procedure 400 can be performed by the graph cache 200. In particular, the graph cache 200 can perform the graph search procedure 400 to search for edge connections in a stored graph structure. In response to receiving an identifier of a target node, the memory address for each neighboring node of the target node is returned by the graph cache 200.

[0043] The graph cache 200 can perform step 402, in which the CAM array 202 is searched for the identifier of the target node. The identifier can be received at input port 218 and thus made available on the search lines SL of the CAM array 202. The identifier can be a vector that is made available on the search lines SL during a read operation. A matching vector is output by the CAM array 202.

[0044] The graph cache 200 can perform step 404 to store the match vector in register 204. The match vector has high values ​​corresponding to CAM lines 212, which store the received identifier, and low values ​​corresponding to CAM lines 212, which store a different identifier. Each high value in the match vector represents an edge connection between the target node and one of its neighbor nodes. The match vector is passed from register 204 to the multiple match resolver 206.

[0045] The graph cache 200 can perform step 406 to generate an output vector. The output vector can be generated by the multiple-match resolver 206. The output vector corresponds to one of the high values ​​in the match vector. In some implementations, the output vector corresponds to the high value that is spatially lowest in the match vector. Every value in the output vector is a low value, except for the high value in the match vector to which the output vector corresponds.

[0046] The graph cache 200 can perform step 408 to supply the output vector to the RAM array 208. The output vector can be fed to the word lines WL of the RAM array 208 by the multiple-match resolver 206. Since the output vector contains only one high value, only one word line WL is activated by the multiple-match resolver 206. The RAM line 216, corresponding to the activated word line WL, outputs its stored value (e.g., the memory address for a neighboring node) on the bit lines BL. Thus, the memory address can be made available at output port 220.

[0047] The graph cache 200 can perform step 410, in which the high value of the output vector is removed from the matching vector stored in register 204. The high value can be removed from the matching vector by performing a bitwise AND operation on the matching vector with the inverse of the output vector and then storing the result of this operation back in register 204.

[0048] Graph cache 200 can execute step 412 to determine if any high values ​​remain in the matching vector. If the matching vector contains further high values, graph cache 200 repeats steps 406-412. These steps can be performed iteratively until no more high values ​​remain in the matching vector. The number of iterations can be equal to the number of high values ​​in the matching vector.

[0049] An example of a matching vector and its corresponding output vectors is shown in Table 1. In this example, the target node's identifier matches three CAM lines 212 of the CAM array 202. Consequently, the matching vector initially stored in register 204 contains three high values ​​(corresponding to the activated matching lines ML of the three CAM lines 212), so three iterations of steps 406-412 are performed. The output vector generated by the multiple matching resolver 206 at each iteration is different. The matching vector stored in register 204 is modified at each iteration. Table 1 iteration Correspondence vector Output vector 1 [0, 0, 1, 0, 1, 0, 1] [0, 0,1, 0, 0, 0, 0] 2 [0, 0, 0, 0, 1, 0, 1] [0, 0, 0, 0, 1, 0, 0] 3 [0, 0, 0, 0, 0, 0, 1] [0, 0, 0, 0, 0, 0, 1]

[0050] Fig. Figure 5 is a flowchart of a graph programming method 500 according to some implementations. The graph programming method 500 is used in conjunction with the Fig. 1 and Fig.2 described. The graph programming procedure 500 can be carried out by the computer system 100. In particular, the processor 102 can carry out the graph programming procedure 500 to store an edge of a graph structure (e.g., a mapping from a target node to a neighbor node) in the graph cache 200.

[0051] Processor 102 can execute step 502 to program the graph cache 200's CAM array 202 with an identifier of the target node. The identifier can be a vector stored in a CAM line 212 during a write operation to the CAM array 202. The CAM array 202 can be programmed in a similar manner to how previously for Fig. 2 described.

[0052] Processor 102 can execute step 504 to program the RAM array 208 of the graph cache 200 with the memory address for the neighboring node. The memory address is a location in memory 106. The memory address can be a vector that is stored in a RAM line 216 during a write operation for the RAM array 208. The RAM array 208 can be programmed in a similar way to how previously for Fig. 2 described.

[0053] Multiple edges of the graph structure can be stored in the graph cache 200. In particular, if the target node has multiple neighboring nodes, the respective memory addresses for the neighboring nodes can be stored in the respective RAM lines 216, and the identifier for the target node can be stored in each of the CAM lines 212 that correspond to these RAM lines 216. In other words, multiple CAM lines 212 of the CAM array 202 can be programmed with the identifier of the target node (in step 502) if multiple memory addresses are stored in the RAM array 208 (in step 504).

[0054] Fig. Figure 6 is a flowchart of a graph processing algorithm 600 according to some implementations. The graph processing algorithm 600 is used in conjunction with the Fig. 1 and Fig.2 described. The graph processing procedure 600 can be carried out by the computer system 100. In particular, the processor 102 can carry out the graph processing procedure 600 when it processes (with a GNN) a graph whose structure is stored in the graph cache 200.

[0055] Processor 102 can perform step 602, in which it retrieves memory addresses for neighboring nodes of a target node from graph cache 200. As mentioned earlier, graph cache 200 stores a graph structure containing the target node and its neighboring nodes. Processor 102 can provide graph cache 200 with an identifier for the target node and, in response, receive the memory addresses for the neighboring nodes from graph cache 200. The received memory addresses are locations within memory 106. As mentioned earlier, memory 106 is distinct from graph cache 200.

[0056] In some implementations, obtaining the memory addresses involves searching for the target node's identifier in the CAM array 202 of the graph cache 200. The matching lines ML of some of the CAM lines 212 are activated when these CAM lines 212 store the identifier. The corresponding word lines WL of the RAM lines 216 are activated. The activated word lines WL of the RAM lines 216 correspond to the activated matching lines ML of the CAM lines 212. The RAM lines 216 with activated word lines WL store the memory addresses. The word lines WL of the RAM lines 216 can be activated serially (e.g., by the multiple-match resolver 206).

[0057] Processor 102 can perform step 604, in which it accesses the adjacent embeddings of neighboring nodes at the memory addresses of memory 106. As mentioned earlier, the memory addresses returned by graph cache 200 are locations of memory 106. Processor 102 can directly access the node embeddings at these locations of memory 106.

[0058] Processor 102 can perform step 606 to update a target embedding of the target node by aggregating the neighbor embeddings of the neighboring nodes. A layer of the GNN can be used to update the target embedding. The updated target embedding of the target node can be based on a previous embedding of the target node as well as on the neighbor embeddings of the neighboring nodes.

[0059] Processor 102 can perform step 608 to store the updated target embedding of the target node in memory 106. The updated embedding of the target node can then be stored again in memory 106 at the location of the previous embedding of the target node. This updated embedding can then be used when aggregating the neighbor embeddings for other nodes of the graph in a layer of the GNN.

[0060] These implementations can offer advantages. A graph structure can be stored in the graph cache 200 by storing edge connections. Each edge connection is a mapping between an identifier of a first node and a memory address for a second node. The graph structure can be stored in the CAM array 202 and the RAM array 208. In this way, the graph structure can be represented more efficiently than in an adjacency matrix. This reduces the amount of memory used by the computer system 100 for processing a graph with a GNN.

Claims

[1] A graph cache (200) comprising the following: a content-addressable memory array, CAM array, (202) comprising CAM rows (210) and matching lines corresponding to the CAM rows, wherein the CAM array is configured to receive an identifier of a target node of a graph structure (300), search for the identifier in the CAM rows and activate those of the matching lines that correspond to the CAM rows which store the identifier; a random access memory (RAM) array (208) comprising RAM lines (214) and word lines corresponding to the RAM lines; and a multiple match resolver (206) connected to the CAM array and the RAM array, wherein the multiple match resolver is configured to serially activate the word lines of the RAM array corresponding to the activated match lines of the CAM array. [2] The graph cache according to claim 1, wherein the CAM array further comprises search lines and the CAM array receives the identifier on the search lines. [3] The graph cache according to claim 2, which further comprises: an input port (212) which is connected to the search lines. [4] The graph cache according to claim 1, wherein the RAM array further comprises bit lines and the RAM array is configured to output memory addresses for neighboring nodes of the target node on the bit lines when the word lines are enabled. [5] The graph cache according to claim 4, which further comprises: an output port (220) which is connected to the bit lines. [6] The graph cache according to claim 1, further comprising: a register (204) connected to the matching lines of the CAM array, wherein an output of the register is connected to an input of the multiple matching resolver. [7] The graph cache according to claim 6, wherein the register is configured to store a match vector with high values, the high values ​​corresponding to the match lines of the CAM array that are enabled. [8] The graph cache according to claim 7, wherein the multiple match resolver is configured to serially generate output vectors corresponding to the high values ​​of the match vector and to feed the output vectors into the RAM array. [9] The graph cache according to claim 1, wherein the multiple match resolver comprises a match token multiple match resolver. [10] The graph cache according to claim 1, wherein the CAM rows comprise ternary content-addressable memory cells and the RAM rows comprise static random-access memory cells. [11] A method implemented by a computer system (100), wherein the method comprises: Obtaining memory addresses for neighboring nodes of a target node from a graph cache (200) of the computer system, wherein the graph cache stores a graph structure (300) that includes the target node and the neighboring nodes, the neighboring nodes being connected to the target node in the graph structure, the memory addresses being locations of a memory (106) of the computer system, the memory being distinct from the graph cache; Accessing the neighboring embeddings of neighboring nodes at the memory addresses of the memory; Updating a target embedding of the target node by aggregating the neighboring embeddings of the neighboring nodes and Storing the target embedding of the target node in memory. [12] The method of claim 11, which further comprises: Storing the graph structure in the graph cache. [13] The method according to claim 12, comprising storing the graph structure in the graph cache: Programming a content-addressable memory array of the graph cache with an identifier of the target node and Programming a direct access memory array of the graph cache with the memory addresses. [14] The method according to claim 11, comprising obtaining the memory addresses: Searching for an identifier of the target node in a content-addressable memory array, CAM array, (202) of the graph cache, wherein matching lines of CAM rows (210) of the CAM array are activated in response to the CAM rows storing the identifier; and Activating word lines of a random access memory (RAM) line (214) of a RAM array, wherein the word lines of the RAM lines correspond to the matching lines of the CAM lines and the RAM lines store the memory addresses. [15] The method according to claim 14, wherein the word lines of the RAM lines are activated serially. [16] The method according to claim 11, comprising obtaining the memory addresses: Adding an identifier of the target node to the graph cache and Receiving the memory addresses from the graph cache. [17] A computer system comprising the following: a processor (102); a graph cache (200) and a memory (106) that is distinct from the graph cache, wherein the memory comprises a non-transitory, computer-readable medium that stores instructions which, when executed by the processor, cause the processor to: Storing a graph structure (300) in the graph cache; Feeding an identifier of a target node of the graph structure to the graph cache; Receiving memory addresses for neighboring nodes of the target node from the graph cache, wherein the neighboring nodes are connected to the target node in the graph structure and the memory addresses are locations of the memory; Accessing neighboring embeddings of neighboring nodes at the memory addresses of the memory; Updating a target embedding of the target node by aggregating the neighboring embeddings of the neighboring nodes and Storing the target embedding of the target node in memory. [18] Computer system according to claim 17, wherein the graph cache has a different architecture than the memory. [19] Computer system according to claim 17, wherein the graph cache comprises: a content-addressable storage array, CAM array, (202) with matching lines; a register (204) connected to the matching lines of the CAM array; a random access memory (RAM) array (208) with word lines and a multiple match resolver (206) connected to the word lines of the RAM array, wherein the register is connected to the multiple match resolver. [20] Computer system according to claim 19, wherein the instructions for storing the graph structure in the graph cache comprise instructions for the following: Programming the CAM array with the identifier of the target node and Programming the RAM array with the memory addresses for the neighboring nodes.

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