Exposure device and exposure method

Abstract

An exposure device according to one embodiment comprises a holder (31) and a control device (11). In an exposure process, the control device is configured to: calculate a value of a magnification component by functional approximation of measurement results from three or more alignment marks arranged on the substrate; set a first lower limit and / or a first upper limit for an alignment correction value of a magnification component; and, in a case where the first lower limit is set and the calculated value is less than the first lower limit, set the alignment correction value of the magnification component to a second correction value that is greater than the calculated value and less than the first correction value.

Description

REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on and claims priority from Japanese Patent Application No. 2023-098698, filed on June 15, 2023. AREA

[0002] The embodiments described herein generally relate to an exposure apparatus and an exposure method. BACKGROUND

[0003] A three-dimensional stacking technique for three-dimensional stacking of carrier materials for semiconductor circuits is known. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram illustrating the flow of a method for manufacturing a semiconductor device. Fig. 2 is a schematic diagram illustrating an example of the arrangement of alignment marks used in the manufacturing steps for semiconductor devices. Fig. 3 is a table illustrating an example of the correction performance of an exposure device and a bonding device with respect to an overlay component in a wafer surface that may remain in a bonding overlay. Fig. 4 is a block diagram showing an example of a configuration of an exposure apparatus according to a first embodiment. Fig. 5 is a flowchart illustrating an example of an exposure method of the exposure apparatus according to the first embodiment. Fig. 6 is a schematic diagram illustrating an example of the results of an exposure process of the exposure apparatus according to the first embodiment. Fig. 7 is a table illustrating an example of an alignment correction value of a wafer magnification component by the exposure process of the exposure apparatus according to the first embodiment. Fig. 8 is a scattergram illustrating an example of the distribution of the wafer magnification component after the exposure process of the exposure apparatus according to the first embodiment. Fig. 9 is a flowchart illustrating an example of a method for manufacturing a semiconductor device according to a second embodiment. Fig. 10 is a box-and-whisker diagram exemplifying a change in the distribution of a wafer enlargement component by the method for manufacturing a semiconductor device according to the second embodiment. Fig. 11 is a flowchart illustrating an example of an exposure method of an exposure apparatus according to a third embodiment. Fig. 12 is a schematic diagram exemplifying the superimposition results of an exposure process of the exposure apparatus according to the third embodiment. Fig. 13 is a flowchart illustrating an example of the method for manufacturing a semiconductor device according to the third embodiment. Fig. 14 is a box-and-whisker diagram showing an example of a change in the distribution of a wafer enlargement component by the method for manufacturing a semiconductor device according to the third embodiment. Fig. 15 is a block diagram illustrating an example of an overall configuration of a storage device according to a fourth embodiment. Fig. 16 is a circuit diagram illustrating an example of a circuit configuration of a memory cell array including the memory device according to the fourth embodiment. Fig. 17 is a perspective view showing an example of a structure of the memory device according to the fourth embodiment. Fig. 18 is a plan view illustrating an example of a planar layout of the memory cell array included in the memory device according to the fourth embodiment. Fig. 19 is a cross-sectional view showing an example of a cross-sectional structure of the memory cell array including the memory device according to the fourth embodiment. Fig. 20 is a cross-sectional view taken along the line XX-XX of Fig. 19 and illustrates an example of a cross-sectional structure of storage columns included in the storage device according to the fourth embodiment. Fig. 21 is a cross-sectional view illustrating an example of a cross-sectional structure of the memory device according to the fourth embodiment. DETAILED DESCRIPTION

[0004] In general, an exposure apparatus according to one embodiment comprises a holder and a control device. The holder is configured to hold a substrate. The control device is configured to perform an exposure process on the substrate. During the exposure process, the control device is further configured to: calculate a calculated value of a magnification component by performing a functional approximation on measurement results of three or more alignment marks arranged on the substrate in an orthogonal coordinate system; set a first lower limit and / or a first upper limit for an alignment correction value of a magnification component;in a case where the calculated value is greater than or equal to the first lower limit value and / or less than or equal to the first upper limit value, setting the orientation correction value of the magnification component to a first correction value; in a case where the first lower limit value is set and the calculated value is less than the first lower limit value, setting the orientation correction value of the magnification component to a second correction value that is greater than the calculated value and less than the first correction value; and in a case where the first upper limit value is set and the calculated value exceeds the first upper limit value, setting the orientation correction value of the magnification component to a third correction value that is greater than the first correction value and less than the calculated value.

[0005] Hereinafter, each of the embodiments will be described with reference to the drawings. Each of the embodiments illustrates an apparatus and a method for implementing the technical concepts of the invention. The drawings are schematic or conceptual. Dimensions, ratios, and the like in each drawing do not necessarily correspond to actual dimensions, ratios, and the like. Where appropriate, illustrations of configurations are omitted. In the present description, components having substantially the same functions and configurations are denoted by the same reference numerals. Reference numerals or the like are denoted by the same reference numerals and are used to distinguish between similar elements.

[0006] In the following description, two types of horizontal directions that intersect each other are respectively referred to as the "X direction" and the "Y direction". In the following description, a plane parallel to the X direction and the Y direction is referred to as the "XY plane". In the following description, a direction perpendicular to a horizontally arranged substrate or the like is referred to as the "Z direction". "Top side" in this context means vertically above a component, such as a horizontally arranged layer. "Bottom side" in this context means vertically below a component, such as a horizontally arranged layer. "Plane view" in this context means that a component, such as a horizontally arranged layer, is visually recognized from above. "Visually recognize" includes observing an object with a microscope, camera, or the like.

[0007] The semiconductor device of the present description is formed by bonding two semiconductor circuit substrates, each on which a semiconductor circuit is formed, and dividing the bonded semiconductor circuit substrates into chips. Hereinafter, the semiconductor circuit substrate is referred to as a "wafer." The process of bonding two wafers is referred to as a "bonding process." A device that performs the bonding process is referred to as a "bonding device." The wafers arranged on the upper and lower sides in the bonding process are referred to as "upper wafer UW" and "lower wafer LW," respectively. A pair of upper wafer UW and lower wafer LW bonded to each other is referred to as a "bonded wafer BW." The "front side of the wafer" refers to the surface on which the semiconductor circuit is formed by a front-end process.The backside of the wafer element refers to a surface on the backside of the front side of the wafer. <0> Method for manufacturing a semiconductor device

[0008] Fig. Figure 1 is a schematic diagram illustrating the flow of a method for manufacturing a semiconductor device. The flow of the method for manufacturing a semiconductor device is described below using Fig. 1 explained.

[0009] First, a wafer is assigned to a lot (“batch assignment”). A batch can comprise multiple wafers. For example, batches can be divided into batches comprising the upper wafer UW and batches comprising the lower wafer LW. Each upper wafer UW is linked to a lower wafer LW. Then, the front-end process is performed on each batch comprising the upper wafer UW and each batch comprising the lower wafer LW. The front-end process comprises a combination of the “exposure process,” “exposure measurement OL (overlay),” and “etching process.”

[0010] For example, the exposure process is a process for transferring a mask pattern (reticle) onto a wafer in units of shots. Each "shot" belongs to a separate exposure area in the exposure process. The arrangement of the shots in the upper wafer UW and the arrangement of the shots in the lower wafer LW are identical. In the exposure process, exposure is performed repeatedly with a shift in the exposure position. That is, the exposure device exposes the wafer using a step-and-repeat method. After that, a portion of the resist material is removed through a development process, and the desired pattern is transferred onto the resist material. In the exposure process, the arrangement and shape of each shot are corrected based on the measurement result of the alignment mark, various correction values, and similar factors.This adjusts (aligns) the position of the overlay between the base pattern and the pattern created by the exposure process.

[0011] Exposure OL measurement is a method for measuring the overlay deviations between the base pattern and the pattern of the resist material formed by the exposure process. The measurement results obtained by exposure OL measurement can be used, for example, to determine the rework of the exposure process or to calculate alignment correction values ​​to be applied to the subsequent batch, and the like.

[0012] The etching process is a process in which an element on the wafer is processed using the resist material created by the exposure process as a mask. The etching process shapes the element on the wafer into a shape based on the pattern of the resist material. The circuit pattern for each layer can be formed through a combination of the exposure and etching processes.

[0013] Note that, although not described in the present specification, the front-end process may include a heating step, a cleaning step, a film-forming step, and the like. By performing the front-end process for each of the upper wafers UW and the lower wafers LW, a desired semiconductor circuit is then formed on the front side of each of the upper wafers UW and the lower wafers LW ("completion of the front-end process"). Thereafter, the bonding process is performed using the linked set of the upper wafer UW and the lower wafer LW.

[0014] During the bonding process, the bonding device holds the front side of the upper wafer UW and the front side of the lower wafer LW facing each other. Furthermore, the bonding device adjusts (aligns) the position of the overlay between the pattern formed on the front side of the upper wafer UW and the pattern formed on the front side of the lower wafer LW based on the measurement result of the alignment mark. Then, the device brings the front side of the upper wafer UW and the front side of the lower wafer LW into contact with each other. This bonds the front side of the upper wafer UW and the front side of the lower wafer LW to form the bonded wafer BW. After that, the OL measurement (overlay) is performed on the bonded wafer BW.

[0015] Bond OL measurement is a method for measuring the overlay deviation between the pattern formed on the bonding surface of the upper wafer UW and the bonding surface of the lower wafer LW. The "bonding layer" refers to a layer in contact with a boundary portion between the upper wafer UW and the lower wafer LW. Both the upper wafer UW and the lower wafer LW have a bonding layer. The measurement results obtained by OL measurement can be used to calculate alignment correction values ​​applied to the exposure process of the subsequent batch, and the like.

[0016] A wiring process is then performed on the bonded wafer BW, forming wiring and pads for external connection to a circuit provided on the bonded wafer BW. The bonded wafer BW is then diced into individual chips through a dicing process, resulting in a plurality of semiconductor devices from one bonded wafer BW.

[0017] In this specification, alignment is part of the wafer shape in the exposure device standard. The overlay deviation amount corresponds to the misalignment between the pattern of the overlay source and the pattern of the overlay target. That is, the component that cannot be corrected by the exposure process based on the alignment measurement results is the overlay deviation. Hereinafter, the correction value used when aligning the overlay position is referred to as the "alignment correction value." When a polynomial is used to correct alignment, the coefficient of each term is referred to as the "alignment correction coefficient." That is, the alignment correction values ​​can be calculated based on the alignment correction coefficient for each term and the exposure position.

[0018] The overlay deviation amounts that can be generated in each exposure process and bonding process can be expressed by a combination of different components. For example, the overlay measurement results (alignment) for each K value can be decomposed using polynomial regression. The overlay components expressed by the K value include, for example, an offset component (shift), a magnification component, and an orthogonality component. The formulas corresponding to the components are shown below. Note that in the following formulas, "x" and "y" correspond to a coordinate (X coordinate) in the X direction and a coordinate (Y coordinate) in the Y direction, respectively. The elements "dx" and "dy" correspond to the overlay deviation amounts in the X direction and Y direction, respectively.“K1” to “K6” correspond to the respective coefficients (polynomial regression coefficients) of the overlay deviation components.

[0019] An offset component (shift) in the X direction is “dx = K1”.

[0020] The displacement component in the Y direction is “dy = K2”.

[0021] The magnification component in the X direction is “dx = K3 x”.

[0022] The magnification component in the Y direction is “dy = K4·y”.

[0023] An orthogonality component in the X direction is “dx = K5 y”.

[0024] An orthogonality component in the Y direction is “dy = K6 x”.

[0025] In this example, the amount of interference deviation Ex in the X direction is calculated by "Ex=K1+K3*x+K5*y." The amount of interference deviation Ey in the Y direction is calculated by "Ey=K2+K4*y+K6*x." In a case where the interference component is expressed by polynomial regression, not only K1 to K6 but also a coefficient associated with a higher-order interference component can be used as the polynomial regression coefficient. In addition, the interference deviation amount described above can be calculated in units of shots and in the plane of the wafer. Hereinafter, the interference component of a magnification component generated in the wafer surface is also referred to as the "wafer magnification component." The wafer magnification component belongs to the wafer size. The randomly generated interference component on the wafer surface is referred to as the "random component."

[0026] Fig. Figure 2 is a schematic diagram showing an example of the arrangement of alignment marks AM in the process steps for manufacturing a semiconductor device. (A) in Fig. Figure 2 shows the arrangement of a plurality of alignment marks AM on the wafer WF, which are measured during the exposure process. (B) in Fig. Figure 2 shows the arrangement of a plurality of alignment marks AM on the wafer WF, which are measured during the bonding process.

[0027] As in (A) of Fig. As shown in Figure 2, during the exposure process, the exposure device measures the alignment marks AM at a plurality of points arranged on the wafer WF (i.e., the upper wafer UW or the lower wafer LW). The number of measured alignment marks AM is preferably three or more. The exposure device can calculate the alignment correction values, such as the displacement component, the magnification component, and the orthogonality component in the X and Y directions, by performing functional approximation on the measurement results of the alignment marks AM at the plurality of points in the orthogonal coordinate system. Furthermore, the exposure device can correct each of the superpositions in units of shots and the superposition in the wafer surface based on the measurement results of the alignment marks AM at the plurality of points.

[0028] As in (B) of Fig. For example, as shown in Figure 2, during the bonding process, the bonding device measures three alignment marks AM_C, AM_L, and AM_R located on the upper wafer UW and the lower wafer LW. The alignment mark AM_C is located near the center of the wafer. The alignment marks AM_L and AM_R are located on either side of the outer edge of the wafer, respectively. The bonding device can calculate the alignment correction values ​​of the displacement component and the rotation component based on the alignment marks AM_C, AM_L, and AM_R of the upper wafer UW and the lower wafer LW. The bonding device can also correct the magnification component of the wafer common to the X and Y directions by deforming the wafer holder.

[0029] Fig. Figure 3 is a table illustrating an example of the correction performance of the exposure device and the bonding device with respect to the overlay component in the wafer surface that may remain in the bond OL. As shown in Fig. As shown in Figure 3, the displacement component can be corrected in both the exposure device and the bonding device. The wafer magnification component (XY common magnification component) common to the X direction and the Y direction can be corrected in both the exposure device and the bonding device. The wafer magnification component (XY differential magnification component) with a difference between the X direction and the Y direction can be corrected in the exposure device. On the other hand, it is difficult to correct the XY differential magnification component in the bonding device. The rotation component (orthogonality component common to the X direction and the Y direction) can be corrected in both the exposure device and the bonding device. The orthogonality component can be corrected in the exposure device.On the other hand, it is difficult to correct the orthogonality component in the bonding device. The random component can be corrected in units of shots in the exposure device. On the other hand, it is difficult to correct the random component in the bonding device.

[0030] For example, the bonding process apparatus may adjust the wafer magnification component (common XY magnification component) of the interference between the upper wafer UW and the lower wafer LW by deforming the lower wafer LW fixture to increase the wafer magnification component of the lower wafer LW. However, the tendency of the random component of the interference changes depending on the amount of deformation of the lower fixture. Therefore, the random component of the bond OL may deteriorate according to the amount of correction of the wafer magnification component by the lower fixture. On the other hand, it is also conceivable to improve the bond OL by aligning the wafer magnification components of the upper wafer UW and the lower wafer LW through the exposure process at the time of patterning the bonded surface.However, adjusting the wafer magnification component on the bonded surface may deteriorate the overlay between the pattern of the bonded surface and the pattern of the base in the other wafer on which the bonded surface exposure process is performed in accordance with the wafer magnification component of the one wafer as a reference. <1> First embodiment

[0031] A first embodiment relates to an exposure apparatus and an exposure method capable of improving the superposition of a wafer enlargement component in a bonding process and the superposition of a bonding layer and a base thereof. The details of the first embodiment are described below. <1-1> Structure of the exposure device 1

[0032] An exposure apparatus 1 according to the first embodiment is configured to transport the wafer WF to and from the coating development apparatus. The "coating development apparatus" is an apparatus that performs pre- and post-processes of the exposure process. The pre-process of the exposure process includes a process of coating the wafer with a resist material (photosensitive material). The post-process of the exposure process includes a process of developing a pattern with which the wafer is exposed. Note that a variety of semiconductor manufacturing apparatuses can also be used as apparatuses used in the pre- and post-processes of the exposure process.

[0033] Fig. 4 is a block diagram showing an example of a configuration of the exposure apparatus 1 according to the first embodiment. As shown in Fig. 4, the exposure device 1 comprises, for example, a control device 11, a storage device 12, a carrier or transport device 13, a communication device 14 and an exposure unit 15.

[0034] The control device 11 is a computer or the like that controls the overall operation of the exposure device 1. The control device 11 controls each of the storage device 12, the support device 13, the communication device 14, and the exposure unit 15. Although not shown, the control device 11 is equipped with a central processing unit (CPU), a read-only memory (ROM), a random access memory (RAM), and the like. The CPU is a processor that executes various programs related to device control. The ROM is a non-volatile storage medium that stores a device control program. The RAM is a volatile storage medium used as the work area of ​​the CPU.

[0035] The storage device 12 is a storage medium used for storing data, programs, and the like. The storage device 12 stores, for example, an exposure recipe 21 and correction value information 22. Note that the storage device 12 may be connected externally to the exposure device 1.

[0036] The exposure recipe 21 is a table in which the settings of the exposure process are recorded. The exposure recipe 21 includes information such as the shape and layout of the shot, an exposure amount (dose), a focus setting, and an alignment setting for each exposure step. Alignment setting includes the selection of a normal mode and upper and lower limit correction modes. During alignment in the normal mode, the alignment is adjusted based on the measurement results of the plurality of alignment marks AM so that it approaches zero within a range where the overlap between the basic pattern and the exposure process pattern is possible.In the alignment in the upper and lower limit correction mode, based on the measurement results of the plurality of alignment marks AM, the wafer magnification component in the exposure process target wafer is adjusted to approach the target value W_Mag_TG within a possible range taking into account the upper limit U_Limit and / or the lower limit L_Limit.

[0037] The correction value information 22 includes information about the target value W_Mag_TG, the upper limit value U_Limit, and the lower limit value L_Limit in the step to which the upper and lower limit value correction mode is applied. The target value W_Mag_TG corresponds to the numerical value of the wafer magnification component of one of the linked sets of the upper wafer UW and the lower wafer LW for which the front-end process has already been completed. For example, the wafer magnification component of the upper wafer UW for which the front-end process has already been completed is used as the target value W_Mag_TG.In this case, in the exposure process associated with the bonded surface of the lower wafer LW, the alignment correction value of the wafer magnification component at the time of alignment is adjusted to approach the wafer magnification component of the upper wafer UW while taking into account the upper limit value U_Limit and / or the lower limit value L_Limit.

[0038] The upper limit value U_Limit and the lower limit value L_Limit specify the range of the alignment measurement value allowed for adjusting the wafer magnification component to the target value W_Mag_TG. The upper limit value U_Limit and the lower limit value L_Limit are based on the management specification of the overlay deviation of the wafer magnification component allowed between the basic pattern and the exposure process pattern. The management specification can be paraphrased as a "management value." The upper limit value U_Limit corresponds to a value obtained by adding the upper limit value (upper limit management value) of the management specification to the target value W_Mag_TG. The lower limit value L_Limit corresponds to a value obtained by adding the lower limit value (lower limit management value) of the management specification to the target value W_Mag_TG.The upper limit of the management specification is a positive numerical value, and the lower limit of the management specification is a negative numerical value. For example, in a case where the management specification is ±2 ppm and the target value W_Mag_TG is 0.5 ppm, the upper limit U_Limit is set to 2.5 ppm and the lower limit L_Limit is set to -1.5 ppm. Note that ppm represents 1 section per million. For example, in a case where the wafer magnification component is 1 ppm as a result of alignment measurement on a wafer with a diameter of 300 mm by the exposure device, it is specified that the wafer diameter is 300.0003 mm in the exposure device standard.Similarly, in a case where the wafer magnification component is -1 ppm, which is due to an alignment measurement on a wafer with a diameter of 300 mm by the exposure device, it is indicated that the diameter of the wafer in the exposure device standard is 299.9997 mm.

[0039] The carrier device 13 is a device equipped with a carrier arm capable of supporting a wafer WF, a transfer station for temporarily placing a plurality of wafers, and the like. For example, the carrier device 13 carries the wafer WF received from an external coating and development device to the exposure unit 15. Furthermore, after the exposure process, the carrier device 13 carries the wafer WF received from the exposure unit 15 to the external coating and development device.

[0040] The communication device 14 is a communication interface that can be connected to the network (not shown). The exposure device 1 can be operated via a terminal in a network.

[0041] The exposure recipe 21 and the correction value information 22 can be stored in a server on the network.

[0042] The exposure unit 15 is a group of elements used in the exposure process. The exposure unit 15 includes, for example, a wafer stage 31, a reticle stage 32, a light source 33, a projection optical system 34, and a camera 35. The wafer stage 31 holds a wafer WF. The reticle stage 32 holds a reticle RT (mask). The respective positions of the stage, the wafer 31, and the reticle 32 can be controlled via the control device 11. The light source 33 irradiates the reticle RT with generated light. The projection optical system 34 collects the light transmitted through the reticle RT onto the surface of the wafer WF. The camera 35 is an imaging device used to measure the alignment marks AM. The wafer WF can be irradiated with light reflected from the mask RT. In this case, the optical projection system includes a plurality of mirrors. <1-2> Exposure method

[0043] Fig. 5 is a flowchart illustrating an example of an exposure method of the exposure apparatus 1 according to the first embodiment. The following will be described with reference to Fig. 5, as an exposure method of the exposure apparatus 1 according to the first embodiment, a case where an exposure process of an exposure step in which an upper and lower limit correction mode is activated is performed is described.

[0044] When the coating and developing device reports the completion of the pre-process for the wafer WF, the exposure device 1 starts the exposure process (start).

[0045] First, the exposure device 1 loads a wafer WF (S101). The loaded wafer WF is held by the holder 31.

[0046] Next, the exposure device 1 checks the exposure recipe 21 (S102). Specifically, the control device 11 determines the process conditions to be applied to the loaded wafer WF based on the exposure recipe 21. The process conditions include, for example, the exposure shape and layout, an exposure amount (dose), a focus adjustment, and an alignment adjustment. In this example, the process conditions under which the alignment of the upper and lower limit correction modes is valid are read.

[0047] Next, the exposure device 1 checks the correction value information 22 (S103). Specifically, the control device 11 acquires detailed alignment settings in the upper and lower correction modes, namely, the target value W_Mag_TG, the upper limit value U_Limit, and the lower limit value L_Limit in the exposure step.

[0048] Next, the exposure device 1 measures the alignment marks AM (S104). Specifically, the stage 31 moves accordingly, and the camera 35 photographs a plurality of alignment marks AM arranged at predetermined positions on the wafer WF. For example, at least three alignment marks AM are photographed. The positions of the alignment marks AM to be photographed in the process of S104 are determined based on the exposure recipe 21.

[0049] Next, the exposure device 1 calculates a base wafer magnification component W_Mag_B (S105). Specifically, the control device 11 calculates the base wafer magnification component W_Mag_B by functionally approximating the measurement results of the plurality of alignment marks AM in the orthogonal coordinate system. The value of the wafer magnification component W_Mag_B may vary for each wafer WF depending on process variations.

[0050] Next, the exposure apparatus 1 checks the value of the wafer magnification component W_Mag_B (S106).

[0051] When the value of the wafer magnification component W_Mag_B is below the lower limit value L_Limit (S106: below L_Limit), the exposure apparatus 1 sets the alignment correction value of the wafer magnification component to “target value W_Mag_TG + wafer magnification component W_Mag_B - lower limit value L_Limit” (S107) and proceeds to the process of S110.

[0052] When the value of the wafer magnification component W_Mag_B is in the range between the lower limit value L_Limit or more and the upper limit value U_Limit or less (S106: in the range between L_Limit or more to U_Limit or less), the exposure apparatus 1 sets the alignment correction value of the wafer magnification component to “target value W_Mag_TG” (S108) and proceeds to the process of S110.

[0053] When the value of the wafer magnification component W_Mag_B exceeds the upper limit value U_Limit (S106: Exceeding U_Limit), the exposure apparatus 1 sets the alignment correction value of the wafer magnification component to “target value W_Mag_TG + wafer magnification component W_Mag_B - upper limit value U_Limit” (S109) and proceeds to the process of S110.

[0054] In process S110, the exposure apparatus 1 executes an exposure sequence (S110). Specifically, the control device 11 controls the wafer stage 31 based on the alignment correction value of the wafer magnification component determined in any of the processes S107, S108, and S109, and irradiates the wafer WF with the light transmitted through the reticle RT using the light source 33.

[0055] When the process S110 is completed, the exposure device 1 unloads the wafer WF (S111). When the wafer WF is unloaded, the exposure device 1 ends the exposure process (End).

[0056] Fig. 6 is a schematic diagram illustrating an example of the superimposition results of the exposure process of the exposure apparatus 1 according to the first embodiment. Fig. For example, Figure 6 shows the basic image shapes corresponding to the wafer magnification component (five conditions of 2 ppm, 1 ppm, 0 ppm, -1 ppm, and -2 ppm) of the lower wafer LW and the image shapes of the exposure process under three conditions of the "with correction" case, the "without correction" case, and the "upper and lower limit correction" case. In this example, the upper limit U_Limit is set to 1 ppm, the lower limit L_Limit is set to -1 ppm, and the target W_Mag_TG is set to 0 ppm.

[0057] "With Correction" is part of the exposure process result when normal mode alignment is applied. When the base wafer magnification component is 2 ppm, 1 ppm, 0 ppm, -1 ppm, and -2 ppm, the wafer magnification component correction value in the exposure process is set to 2 ppm, 1 ppm, 0 ppm, -1 ppm, and -2 ppm based on the base wafer alignment measurement value. As a result, the overlay deviation (exposure OL) of the exposure pattern with respect to the base becomes 0 ppm in each case where the base wafer magnification component is 2 ppm, 1 ppm, 0 ppm, -1 ppm, and -2 ppm. Therefore, in the exposure process with correction, even if the magnification component of the base wafer is 2 ppm, 1 ppm, 0 ppm, -1 ppm or -2 ppm, the deviation of the overlay (exposure OL) of the wafer magnification component between the base pattern and the exposure pattern can be kept within the management specification (“OK” in Fig. 6).

[0058] "No correction" refers to the exposure process result when the wafer magnification component correction based on the alignment measurement value is not applied. For example, the alignment correction value of the wafer magnification component in the exposure process is set to 0 ppm based on the preset alignment correction value, even if the base wafer magnification component is 2 ppm, 1 ppm, 0 ppm, -1 ppm, or -2 ppm. For example, the preset alignment correction value is set based on the numerical value of the wafer magnification component of the upper wafer UW. In this example, the numerical value of the wafer magnification component of the upper wafer UW is 0 ppm.In this case, the deviation of the overlay (exposure OL) of the exposure pattern with respect to the base is -2 ppm, -1 ppm, 0 ppm, -1 ppm, and -2 ppm, respectively. Therefore, in the exposure process without correction, in a case where the base wafer magnification component is 1 ppm, 0 ppm, and -1 ppm, the overlay deviation of the wafer magnification component between the base pattern and the exposure pattern can be maintained within the management specification ("OK" in . Fig. 6). On the other hand, in the exposure process without correction, in a case where the base wafer magnification component is 2 ppm and -2 ppm, the overlay deviation of the wafer magnification component between the base pattern and the exposure pattern cannot be kept within the management specification (“NG” in Fig. 6).

[0059] The "upper and lower limit correction" is one of the exposure process results when the upper and lower limit correction mode adjustment is applied. When the base wafer magnification component is 2 ppm, 1 ppm, 0 ppm, -1 ppm, and -2 ppm, the alignment correction value of the wafer magnification component during the exposure process is set to 1 ppm, 0 ppm, 0 ppm, 0 ppm, and -1 ppm, respectively. Specifically, in a case where the base wafer magnification component is in the range of -1 ppm or more and 1 ppm or less, the alignment correction value of the wafer magnification component during the exposure process is set to 0 ppm based on the target value W_Mag_TG.On the other hand, in a case where the base wafer magnification component is 2 ppm, the alignment correction value of the wafer magnification component during the exposure process is set to 0 ppm (target value W_Mag_TG) + 2 ppm (wafer magnification component W_Mag_B) - 1 ppm (upper limit U_Limit) = 1 ppm based on the upper limit U_Limit. Similarly, in a case where the base wafer magnification component is -2 ppm, the alignment correction value of the wafer magnification component during the exposure process is set to 0 ppm (target value W_Mag_TG) + (-2 ppm) (wafer magnification component W_Mag_B) - (-1 ppm) (lower limit L_Limit) = 1 ppm based on the lower limit L_Limit. As a result, the deviation of the overlay (exposure OL) of the exposure pattern for each of the cases where the base wafer magnification component is 2 ppm, 1 ppm, 0 ppm, -1 ppm, and -2 ppm, respectively, is -1 ppm, -1 ppm, 0 ppm, 1 ppm, and 1 ppm.Therefore, in the exposure process with upper and lower limit correction, even in a case where the base wafer magnification component is 2 ppm, 1 ppm, 0 ppm, -1 ppm, or -2 ppm, the overlay deviation of the wafer magnification component between the base pattern and the exposure pattern can be kept within the management specification (“OK” in . Fig. 6).

[0060] Fig. 7 is a table illustrating an example of an alignment correction value of a wafer magnification component by the exposure process of the exposure apparatus 1 according to the first embodiment. Fig. Figure 7 shows an example of a result of executing the exposure process in which the alignment of the upper and lower limit correction modes is applied to 10 wafers WF. It shows an alignment measurement value (base wafer magnification component W_Mag_B), an alignment correction value of the applied wafer magnification component, and a prediction value for the overlay deviation for these results. In this example, the target value W_Mag_TG is set to 0.5 ppm, the upper limit value U_Limit is set to 2.5 ppm, which is 2 ppm higher than the target value W_Mag_TG, and the lower limit value L_Limit is set to -1.5 ppm, which is 2 ppm lower than the target value W_Mag_TG.

[0061] As in Fig. As shown in Figure 7, the alignment measurements of the 10 wafers (No. 1 to No. 10) are 2.3 ppm, -1.1 ppm, 1.2 ppm, 3.2 ppm, 1.6 ppm, 0.5 ppm, -1.4 ppm, -2.3 ppm, -0.3 ppm, and 1.5 ppm, respectively. In this example, wafer No. 4 exceeds the upper limit U_Limit (upper limit NG), and wafer No. 8 falls below the lower limit L_Limit (lower limit NG).

[0062] In this case, the wafer magnification component alignment correction value applied to wafer No. 4 is set to 0.5 ppm (target value W_Mag_TG) + 3.2 ppm (wafer magnification component W_Mag_B) - 2.5 ppm (upper limit value U_Limit) = 1.2 ppm based on the process of S109. The wafer magnification component alignment correction value applied to wafer No. 8 is set to 0.5 ppm (target value W_Mag_TG) + (-2.3 ppm) (wafer magnification component W_Mag_B) - (-1.5 ppm) (lower limit value L_Limit) = 0.3 ppm based on the process of S107. The wafer magnification component alignment correction value applied to the wafers except No. 4 and No. 7 is set to 0.5 ppm based on the process of S108.

[0063] The overlay deviation prediction values ​​for wafers No. 1 to No. 10 by applying the wafer magnification component correction described above are -1.8 ppm, 1.6 ppm, -0.7 ppm, -2.0 ppm, -1.1 ppm, 0 ppm, 1.9 ppm, 2.0 ppm, 0.8 ppm, and -1.0 ppm, respectively. As described above, the overlay deviation prediction values ​​for wafers No. 1 to No. 10 are within the management specifications. That is, the wafer magnification component of each of wafers No. 1 to No. 10 is set to a value as close as possible to the target W_Mag_TG, while the overlay deviation with respect to the baseline is set within the management specifications.

[0064] Fig. 8 is a scattergram illustrating an example of the distribution of a wafer magnification component after the exposure process of the exposure apparatus 1 according to the first embodiment. Fig. Figure 8 shows the distribution of the wafer magnification component in a case where the alignment in normal mode is set to the Fig. 7, and the distribution of the wafer magnification component in a case where the alignment in the upper and lower limit correction mode is set to the values ​​shown in Fig. 7 shown 10 wafer WF is applied. As shown in Fig. As shown in Figure 8, 3σ of the wafer magnification component in a case where alignment is applied in the normal mode is 5.3 ppm. On the other hand, 3σ of the wafer magnification component in a case where the upper and lower limit correction mode is applied is 1.1 ppm. As described above, the deviation of the wafer magnification component in a case where the upper and lower limit correction mode is applied is smaller than the deviation of the wafer magnification component in a case where alignment is applied in the normal mode. <1-3> Advantageous effects of the first embodiment

[0065] In the bonding layer exposure process, the exposure apparatus 1 according to the first embodiment performs alignment based on the base wafer magnification component W_Mag_B, the target value W_Mag_TG, the upper limit value U_Limit, and the lower limit value L_Limit. Specifically, the wafer magnification component of the bonding layer is corrected to the target value W_Mag_TG when the wafer magnification component W_Mag_B is within the range of the lower limit value L_Limit or more and the upper limit value U_Limit or less. Furthermore, the wafer magnification component of the bonding layer is corrected to approach the target value W_Mag_TG within the management specification of the interference between the base pattern and the exposure process pattern when the wafer magnification component W_Mag_B is outside the range of the upper limit value U_Limit or more and the lower limit value L_Limit or less.

[0066] Therefore, the exposure apparatus 1 according to the first embodiment can correct the interference between the interconnection layer and its base within a range where the influence on yield is small, and suppress the variation of the wafer magnification component in the interconnection layer. By setting the correction amount of the wafer magnification component in the interconnection process to a substantially constant value, the deterioration of the random component due to the variation of the wafer magnification component can be suppressed. Therefore, the exposure apparatus 1 according to the first embodiment can improve both the interference of the interconnection layer and its base and the interference of the upper wafer UW and the lower wafer LW in the interconnection process, and improve the yield of the semiconductor device.

[0067] Note that the alignment in the exposure process is usually adjusted to minimize the overlay deviation between the base pattern and the exposure process pattern, that is, to achieve the calculated value of the magnification component. Furthermore, in a case where the target value W_Mag_TG of the wafer magnification component is set, the alignment correction value of the wafer magnification component is assumed to be set to the target value W_Mag_TG. In contrast, in the exposure method of the first embodiment, the alignment correction value of the magnification component may deviate from both the target value W_Mag_TG and the calculated value (wafer magnification component W_Mag_B).

[0068] The alignment correction value of the magnification component in the first embodiment may be set to at least the first correction value (target value W_Mag_TG) when the calculated value of the wafer magnification component (wafer magnification component W_Mag_B) is within the range of the lower limit value L_Limit or more and the upper limit value U_Limit or less, to the second correction value that is larger than the wafer magnification component W_Mag_B and smaller than the target value W_Mag_TG in a case where the wafer magnification component W_Mag_B is smaller than the lower limit value L_Limit, and to the third correction value that is larger than the target value W_Mag_TG and smaller than the wafer magnification component W_Mag_B in a case where the wafer magnification component W_Mag_B exceeds the upper limit value U_Limit, according to the management specification of the overlay deviation.The second correction value is preferably a value obtained by adding the calculated value to the first correction value and further subtracting the lower limit value L_Limit. The third correction value is preferably a value obtained by adding the calculated value to the first correction value and further subtracting the upper limit value U_Limit. <2> Second embodiment

[0069] A second embodiment relates to a method for manufacturing a semiconductor device, in which the exposure method described in the first embodiment is applied to a plurality of layers near an interconnection layer, and a variation in a wafer magnification component with respect to a target value in chucks is suppressed. The following describes the details of the second embodiment mainly with respect to differences from the first embodiment. <2-1> Method for manufacturing a semiconductor device

[0070] Fig. 9 is a flowchart illustrating an example of the method for manufacturing a semiconductor device according to the second embodiment. Hereinafter, as the method for manufacturing a semiconductor device according to the second embodiment, a case will be described in which the exposure process is carried out using the upper and lower limit correction modes in three exposure steps for a predetermined wafer WF, referring to Fig. 9 is referred to.

[0071] First, in the exposure step associated with a first layer, the exposure process is performed using the upper and lower limit correction modes (S201). Next, in the exposure step associated with a second layer, the exposure process is performed using the upper and lower limit correction modes (S202). Next, in the exposure step associated with a third layer (bonding layer), the exposure process is performed using the upper and lower limit correction modes (S203). Subsequently, the bonding process is performed using the wafers WF for which the respective processes S201 to S203 have been performed (S204). When the alignment correction value is calculated in each of the processes S201 to S203, since the wafers WF to be combined are the same, the same target value W_Mag_TG of the wafer magnification component is used.On the other hand, the upper limit U_Limit and the lower limit L_Limit of the wafer magnification component can be set individually for each exposure step.

[0072] Fig. 10 is a box-and-whisker diagram showing an example of a change in the distribution of a wafer enlargement component by the method for manufacturing a semiconductor device according to the second embodiment. Fig. Fig. 10 shows a change in the variation of the wafer magnification component in a case where the exposure process to which the adjustment of the upper and lower limit correction mode is applied as in Fig. 9, is carried out in each of the first to third shifts in a predetermined batch. In this example, the target value W_Mag_TG is 0 ppm.

[0073] As in Fig. As shown in Figure 10, the area of ​​the wafer magnification component in the base of the first layer is 6.0 ppm (measurement (1)).

[0074] In the first layer, the allowable value (management specification) of the wafer magnification component deviation is ± 1.0 ppm. The first layer exposure process is performed using the upper limit U_Limit and the lower limit L_Limit, which are set based on this numerical value (exposure (1)). This improves the wafer magnification component range in the first layer by 2 ppm to 4.0 ppm (measurement (2)).

[0075] In the second layer, the allowable value (management specification) of the wafer magnification component deviation is ± 0.4 ppm. The exposure process of the second layer is performed using the upper limit U_Limit and the lower limit L_Limit, which are set based on this numerical value (exposure (2)). This improves the wafer magnification component range in the second layer by 0.8 ppm to 3.2 ppm (measurement (3)).

[0076] In the third layer, the allowable value (management specification) of the wafer magnification component deviation is ± 0.5 ppm. The third layer exposure process is performed using the upper limit U_Limit and the lower limit L_Limit, which are set based on this numerical value (Exposure (3)). As a result, the wafer magnification component range in the third layer is improved by 1.0 ppm to 2.2 ppm (Measurement (3)). <2-2> Advantageous effects of the second embodiment

[0077] As described above, the alignment in the upper and lower limit correction mode described in the first embodiment can be applied to a layer other than the interconnect layer, or in a plurality of steps. Then, in the method for manufacturing a semiconductor device according to the second embodiment, the alignment to which the upper and lower limit correction mode is applied is performed in a plurality of steps, so that the wafer magnification component reaches the target value in stages.

[0078] As a result, the method for manufacturing a semiconductor device according to the second embodiment can reduce the correction amount of the interference between the bonding layer and the base thereof and improve the interference between the bonding layer and the base thereof compared to the case where the alignment of the upper and lower limit correction modes is applied only to the bonding layer. Furthermore, the method for manufacturing a semiconductor device according to the second embodiment can suppress the deterioration of the random component in the bonding process, similar to the first embodiment. Therefore, the method for manufacturing a semiconductor device according to the second embodiment can improve the yield of the semiconductor device. <3> Third embodiment

[0079] In the third embodiment, the exposure apparatus 1 is configured so that the upper limit value U_Limit and the lower limit value L_Limit of the wafer magnification component can be set independently in the X and Y directions. Then, the upper limit value U_Limit and the lower limit value L_Limit are set in the X and Y directions according to the overlay margins, respectively, and the range in the wafer magnification component with respect to the target value is gradually suppressed. The following describes the details of the third embodiment mainly with respect to the differences from the first and second embodiments. <3-1> Exposure method

[0080] Fig. 11 is a flowchart illustrating an example of an exposure method of the exposure apparatus according to the third embodiment. The following will be described with reference to Fig. 11, as an exposure method of the exposure apparatus 1 according to the third embodiment, a case in which an exposure process of an exposure step in which an upper and lower limit correction mode is activated is performed will be described.

[0081] When the coating and developing device reports the completion of the pre-process for the wafer WF, the exposure device 1 starts the exposure process (start).

[0082] First, the exposure apparatus 1 performs the same processes as in S101 to S104, similar to the first embodiment. That is, the exposure apparatus 1 loads the wafer WF (S101). Then, the exposure apparatus 1 checks the exposure recipe 21 (S102) and checks the correction value information 22 (S103). Then, the exposure apparatus 1 measures the alignment marks AM (S104).

[0083] Next, the exposure device 1 calculates the basic wafer magnification components W_Mag_BX and W_Mag_BY (S301). Specifically, the control device 11 calculates the basic wafer magnification component (W_MagBX) in the X direction and the basic wafer magnification component (W_MagBY) in the Y direction by performing functional approximation on the measurement results of the plurality of alignment marks AM in the orthogonal coordinate system.

[0084] Next, the exposure device 1 sets an alignment correction value of the wafer magnification component in the X direction based on the wafer magnification component W_Mag_BX, the target value W_Mag_TG, the lower limit value L_Limit_X, and the upper limit value U_Limit_X (S302). Specifically, the exposure device 1 performs the processes similar to S106 to S109 in Fig. 5 to calculate the alignment correction value of the wafer magnification component in the X direction. The upper limit value U_Limit_X is a value based on the upper limit management value of the wafer magnification component in the X direction in the exposure step. The lower limit value L_Limit_X is a value based on the lower limit management value of the wafer magnification component in the X direction in the exposure step. For example, in a case where the value of W_MagBX is smaller than the lower limit value L_Limit_X, the alignment correction value of the wafer magnification component in the X direction is set by the exposure device 1 to "target value W_Mag_TG + wafer magnification component W_Mag_BX - lower limit value L_Limit_X".If the value of W_MagBX is within the range of the lower limit value L_Limit_X or higher and the upper limit value U_Limit_X or lower, the exposure device 1 sets the alignment correction value of the wafer magnification component in the X direction to the "target value W_Mag_TG." If the value of W_MagBX exceeds the upper limit value U_Limit_X, the exposure device 1 sets the alignment correction value of the wafer magnification component in the X direction to "target value W_Mag_TG + wafer magnification component W_Mag_BX - upper limit value U_Limit_X."

[0085] Next, the exposure device 1 sets an alignment correction value of the wafer magnification component in the Y direction based on the wafer magnification component W_Mag_BY, the target value W_Mag_TG, the lower limit value L_Limit_Y, and the upper limit value U_Limit_Y (S303). Specifically, the exposure device 1 performs the operations performed in S106 to S109 in Fig. 5 to calculate the alignment correction value of the wafer magnification component in the Y direction. The upper limit value U_Limit _Y is a value based on the upper limit management value of the wafer magnification component in the Y direction in the exposure step. The lower limit value L_Limit _Y is a value based on the lower limit management value of the wafer magnification component in the Y direction in the exposure step. The upper limit value U_Limit _Y can be the same as or different from the upper limit value U_Limit _X. The lower limit value L_Limit _Y can be the same as or different from the lower limit value L_Limit _X. For example, in a case where the value of W_MagBY is smaller than the lower limit value L_Limit_Y, the alignment correction value of the wafer magnification component in the Y direction of the exposure apparatus 1 is set to “target value W_Mag_TG + wafer magnification component W_Mag_BY - lower limit value L_Limit_Y”.If the value of W_MagBY is within the range of the lower limit value L_Limit_Y or higher and the upper limit value U_Limit_Y or lower, the exposure device 1 sets the alignment correction value of the wafer magnification component in the Y direction to the "target value W_Mag_TG." If the value of W_MagBY exceeds the upper limit value U_Limit_Y, the exposure device 1 sets the alignment correction value of the wafer magnification component in the Y direction to "target value W_Mag_TG + wafer magnification component W_Mag_BY - upper limit value U_Limit_Y."

[0086] Next, the exposure apparatus 1 executes an exposure sequence similar to the first embodiment (S110). Specifically, the control device 11 controls a wafer stage 31 based on the alignment correction value of the wafer magnification component determined in processes S302 and S303, and irradiates the wafer WF with the light transmitted through the reticle RT using a light source 33.

[0087] When the process of S110 is completed, the exposure device 1 unloads the wafer WF (S111). When the wafer WF is unloaded, the exposure device 1 ends the exposure process (End).

[0088] In processes S302 and S303, a common component (wafer magnification component W_Mag_B) of the wafer magnification components in the X and Y directions can be used as the value of the basic wafer magnification component. The upper and lower limit correction mode can be applied to the calculation of the alignment correction value of one of the wafer magnification components in the X and Y directions, and the normal mode can be applied to the calculation of the alignment correction value of the other wafer magnification component. In this case, one of the values ​​S302 and S303 is omitted. Furthermore, in the upper and lower limit correction mode, in a case where both the upper limit and the lower limit of the management specification are essentially zero, the alignment is similar to the normal mode.That is, in the upper and lower limit value correction mode, the exposure device 1 can perform alignment to which the upper and lower limit value correction mode is applied substantially only in one direction by setting the upper limit value and the lower limit value of one of the management specifications in the X direction and the Y direction to substantially zero and setting the upper limit value and the lower limit value of the other of the management specifications in the X direction and the Y direction accordingly.

[0089] Fig. 12 is a schematic diagram illustrating an example of superimposition results by the exposure process of the exposure apparatus according to the third embodiment. Fig. Figure 12 shows the basic image shape corresponding to the wafer magnification component (five conditions of 2 ppm, 1 ppm, 0 ppm, -1 ppm, and -2 ppm) and the image shape of the exposure process under three conditions of the "X normal / Y upper and lower limit correction" case, the "X upper and lower limit correction / Y normal" case, and the "X / Y upper and lower limit correction" case. In this example, the upper limit values ​​U_Limit _X and U_Limit _Y are set to 1 ppm, the lower limit values ​​L_Limit _X and L_Limit _Y are set to -1 ppm, and the target value W_Mag_TG is set to 0 ppm. Hereinafter, the alignment correction value of the wafer magnification component in the X direction / Y direction in the exposure process is referred to as the "X / Y correction value." The overlay deviation of the exposure pattern in the X direction / Y direction is referred to as the "OL deviations X / Y."

[0090] The "X Normal / Y Upper and Lower Limit Correction" is the exposure process result when the normal mode is aligned in the X direction and the upper and lower limit correction mode is aligned in the Y direction. When the wafer's base magnification component is 2 ppm, 1 ppm, 0 ppm, -1 ppm, and -2 ppm, the X / Y correction value is set to 2 / 1 ppm, 1 / 0 ppm, 0 / 0 ppm, -1 / 0 ppm, and -2 / -1 ppm, respectively.

[0091] Specifically, the alignment correction value of the wafer magnification component in the X direction is set to the same value as the basic wafer magnification component in the X direction based on the alignment application in the normal mode. On the other hand, the alignment correction value of the wafer magnification component in the Y direction is set to 0 ppm based on the target value W_Mag_TG in a case where the basic wafer magnification component in the Y direction is in the range of -1 ppm or more and 1 ppm or less. When the basic wafer magnification component in the Y direction is 2 ppm, the alignment correction value of the wafer magnification component in the Y direction is set to 0 ppm (target value W_Mag_TG) + 2 ppm (wafer magnification component W_Mag_B) - 1 ppm (upper limit U_Limit_Y) = 1 ppm because the upper limit U_Limit_Y is exceeded.When the base wafer magnification component is -2 ppm, the alignment correction value of the wafer magnification component in the Y direction is set to 0 ppm (target value W_Mag_TG) + (-2 ppm) (wafer magnification component W_Mag_B) - (-1 ppm) (lower limit L_Limit_Y) = -1 ppm because it is below the lower limit L_Limit_Y. Therefore, the OL deviations X / Y for the case where the base wafer magnification component is 2 ppm, 1 ppm, 0 ppm, -1 ppm, and -2 ppm are 0 / -1 ppm, 0 / -1 ppm, 0 / 0 ppm, 0 / 1 ppm, and 0 / 1 ppm, respectively. Therefore, in the exposure process, in the case of X normal / Y upper and lower limit correction, even if the base wafer magnification component is 2 ppm, 1 ppm, 0 ppm, -1 ppm or -2 ppm, the overlay deviation of the wafer magnification component between the base pattern and the exposure pattern can be kept within the management specification.

[0092] "X upper and lower limit correction / Y normal" refers to the exposure process results when the X-direction alignment of the upper and lower limit correction mode and the Y-direction alignment of the normal mode are applied. When the wafer's base magnification component is 2 ppm, 1 ppm, 0 ppm, -1 ppm, and -2 ppm, the X / Y correction value is set to 1 / 2 ppm, 0 / 1 ppm, 0 / 0 ppm, 0 / -1 ppm, and -1 / -2 ppm, respectively. Specifically, the wafer magnification component alignment correction value in the Y direction is set to the same value as the base wafer magnification component in the Y direction, based on the normal mode alignment application. On the other hand, the alignment correction value of the wafer magnification component in the X direction is set to 0 ppm based on the target value W_Mag_TG in a case where the basic wafer magnification component in the X direction is in the range of -1 ppm or more and 1 ppm or less.When the base wafer magnification component in the X direction is 2 ppm, the alignment correction value of the wafer magnification component in the X direction is set to 0 ppm (target value W_Mag_TG) + 2 ppm (wafer magnification component W_Mag_B) - 1 ppm (upper limit U_Limit_X) = 1 ppm because it is above the upper limit U_Limit_X. When the base wafer magnification component is -2 ppm, the alignment correction value of the wafer magnification component in the X direction is set to 0 ppm (target value W_Mag_TG) + (-2 ppm) (wafer magnification component W_Mag_B) - (-1 ppm) (lower limit L_Limit_X) = -1 ppm based on the lower limit L_Limit_X. As a result, the OL deviations X / Y for the case where the base wafer magnification component is 2 ppm, 1 ppm, 0 ppm, -1 ppm and -2 ppm are -1 / 0 ppm, -1 / 0 ppm, 0 / 0 ppm, 1 / 0 ppm and 1 / 0 ppm, respectively.Therefore, in the exposure process, in the case of X upper and lower limit / Y normal, even if the base wafer magnification component is 2 ppm, 1 ppm, 0 ppm, -1 ppm or -2 ppm, the overlay deviation of the wafer magnification component between the base pattern and the exposure pattern can be kept within the management specification.

[0093] The "X / Y upper and lower limit correction" is one of the exposure process results when the alignment of the upper and lower limit correction mode is applied in the X and Y directions. When the wafer's base magnification component is 2 ppm, 1 ppm, 0 ppm, -1 ppm, and -2 ppm, the X / Y correction value is set to 1 / 1 ppm, 0 / 0 ppm, 0 / 0 ppm, 0 / 0 ppm, and -1 / -1 ppm, respectively. That is, the wafer magnification component alignment correction value used in the X / Y upper and lower limit correction is similar to a combination of the wafer magnification component Y-direction alignment correction value in the case of the X-normal / upper and lower limit correction and the wafer magnification component X-direction alignment correction value in the case of the X-normal / upper and lower limit correction / Y-normal correction.Therefore, the X / Y OL deviations for the case where the base wafer magnification component is 2 ppm, 1 ppm, 0 ppm, -1 ppm, and -2 ppm are -1 / -1 ppm, -1 / -1 ppm, 0 / 0 ppm, 1 / 1 ppm, and 1 / 1 ppm, respectively. Therefore, in the case of X / Y upper and lower limit correction during exposure, even if the base wafer magnification component is 2 ppm, 1 ppm, 0 ppm, -1 ppm, or -2 ppm, the overlay deviation of the wafer magnification component between the base pattern and the exposure pattern can be maintained within the management specification. <3-2> Method for manufacturing a semiconductor device

[0094] Fig. 13 is a flowchart illustrating an example of the method for manufacturing a semiconductor device according to the third embodiment. The following will be described with reference to Fig. 13, as a method of manufacturing a semiconductor device according to the third embodiment, a case will be described in which an exposure process capable of separately using a normal mode and upper and lower limit correction modes in two directions is carried out in three exposure steps for a predetermined wafer WF.

[0095] First, in the exposure step associated with the first layer, the exposure process is performed with the wafer magnification component in the first direction (for example, the X direction) set in the normal mode and the wafer magnification component in the second direction (for example, the Y direction) set in the upper and lower limit correction mode (S311). Next, in the exposure step associated with the second layer, the exposure process is performed with the wafer magnification component in the second direction (for example, the Y direction) set in the normal mode and the wafer magnification component in the first direction (for example, the X direction) set in the upper and lower limit correction mode (S312).Next, in an exposure step associated with the third layer (bonding layer), an exposure process is performed in which the wafer magnification components in the first direction and the second direction are set in the upper and lower limit correction mode (S313). Then, the bonding process is performed using the wafers WF for which the respective processes from S311 to S313 have been performed (S314). When calculating the alignment correction value in each of S311 to S313, since the wafers WF to be bonded are the same, the same target value W_Mag_TG of the wafer magnification component is used. On the other hand, the upper limit value U_Limit and the lower limit value L_Limit of the wafer magnification component in each of the first and second directions can be set individually for each exposure step.

[0096] Fig. 14 is a box-and-whisker diagram showing an example of a change in the distribution of a wafer enlargement component by the method for manufacturing a semiconductor device according to the third embodiment. Fig. Fig. 14 shows a change in the variation of the wafer magnification component (W_Mag_X) in the X direction and the wafer magnification component (W_Mag_Y) in the Y direction in a case where the exposure process to which the upper and lower limit alignment mode is applied is as in Fig. 13, is carried out in each of the first to third shifts in a given batch. In this example, the target value W_Mag_TG is 0 ppm.

[0097] As in Fig. As shown in Figure 14, the range of the wafer magnification component in the X direction is 6.0 ppm, and the range of the wafer magnification component in the Y direction is 6.0 ppm (measurement (1)). That is, the range of the wafer magnification component X / Y is 6.0 / 6.0 ppm.

[0098] In the first layer, high-precision overlay in the Y direction is required, while an allowable value (management specification) of the deviation of the wafer magnification component in the X direction is ± 1.5 ppm. Therefore, in the exposure process of the first layer, the upper and lower limit correction modes are applied in the X direction, and the alignment, to which the normal mode is applied in the Y direction, is performed based on the management specification (exposure (1)). Therefore, in the exposure process of the first layer, only the range of the wafer magnification component in the X direction is improved by 3.0 ppm. Therefore, the range of the wafer magnification component X / Y after the first layer process is 3.0 / 6.0 ppm (measurement (2)).

[0099] In the second layer, high-precision overlay in the X direction is required, while the allowable value (management specification) of the deviation of the wafer magnification component in the Y direction is ± 1.5 ppm. Therefore, in the exposure process of the second layer, the upper and lower limit correction modes are applied in the Y direction, and the alignment, to which the normal mode is applied, is performed based on the management specification (exposure (2)). Therefore, in the exposure process of the second layer, only the wafer magnification component range in the Y direction is improved by 3.0 ppm. Therefore, the wafer magnification component range X / Y after the second layer process is 3.0 / 3.0 ppm (measurement (3)).

[0100] In the third layer, the allowable value (management specification) of the deviation of the wafer magnification component in the X and Y directions is ±0.5 ppm each. Therefore, in the third layer exposure process, the upper and lower limit correction modes in the X and Y directions are applied based on the management specification (Exposure (3)). As a result, in the third layer exposure process, the range of the wafer magnification component is improved by 1.0 ppm in each of the X and Y directions. As a result, the range of the wafer magnification component X / Y after the third layer process is 2.0 / 2.0 ppm (Measurement (4)).

[0101] Note that in the present example, the case where alignment in the normal mode is applied in the direction where high-precision overlay is required was described, but the present invention is not limited to this. Alignment in the upper and lower limit correction modes may be applied in a direction where high-precision overlay is required. In this case, the management specification in the direction where high-precision overlay is required is set to zero or a small value within a possible range. <3-3> Advantageous effects of the third embodiment

[0102] As described above, the upper limit value and the lower limit value can be individually provided in each of the X and Y directions in the orientation of the upper and lower limit value correction mode as described in the first embodiment. Then, in the method for manufacturing a semiconductor device according to the third embodiment, the orientation of the upper and lower limit value correction mode is applied in a direction in which there is a margin in the management specification based on the management specification of the overlay in the X direction and the management specification of the overlay in the Y direction. Then, in the method for manufacturing a semiconductor device according to the third embodiment, the wafer magnification component is caused to reach the target value in stages, similarly to the second embodiment.

[0103] As a result, the method for manufacturing a semiconductor device according to the third embodiment can reduce the correction amount of the interference between the interconnection layer and the base thereof and improve the interference between the interconnection layer and the base thereof compared to the case where the alignment of the upper and lower limit correction modes is applied only to the interconnection layer, similarly to the second embodiment. Furthermore, the method for manufacturing a semiconductor device according to the third embodiment can suppress the deterioration of the random component in the bonding process, similarly to the first embodiment. Therefore, the method for manufacturing a semiconductor device according to the third embodiment can improve the yield of the semiconductor device. <4> The fourth embodiment

[0104] The fourth embodiment relates to a specific example of a semiconductor device manufactured using the exposure method described in the preceding embodiments. A memory device having a bonding structure will be explained below as a specific example of the semiconductor device. <4-1> Overall configuration of the storage device 100

[0105] Fig. 15 is a block diagram illustrating an example of an overall configuration of a storage device 100 according to a fourth embodiment. As shown in Fig. 15, the memory device 100 includes, for example, a memory interface (memory I / F) 101, a sequencer 102, a memory cell array 103, a driver module 104, a row decoder module 105, and a sense amplifier module 106.

[0106] The memory interface 101 is a hardware interface connected to an external memory controller via a CH channel. The memory interface 101 performs communication between the memory device 100 and the memory controller according to an interface standard. For example, the memory interface 101 supports the NAND interface standard.

[0107] The sequencer 102 is a control circuit that controls the entire operation of the memory device 100. The sequencer 102 controls the driver module 104, the row decode module 105, the sense amplifier module 106, and the like based on a command received via the memory interface 101 to perform a read operation, a write operation, an erase operation, and the like.

[0108] The memory cell array 103 is a memory circuit including a plurality of memory cells. The memory cell array 103 includes a plurality of blocks BLKO to BLKn (n is an integer of 1 or more). Each of the blocks BLK is used, for example, as a data erase unit. The memory cell array 103 is provided with a plurality of bit lines and a plurality of word lines. Each of the memory cells is linked, for example, to one of the bit lines BL and one of the word lines WL. Each of the memory cells is identified based on an address identifying the word line WL and an address identifying the bit line BL.

[0109] Driver module 104 is a driver circuit that generates voltages used in read, write, and erase operations, and the like. Driver module 104 is connected to row decoder module 105 via a plurality of signal lines. Driver module 104 can vary the voltage to be applied to each of the signal lines based on the page address received via memory interface 101.

[0110] The row decoder module 105 is a decoder that decodes a row address received via the memory interface 101. The row decoder module 105 selects a block BLK based on a decoding result. The row decoder module 105 transmits voltages applied to the respective signal lines to the respective lines (e.g., word lines WL) provided in the selected block BLK.

[0111] The sense amplifier module 106 is a read circuit that samples the data read from the selected block BLK based on the voltage of the bit line BL in a read operation. The sense amplifier module 106 transmits the read data to the memory controller via the memory interface 101. In a write operation, the sense amplifier module 106 can apply the voltage associated with the data to be written to the memory cell for each bit line BL. <4-2> Circuit configuration of memory cell array 103

[0112] Fig. 16 is a circuit diagram illustrating an example of a circuit configuration of the memory cell array 103 included in the memory device 100 according to the fourth embodiment. Fig. 16 illustrates one BLK block among a plurality of BLK blocks included in the memory cell array 103. As shown in Fig. 16, the block BLK comprises, for example, four string units SU0 to SU3.

[0113] Each of the string units SU includes a plurality of NAND strings NS. The NAND strings NS are each connected to bit lines BL0 through BLm (m is an integer of 1 or more). Different column addresses are assigned to each bit line BL0 through BLm. Each bit line BL is shared by the NAND strings NS, which are assigned the same column address among the blocks BLK. Each NAND string NS includes, for example, memory cell transistors MT0 through MT7 and selection transistors STD and STS.

[0114] Each memory cell transistor MT includes a control gate and a charge storage layer and stores data non-volatilely. The memory cell transistors MT0 to MT7 of each NAND string NS are connected in series. The control gates of the memory cell transistors MT0 to MT7 are connected to the word lines WL0 to WL7, respectively. Each of the word lines WL0 to WL7 is dedicated to each block BLK. For example, a group of a plurality of memory cell transistors MT connected to the common word line WL in the same string unit SU is referred to as a "cell unit CU." If each memory cell transistor MT stores 1-bit data, the cell unit CU stores "1-page data." The cell unit CU can have a storage capacity of two pages or more, depending on the number of bits of data stored by the memory cell transistor MT.

[0115] Each of the selection transistors STD and STS is used to select the string unit SU. The drain of the selection transistor STD is connected to the associated bit line BL. The source of the selection transistor STD is connected to one end of the series-connected memory cell transistors MT0 to MT7. The gates of the selection transistors STD, which comprise the string units SU0 to SU3, are connected to the selection gate lines SGD0 to SGD3. The drain of the selection transistor STS is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of the selection transistor STS is connected to the source line SL. The gate of the selection transistor STS is connected to the selection gate line SGS. The source line SL is shared by a plurality of blocks BLK, for example. <4-3> Structure of the storage device 100

[0116] An example of the structure of the memory device 100 according to the fourth embodiment will be described below. In the fourth embodiment, the X direction, for example, corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL, for example. The Z direction corresponds to a vertical direction relative to a front side of a semiconductor substrate (wafer) used to form the memory device 100.

[0117] Fig. 17 is a perspective view showing an example of a structure of the memory device 100 according to the fourth embodiment. As shown in Fig. As shown in Figure 17, the memory device 100 includes a memory chip MC and a CMOS chip CC. The memory chip MC includes, for example, a memory region MR, hookup regions HR1 and HR2, and a pad region PR1. The CMOS chip CC includes, for example, a sense amplifier region SR, a peripheral circuit region PERI, transfer regions XR1 and XR2, and a pad region PR2.

[0118] The memory region MR comprises the memory cell array 103. The terminal regions HR1 and HR2 comprise an interconnect or the like, which serves to connect the stacked interconnect provided for the memory chip MC and the row decoder module 105 provided for the CMOS chip CC. The terminal region PR1 comprises a terminal or the like, which serves to connect the memory device 100 and the memory control unit. The terminal regions HR1 and HR2 clamp the memory region MR in the X direction. The terminal region PR1 borders the memory region MR and the two terminal regions HR1 and HR2 in the Y direction.

[0119] The sense amplifier region SR includes the sense amplifier module 106. The peripheral circuit region PERI includes the sequencer 102, the driver module 104, and the like. The transfer regions XR1 and XR2 include the row decoder module 105. The pad region PR2 includes the memory interface 101. The sense amplifier region SR and the peripheral circuit region PERI are arranged side by side in the Y direction and overlap the memory region MR in the Z direction. The transfer regions XR1 and XR2 sandwich one set of the sense amplifier region SR and the peripheral circuit region PERI in the X direction and overlap the terminal regions HR1 and HR2, respectively. The terminal region PR2 overlaps the terminal region PR1 of the memory chip MC in the Z direction.

[0120] The memory chip MC includes a plurality of bonding pads BP in the respective lower portions of the memory region MR, the terminal regions HR1 and HR2, and the pad region PR1. The bonding pads BP of the memory region MR are connected to the linked bit lines BL. The bonding pads BP of the terminal regions HR are connected to linked interconnections (e.g., word lines WL) under the stacked interconnections provided for the memory region MR. The bonding pad BP of the pad region PR1 is connected to a pad (not shown) provided on the top surface of the memory chip MC. The pad provided on the top surface of the memory chip MC is used, for example, for the connection between the memory device 100 and the memory controller.

[0121] The CMOS chip CC includes a plurality of bonding pads BP in the respective upper portions of the sense amplifier region SR, the peripheral circuit region PERI, the transfer regions XR1 and XR2, and the pad region PR2.

[0122] The bonding pads BP of the sense amplifier region SR overlap the bonding pads BP of the memory region MR in the Z direction. The bonding pads BP of the transfer regions XR1 and XR2 overlap the bonding pads BP of the connection regions HR1 and HR2, respectively, in the Z direction. The bonding pads BP of the pad region PR1 overlap the bonding pads BP of the pad region PR2 in the Z direction.

[0123] The memory device 100 has a structure in which the lower surface (front side of the semiconductor substrate on which the memory chip MC is formed) of the memory chip MC and the upper surface (front side of the semiconductor substrate on which the CMOS chip CC is formed) of the CMOS chip CC are bonded together. Of the bonding pads BP provided for the memory device 100, two opposing bonding pads BP between the memory chip MC and the CMOS chip CC are electrically connected by bonding. Thus, the circuitry in the memory chip MC and the circuitry in the CMOS chip CC are electrically connected via the bonding pads BP. A set of two opposing bonding pads BP between the memory chip MC and the CMOS chip CC may have a boundary or be connected to each other. <4-3-1> Structure of the memory cell array 103

[0124] The structure of the memory cell array 103 is explained below. (Planar layout of memory cell array 103)

[0125] Fig. 18 is a plan view showing an example of a planar layout of the memory cell array 103 included in the memory device 100 according to the fourth embodiment. Fig. 18 shows an area comprising a block BLK in the memory region MR. As in Fig. As shown in Figure 18, the memory device 100 includes, for example, a plurality of slots SLT, a plurality of slots SHE, a plurality of memory columns MP, a plurality of bit lines BL, and a plurality of contacts CV. In the memory area MR, a planar layout described below is repeatedly arranged in the Y direction.

[0126] For example, each slot SLT has a structure in which an insulating element is embedded. Each slot SLT isolates adjacent connections (for example, the word lines WL0 to WL7 and the select gate lines SGD and SGS) across the slot SLT. Each slot SLT has a section extending along the X direction that crosses the memory area MR and the connection areas HR1 and HR2 along the X direction. The slots SLT are arranged in the Y direction. The areas bounded by the slots SLT belong to the blocks BLK.

[0127] For example, each SHE slot has a structure in which an insulating element is embedded. The SHE slots isolate adjacent interconnections (at least the selected gate line SGD) from each other via the SLT slots. Each SHE slot has a portion extending along the X direction and crossing the memory area MR. The SHE slots are arranged in the Y direction. In this example, three SHE slots are arranged between adjacent SLT slots. A plurality of areas divided by the SLT and SHE slots each belong to the string units SU0 to SU3.

[0128] For example, each memory column MP functions as a NAND string NS. The memory columns MP are arranged, for example, in 19 rows, staggered in a region between two adjacent slots SLT. Furthermore, the respective slots SHE overlap the fifth row of memory columns MP, the tenth row of memory columns M, and the fifteenth row of memory columns MP from the top of the diagram.

[0129] Each of the bit lines BL has a section extending along the Y direction and intersecting an area where the blocks BLK are provided along the Y direction. The bit lines BL are arranged in the X direction. Each bit line BL is arranged to overlap at least one memory column MP for each string unit SU. In this example, two bit lines BL overlap each memory column MP.

[0130] Each contact CV is provided between a bit line BL among the bit lines BL that overlap the memory column MP and the memory column MP. The contact CV electrically connects the memory column MP and the bit line BL. Note that the illustration of the contact CV between the memory column MP, which overlaps the slot SHE, and the bit line BL is omitted. (Cross-sectional structure of the memory cell array 103)

[0131] Fig. 19 is a cross-sectional view showing an example of a cross-sectional structure of the memory cell array 103 included in the memory device 100 according to the fourth embodiment. Fig. Figure 19 shows a cross-section taken along the Y-direction and includes the storage columns MP and the slot SLT in the storage area MR. As shown in Fig. 19, the memory device 100 includes, for example, insulating layers 110 to 118, conductive layers 120 to 126, and contacts V1 and V2.

[0132] The insulating layer 110 is provided, for example, in the lowest layer of the memory chip MC. The layer in which the insulating layer 110 is formed can be provided with an interconnection that serves to connect the conductive layer 120 and / or the contact pad PD. The conductive layer 120 is provided on the insulating layer 110. The insulating layer 111 is provided on the conductive layer 120. The conductive layers 121 and the insulating layers 112 are alternately provided on the insulating layer 111. The insulating layer 113 is provided on the uppermost conductive layer 121. The conductive layers 122 and the insulating layers 114 are alternately provided on the insulating layer 113. The insulating layer 115 is provided on the uppermost conductive layer 122. The conductive layers 123 and the insulating layers 116 are alternately provided on the insulating layer 115.The insulating layer 117 is provided on the uppermost conductive layer 123. The conductive layer 124 is provided on the insulating layer 117. The insulating layer 118 is provided on the conductive layer 124. The layer in which the insulating layer 118 is formed includes the contacts V1 and V2 and the conductive layers 125 and 126. The contact V1 is provided on the conductive layer 124. The conductive layer 125 is provided on the contact V1. The contact V2 is provided on the conductive layer 125. The conductive layer 126 is provided on the contact V2.

[0133] Each of the conductive layers 120, 121, 122, and 123 has, for example, a plate-shaped portion extending along the XY plane. The conductive layer 124 has, for example, a line-shaped portion extending in the Y direction. The conductive layers 120, 121, and 123 are used as the source line SL, the select gate line SGS, and the select gate line SGD, respectively. The conductive layers 123 are used as the word lines WL0 to WL7, in order from bottom to top. The conductive layer 124 is used as the bit line BL. The conductive layers 124 and 125 are connected to each other via the contact V1. The conductive layer 125 and the conductive layer 126 are connected to each other via the contact V2. The conductive layer 126 is in contact with the interface (bonding surface) of the memory chip MC and is used as a bonding pad BP. The conductive layer 126 comprises, for example, copper.

[0134] The slot SLT has a plate-shaped portion extending along the XZ plane and separating the insulating layers 111 to 116 and the conductive layers 121 to 123. Each memory column MP is provided to extend along the Z direction and extends through the insulating layers 111 to 116 and the conductive layers 121 to 123. Each memory column MP includes, for example, a core element 130, a semiconductor layer 131, and a stacked film 132. The core element 130 is an insulator extending along the Z direction. The semiconductor layer 131 covers the core element 130. A lower portion of the semiconductor layer 131 is in contact with the conductive layer 120. The stacked layer 132 covers the side surface of the semiconductor layer 131. The contact CV is provided on the semiconductor layer 131. The semiconductor layer 131 is electrically connected to the conductive layer 124 via the contact CV.

[0135] Note that the illustrated region represents the contact CV belonging to one of the two memory columns MP. A contact CV is connected in a region (not shown) to the memory column MP to which the contact CV is not connected in that region. A portion where the memory column MP intersects the conductive layers 61 functions as a selection transistor STS. The portion where the memory column MP intersects the conductive layer 122 functions as a memory cell transistor MT. The portion where the memory column MP intersects the conductive layers 123 functions as a selection transistor STD. In the following explanation, the interconnection layer portions including the conductive layers 124, 125, and 126 are referred to as "MO," "M1," and "M2," respectively. (Cross-sectional structure of the storage column MP)

[0136] Fig. 20 is a cross-sectional view taken along the line XX-XX of Fig. 19 and illustrates an example of a cross-sectional structure of storage columns MP included in the storage device 10 according to the fourth embodiment. Fig. Figure 20 illustrates a cross-section including the storage column MP and the conductive layer 122 and extending parallel to the X-direction and the Y-direction. As shown in Fig. 20, the stacked film 132 includes, for example, a tunnel insulating film 133, an insulating film 134, and a block insulating film 135.

[0137] The core element 130 is provided, for example, in the center part of the memory column MP. The semiconductor layer 131 surrounds the side surface of the core element 130. The tunnel insulating film 133 surrounds the side surface of the semiconductor layer 131. The insulating film 134 surrounds the side surface of the tunnel insulating film 133. The block insulating film 135 surrounds the side surface of the insulating film 134. The conductive layer 122 surrounds the side surface of the block insulating film 135. The semiconductor layer 131 is used as a channel (current path) of the memory cell transistors MT0 to MT7 and the selection transistors STD and STS. Both the tunnel insulating film 133 and the block insulating film 135 contain, for example, silicon oxide (SiO 2 ). The insulating film 134 is used as the charge storage layer of the memory cell transistor MT and comprises, for example, silicon nitride (SiN). Thus, each of the memory columns MP acts as a NAND chain NS. <4-3-2> Cross-sectional structure of the storage device 100

[0138] Fig. 21 is a cross-sectional view illustrating an example of a cross-sectional structure of the storage device 100 according to the fourth embodiment. Fig. 21 shows a cross section including the memory region MR and the sense amplifier region SR, ie, a cross section including the memory chip MC and the CMOS chip CC. As in Fig. 21, the memory device 100 comprises a semiconductor substrate 140, conductive layers GC and 141 to 144, and contacts CS and C0 to C3 in the sense amplifier region SR.

[0139] The semiconductor substrate 140 is a substrate used to form the CMOS chip CC. The semiconductor substrate 140 includes a plurality of well regions (not shown). For example, a transistor TR is formed in each of the plurality of well regions. The plurality of well regions are separated from each other, for example, by shallow trench isolation (STI). A conductive layer GC is provided on the semiconductor substrate 140 over a gate insulating film. The conductive layer GC in the sense amplifier region SR is used as the gate electrode of the transistor TR included in the sense amplifier module 106. The contact C0 is provided on the conductive layer GC. Two contacts CS are provided on the semiconductor substrate 140 in association with the source and drain of the transistor TR.

[0140] The conductive layer 141 is provided on each of the contacts CS and the contact C0. The contact C1 is provided on the conductive layer 141. The conductive layer 142 is provided on the contact C1. The conductive layers 141 and 142 are electrically connected via the contact C1. The contact C2 is provided on the conductive layer 142. The conductive layer 143 is provided on the contact C2. The conductive layers 142 and 143 are electrically connected via the contact C2. The contact C3 is provided on the conductive layer 143. The conductive layer 144 is provided on the contact C3. The conductive layers 143 and 144 are electrically connected via the contact C3. Hereinafter, the interconnection layers in which the conductive layers 141 to 144 are provided are referred to as "D0", "D1", "D2", and "D3", respectively.

[0141] The conductive layer 144 is in contact with the interface (bonding surface) of the CMOS chip CC and is used as a bonding pad BP. The conductive layer 144 in the sense amplifier region SR is connected to the conductive layer 126 (i.e., the bonding pad BP of the memory chip MC) in the memory region MR, which is arranged to face the conductive layer 144. Furthermore, each conductive layer 144 in the sense amplifier region SR is electrically connected to a bit line BL. The conductive layer 144 comprises, for example, copper. In the memory device 100, the interconnection layer D3 of the CMOS chip CC and the interconnection layer M2 of the memory chip MC are adjacent to each other because the memory chip MC and the CMOS chip CC are interconnected.

[0142] In the present example, the semiconductor substrate used to form the memory chip MC is removed along with processes such as pad formation after the bonding process. Note that the semiconductor substrate used to form the memory chip MC may remain. Furthermore, the number of interconnect layers of the memory chip MC and the CMOS chip CC may be changed according to the configuration of the memory device 100. <4-4> Advantageous effects of the fourth embodiment

[0143] The exposure method described in the first embodiment and the semiconductor device manufacturing method described in the second and third embodiments can be applied to the manufacturing of the memory device 100 according to the fourth embodiment described above. A case where the semiconductor device manufacturing method according to the third embodiment is applied to the memory device 100 according to the fourth embodiment will be described below.

[0144] For example, in the interconnect layer M0, the bit line BL, which has a portion extending in the Y direction, is a main pattern. The difficulty of overlaying in the X direction is high, and there is a margin in the management specification of the overlay in the Y direction. In the interconnect layer M1, the conductive layer 125 is provided with a portion extending in the X direction. The difficulty of overlaying in the Y direction is high, and there is a margin in the description of the overlay in the X direction. Since a relatively coarse pattern is processed in the interconnect layer M0, there is a margin in the descriptions of the overlay in both the X direction and the Y direction.

[0145] In this case, when aligning the exposure process associated with the link layer M0, it is preferable to apply the upper and lower limit correction mode in the Y direction and the normal mode in the X direction. Similarly, when aligning the exposure process associated with the link layer M1, it is preferable to apply the upper and lower limit correction mode in the X direction and the normal mode in the Y direction. When aligning the exposure process associated with the link layer M2, it is preferable to apply the upper and lower limit correction mode in both the X and Y directions.

[0146] As described above, the alignment of the upper and lower limit correction modes with respect to one or both of the X and Y directions is applied according to the pattern provided in each layer. In other interconnect layers, the alignment of the upper and lower limit correction modes can be applied accordingly based on the management specifications of the overlay in the X and Y directions. As a result, the yield of the memory device 100 according to the fourth embodiment can be improved by applying the method for manufacturing a semiconductor device according to the third embodiment.

[0147] Note that an object to which the exposure method described in the first embodiment and the method for manufacturing a semiconductor device described in the second and third embodiments are applied is not limited to the memory device 100. An object to which the exposure method described in the first embodiment and the method for manufacturing a semiconductor device described in the second and third embodiments are applied may be a semiconductor device having a bonding structure. <5> Further embodiment

[0148] In the above embodiments, the flowcharts used to describe the exposure method and the method for manufacturing a semiconductor device are merely examples. In the operations described using the flowcharts, the order of the processes is interchangeable within a permissible range; other processes may be added, or some of the processes may be omitted. Fig. Figure 9, which is described in the second embodiment, illustrates a case where the exposure process to which the upper and lower limit correction mode is applied is performed in three layers, but the present invention is not limited to this. In the second embodiment, the exposure process to which the upper and lower limit correction mode is applied may be performed in two or more layers. Similarly, Figure 9 illustrates Fig. 13 illustrates a case where the exposure process to which the upper and lower limit correction modes in the X direction and / or the Y direction are applied is performed in three layers in the third embodiment, but the present invention is not limited to this. In the third embodiment, the exposure process to which the upper and lower limit correction modes in the X direction and / or the Y direction are applied may be performed in two or more layers.

[0149] In the above embodiments, the case where the alignment correction in which both the upper limit value U_Limit and the lower limit value L_Limit of the wafer magnification component are set is performed in the upper and lower limit value correction modes has been described, but the present invention is not limited to this. In the upper and lower limit value correction modes, only the upper limit value U_Limit of the wafer magnification component or only the lower limit value L_Limit of the wafer magnification component may be set. For example, in a case where only the lower limit value L_Limit is set in the upper and lower limit value correction modes, in the process of S106, Fig. 5, in a case where the value of the basic wafer magnification component W_Mag _B is equal to or greater than L_Limit, the process of S108 is executed. For example, in a case where only the upper limit value U_Limit is set in the upper and lower limit correction mode, in the process of S106, Fig. 5, when the value of the base wafer magnification component W_Mag_B is equal to or less than U_Limit, the process of S108 is executed. Alignment correction in which only the upper limit value U_Limit or the lower limit value L_Limit of the wafer magnification component is adjusted in this way can be applied independently in the X direction and the Y direction, as in the third embodiment.

[0150] As the control device 11, a microprocessor unit (MPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or the like may be used instead of the CPU. Furthermore, each of the processes described in the above embodiments may be implemented using dedicated hardware. The processes described in the above embodiments may be a mixture of processes executed by software and processes executed by hardware, or only one of these processes may be used.

[0151] The circuit configuration, planar layout, and cross-sectional structure of the memory device 100 described in the fourth embodiment can be changed according to the design of the memory device 100. For example, although the fourth embodiment exemplified the case where the memory chip MC is provided on the CMOS chip CC, the CMOS chip CC may also be provided on the memory chip MC. In the fourth embodiment, the case where the memory chip MC is associated with the lower wafer LW and the CMOS chip CC with the upper wafer UW was exemplified, but the memory chip MC may be associated with the upper wafer UW and the CMOS chip CC with the lower wafer LW.

[0152] In the present specification, the term "connection" means that two elements are electrically connected to each other, and does not exclude the possibility of another element being interposed therebetween. The term "electrically connected" may mean that an insulator is interposed therebetween, as long as operation as if electrically connected is possible. The term "region" may be regarded as indicating a configuration included in the semiconductor substrate. For example, in a case where the semiconductor substrate 140 is prescribed to include the memory region MR, the memory region MR is connected to an upper region of the semiconductor substrate 140. The bonding pads BP may also be referred to as "common metal." The camera 35 of the exposure device 1 may have a configuration in which an optical system (microscope) and a light receiving sensor are separated.The measuring mechanism associated with camera 35 may be connected externally to exposure device 1. In this specification, "overlay deviation" may also be referred to as "misalignment." "Visually detecting" includes viewing an object from a desired direction through a microscope, camera, or the like.

[0153] Some or all of the embodiments described above may be described as, but are not limited to, the following supplementary notes: [Supplementary Note 1]

[0154] Exposure device comprising: a holder (31) configured to hold a carrier material; and a control device (11) configured to carry out an exposure process on the carrier material; wherein the control device in the exposure process is further configured to to calculate a calculated value (W_Mag_B) of a magnification component by performing a functional approximation on measurement results of three or more alignment marks arranged on the substrate in an orthogonal coordinate system; to set a first lower limit (L_Limit) and / or a first upper limit (U_Limit) for an alignment correction value of a magnification component; in a case where the calculated value is greater than or equal to the first lower limit and / or less than or equal to the first upper limit, setting the orientation correction value of the magnification component to a first correction value (W_Mag_TG); in a case where the first lower limit value is set and the calculated value is smaller than the first lower limit value, sets the alignment correction value of the magnification component to a second correction value that is larger than the calculated value and smaller than the first correction value; and in a case where the first upper limit value is set and the calculated value exceeds the first upper limit value, set the alignment correction value of the magnification component to a third correction value that is larger than the first correction value and smaller than the calculated value. [Supplementary Note 2]

[0155] The exposure device of Supplementary Note 1, where the second correction value is a value obtained by adding the calculated value to the first correction value and then subtracting the first lower limit value, and the third correction value is a value obtained by adding the calculated value to the first correction value and subsequent subtraction of the first upper limit. [Supplementary Note 3]

[0156] The exposure device of Supplementary Note 1, where the first lower limit value is a value obtained by adding the first correction value to a lower limit management value of an overlay deviation of the magnification component in a target step of the exposure process, and the first upper limit value is a value obtained by adding the first correction value to an upper limit control value of the superposition deviation of the magnification component in the target step of the exposure process. [Supplementary Note 4]

[0157] The exposure device of Supplementary Note 1, where the orthogonal coordinate system comprises a first direction and a second direction which is orthogonal to the first direction, the first correction value, the second correction value and the third correction value are each an alignment correction value of a magnification component in the first direction, the control device is further configured to set a second lower limit and / or a second upper limit for an alignment correction value of a magnification component; in a case where the calculated value is greater than or equal to the second lower limit value and / or less than or equal to the second upper limit value, setting an orientation correction value of a magnification component in the second direction to a fourth correction value; in a case where the second lower limit value is set and the calculated value is smaller than the second lower limit value, sets the orientation correction value of the magnification component in the second direction to a fifth correction value that is larger than the calculated value and smaller than the fourth correction value; and in a case where the second upper limit value is set and the calculated value exceeds the second upper limit value, set the orientation correction value of the magnification component in the second direction to a sixth correction value which is larger than the fourth correction value and smaller than the calculated value, the second lower limit differs from the first lower limit and the second upper limit differs from the first upper limit. [Additional Note 5]

[0158] The exposure device of Supplementary Note 1, in which the orthogonal coordinate system comprises a first direction and a second direction which is orthogonal to the first direction, the first correction value, the second correction value and the third correction value are each an alignment correction value of a magnification component in the first direction and the control device is further configured to set, in the exposure process, an alignment correction value of a magnification component in the second direction to substantially the same value as the calculated value. [Supplementary Note 6]

[0159] Exposure method comprising: Calculating a calculated value (W_Mag_B) of a magnification component by performing a functional approximation on measurement results of three or more alignment marks arranged on a substrate in an orthogonal coordinate system; Setting a first lower limit (L_Limit) and / or a first upper limit (U_Limit) for an alignment correction value of a magnification component; in a case where the calculated value is greater than or equal to the first lower limit and / or less than or equal to the first upper limit, sets the orientation correction value of the magnification component to a first correction value (W_Mag_TG); in a case where the first lower limit value is set and the calculated value is smaller than the first lower limit value, setting the alignment correction value of the magnification component to a second correction value that is larger than the calculated value and smaller than the first correction value, and in a case where the first upper limit value is set and the calculated value exceeds the first upper limit value, the alignment correction value of the magnification component is set to a third correction value which is larger than the first correction value and smaller than the calculated value. [Supplementary Note 7]

[0160] The exposure method of Supplementary Note 6, in which the second correction value is a value determined by adding the calculated value to the first correction value and then subtracting the first lower limit value, and the third correction value is a value determined by adding the calculated value to the first correction value and then subtracting the first upper limit value. [Supplementary Note 8]

[0161] The exposure method of Supplementary Note 6, where the first lower limit value is a value obtained by adding the first correction value to a lower limit management value of an overlay deviation of the magnification component in a target step of an exposure process, and the first upper limit value is a value obtained by adding the first correction value to an upper limit management value of the superposition deviation of the magnification component in the target step of the exposure process. [Supplementary Note 9]

[0162] The exposure method of Supplementary Note 6, in which the orthogonal coordinate system comprises a first direction and a second direction which is orthogonal to the first direction, the first correction value, the second correction value and the third correction value are each an alignment correction value of a magnification component in the first direction, the method further comprising: Setting a second lower limit and / or a second upper limit for an alignment correction value of a magnification component; in a case where the calculated value is greater than or equal to the second lower limit value and / or less than or equal to the second upper limit value, setting an orientation correction value of a magnification component in the second direction to a fourth correction value; in a case where the second lower limit value is set and the calculated value is smaller than the second lower limit value, setting the orientation correction value of the magnification component in the second direction to a fifth correction value that is larger than the calculated value and smaller than the fourth correction value; in a case where the second upper limit value is set and the calculated value exceeds the second upper limit value, the orientation correction value of the magnification component in the second direction is set to a sixth correction value which is larger than the fourth correction value and smaller than the calculated value; the second lower limit differs from the first lower limit and the second upper limit differs from the first upper limit. [Supplementary Note 10]

[0163] The exposure method of Supplementary Note 6, in which the orthogonal coordinate system comprises a first direction and a second direction which is orthogonal to the first direction, the first correction value, the second correction value and the third correction value are each an alignment correction value of a magnification component in the first direction, the method further comprising set an orientation correction value of a magnification component in the second direction to substantially the same value as the calculated value. [Supplementary Note 11]

[0164] A method of manufacturing a semiconductor device, comprising: in a first exposure step Calculating a first calculated value (W_Mag_B) of a magnification component by performing a functional approximation on measurement results of three or more alignment marks arranged on a substrate in an orthogonal coordinate system; Setting a first lower limit (L_Limit) and / or a first upper limit (U_Limit) for an alignment correction value of a magnification component; in a case where the first calculated value is greater than or equal to the first lower limit and / or less than or equal to the first upper limit, sets the orientation correction value of the magnification component to a first correction value (W_Mag_TG); in a case where the first lower limit value is set and the first calculated value is smaller than the first lower limit value, setting the alignment correction value of the magnification component to a second correction value that is larger than the first calculated value and smaller than the first correction value, and in a case where the first upper limit value is set and the first calculated value exceeds the first upper limit value, the alignment correction value of the magnification component is set to a third correction value which is larger than the first correction value and smaller than the first calculated value. [Additional Note 12]

[0165] A method of manufacturing a semiconductor device according to Supplementary Note 11, wherein the second correction value is a value obtained by adding the first calculated value to the first correction value and then subtracting the first lower limit value, and the third correction value is a value determined by adding the first calculated value to the first correction value and then subtracting the first upper limit value. [Supplementary Note 13]

[0166] A method of manufacturing a semiconductor device according to Supplementary Note 11, wherein the first lower limit value is a value obtained by adding the first correction value to a lower limit management value of an overlay deviation of the magnification component in the first exposure step, and the first upper limit value is a value obtained by adding the first correction value to an upper limit management value of the superposition deviation of the magnification component in the first exposure step. [Supplementary Note 14]

[0167] A method of manufacturing a semiconductor device according to Supplementary Note 11, wherein the orthogonal coordinate system comprises a first direction and a second direction which is orthogonal to the first direction, the first correction value, the second correction value and the third correction value are each an alignment correction value of a magnification component in the first direction, In the first exposure step, the method further comprises: further setting a second lower limit and / or a second upper limit for an alignment correction value of a magnification component; in a case where the first calculated value is greater than or equal to the second lower limit value and / or less than or equal to the second upper limit value, setting an orientation correction value of a magnification component in the second direction to a fourth correction value; in a case where the second lower limit value is set and the first calculated value is smaller than the second lower limit value, setting the orientation correction value of the magnification component in the second direction to a fifth correction value that is larger than the first calculated value and smaller than the fourth correction value; in a case where the second upper limit value is set and the first calculated value exceeds the second upper limit value, the orientation correction value of the magnification component in the second direction is set to a sixth correction value which is larger than the fourth correction value and smaller than the first calculated value; the second lower limit differs from the first lower limit and the second upper limit differs from the first upper limit. [Additional Note 15]

[0168] A method of manufacturing a semiconductor device according to Supplementary Note 11, wherein the orthogonal coordinate system comprises a first direction and a second direction which is orthogonal to the first direction, the first correction value, the second correction value and the third correction value are each an alignment correction value of a magnification component in the first direction, the method further comprising in the first exposure step, setting an alignment correction value of a magnification component in the second direction to substantially the same value as the first calculated value. [Supplementary Note 16]

[0169] The method of manufacturing a semiconductor device according to Supplementary Note 11, further comprising: in a second exposure step after the first exposure step for the carrier material Calculating a second calculated value of a magnification component by functional approximation to measurement results of three or more alignment marks arranged on the substrate in an orthogonal coordinate system; Setting a third lower limit and / or a third upper limit for an alignment correction value of a magnification component; in a case where the second calculated value is greater than or equal to the third lower limit and / or less than or equal to the third upper limit, to set the alignment correction value of the magnification component to a seventh correction value; in a case where the third lower limit value is set and the second calculated value is smaller than the third lower limit value, sets the alignment correction value of the magnification component to an eighth correction value that is larger than the second calculated value and smaller than the seventh correction value; and in a case where the third upper limit value is set and the second calculated value exceeds the third upper limit value, the alignment correction value of the magnification component is set to a ninth correction value which is larger than the seventh correction value and smaller than the second calculated value. [Additional Note 17]

[0170] A method of manufacturing a semiconductor device according to Supplementary Note 16, wherein the orthogonal coordinate system comprises a first direction and a second direction which is orthogonal to the first direction, the first correction value, the second correction value and the third correction value are each an alignment correction value of a magnification component in the first direction and each of the seventh, eighth and ninth correction values ​​is an alignment correction value of a magnification component in the second direction. [Supplementary Note 18]

[0171] The exposure method of Supplementary Note 6, in which the carrier material is a semiconductor carrier material. Although specific embodiments have been described, these embodiments are to be considered only as examples and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; further, various omissions, substitutions, and changes may be made in the form of the embodiments described herein without departing from the spirit of the inventions. The appended claims and their equivalents are intended to cover such forms or other embodiments that fall within the scope and spirit of the inventions. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2023-098698

[0001]

Claims

[1] An exposure device comprising: a holder (31) configured to hold a carrier material; and a control device (11) configured to carry out an exposure process on the carrier material; wherein in the exposure process, the control device is further configured to to calculate a calculated value (W_Mag_B) of a magnification component by performing a functional approximation on measurement results of three or more alignment marks arranged on the substrate in an orthogonal coordinate system; to set a first lower limit (L_Limit) and / or a first upper limit (U_Limit) for an alignment correction value of a magnification component; in a case where the calculated value is greater than or equal to the first lower limit value and / or less than or equal to the first upper limit value, setting the orientation correction value of the magnification component to a first correction value (W_Mag_TG); in a case where the first lower limit value is set and the calculated value is smaller than the first lower limit value, sets the alignment correction value of the magnification component to a second correction value that is larger than the calculated value and smaller than the first correction value; and in a case where the first upper limit value is set and the calculated value exceeds the first upper limit value, sets the alignment correction value of the magnification component to a third correction value that is larger than the first correction value and smaller than the calculated value. [2] Exposure device according to claim 1, wherein the second correction value is a value obtained by adding the calculated value to the first correction value and further subtracting the first lower limit value, and the third correction value is a value obtained by adding the calculated value to the first correction value and further subtracting the first upper limit value. [3] Exposure device according to claim 1, wherein the first lower limit value is a value obtained by adding the first correction value to a lower limit management value of an overlay deviation of the magnification component in a target step of the exposure process, and the first upper limit value is a value obtained by adding the first correction value to an upper limit management value of the superposition deviation of the magnification component in the target step of the exposure process. [4] Exposure device according to claim 1, wherein the orthogonal coordinate system comprises a first direction and a second direction orthogonal to the first direction, the first correction value, the second correction value and the third correction value are each an alignment correction value of a magnification component in the first direction, in the exposure process, the control device is further configured to set a second lower limit and / or a second upper limit for an alignment correction value of a magnification component; in a case where the calculated value is greater than or equal to the second lower limit value and / or less than or equal to the second upper limit value, setting an orientation correction value of a magnification component in the second direction to a fourth correction value; in a case where the second lower limit value is set and the calculated value is smaller than the second lower limit value, setting the orientation correction value of the magnification component in the second direction to a fifth correction value that is larger than the calculated value and smaller than the fourth correction value; and in a case where the second upper limit value is set and the calculated value exceeds the second upper limit value, setting the orientation correction value of the magnification component in the second direction to a sixth correction value which is larger than the fourth correction value and smaller than the calculated value, the second lower limit differs from the first lower limit and the second upper limit differs from the first upper limit. [5] Exposure device according to claim 1, wherein the orthogonal coordinate system comprises a first direction and a second direction which is orthogonal to the first direction, the first correction value, the second correction value and the third correction value are each an alignment correction value of a magnification component in the first direction, and in the exposure process, the control device is further configured to set an orientation correction value of a magnification component in the second direction to substantially the same value as the calculated value. [6] Exposure method comprising: Calculating a calculated value (W_Mag_B) of a magnification component by performing a functional approximation on measurement results of three or more alignment marks arranged on a substrate in an orthogonal coordinate system; Setting a first lower limit (L_Limit) and / or a first upper limit (U_Limit) for an alignment correction value of a magnification component; in a case where the calculated value is greater than or equal to the first lower limit value and / or less than or equal to the first upper limit value, setting the orientation correction value of the magnification component to a first correction value (W_Mag_TG); in a case where the first lower limit value is set and the calculated value is smaller than the first lower limit value, setting the alignment correction value of the magnification component to a second correction value that is larger than the calculated value and smaller than the first correction value, and in a case where the first upper limit value is set and the calculated value exceeds the first upper limit value, setting the alignment correction value of the magnification component to a third correction value which is larger than the first correction value and smaller than the calculated value. [7] The exposure method according to claim 6, wherein the second correction value is a value obtained by adding the calculated value to the first correction value and further subtracting the first lower limit value, and the third correction value is a value obtained by adding the calculated value to the first correction value and further subtracting the first upper limit value. [8] Exposure method according to claim 6, wherein the first lower limit value is a value obtained by adding the first correction value to a lower limit management value of an overlay deviation of the magnification component in a target step of an exposure process, and the first upper limit value is a value obtained by adding the first correction value to an upper limit management value of the superposition deviation of the magnification component in the target step of the exposure process. [9] Exposure method according to claim 6, wherein the orthogonal coordinate system comprises a first direction and a second direction orthogonal to the first direction, the first correction value, the second correction value and the third correction value are each an alignment correction value of a magnification component in the first direction, the method further comprising: Setting a second lower limit and / or a second upper limit for an alignment correction value of a magnification component; in a case where the calculated value is greater than or equal to the second lower limit value and / or less than or equal to the second upper limit value, setting an orientation correction value of a magnification component in the second direction to a fourth correction value; in a case where the second lower limit value is set and the calculated value is smaller than the second lower limit value, setting the orientation correction value of the magnification component in the second direction to a fifth correction value that is larger than the calculated value and smaller than the fourth correction value; in a case where the second upper limit is set and the calculated value exceeds the second upper limit, setting the orientation correction value of the magnification component in the second direction to a sixth correction value which is greater than the fourth correction value and smaller than the calculated value; the second lower limit differs from the first lower limit and the second upper limit differs from the first upper limit. [10] The exposure method according to claim 6, wherein the orthogonal coordinate system comprises a first direction and a second direction which is orthogonal to the first direction, the first correction value, the second correction value and the third correction value are each an alignment correction value of a magnification component in the first direction, the method further comprising Setting an alignment correction value of a magnification component in the second direction to substantially the same value as the calculated value. [11] The exposure method according to claim 6, further comprising: Calculating a second calculated value of a magnification component by performing a functional approximation on measurement results of three or more alignment marks arranged on the substrate in an orthogonal coordinate system; Setting a third lower limit and / or a third upper limit for an alignment correction value of a magnification component; in a case where the second calculated value is greater than or equal to the third lower limit value and / or less than or equal to the third upper limit value, setting the alignment correction value of the magnification component to a seventh correction value; in a case where the third lower limit value is set and the second calculated value is smaller than the third lower limit value, setting the alignment correction value of the magnification component to an eighth correction value that is larger than the second calculated value and smaller than the seventh correction value; and in a case where the third upper limit value is set and the second calculated value exceeds the third upper limit value, setting the alignment correction value of the magnification component to a ninth correction value that is larger than the seventh correction value and smaller than the second calculated value. [12] The exposure method according to claim 11, wherein the orthogonal coordinate system comprises a first direction and a second direction which is orthogonal to the first direction, the first correction value, the second correction value and the third correction value are each an alignment correction value of a magnification component in the first direction and the seventh correction value, eighth correction value and ninth correction value are each an alignment correction value of a magnification component in the second direction. [13] The exposure method according to claim 6, wherein the substrate is a semiconductor substrate.

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