Time-synchronized sensor data for robotics systems and applications

Abstract

In various examples, sets of correlated timestamps are sampled from clock sources. These sets of correlated timestamps are used to calculate translation data, such as offsets and / or rates of change of the clock sources. The offsets and / or rates of change can be used to translate a timestamp into a reference time domain. The sampled clock sources can be frequency-locked, and the translation can be performed without using the rates of change. For example, a running average of the offsets can be used to perform the translation. The translated timestamps and corresponding sensor measurements can be provided to one or more applications for use in performing one or more operations on a machine, such as perception and / or control operations.

Description

BACKGROUND

[0001] A computing system, such as a robotics system, may use an array of sensors to perceive the environment, such as cameras, LIDAR (Light Detection and Ranging) sensors, RADAR (Radar Detection and Ranging) sensors, inertial measurement units (IMUs), temperature sensors, and / or humidity sensors. The sensors may capture various aspects of the environment, such as visual data, depth information, motion information, position information, and / or environmental conditions. Constructing a comprehensive and coherent understanding of the environment may require fusing measurements from the sensors while accurately capturing the relative timing between different sensor events. However, different sensors may rely on different clock sources, which can introduce variations in timing.

[0002] A global positioning system (GPS) signal (or more generally, a global navigation satellite system (GNSS)) can be used to synchronize clocks associated with different clock sources. To do this, a GPS receiver can compare an internal clock with a received GPS time to adjust the internal clock. Additionally, the received GPS time can be used to generate a pulse-per-second (PPS) signal that other components use as a reference signal for clock synchronization. The Network Time Protocol (NTP) can also be used to synchronize clocks associated with different clock sources. To do this, NTP clients can request time information from NTP servers and adjust appropriate clocks based on the received time information to align the clocks with a global reference clock.However, effective NTP or GPS-based clock synchronization may not always be possible in certain scenarios, such as indoor environments where there may be limited or obstructed access to GPS signals and / or network communications. SUMMARY

[0003] Embodiments of the present disclosure relate to time-synchronized sensor data for robotic systems and applications suitable for GPS and internet-based environments. Systems and methods are disclosed that can be used to translate timestamps for sensor measurements referenced to different clock sources into a common time domain without requiring access to network time.

[0004] In contrast to conventional systems, such as those described above, disclosed approaches may use sets of correlated samples from clock sources to compute translation data between clock sources and use the translation data to perform time-domain translation for time data from sensor measurements. In at least one embodiment, sets of correlated timestamps are sampled from the clock sources. The sets of correlated timestamps may be used to compute translation data, such as offsets and / or rates of change of the clock sources. The offsets and / or rates of change may be used to translate a timestamp into a reference time domain. In at least one embodiment, the sampled clock sources are frequency-locked, and the translation is performed without using the rates of change.For example, a running average of the offsets can be used to perform the translation. The translated timestamps and corresponding sensor measurements can be provided to one or more applications for use in performing one or more operations for a machine, such as sensing and / or control operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present systems and methods for time-synchronized sensor data for robotic systems and applications are described in detail below with reference to the accompanying drawings, wherein: Fig. 1 is an example of a time synchronization system according to some embodiments of the present disclosure; Fig. 2 is an example diagram of sampled sets of correlated timestamps with a set of timestamps corresponding to a sensor measurement, according to some embodiments of the present disclosure; Fig. 3 is a flowchart illustrating a method for translating timestamps into a reference time domain based on receiving sets of correlated timestamps, according to some embodiments of the present disclosure; Fig. 4 is a flowchart illustrating a method for converting time data into a reference time domain based on correlated samples from clock sources, according to some embodiments of the present disclosure; Fig. 5 is a flowchart illustrating a method for initializing a time synchronization system according to some embodiments of the present disclosure; Fig. 6A is an illustration of an exemplary autonomous vehicle according to some embodiments of the present disclosure; Fig. 6B shows an example of camera positions and fields of view for the exemplary autonomous vehicle from Fig. 6A is in accordance with some embodiments of the present disclosure; Fig. 6C is a block diagram of an exemplary system architecture for the exemplary autonomous vehicle of Fig. 6A is in accordance with some embodiments of the present disclosure; Fig. 6D is a system diagram for communication between one or more cloud-based servers and the exemplary autonomous vehicle of Fig. 6A is in accordance with some embodiments of the present disclosure; Fig. 7 is a block diagram of an exemplary computing device suitable for use in implementing some embodiments of the present disclosure; and Fig. 8 is a block diagram of an exemplary data center suitable for use in implementing some embodiments of the present disclosure. DETAILED DESCRIPTION

[0006] Systems and methods are disclosed relating to time-synchronized sensor data for robotic systems and applications. Although the present disclosure is described with respect to an exemplary autonomous or semi-autonomous vehicle 600 (alternatively referred to herein as "vehicle 600" or "ego machine 600," an example of which is provided with respect to the Fig. 6A through 6D), the present disclosure is not limited thereto. For example, the systems and methods described herein may be used by, without limitation, non-autonomous vehicles, semi-autonomous vehicles (e.g., in one or more adaptive driver assistance systems (ADAS)), autonomous vehicles, guided and unguided robots or robotic platforms, warehouse vehicles, off-highway vehicles, vehicles coupled to one or more trailers, flying vessels, boats, shuttles, emergency response vehicles, motorcycles, electric or motorized bicycles, aircraft, construction vehicles, underwater vehicles, drones, and / or other types of vehicles.Furthermore, although the present disclosure may be described with respect to sensor data and perception, this is not intended to be limiting, and the systems and methods described herein may be used in augmented reality, virtual reality, mixed reality, robotics, security and surveillance, autonomous or semi-autonomous machine applications, and / or any other technology spaces where time domain conversion may be used.

[0007] Disclosed approaches may use sets of correlated samples from clock sources to compute translation data between clock sources and use the translation data to perform time-domain translation for time data from sensor measurements. In at least one embodiment, sets of correlated timestamps are sampled from the clock sources, such as a time stamp counter (TSC) clock source and a precision timing protocol (PTP) hardware clock (PHC) clock source. The sets of correlated timestamps may be used to compute translation data, such as offsets and / or rates of change of the clock sources. The offsets and / or rates of change may be used to translate a timestamp into a reference time domain. In at least one embodiment, the sampled clock sources are frequency-locked, and the translation is performed without using the rates of change.For example, a running average of the offsets can be used to perform the translation. The translated timestamps and corresponding sensor measurements can be provided to one or more applications for use in performing one or more operations for a machine (e.g., as streams of sensor measurements with translated timestamps), such as sensing and / or control operations.

[0008] In at least one embodiment, the reference time domain is a system time domain corresponding to a system time clock source. The system time source may be kept synchronized with one of the sampled clock sources (e.g., the PHC clock source). In at least one embodiment, the system may determine whether network time is available to initialize the clock sources for time domain conversion. If network time is not available, the system time clock source may be updated to reflect a persistent clock source, such as a real-time clock (RTC) clock source. If network time is available, both the system time clock source and the persistent clock source may be updated to reflect network time. The sampled clock source to be kept synchronized with the system time clock source may be updated to reflect the system time clock source. One or more of the other clock sources (e.g.,A clock source (e.g., a TSC clock source) used for sampling may then be locked to the updated clock source. In at least one embodiment, the initialization is performed as part of, or in response to, a boot sequence for a computing platform.

[0009] The systems and methods described herein may be used for a variety of purposes, including, but not limited to, machine control, machine locomotion, machine propulsion, synthetic data generation, model training, perception, augmented reality, virtual reality, mixed reality, robotics, security and surveillance, autonomous or semi-autonomous machine applications, deep learning, environmental simulation, object or actor simulation and / or digital twinning, data center processing, conversational AI, light transport simulation (e.g., ray tracing, path tracing, etc.), collaborative content creation for 3D assets, cloud computing, generative AI, (large) language models, and / or any other suitable applications.

[0010] Disclosed embodiments may be included in a variety of different systems, such as automotive systems (e.g., a control system for an autonomous or semi-autonomous machine, a perception system for an autonomous or semi-autonomous machine), systems implemented using a robot, air systems, media systems, boat systems, intelligent area monitoring systems, systems for performing deep learning operations, systems for performing simulation operations, systems for performing digital twin operations, systems implemented using an edge device, systems including one or more virtual machines (VMs), systems for performing synthetic data generation operations, systems implemented at least partially in a data center, systems for performing conversational AI operations,Systems for performing light transport simulation, systems for performing collaborative content creation for 3D assets, systems implemented at least in part using cloud computing resources, systems for performing generative AI operations, systems that implement a Large Language Model (LLM) or for performing operations using it, and / or other types of systems.

[0011] With reference to Fig. 1 is Fig. 1 illustrates an example of a time synchronization system 100 according to some embodiments of the present disclosure. It should be understood that these and other arrangements described herein are set forth as examples only. Other arrangements and elements (e.g., engines, interfaces, functions, sequences, groupings of functions, etc.) may be used in addition to or in place of those shown, and some elements may be omitted entirely. Furthermore, many of the elements described herein are functional entities that may be implemented as discrete or distributed components, or in conjunction with other components, and in any suitable combination and location. Various functions described herein as being performed by entities may be performed by hardware, firmware, and / or software.For example, various functions may be performed by a processor executing instructions stored in memory. In some embodiments, the systems, methods, and processes described herein may be implemented using similar components, features, and / or functionality as those of the exemplary autonomous or semi-autonomous vehicle 600 of FIGS. Fig. 6A to Fig. 6D, the exemplary computing device 700 of Fig. 7 and / or the exemplary data center 800 from Fig. 8 can be executed.

[0012] The time synchronization system 100 may include, among additional or alternative components, a computing platform 102 and one or more sensors, such as sensor(s) 104A, sensor(s) 104B, and sensor(s) 104C (which may be referred to as "sensors 104"). The computing platform 102 may include, among additional or alternative components, a user space 106, a kernel space 108, and a system or hardware space 110.

[0013] The user space 106 may include, among additional or alternative components, one or more applications, such as application(s) 112, one or more sensor drivers, such as sensor driver(s) 114A, sensor driver(s) 114B, and sensor driver(s) 114C (which may be referred to as “sensors 114”), and one or more translators, such as translator(s) 116. Kernel space 108 may include, among additional or alternative components, one or more sensor drivers, such as sensor driver(s) 118A and sensor driver(s) 118B (which may be referred to as "sensors 118"), one or more clock managers, such as clock manager(s) 120B and clock manager(s) 120C, one or more skew analyzers, such as clock sampler(s) 122, and one or more clock sources, such as clock source(s) 124C.The system or hardware space 110 may include, among additional or alternative components, one or more clock managers, such as clock manager(s) 120A, one or more clock sources, such as clock source(s) 124A, and one or more interfaces, such as interface(s) 130A, interface(s) 130B, and interface(s) 130C (which may be referred to as "interfaces 130"). In at least one embodiment, one or more of the sensors may include one or more clock sources, such as clock source(s) 124B, included in the sensor(s) 104B.

[0014] As an overview, sensors 104 may be configured to provide sensor measurements to computing platform 102 using interfaces 130. Clock managers, such as clock managers 120A, 120B, or 120C (which may be referred to as "clock manager 120"), may be configured to provide timing data indicating timestamps of the sensor measurements, where the timing data may be related to various clock sources, such as clock source 124A, 124B, or 124C (which may be referred to as "clock sources 124"). Clock sampler 122 may be configured to sample a plurality of clock sources to generate sets of correlated samples, such as a timestamp related to clock source 124A and a corresponding timestamp related to clock source 124B.The translator 116 may be configured to calculate translation data between one or more of the clock sources 124, such as the clock source 124A and the clock source 124B, using sets of correlated samples, such as sets of correlated timestamps sampled using the clock sampler 122.

[0015] The sensor drivers 118, if present, may provide interfaces between the sensors 104, the kernel space 108, and / or the user space 106. Furthermore, the sensor drivers 114, if present, may provide interfaces between the sensors 104, the kernel space 108, and / or the application(s) 112. In the example shown, the sensor drivers 114 may be configured to provide timestamps of sensor measurements to the translator 116 and receive corresponding translation data. The sensor drivers 114 may use the translation data to translate and / or convert the timestamps into a reference time range. Furthermore, the sensor drivers 114 may provide the sensor measurements and timestamps corresponding to the reference time range to the application(s) 112.The application(s) 112 may use the sensor measurements and timestamps for various purposes, such as performing sensing and / or control operations of a machine(s). In other examples, the sensor drivers 118 may perform at least some of the functionality of the sensor drivers 114. For example, the sensor drivers 118 may be configured to provide timestamps to the translator 116 and / or receive corresponding translation data.

[0016] Sensors 104 may be configured to generate sensor data. In one or more embodiments, the sensors may include at least one of one or more physical sensors in a physical environment or one or more virtual sensors in a simulated environment. For example, the one or more sensors may correspond to a physical or simulated version of vehicle 600, as described herein, or another machine and / or robot.

[0017] The sensor data from the sensors 104 may include, among other things, sensor data from any of the sensors of the vehicle 600 (and / or other vehicles or objects, such as robotic devices, VR systems, AR systems, etc. in some examples). For example, and with reference to the Fig. 6A-6C, the sensor data may include data collected by, among others, one or more Global Navigation Satellite System (GNSS) sensors 658 (e.g., one or more Global Positioning System sensors, Differential GPS (DGPS), etc.), one or more RADAR sensors 660, one or more ultrasonic sensors 662, one or more LIDAR sensors 664, one or more Inertial Measurement Unit (IMU) sensors 666 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 696, one or more stereo cameras 668, one or more wide-view cameras 670 (e.g., fisheye cameras), one or more infrared cameras 672, one or more surround cameras 674 (e.g., 360-degree cameras), one or more several long-range and / or medium-range cameras 698, one or more speed sensors 644 (e.g.for measuring the speed of the vehicle 600 and / or the distance traveled) and / or other types of sensors.

[0018] In some examples, the sensor data may include sensor data generated using one or more forward-facing sensors, side-view sensors, and / or rear-view sensors. This sensor data may be useful to the computing platform 102 (e.g., using the applications 112) to identify, detect, classify, and / or track the movement of objects around the vehicle 600 within the environment. In embodiments, any number of sensors may be used to generate multiple fields of view (e.g., the fields of view of the long-range cameras 698, the forward-facing stereo camera 668, and / or the forward-facing wide-view camera 670). Fig. 6B) and / or sensor fields (e.g., a LIDAR sensor 664, a RADAR sensor 660, etc.). As used herein, the sensor data or portions of sensor data may refer to raw sensor data, preprocessed sensor data, or a combination thereof.

[0019] The sensor data may include image data representing one or more images, image data representing a video (e.g., snapshots of a video), data representing sensory fields from sensors (e.g., depth maps for LIDAR sensors, a value chart for ultrasonic sensors, etc.), and / or data representing measurements from sensors. If the sensor data includes image data, any type of image data format may be used, such as, for example and without limitation, compressed images such as in JPEG (Joint Photographic Experts Group) or YUV (Luminance / Chrominance) formats, compressed images as still images derived from a compressed video format such as H.264 / AVC (Advanced Video Coding) or H.265 / HEVC (High Efficiency Video Coding), raw images such as those derived from RCCB (Red Clear Blue), RCCC (Red Clear Blue) or another type of imaging sensor, and / or other formats.Additionally, in some examples, the sensor data may be used within the computing platform 102 without any preprocessing (e.g., in a raw or captured format), while in other examples, the sensor data may be subjected to preprocessing (e.g., noise compensation, demosaicing, scaling, cropping, magnification, white balancing, tone curve adjustment, etc., such as using a sensor data preprocessor (not shown)).

[0020] If the sensor data includes IMU data, the IMU data may capture various sensed physical properties of the environment and / or motion-related information. For example, the IMU data may indicate accelerations along multiple axes (e.g., linear accelerations), rotation rates (e.g., angular velocities), and / or magnetic field strength (e.g., for compass orientation). In one or more embodiments, the IMU data indicates the motion, orientation, and / or spatial positioning of the vehicle 600. By way of example, and not limitation, the IMU data may be in the form of raw measurements, including three-axis accelerometer readings, three-axis gyroscope readings, and / or three-axis magnetometer readings.Additionally or alternatively, at least some of the IMU data may be subjected to preprocessing steps, such as noise filtering, calibration, sensor fusion algorithms (combining accelerometer, gyroscope, and magnetometer data), and / or bias compensation. Preprocessing may improve the accuracy, stability, and / or reliability of the IMU data, enabling more precise motion tracking, navigation, and orientation estimation using the computing platform 102.

[0021] In at least one embodiment, sensors 104 may be configured to provide sensor measurements to computing platform 102 using interfaces 130. A sensor measurement may refer to one or more values ​​and / or a portion of sensor data obtained from one or more sensors 104 as a result of detecting and / or quantifying a physical and / or environmental phenomenon. In at least one embodiment, the value and / or portion of sensor data may correspond to one or more specific points in time and / or one or more time periods representing a corresponding detection or quantification of a physical and / or environmental property.When a sensor measurement corresponds to one or more values, the value may be generated from the corresponding portion(s) of sensor data using the sensor 104 and / or other components, such as components of the computing platform 102.

[0022] The interfaces 130 may be configured to facilitate communication and interaction between the sensors 104 and the computing platform 102. Although the sensors 104 are shown as being external to the computing platform 102, one or more of the sensors 104 may be included within the computing platform 102. By way of example, and not limitation, the interfaces 130 may be configured to receive data from the sensors 104, such as data representing sensor measurements. In one or more embodiments, the interfaces 130 may be configured to perform signal conditioning, provide protocol support, implement control and configuration, implement synchronization, and / or provide power to the sensors 104.

[0023] Non-limiting examples of interfaces 130 include one or more of any combination of a general purpose input / output (GPIO) interface (e.g., for an IMU), a controller area network (CAN) interface (e.g., for a robot and / or autonomous vehicle platform), an Ethernet interface (e.g., for a LIDAR sensor), or a video interface (VI) (e.g., for a camera).

[0024] In at least one embodiment, one or more sensor measurements may have one or more timestamps assigned and / or associated with them, where the one or more timestamps may indicate and / or correspond to the one or more specific points in time and / or the one or more time periods for the sensor measurement(s). In at least one embodiment, the sensor measurements and / or timestamps may correspond to one or more measurement times, one or more sampling rates, and / or one or more organizations as time series data. A measurement time may indicate a specific point in time at which a sensor acquires the portion of data, thereby providing a temporal reference for a sensor measurement. A sampling rate may indicate a frequency at which portions of sensor data are acquired and may affect the temporal resolution and frequency of sensor measurements.

[0025] The timestamps may be associated with sensor measurements using a corresponding clock manager 120. A clock manager 120 may associate timing data indicating and / or representing one or more timestamps corresponding to one or more sensor measurements. The timing data for a clock manager 120 may be related to a corresponding clock source 124. For example, the timing data generated using clock manager 120A may be related to clock source 124A, the timing data generated using clock manager 120B may be related to clock source 124B, and the timing data generated using clock manager 120C may be related to clock source 124C.

[0026] As in Fig. 1, a clock source 124 may include any combination of a hardware clock source or a software clock source. For example, clock source 124C is a software clock source, such as a system clock source in kernel space 108. As another example, clock sources 124A and 124B are hardware clock sources. By way of example, and not by way of limitation, clock source 124A may include a time stamp counter (TSC) clock source, and clock source 124B may include a pulse-per-second (PHC) hardware clock source.

[0027] A TSC clock source can be used to measure the passage of time at a fine-grained level. The TSC clock source can be implemented using a high-resolution hardware-based counter that increments at a substantially constant rate used for precise time measurements. In at least one embodiment, the TSC clock source is implemented using a register that accumulates time increments at each clock cycle since the TSC clock source was reset. A PHC clock source can be used to measure the passage of time by generating a pulse signal once per second or at a different time increment. A PHC clock source can be implemented as a hardware component that generates a precise pulse signal synchronized to Coordinated Universal Time (UTC) or another reference time standard.

[0028] While specific examples of clock sources 124 are provided, any combination of clock sources may be used. Examples of clock sources 124 include software clock sources, hardware clock sources, high-frequency oscillator clock sources, programmable interval timer (PIT) clock sources, high-resolution timer (HIT) clock sources, atomic clock sources, phase-locked loop (PLL) clock sources, or processor clock sources.

[0029] As in Fig. 1, the clock sources 124 and the location of the clock sources 124 may vary. For example, a clock source, such as a clock source 124B, may be located outside the computing platform 102, such as the clock source 124B, or within the computing platform 102. Further, a clock source may be included in the user space 106 (not shown), the kernel space 108 (e.g., the clock source 124C), or the system or hardware space 110 (e.g., the clock source 124A). Further, the corresponding clock managers 120 may be included in any suitable space or environment, examples of which are described in Fig. 1 are shown.

[0030] The timing data provided by a clock manager 120 may vary, for example, based on the type of clock source and / or design requirements or choices. For example, in one or more embodiments, a clock manager 120 may generate timing data representing a timestamp, or another component, such as a sensor driver 118, a sensor driver 114, or another component, may be used at least in part to generate a timestamp from the timing data.

[0031] For example, if clock source 124A includes a TSC clock source, the timing data may include a data-ready TSC. The data-ready TSC may represent one or more specific values ​​from the TSC clock source. Sensor driver 114A may use the data-ready TSC received with a corresponding sensor measurement to generate a timestamp for the sensor measurement.

[0032] As another example, if clock source 124B includes a PHC clock source, clock manager 120B may use a pulse signal from the PHC clock source as a reference point to calculate a precision time protocol (PTP) timestamp for a sensor measurement. In at least one embodiment, sensor driver(s) 118 and clock manager 120B are implemented using a Linux PTP stack. The PTP timestamp may be provided to sensor driver 114B with the sensor measurement.

[0033] As an additional example, if clock source 124C includes a system time clock source (a reference for measuring time within the operating system), clock manager 120C may respond to a request for the system time with a corresponding system time timestamp. In the example shown, the timestamp may be requested by sensor driver 114C, but another component could initiate the request. By way of example and not limitation, sensor driver 114C may receive one or more sensor measurements (e.g., CAN data) and request a corresponding system time timestamp from clock manager 120C.

[0034] Clock sampler 122 and translator 116 can be used to translate or convert the timing data for sensor measurements referenced to various clock sources into a reference or common time domain. The reference time domain can provide application(s) 112 with a comprehensive and coherent understanding of the environment by accurately capturing the relative timing between different sensor events.

[0035] As described herein, clock sampler 122 may be configured to sample a plurality of clock sources to generate sets of correlated samples, such as a timestamp related to clock source 124A and a corresponding timestamp related to clock source 124B. For example, clock sampler 122 may simultaneously or concurrently sample multiple clock sources to generate a set of correlated samples (e.g., a TSC timestamp and a PTP timestamp). Sets of correlated samples may be generated on demand, periodically, and / or using a sampling rate.

[0036] One or more of the clock sources sampled by clock sampler 122 may be frequency-locked or may be free-running. In the example shown, clock source 124A is frequency-locked to clock source 124B. The frequency locking may be hardware-based and / or software-based. For example, a hardware-based frequency lock 140 is shown. Frequency locking may simplify the calculations performed by translator 116 and increase the accuracy of the translated timestamps by reducing or eliminating drift between the clock sources.

[0037] In at least one embodiment, frequency lock 140 is implemented using a digital PLL with a state machine, for example, using feedback to compare the phase and frequency of a reference signal with a clock signal to adjust the frequency of the clock signal to match the reference signal. In at least one embodiment, clock source 124B (e.g., a PHC clock source) is used as the reference signal. As further examples, frequency locking may be performed using a frequency synthesizer and / or digital signal processing techniques.

[0038] With reference to Fig. 2 is Fig. 2 shows an example of a graph 200 of sets of correlated timestamps with a set of timestamps corresponding to a sensor measurement, according to some embodiments of the present disclosure. The sets of correlated timestamps may be sampled using the clock sampler 122, as described herein. In the example shown, the sets of correlated timestamps include a timestamp 210A, a timestamp 210B, a timestamp 210C, and a timestamp 210D (which may be referred to as "timestamp 210") and a timestamp 212A, a timestamp 212B, a timestamp 212C, and a timestamp 212D (which may be referred to as "timestamp 212"). The timestamps 210 may be referenced to the clock source 124B, and the timestamps 212 may be referenced to the clock source 124A. Fig. 2 shows a set of correlated timestamps including timestamp 210A and timestamp 212A, a set of correlated timestamps including timestamp 210B and timestamp 212B, a set of correlated timestamps including timestamp 210C and timestamp 212C, and a set of correlated timestamps including timestamp 210D and timestamp 212D. In graph 200, the timestamp value may represent the value of the timestamp, and the timestamp index may represent a time value related to a sample or concurrent measurement performed using clock sampler 122 (e.g., at a sample rate).

[0039] As described herein, translator 116 may be configured to calculate translation data between one or more of clock sources 124 using the sets of correlated samples from clock sampler 122. The translation data may, for example, represent any information used to translate one or more timestamps, such as timestamp 222 corresponding to clock source 124A, into a reference time domain. For example, the reference time domain may correspond to clock source 124B and / or clock source 124C, where timestamp 222 corresponds to timestamp 220 translated into the reference time domain.

[0040] The translation for a timestamp may be performed using an offset to the timestamp and may correspond to one or more differences of offsets between one or more sets of correlated timestamps and / or one or more rates of change between the sets of correlated timestamps. For example, Fig. 2 indicates a difference (or offset) 228 between the timestamp 210A and the timestamp 212A of a set of correlated timestamps. Fig. 2 also shows a rate of change 230 for timestamps 210 and a rate of change 232 for timestamps 212. In at least one embodiment, translator 116 calculates one or more of the differences and / or rates of change between one or more of the timestamps and translates a timestamp using the differences and / or rates of change. In at least one embodiment, translator 116 calculates the offset without calculating the rates of change. For example, if clock sources 124A and 124B are frequency-locked, the rates of change may not be required to perform translation.

[0041] By way of example and not limitation, timestamps PTP referenced to the clock source 124B may be related to a timestamp index t in accordance with equation (1): PTP[t]=c*t+d, where c may refer to the rate of change 230 and d may refer to a y-intercept or offset corresponding to the timestamps 210. Similarly, timestamps TSC referenced to the clock source 124A may be related to the timestamp index t in accordance with equation (2): TSC[t]=a*t+b, where α may refer to the rate of change 232 and b may refer to a y-intercept or offset corresponding to the timestamps 212.

[0042] Thus, in at least one embodiment, the translator 116 may provide a TSC timestamp t TSC into a PTP timestamp in accordance with equation 3: PTP[tTSC]=c*(tTSC−b) / a+d.

[0043] As described herein, the rates of change may not be required to perform translation when clock sources 124A and 124B are frequency locked. For example, translator 116 may operate using frequency locking in accordance with the simplifying assumption that α ~ = c and that clock sources 124A and 124B have a constant offset from each other (e.g., where "-b + d" represents the offset between clock sources 124A and 124B). More generally, the relationship between α and c may be expressed as ca∼=k where k may be a predefined constant that does not need to be calculated from sets of correlated samples. In at least one embodiment, translator 116 may calculate the offset between clock sources 124A and 124B as a running average between the sets of correlated timestamps.

[0044] Although Fig. 2 with respect to clock sources 124A and 124B, translator 116 may use similar approaches to translate other clock sources into the reference time domain, such as clock source 124C. Further, although clock source 124B (e.g., a PHC clock source) is described as being used as the reference time domain, the reference time domain may be different. In at least one embodiment, translator 116 may not translate timestamps for clock source 124C into the reference time domain. For example, as in Fig. 1, the clock source 124C may be synchronized with the clock source 124B (e.g., continuously). If the clock source 124C is a system time clock source, the reference time range may thus correspond to the system time.

[0045] In at least one embodiment, to synchronize clock source 124C with clock source 124B, clock manager 120C may use clock source 124B to perform one or more step changes to a counter of clock source 124C, and / or may perform one or more frequency adjustments to clock source 124C. In at least one embodiment, step changes may be performed only when the service is started (e.g., at boot time), and frequency adjustments may be performed thereafter (e.g., at runtime).

[0046] In at least one embodiment, the sensor drivers 114 provide the time data and / or corresponding timestamps to the translator 116 for translation or conversion into the reference time domain (e.g., according to Fig. 2). For example, in response to receiving time data and one or more corresponding sensor measurements, a sensor driver 114 may provide one or more timestamps and / or time data to the translator 116. The translator 116 may convert the timestamp and / or time data into the reference time domain using appropriate translation data and send the converted data back to the sensor driver 114. The sensor driver 114 may then provide the converted data to one or more of the applications 112 with the corresponding sensor measurement(s) using communications 132A, 132B, or 132C (which may be referred to as "communications 132"). By way of example and not limitation, each of the communications 132 may include a sensor measurement and a corresponding timestamp referenced to system time (or another reference time domain).Thus, in at least one embodiment, the application(s) 112 may receive timestamps referenced to a common time domain, independent of the initial clock source used to associate time data with a sensor measurement.

[0047] In examples where there are multiple possible initial time ranges for timestamps, translator 116 may determine which time range a timestamp refers to and apply translation data corresponding to the determined time range. The time range may be determined by translator 116, for example, using an identifier or indicator of sensor driver 114 and / or the time range. The identifier or indicator may be received in one or more messages from sensor driver 114 (e.g., with the timestamp(s)). In at least one embodiment, sensor drivers 114 may provide the timestamps to translator 116 when the time data is received by sensor drivers 114. In at least one embodiment, sensor drivers 114 receive the time data in one or more streams of time data and sensor measurements from sensors 104.In at least one embodiment, translator 116 performs time domain conversion on streams of time data and corresponding sensor measurements from sensors 104 to applications 112.

[0048] In at least one embodiment, translator 116 performs the translation using current translation data, such as the current offset and / or rate-of-change values ​​calculated from sets of correlated time samples (e.g., the running average). In at least one embodiment, translator 116 may determine which translation data to use to perform the conversion. For example, the translation data applied may depend on the time range to which a timestamp is referenced and / or a timestamp index or timestamp order associated with the timestamp. As an example, if a clock source is free-running, translator 116 may look up a corresponding rate-of-change for the clock source. However, the rate-of-change may not be required if the clock sources are frequency-locked.

[0049] The information in relation to Fig. The examples provided in Figure 1 indicate the flexibility in configuring computing platform 102 according to disclosed embodiments. Although particular functionality may be described with respect to particular components, that functionality may be achieved at least in part using different or additional components. For example, functionality described as being performed in user space 106, kernel space 108, or system or hardware space 110 may be performed at least in part using any combination of user spaces, kernel spaces, and system spaces. Further, the functionality of one or more sensor drivers 118 or 114 may not be required or may be incorporated into one or more different components.As another example, the clock sampler 122, the translator 116, and / or at least a portion of their functionality may be provided in the same or different user spaces 106, kernel spaces 108, or system or hardware spaces 110. Furthermore, at least a portion of the functionality may be at least partially integrated into one or more of the sensor drivers 114, the sensor drivers 118, and / or the applications 112. As an example, one or more of the sensor drivers 114 may include a translator 116 to perform time-domain translation for time data received by the sensor driver 114 and / or from one or more other sensor drivers 114, sensor drivers 118, and / or interfaces 130. In at least one embodiment, the translator 116 provides the translation data to a requesting sensor driver 114, and the sensor driver 114 performs the translation.Although sensor measurements have been described, disclosed approaches may be more generally applicable to other forms of time-stamped data, where the time data is referenced to various clock sources (e.g., network protocols, web server protocols, etc.).

[0050] As described herein, the application(s) 112 may use the sensor measurements and timestamps for various purposes, such as performing perception and / or control operations of a machine(s). The application(s) 112 may be a game, a video streaming application, a machine control application, a machine locomotion application, a machine propulsion application, a synthetic data generation application, a model training application, a perception application, an augmented reality application, a virtual reality application, a mixed reality application, a robotics application, a security and surveillance application, an autonomous or semi-autonomous machine application, a deep learning application, an environmental simulation application, a data center processing application, a generative AI application, an application using (large) language models, a conversational AI application, a light transport simulation application (e.g.,ray tracing, path tracing, etc.), a collaborative content creation application for 3D assets, a digital twin system application, a cloud computing application, a mobile application, a computer application, a console application, a tablet application, a robotics application, an autonomous vehicle application, and / or any other type of application or service.

[0051] Regarding the Fig. 3, Fig. 4 and Fig. 5, each block of methods 300, 400, 500, and other methods described herein includes a computational process that may be performed using any combination of hardware, firmware, and / or software. For example, various functions may be performed by a processor executing instructions stored in a memory. The methods may also be embodied as computer-usable instructions stored on computer storage media. The methods may be provided by a standalone application, a service, or a hosted service (standalone or in combination with another hosted service), or a plug-in for another product, to name a few. Additionally, the methods are exemplified with respect to the time synchronization system 100 of Fig. 1. However, these methods may additionally or alternatively be performed by any system or combination of systems, including, but not limited to, those described herein.

[0052] Fig. 3 is a flowchart illustrating a method 300 for translating timestamps into a reference time domain based on receiving sets of correlated timestamps, according to some embodiments of the present disclosure. The method 300 includes, at block B302, receiving one or more sampled sets of correlated timestamps. For example, the translator 116 may receive one or more sets of correlated timestamps sampled using the clock sampler 122. The sets of correlated timestamps may include one or more timestamps referenced to the clock source 124A and one or more timestamps referenced to the clock source 124B.

[0053] At block B304, the method 300 includes calculating one or more offsets between clock sources. For example, using the one or more sampled sets of correlated timestamps, the translator 116 may calculate one or more offsets (e.g., and one or more rates of change) between the clock source 124A and the clock source 124B (e.g., according to Fig. 2) calculate.

[0054] At block B306, method 300 includes converting one or more timestamps into a reference time domain. For example, translator 116 may translate one or more timestamps (e.g., received from sensor drivers 114) of one or more sensor measurements into a reference time domain using the one or more offsets (e.g., and the one or more rates of change).

[0055] At block B308, the method 300 includes performing one or more operations for a machine. For example, the applications 112 may perform one or more operations for the vehicle 600 (or another machine) using the one or more sensor measurements and the one or more timestamps translated into the reference time domain.

[0056] Fig. 4 is a flowchart illustrating a method 400 for converting time data into a reference time domain based on correlated samples from clock sources, according to some embodiments of the present disclosure. The method 400 includes, at block B402, sampling a plurality of clock sources to generate one or more sets of correlated timestamps. For example, the clock sampler 122 may sample the clock sources 124A and 124B to generate one or more sets of correlated samples of the clock sources 124A and 124B.

[0057] At block B404, method 400 includes calculating one or more offsets between clock sources. For example, translator 116 may calculate one or more offsets between clock sources 124A and 124B (e.g., and one or more rates of change) using the one or more sets of correlated samples.

[0058] At block B406, method 400 includes converting time data into a reference time domain. For example, translator 116 may convert time data for one or more sensor measurements into a reference time domain using the one or more offsets (e.g., and the one or more rates of change).

[0059] At block B406, the method 400 includes performing one or more operations for a machine. For example, the applications 112 may perform one or more operations for the vehicle 600 (or another machine) using the one or more sensor measurements and the time data translated into the reference time domain.

[0060] Fig. 5 is a flowchart illustrating a method 500 for initializing a time synchronization system according to some embodiments of the present disclosure. In at least one embodiment, the method 500 may be performed to initialize the time synchronization system 100 to perform time domain conversion. In at least one embodiment, the method 500 may be performed as part of and / or in response to a boot sequence of the computing platform 102. In at least one embodiment, during regular operation of the computing platform 102, no network time is used to determine timestamps of sensor measurements for the applications 112.

[0061] The method 500 includes, at block B502, determining whether network time is available. For example, one or more of the clock managers 120 may determine whether network time is available for the computing platform 102.

[0062] If it is determined at block B504 that network time is not available, a first clock source may be updated using a persistent clock source. For example, the clock manager(s) 120 may update the clock source 124C (e.g., a system clock source) using a persistent clock source 150, such as a real-time clock (RTC) clock source of the computing platform 102. The persistent clock source 150 may use a power source, such as a battery, a backup power supply, an uninterruptible power supply (UPS), a capacitor, a secondary power supply, etc., so that the persistent clock source 150 can continue to keep time while a primary power source is off or otherwise unavailable.

[0063] If it is determined at block B506 that network time is available, the initial clock sources and the persistent clock source may be updated using the network time. For example, clock manager(s) 120 may update clock source 124C and persistent clock source 150 to reflect the network time.

[0064] At block B508, method 500 includes updating a second clock source using the first clock source. For example, clock manager(s) 120 may update clock source 124B (e.g., a PHC clock source) using clock source 124C (e.g., a system clock source).

[0065] At block B510, method 500 includes locking a third clock source to the second clock source. For example, clock manager(s) 120 may frequency lock clock source 124A (e.g., a TSC clock source) to clock source 124B (e.g., a PHC clock source). Clock sampler 122 may sample clock sources 124A and 124B for time-domain conversion based at least on the frequency lock. Example autonomous vehicle

[0066] Fig. 6A is an illustration of an exemplary autonomous vehicle 600 according to some embodiments of the present disclosure. The autonomous vehicle 600 (alternatively referred to herein as "vehicle 600") may include, without limitation, a passenger vehicle, such as a car, a truck, a bus, a first responder vehicle, a shuttle, an electric or motorized bicycle, a motorcycle, a fire engine, a police vehicle, an ambulance, a boat, a construction vehicle, an underwater vehicle, a robotic vehicle, a drone, an aircraft, a vehicle coupled to a trailer (e.g., a semi-trailer truck used to haul cargo), and / or another type of vehicle (e.g., one that is unmanned and / or accommodates one or more passengers).Autonomous vehicles are generally described in terms of automation levels defined by the National Highway Traffic Safety Administration (NHTSA), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (SAE) "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (Standard No. J3016-201806, published June 15, 2018, Standard No. J3016-201606, published September 30, 2016, and previous and future versions of this standard). The vehicle 600 may be capable of functionality according to one or more of the levels 3-5 of the autonomous driving levels. The vehicle 600 may be capable of functionality according to one or more of the levels 1-5 of the autonomous driving levels.For example, the vehicle 600 may be capable of driver assistance (Level 1), partial automation (Level 2), conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment. The term "autonomous" as used herein may include any and / or all types of autonomy for the vehicle 600 or other machine, such as fully autonomous, highly autonomous, conditionally autonomous, partially autonomous, providing assistive autonomy, semi-autonomous, primarily autonomous, or another designation.

[0067] The vehicle 600 may include components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. The vehicle 600 may include a propulsion system 650, such as an internal combustion engine, a hybrid electric power plant, a pure electric motor, and / or another type of propulsion system. The propulsion system 650 may be connected to a drivetrain of the vehicle 600, which may include a transmission to enable propulsion of the vehicle 600. The propulsion system 650 may be controlled in response to receiving signals from the throttle / accelerator pedal 652.

[0068] A steering system 654, which may include a steering wheel, may be used to steer the vehicle 600 (e.g., along a desired path or route) when the propulsion system 650 is operating (e.g., when the vehicle is moving). The steering system 654 may receive signals from a steering actuator 656. The steering wheel may be optional for full automation (Level 5) functionality.

[0069] The brake sensor system 646 may be used to apply the vehicle brakes in response to receiving signals from the brake actuators 648 and / or brake sensors.

[0070] One or more controllers 636 that control one or more system-on-chips (SoCs) 604 ( Fig. 6C) and / or one or more GPUs may provide signals (e.g., representative of commands) to one or more components and / or systems of the vehicle 600. For example, the controller(s) may send signals to apply the vehicle brakes via one or more brake actuators 648, to apply the steering system 654 via one or more steering actuators 656, to apply the propulsion system 650 via one or more throttles / gas pedals 652. The controller(s) 636 may include one or more on-board (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and issue operational commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in driving the vehicle 600.The controller(s) 636 may include a first controller 636 for autonomous driving functions, a second controller 636 for functional safety functions, a third controller 636 for artificial intelligence functionality (e.g., computer vision), a fourth controller 636 for infotainment functionality, a fifth controller 636 for redundancy in emergency conditions, and / or other controllers. In some examples, a single controller 636 may handle two or more of the above functionalities, two or more controllers 636 may handle a single functionality, and / or any combination thereof.

[0071] The controller(s) 636 may provide the signals to control one or more components and / or systems of the vehicle 600 in response to sensor data received from one or more sensors (e.g., sensor inputs). The sensor data may be received, for example, and without limitation, from one or more Global Navigation Satellite System ("GNSS") sensors 658 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 660, one or more ultrasonic sensors 662, one or more LIDAR sensors 664, one or more Inertial Measurement Unit (IMU) sensors 666 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 666, one or more stereo cameras 668, one or more wide-view cameras 670 (e.g.,fisheye cameras), one or more infrared cameras 672, one or more surround cameras 674 (e.g., 360-degree cameras), one or more long-range and / or medium-range cameras 668, one or more speed sensors 644 (e.g., for measuring the speed of the vehicle 600), one or more vibration sensors 642, one or more steering sensors 640, one or more brake sensors (e.g., as part of the brake sensor system 646), and / or other types of sensors.

[0072] One or more of the controller(s) 636 may receive inputs (e.g., represented by input data) from an instrument cluster 632 of the vehicle 600 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (HMI) display 634, an audible annunciator, a speaker, and / or via other components of the vehicle 600. The outputs may include information such as vehicle speed, velocity, time, map data (e.g., the high-resolution ("HD") map 622 of Fig. 6C), location data (e.g., the location of the vehicle 600, such as on a map), direction, location of other vehicles (e.g., an occupancy grid), information about objects and status of objects as perceived by the controller(s) 636, etc. For example, the HMI display 634 may display information about the presence of one or more objects (e.g., a road sign, warning sign, traffic light change, etc.) and / or information about maneuvers the vehicle has performed, is performing, or will perform (e.g., changing lanes now, entering exit 34B in two miles, etc.).

[0073] The vehicle 600 further includes a network interface 624 that may utilize one or more wireless antennas 626 and / or one or more modems to communicate over one or more networks. For example, the network interface 624 may be capable of communication over Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communication ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000"), etc. The wireless antenna(s) 626 may also enable communication between surrounding objects (e.g., vehicles, mobile devices, etc.) using one or more local area networks, such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or one or more low-power wide area networks ("LPWANs"), such as LoRaWAN, SigFox, etc.

[0074] Fig. Figure 6B is an example of camera positions and fields of view for the example autonomous vehicle 600 of Fig. 6A according to some embodiments of the present disclosure. The cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, additional and / or alternative cameras may be included and / or the cameras may be located at various positions on the vehicle 600.

[0075] The camera types for the cameras may include, but are not limited to, digital cameras that may be adapted for use with the components and / or systems of the vehicle 600. The camera(s) may operate at Automotive Safety Integrity Level (ASIL) B and / or another ASIL. The camera types may be capable of any image capture rate, such as 60 frames per second (fps), 120 fps, 240 fps, etc., depending on the embodiment. The cameras may be capable of using rolling shutters, global shutters, another type of shutter, or a combination thereof.In some examples, the color filter array may include a red-clear-clear-clear color filter array (RCCC color filter array), a red-clear-clear-blue color filter array (RCCB color filter array), a red-blue-green-clear color filter array (RBGC color filter array), a Foveon X3 color filter array, a Bayer sensor color filter array (RGGB color filter array), a monochrome sensor color filter array, and / or another type of color filter array. In some embodiments, clear-pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, may be used in an effort to increase light sensitivity.

[0076] In some examples, one or more of the cameras may be used to perform advanced driver assistance system (ADAS) functions (e.g., as part of a redundant or fail-safe design). For example, a multifunction mono camera may be installed to provide functions including lane departure warning, traffic sign support, and intelligent headlight control. One or more of the cameras (e.g., all cameras) may record and provide image data (e.g., video) simultaneously.

[0077] One or more of the cameras may be mounted in a mounting assembly, such as a custom-designed (three-dimensional ("3D") printed) assembly, to cut out stray light and reflections from inside the car (e.g., reflections from the dashboard reflected in the windshield mirrors) that may interfere with the camera's image data acquisition capabilities. With reference to wing mirror mounting assemblies, the wing mirror assemblies may be custom 3D printed so that the camera mounting plate conforms to the shape of the wing mirror. In some examples, the camera(s) may be integrated into the wing mirror. For side-view cameras, the camera(s) may also be integrated into the four pillars at each corner of the cabin.

[0078] Cameras with a field of view that includes portions of the environment in front of the vehicle 600 (e.g., forward-facing cameras) can be used for surround visibility to help identify forward paths and obstacles, as well as to help provide, using one or more controllers 636 and / or control SoCs, information critical for generating an occupancy grid and / or determining preferred vehicle paths. Forward-facing cameras can be used to perform many of the same ADAS functions as LIDAR, including emergency braking, pedestrian detection, and collision avoidance. Forward-facing cameras can also be used for ADAS features and systems, including lane departure warnings ("LDW"), autonomous cruise control ("ACC"), and / or other features such as traffic sign recognition.

[0079] A variety of cameras may be used in a forward-facing configuration, including, for example, a monocular camera platform that includes a complementary metal oxide semiconductor ("CMOS") color imager. Another example may be a wide-view camera(s) 670 that may be used to perceive objects coming into view from the periphery (e.g., pedestrians, crossing traffic, or bicycles). Although in Fig. 6B illustrates only one wide-view camera, there may be any number (including zero) of wide-view cameras 670 on the vehicle 600. Additionally, any number of long-range camera(s) 668 (e.g., a long-range stereo camera pair) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. The long-range camera(s) 668 may also be used for object detection and classification, as well as basic object tracking.

[0080] Any number of stereo cameras 668 may also be included in a forward-facing configuration. In at least one embodiment, one or more of the stereo camera(s) 668 may include an integrated control unit comprising a scalable processing unit that may provide programmable logic ("FPGA") and a multi-core microprocessor with an integrated Controller Area Network ("CAN") or an Ethernet interface on a single chip. Such a unit may be used to generate a 3D map of the vehicle's surroundings, including a distance estimate for all points in the image. Alternative stereo camera(s) 668 may include one or more compact stereo vision sensors that may include two camera lenses (one each on the left and right) and an image processing chip that measures the distance from the vehicle to the target object and processes the generated information (e.g.,metadata) to activate the autonomous emergency braking and lane departure warning functions. Other types of stereo camera(s) 668 may be used in addition to or alternatively to those described here.

[0081] Cameras with a field of view that includes portions of the environment to the side of the vehicle 600 (e.g., side view cameras) may be used for surround visibility, providing information used to create and update the occupancy grid, as well as to generate side impact collision warnings. For example, the surround camera(s) 674 (e.g., four surround cameras 674, as shown in Fig. 6B) may be positioned on the vehicle 600. The surround view camera(s) 674 may include one or more wide view cameras 670, one or more fisheye cameras, one or more 360-degree cameras, and / or the like. For example, four fisheye cameras may be positioned at the front, rear, and sides of the vehicle. In an alternative arrangement, the vehicle may utilize three surround view camera(s) 674 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround view camera.

[0082] Cameras with a field of view that includes portions of the environment behind the vehicle 600 (e.g., rearview cameras) may be used for parking assistance, surround view, rear collision warnings, and occupancy grid creation and updating. A wide variety of cameras may be used, including, but not limited to, cameras that are also suitable as one or more forward-facing cameras (e.g., long-range and / or medium-range camera(s) 668, stereo camera(s) 668), infrared camera(s) 672, etc.), as described herein.

[0083] Fig. 6C is a block diagram of an example system architecture for the example autonomous vehicle 600 of Fig. 6A according to some embodiments of the present disclosure. It should be understood that these and other arrangements described herein are set forth only as examples. Other arrangements and elements (e.g., engines, interfaces, functions, sequences, groupings of functions, etc.) may be used in addition to or in place of those shown, and some elements may be omitted entirely. Further, many of the elements described herein are functional entities that may be implemented as discrete or distributed components, or in conjunction with other components, and in any suitable combination and location. Various functions described herein as being performed by entities may be performed by hardware, firmware, and / or software. For example, various functions may be performed by a processor executing instructions stored in memory.

[0084] Each of the vehicle’s components, features and systems 600 in Fig. 6C are illustrated as being connected via bus 602. Bus 602 may include a Controller Area Network (CAN) data interface (alternatively referred to herein as a "CAN bus"). A CAN may be a network within vehicle 600 used to assist in controlling various features and functionality of vehicle 600, such as brake application, acceleration, braking, steering, windshield wipers, etc. A CAN bus may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). The CAN bus may be read to find steering wheel angle, ground speed, engine revolutions per minute (RPMs), button positions, and / or other vehicle status indicators. The CAN bus may be ASIL B compliant.

[0085] Although bus 602 is described herein as a CAN bus, this is not intended to be limiting. For example, FlexRay and / or Ethernet may be used in addition to or alternatively to the CAN bus. Additionally, although a single line is used to represent bus 602, this is not intended to be limiting. For example, there may be any number of buses 602, which may include one or more CAN buses, one or more FlexRay buses, one or more Ethernet buses, and / or one or more other types of buses using a different protocol. In some examples, two or more buses 602 may be used to perform different functions and / or may be used for redundancy. For example, a first bus 602 may be used for collision avoidance functionality and a second bus 602 may be used for actuation control.In any example, each bus 602 may communicate with any of the components of the vehicle 600, and two or more buses 602 may communicate with the same components. In some examples, each SoC 604, controller 636, and / or computer within the vehicle may have access to the same input data (e.g., inputs from sensors of the vehicle 600) and may be connected to a common bus, such as the CAN bus.

[0086] The vehicle 600 may include one or more controllers 636, such as those described herein with respect to Fig. 6A. The controller(s) 636 may be used for a variety of functions. The controller(s) 636 may be coupled to any of the various other components and systems of the vehicle 600 and may be used to control the vehicle 600, artificial intelligence of the vehicle 600, infotainment for the vehicle 600, and / or the like.

[0087] The vehicle 600 may include one or more systems on a chip (SoC) 604. The SoC 604 may include CPU(s) 606, GPU(s) 608, processor(s) 610, cache(s) 612, accelerators 614, data storage 616, and / or other unillustrated components and features. The SoC(s) 604 may be used to control the vehicle 600 in a variety of platforms and systems. For example, the SoC(s) 604 may be combined in a system (e.g., the system of the vehicle 600) with an HD card 622 that may receive map updates and / or updates via a network interface 624 from one or more servers (e.g., server 678 from Fig. 6D).

[0088] The CPU(s) 606 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). The CPU(s) 606 may include multiple cores and / or L2 caches. For example, in some embodiments, the CPU(s) 606 may include eight cores in a coherent multiprocessor configuration. In some embodiments, the CPU(s) 606 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., a 2 MB L2 cache). The CPU(s) 606 (e.g., the CCPLEX) may be configured to support concurrent cluster operation, allowing any combination of the clusters of the CPU(s) 606 to be active at any one time.

[0089] The CPU(s) 606 may implement power management capabilities that include one or more of the following features: Individual hardware blocks may be automatically clocked when idle to conserve dynamic power; each core clock may be clocked when the core is not actively executing instructions due to the execution of WFI / WFE instructions; each core may be independently power controlled; each core cluster may be independently clocked when all cores are clocked or power controlled; and / or each core cluster may be independently power controlled when all cores are power controlled. The CPU(s) 606 may further implement an advanced algorithm for managing power states, where allowed power states and expected wake-up times are specified, and the hardware / microcode determines the best power state to enter for the core, cluster, and CCPLEX.The processing cores can support simplified power state input sequences in software, offloading the work to microcode.

[0090] The GPU(s) 608 may include an integrated GPU (alternatively referred to herein as an "iGPU"). The GPU(s) 608 may be programmable and may be efficient for parallel workloads. In some examples, the GPU(s) 608 may use an extended tensor instruction set. The GPU(s) 608 may include one or more streaming microprocessors, where each streaming microprocessor may include an L1 cache (e.g., an L1 cache with a memory capacity of at least 66 KB) and two or more of the streaming microprocessors may share an L2 cache (e.g., an L2 cache with a memory capacity of 512 KB). In some embodiments, the GPU(s) 608 may include at least eight streaming microprocessors. The GPU(s) 608 may use one or more Compute Application Programming Interface(s) (API(s)).Additionally, the GPU(s) 608 may utilize one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA).

[0091] The GPU(s) 608 may be performance-optimized for best performance in automotive and embedded use cases. For example, the GPU(s) 608 may be fabricated on a fin field-effect transistor (FinFET). However, this is not intended to be limiting, and the GPU(s) 608 may be fabricated using other semiconductor manufacturing processes. Each streaming microprocessor may include a number of mixed-precision processing cores partitioned into multiple blocks. For example, and without limitation, 64 PF32 cores and 32 PF64 cores may be partitioned into four processing blocks. In such an example, each processing block may be assigned 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two NVIDIA mixed-precision TENSOR COREs for deep learning matrix arithmetic, an L0 instruction cache, a warp scheduler, a dispatch unit, and / or a 64 KB register file.Additionally, streaming microprocessors can include independent parallel integer and floating-point data paths to provide efficient execution of workloads with a mix of computation and addressing calculations. Streaming microprocessors can include independent thread scheduling capability to enable finer synchronization and collaboration between parallel threads. Streaming microprocessors can include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0092] The GPU(s) 608 may include high-bandwidth memory (HBM) and / or a 16 GB HBM2 memory subsystem to provide, in some examples, a peak memory bandwidth of approximately 600 GB / second. In some examples, synchronous graphics random access memory (SGRAM), such as double data rate type five synchronous graphics random access memory (GDDR5), may be used in addition to or as an alternative to the HBM memory.

[0093] The GPU(s) 608 may include unified memory technology that includes access counters to enable more accurate migration of memory pages to the processor that accesses them most frequently, thereby improving efficiency for shared memory areas between processors. In some examples, address translation service (ATS) support may be used to enable the GPU(s) 608 to directly access the page tables of the CPU(s) 606. In such examples, when the memory management unit (MMU) of the GPU(s) 608 experiences a fault, an address translation request may be transmitted to the CPU(s) 606. In response, the CPU(s) 606 may look up the virtual-to-physical mapping for the address in their page tables and transmit the translation back to the GPU(s) 608.Thus, the unified memory technology may enable a single unified virtual address space for memory of both the CPU(s) 606 and the GPU(s) 608, thereby simplifying the programming and porting of GPU(s) 608 applications to the GPU(s) 608.

[0094] Additionally, the GPU(s) 608 may include an access counter that can track the frequency of the GPU(s) 608 accessing memory of other processors. The access counter can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently.

[0095] The SoC(s) 604 may include any number of cache(s) 612, including those described herein. For example, the cache(s) 612 may include an L3 cache available to both the CPU(s) 606 and the GPU(s) 608 (e.g., connected to both the CPU(s) 606 and the GPU(s) 608). The cache(s) 612 may include a write-back cache that can track line states, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). The L3 cache may include 4 MB or more, depending on the embodiment, although smaller cache sizes may be used.

[0096] The SoC(s) 604 may include arithmetic logic unit(s) (ALU(s)) that may be utilized in performing processing related to any of the vehicle's 600 variety of tasks or operations, such as processing DNNs. Additionally, the SoC(s) 604 may include floating-point unit(s) (FPU(s))—or other types of mathematical coprocessors or numerical coprocessors—for performing mathematical operations within the system. For example, the SoC(s) 104 may include one or more FPUs integrated as execution units within a CPU(s) 606 and / or GPU(s) 608.

[0097] The SoC(s) 604 may include one or more accelerators 614 (e.g., hardware accelerators, software accelerators, or a combination thereof). For example, the SoC(s) 604 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. The large on-chip memory (e.g., 4 MB SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. The hardware acceleration cluster may be used to supplement the GPU(s) 608 and offload some of the tasks of the GPU(s) 608 (e.g., to free up more cycles of the GPU(s) 608 to perform other tasks). As an example, the accelerator(s) 614 may be used for targeted workloads (e.g., perception, convolutional neural networks (CNNs), etc.) that are stable enough to be accelerable.The term “CNN” as used herein can include all types of CNNs, including region-based or regional convolutional neural networks (RCNNs) and fast RCNNs (e.g., as used for object detection).

[0098] The accelerator(s) 614 (e.g., the hardware acceleration cluster) may include one or more deep learning accelerators (DLAs). The DLA(s) may include one or more tensor processing units (TPUs), which may be configured to provide an additional tens of trillion operations per second for deep learning applications and inference. The TPUs may be accelerators configured and optimized to perform image processing functions (e.g., for CNNs, RCNNs, etc.). The DLA(s) may be further optimized for a specific set of neural network types and floating-point operations, as well as inference. The design of the DLA(s) may provide more performance per millimeter than a general-purpose GPU and significantly exceeds the performance of a CPU.The TPU(s) can perform several functions, including a single-instance convolution function that supports, for example, INT8, INT16, and FP16 data types for both features and weights, as well as post-processing functions.

[0099] The DLA(s) may quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example and without limitation: a CNN for object identification and detection using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for emergency vehicle detection and identification using data from microphones; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and / or a CNN for safety and / or security-related events.

[0100] The DLA(s) can perform any function of the GPU(s) 608, and by using an inference accelerator, for example, a designer can target either the DLA(s) or the GPU(s) 608 for any function. For example, the designer can focus the processing of CNNs and floating-point operations on the DLA(s) and leave other functions to the GPU(s) 608 and / or the other accelerator(s) 614.

[0101] The accelerator(s) 614 (e.g., the hardware acceleration cluster) may include one or more programmable vision accelerators (PVAs), which may alternatively be referred to herein as a computer vision accelerator. The PVA(s) may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (ADAS), autonomous driving, and / or augmented reality (AR) and / or virtual reality (VR) applications. The PVA(s) may provide a balance between performance and flexibility. For example, each PVA(s) may include, for example and without limitation, any number of reduced instruction set computing (RISC) cores, direct memory access (DMA), and / or any number of vector processors.

[0102] The RISC cores may interact with image sensors (e.g., the image sensors of any of the cameras described herein), image signal processor(s), and / or the like. Each of the RISC cores may include any amount of memory. The RISC cores may use any of a number of protocols, depending on the embodiment. In some examples, the RISC cores may execute a real-time operating system (RTOS). The RISC cores may be implemented using one or more integrated circuit devices, application-specific integrated circuits (ASICs), and / or memory devices. For example, the RISC cores may include an instruction cache and / or tightly coupled RAM.

[0103] The DMA may enable components of the PVA(s) to access system memory independently of the CPU(s) 606. The DMA may support any number of features used to provide optimization for the PVA, including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In some examples, the DMA may support up to six or more dimensions of addressing, which may include block width, block height, block depth, horizontal block increments, vertical block increments, and / or depth increments.

[0104] The vector processors may be programmable processors that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In some examples, the PVA may include a PVA core and two vector processing subsystem partitions. The PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripherals. The vector processing subsystem may operate as the primary processing engine of the PVA and may include a vector processing unit (VPU), an instruction cache, and / or vector memory (e.g., VMEM). A VPU core may include a digital signal processor, such as a single instruction multiple data (SIMD) very long instruction word (VLIW) digital signal processor. The combination of SIMD and VLIW can improve throughput and speed.

[0105] Each of the vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in some examples, each of the vector processors may be configured to execute independently of the other vector processors. In other examples, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in some embodiments, the plurality of vector processors included in a single PVA may execute the same computer vision algorithm, but on different regions of an image. In other examples, the vector processors included in a particular PVA may concurrently execute different computer vision algorithms on the same image, or even execute different algorithms on consecutive images or portions of an image.Among other things, any number of PVAs may be included in the hardware acceleration cluster, and any number of vector processors may be included in each of the PVAs. Additionally, the PVA(s) may include additional error correction code (ECC) memory to improve overall system security.

[0106] The accelerator(s) 614 (e.g., the hardware acceleration cluster) may include an on-chip and SRAM computer vision network for providing high-bandwidth, low-latency SRAM to the accelerator(s) 614. In some examples, the on-chip memory may include at least 4 MB of SRAM, consisting of, for example, and without limitation, eight field-configurable memory blocks accessible by both the PVA and the DLA. Each pair of memory blocks may include an advanced peripheral bus (APB) interface, configuration circuitry, a controller, and a multiplexer. Any type of memory may be used. The PVA and the DLA may access the memory via a backbone that provides high-speed access to the memory to the PVA and the DLA. The backbone may include an on-chip computer vision network connecting the PVA and the DLA to the memory (e.g.,using the APB).

[0107] The on-chip computer vision network may include an interface that determines that both the PVA and the DLA are ready and providing valid signals before transmitting any control signal / address / data. Such an interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communications for continuous data transmission. This type of interface may conform to ISO 26262 or IEC 61508, although other standards and protocols may be used.

[0108] In some examples, the SoC(s) 604 may include a real-time ray tracing hardware accelerator, such as described in U.S. Patent Application No. 16 / 101,232, filed August 10, 2018. The real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the positions and extents of objects (e.g., within a world model) to generate real-time visualization simulations for radar signal interpretation, sound propagation synthesis and / or analysis, simulation of sonar systems, general wave propagation simulation, comparison with lidar data for localization and / or other functions, and / or for other uses. In some embodiments, one or more tree traversal units (TTUs) may be used to perform one or more ray tracing-related operations.

[0109] The accelerator(s) 614 (e.g., the hardware acceleration cluster) have a wide range of uses for autonomous driving. The PVA can be a programmable vision accelerator that can be used for key processing stages in ADAS and autonomous vehicles. The capabilities of the PVA are a good match for algorithmic domains that require predictable processing with low power and low latency. In other words, the PVA is good for semi-dense or dense regular computation, even for small datasets, that require predictable runtimes with low latency and low power. Thus, in the context of autonomous vehicle platforms, the PVAs are designed to execute classical computer vision algorithms because they are efficient at object detection and operate on integer mathematics.

[0110] For example, according to one embodiment of the technology, the PVA is used to perform computer stereo vision. A semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. Many Level 3-5 autonomous driving applications require on-the-fly motion estimation / stereo matching (e.g., structure from motion, pedestrian detection, lane detection, etc.). The PVA can perform computer stereo vision on inputs from two monocular cameras.

[0111] In some examples, the PVA can be used to perform dense optical flow. According to the processing, raw radar data is processed (e.g., using a fast 4D Fourier transform) to provide processed radar. In other examples, the PVA is used for runtime depth processing, for example, by processing raw runtime data to provide processed runtime data.

[0112] The DLA can be used to implement any type of network to improve control and driving safety, including, for example, a neural network that outputs a confidence measure for each object detection. Such a confidence value can be interpreted as a probability or as providing a relative "weight" of each detection compared to other detections. This confidence value allows the system to make further decisions about which detections should be considered true positives rather than false positives. For example, the system can set a confidence threshold and consider only detections that exceed the threshold as true positives.In an automatic emergency braking (AEB) system, false positive detections would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. Therefore, only the most certain detections should be considered as triggers for AEB. The DLA may execute a neural network to regress the confidence value. The neural network may take as its input at least a subset of parameters, such as bounding box dimensions, ground plane estimation obtained (e.g., from another subsystem), output of the inertial measurement unit (IMU) sensor 666 correlated with the orientation of the vehicle 600, distance, 3D position estimates of the object obtained by the neural network, and / or other sensors (e.g., LIDAR sensor(s) 664 or RADAR sensor(s) 660), among others.

[0113] The SoC(s) 604 may include data storage 616 (e.g., memory). The data storage 616 may be on-chip memory of the SoC(s) 604, which may store neural networks to be executed on the GPU and / or the DLA. In some examples, the data storage 616 may be large enough in capacity to store multiple neural network instances for redundancy and security. The data storage 612 may include L2 or L3 cache(s). Reference to the data storage 616 may include reference to the memory associated with the PVA, the DLA, and / or the other accelerator(s) 614, as described herein.

[0114] The SoC(s) 604 may include one or more processor(s) 610 (e.g., embedded processors). The processor(s) 610 may include a boot and power management processor, which may be a dedicated processor and a dedicated subsystem for handling boot power and management functions and associated security enforcement. The boot and power management processor may be part of the boot sequence of the SoC(s) 604 and may provide runtime power management services. The boot power and management processor may provide clock and power programming, assistance with system low-power state transitions, management of thermal and temperature sensors of the SoC(s) 604, and / or management of the power states of the SoC(s) 604.Each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC(s) 604 may use the ring oscillators to detect temperatures of the CPU(s) 606, GPU(s) 608, and / or accelerator 614. If temperatures are determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine and place the SoC(s) 604 into a lower power state and / or place the vehicle 600 into a chauffeur-into-safe-stop mode (e.g., bring the vehicle 600 to a safe stop).

[0115] Processor(s) 610 may further include a set of embedded processors that may serve as an audio processing engine. The audio processing engine may be an audio subsystem that enables full hardware support for multi-channel audio across multiple interfaces and a wide and flexible range of audio I / O interfaces. In some examples, the audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0116] The processor(s) 610 may further include an always-on processor engine that may provide necessary hardware features to support low-power sensor management and wake-up use cases. The always-on processor engine may include a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O control peripherals, and routing logic.

[0117] The processor(s) 610 may further include a safety cluster engine, which includes a dedicated processor subsystem for handling safety management for automotive applications. The safety cluster engine may include two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, an interrupt controller, etc.), and / or routing logic. In a safety mode, the two or more cores may operate in a lock-step mode, functioning as a single core with comparison logic to detect differences between their operations.

[0118] The processor(s) 610 may further include a real-time camera engine, which may include a dedicated processor subsystem for handling real-time camera management.

[0119] The processor(s) 610 may further include a high dynamic range signal processor, which may include an image signal processor that is a hardware engine that is part of the camera processing pipeline.

[0120] The processor(s) 610 may include a video image compositor, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to generate the final image for the playback window. The video image compositor may perform lens distortion correction on the wide-view camera(s) 670, the surround camera(s) 674, and / or on in-cabin monitoring camera sensors. The in-cabin monitoring camera sensor is preferably monitored by a neural network executing on another instance of the advanced SoC configured to identify in-cabin events and respond accordingly.An in-cabin system can perform lip reading to activate cellular service and place a phone call, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. Certain functions are available to the driver only when the vehicle is operating in autonomous mode and are disabled otherwise.

[0121] The video image compositer may incorporate enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, when motion occurs in a video, the noise reduction appropriately weights spatial information, thereby reducing the weight of information provided by neighboring frames. When an image or part of an image contains no motion, the temporal noise reduction performed by the video image compositer may use information from the previous frame to reduce noise in the current frame.

[0122] The video image compositor may also be configured to perform stereo rectification on input stereo lens images. The video image compositor may further be used for user interface composition when the operating system desktop is in use and the GPU(s) 608 are not required to continuously render new surfaces. Even when the GPU(s) 608 are turned on and active to perform 3D rendering, the video image compositor may be used to offload the GPU(s) 608 to improve performance and responsiveness.

[0123] The SoC(s) 604 may further include a Mobile Industrial Processor Interface (MIPI) serial camera interface for receiving video and input from cameras, a high-speed interface, and / or a video input block that may be used for camera and related pixel input functions. The SoC(s) 604 may further include one or more input / output controllers that may be controlled by software and used to receive I / O signals that are not bound to a specific role.

[0124] The SoC(s) 604 may further include a wide range of peripheral interfaces to enable communication with peripherals, audio codecs, power management, and / or other devices. The SoC(s) 604 may be used to process data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet), sensors (e.g., LIDAR sensor(s) 664, RADAR sensor(s) 660, etc., which may be connected via Ethernet), data from the bus 602 (e.g., speed of the vehicle 600, steering wheel position, etc.), and data from GNSS sensor(s) 658 (e.g., connected via Ethernet or CAN bus). The SoC(s) 604 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and which may be used to free the CPU(s) 606 from routine data management tasks.

[0125] The SoC(s) 604 may be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and efficiently uses computer vision and ADAS techniques for diversity and redundancy, and providing a platform for a flexible, reliable driving software stack along with deep learning tools. The SoC(s) 604 may be faster, more reliable, and even more power- and space-efficient than conventional systems. For example, the accelerator(s) 614, when combined with the CPU(s) 606, GPU(s) 608, and memory(s) 616, may provide a fast, efficient platform for Level 3-5 autonomous vehicles.

[0126] The technology thus provides capabilities and functionality that cannot be achieved by conventional systems. For example, computer vision algorithms can be executed on CPUs, which can be configured using high-level programming languages ​​such as the C programming language to perform a wide variety of processing algorithms on a wide variety of visual data. However, CPUs are often unable to meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In particular, many CPUs are unable to execute complex object detection algorithms in real time, which is a requirement of in-vehicle ADAS applications and a requirement for practical Level 3-5 autonomous vehicles.

[0127] Unlike conventional systems, by providing a CPU complex, a GPU complex, and a hardware acceleration cluster, the technology described herein enables multiple neural networks to be executed simultaneously and / or sequentially and the results to be combined to enable Level 3-5 autonomous driving functionality. For example, a CNN executing on the DLA or dGPU (e.g., GPU(s) 620) may include text and word recognition, allowing the supercomputer to read and understand traffic signs, including signs for which the neural network has not been specifically trained. The DLA may further include a neural network capable of identifying, interpreting, and providing a semantic understanding of the sign, and passing this semantic understanding to the path planning modules executing on the CPU complex.

[0128] As another example, multiple neural networks can be executed simultaneously, as required for Level 3, 4, or 5 driving. For example, a warning sign consisting of "Warning: Flashing lights indicate icy conditions," along with an electrical light, can be interpreted independently or jointly by multiple neural networks. The sign itself can be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the text "Flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which informs the vehicle's path-planning software (preferably running on the CPU complex) that if flashing lights are detected, icy conditions exist.The flashing light can be identified by running a third deployed neural network across multiple images, thereby informing the vehicle's path planning software of the presence (or absence) of flashing lights. All three neural networks can be executed simultaneously, such as within the DLA and / or on the GPU(s) 608.

[0129] In some examples, a CNN for facial recognition and vehicle owner identification may use data from camera sensors to identify the presence of an authorized driver and / or owner of the vehicle 600. The always-on sensor processing engine may be used to unlock the vehicle when the owner approaches the driver's door and turn on the lights, and in security mode, disarm the vehicle when the owner exits the vehicle. In this way, the SoC(s) 604 provide security against theft and / or carjacking.

[0130] In another example, a CNN for emergency vehicle detection and identification may use data from microphones 666 to detect and identify emergency vehicle sirens. Unlike conventional systems that use general classifiers to detect sirens and manually extract features, the SoC(s) 604 use the CNN to classify ambient and urban noise, as well as visual data. In a preferred embodiment, the CNN running on the DLA is trained to identify the relative closing speed of the emergency vehicle (e.g., using the Doppler effect). The CNN may also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, as identified by the GNSS sensor(s) 658.Thus, for example, when operating in Europe, the CNN attempts to detect European sirens, and when operating in the United States, the CNN attempts to identify only North American sirens. Once an emergency vehicle is detected, a control program can be used to execute an emergency vehicle safety routine, slow the vehicle, pull to the side of the road, park the vehicle, and / or idle the vehicle using ultrasonic sensors 662 until the emergency vehicle(s) pass.

[0131] The vehicle may include one or more CPU(s) 618 (e.g., discrete CPU(s) or dCPU(s)) that may be coupled to the SoC(s) 604 via a high-speed connection (e.g., PCIe). The CPU(s) 618 may, for example, include an x86 processor. The CPU(s) 618 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and the SoC(s) 604 and / or monitoring the status and health of the controller(s) 636 and / or the infotainment SoC 630.

[0132] The vehicle 600 may include one or more GPU(s) 620 (e.g., discrete GPU(s) or dGPU(s)) that may be coupled to the SoC(s) 604 via a high-speed interconnect (e.g., NVIDIA's NVLINK). The GPU(s) 620 may provide additional artificial intelligence functionality, such as by executing redundant and / or distinct neural networks, and may be used to train and / or update neural networks based on inputs (e.g., sensor data) from sensors of the vehicle 600.

[0133] The vehicle 600 may further include the network interface 624, which may include one or more wireless antennas 626 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). The network interface 624 may be used to enable wireless connectivity over the internet to the cloud (e.g., to the server(s) 678 and / or other network devices), to other vehicles, and / or to computing devices (e.g., passenger client devices). To communicate with other vehicles, a direct connection may be established between the two vehicles and / or an indirect connection may be established (e.g., via networks and over the internet). Direct connections may be provided using a vehicle-to-vehicle communication link.The vehicle-to-vehicle communication link may provide information to the vehicle 600 about vehicles in the vicinity of the vehicle 600 (e.g., vehicles in front of, to the side of, and / or behind the vehicle 600). This functionality may be part of a cooperative adaptive cruise control functionality of the vehicle 600.

[0134] The network interface 624 may include an SoC that provides modulation and demodulation functionality and enables the controller(s) 636 to communicate over wireless networks. The network interface 624 may include a radio frequency front-end for upconverting from baseband to radio frequency and downconverting from radio frequency to baseband. The frequency conversions may be performed by well-known processes and / or may be performed using superheterodyne processes. In some examples, the radio frequency front-end functionality may be provided by a separate chip. The network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0135] The vehicle 600 may further include one or more data stores 628, which may include off-chip memory (e.g., outside the SoC(s) 604). The data store(s) 628 may include one or more memory elements, including RAM, SRAM, DRAM, VRAM, flash, hard drives, and / or other components and / or devices capable of storing at least one bit of data.

[0136] The vehicle 600 may further include one or more GNSS sensors 658. The GNSS sensor(s) 658 (e.g., GPS, assisted GPS sensors, differential GPS (DGPS) sensors, etc.) assist in mapping, sensing, occupancy grid generation, and / or path planning functions. Any number of GNSS sensors 658 may be used, including, for example, and without limitation, a GPS using a USB connector with an Ethernet-to-serial (RS-232) bridge.

[0137] The vehicle 600 may further include one or more RADAR sensors 660. The RADAR sensor(s) 660 may be used by the vehicle 600 for long-range vehicle detection, even in darkness and / or severe weather conditions. RADAR functional safety levels may be ASIL B. The RADAR sensor(s) 660 may use the CAN bus and / or bus 602 (e.g., to transmit data generated by the RADAR sensor(s) 660) for control and to access object tracking data, with raw data being accessed via Ethernet in some examples. A wide variety of RADAR sensor types may be used. For example, and without limitation, the RADAR sensor(s) 660 may be suitable for front, rear, and side RADAR use. In some examples, one or more Pulse Doppler RADAR sensors are used.

[0138] The RADAR sensor(s) 660 may include various configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In some examples, long-range RADAR may be used for adaptive cruise control functionality. Long-range RADAR systems may provide a wide field of view realized by two or more independent scans, such as within a 250 m range. The RADAR sensor(s) 660 may help distinguish between static and moving objects and may be used by ADAS systems for emergency braking assistance and forward collision warning. Long-range RADAR sensors may include monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and a high-speed CAN and FlexRay interface.In a six-antenna example, the middle four antennas can create a focused beam pattern designed to record the surroundings of vehicle 600 at higher speeds with minimal interference from traffic in adjacent lanes. The other two antennas can expand the field of view, making it possible to quickly detect vehicles entering or exiting the lane of vehicle 600.

[0139] Medium-range radar systems, for example, can have a range of up to 660 m (front) or 80 m (rear) and a field of view of up to 42 degrees (front) or 650 degrees (rear). Short-range radar systems can, without limitation, include radar sensors designed to be installed at both ends of the rear bumper. When installed at both ends of the rear bumper, such radar sensor systems can generate two beams that continuously monitor the blind spot area to the rear and side of the vehicle.

[0140] Short-range radar systems can be used in an ADAS system for blind spot detection and / or lane change assistance.

[0141] The vehicle 600 may further include one or more ultrasonic sensors 662. The ultrasonic sensor(s) 662, which may be positioned at the front, rear, and / or sides of the vehicle 600, may be used for parking assistance and / or for creating and updating an occupancy grid. A wide variety of ultrasonic sensors 662 may be used, and different ultrasonic sensors 662 may be used for different sensing ranges (e.g., 2.5 m, 4 m). The ultrasonic sensor(s) 662 may operate at functional safety levels of ASIL B.

[0142] The vehicle 600 may include one or more LIDAR sensors 664. The LIDAR sensor(s) 664 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. The LIDAR sensor(s) 664 may be functional safety level ASIL B. In some examples, the vehicle 600 may include multiple LIDAR sensors 664 (e.g., two, four, six, etc.) that may use Ethernet (e.g., to provide data to a Gigabit Ethernet switch).

[0143] In some examples, the LIDAR sensor(s) 664 may be capable of providing a list of objects and their distances for a 360-degree field of view. The commercially available LIDAR sensor(s) 664 may have an advertised range of approximately 600 m with an accuracy of 2 cm-3 cm and with support for, for example, a 600 Mbps Ethernet connection. In some examples, one or more non-protruding LIDAR sensors 664 may be used. In such examples, the LIDAR sensor(s) 664 may be implemented as a small device that may be embedded in the front, rear, sides, and / or corners of the vehicle 600. In such examples, the LIDAR sensor(s) 664 may provide up to a 120-degree horizontal field of view and a 35-degree vertical field of view with a range of 200 m even for low-reflectivity objects.The front-mounted LIDAR sensor(s) 664 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0144] In some examples, LIDAR technologies such as 3D flash LIDAR may also be used. 3D flash LIDAR uses a laser flash as a transmission source to illuminate the vehicle's surroundings up to approximately 200 m. A flash LIDAR unit includes a receiver that records the laser pulse time of flight and the reflected light at each pixel, which in turn corresponds to the range from the vehicle to the objects. Flash LIDAR can enable highly accurate and distortion-free images of the surroundings to be created with each laser flash. In some examples, four flash LIDAR sensors may be deployed, one on each side of the vehicle. Available 3D flash LIDAR systems include a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device).The flash lidar device can use a 5-nanosecond Class I (eye-safe) laser pulse per image and can capture the reflected laser light as 3D range point clouds and simultaneously recorded intensity data. By using flash lidar, and because flash lidar is a solid-state device with no moving parts, the lidar sensor(s) 664 can be less susceptible to motion blur, vibration, and / or shock.

[0145] The vehicle may further include one or more IMU sensors 666. In some examples, the IMU sensor(s) 666 may be located at a center of the rear axle of the vehicle 600. The IMU sensor(s) 666 may include, for example and without limitation, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other types of sensors. In some examples, such as in six-axis applications, the IMU sensor(s) 666 may include accelerometers and gyroscopes, while in nine-axis applications, the IMU sensor(s) 666 may include accelerometers, gyroscopes, and magnetometers.

[0146] In some embodiments, the IMU sensor(s) 666 may be implemented as a miniaturized, high-performance GPS-based inertial navigation system (GPS / INS) that combines microelectromechanical system (MEMS) inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filter algorithms to provide estimates of position, velocity, and attitude. Thus, in some examples, the IMU sensor(s) 666 may enable the vehicle 600 to estimate heading without requiring input from a magnetic sensor by directly observing velocity changes from the GPS and correlating them with the IMU sensor(s) 666. In some examples, the IMU sensor(s) 666 and the GNSS sensor(s) 658 may be combined into a single integrated unit.

[0147] The vehicle may include one or more microphones 666 located in and / or around the vehicle 600. The microphone(s) 666 may be used for, among other things, emergency vehicle detection and identification.

[0148] The vehicle may further include any number of camera types, including stereo camera(s) 668, wide-view camera(s) 670, infrared camera(s) 672, surround camera(s) 674, long-range and / or medium-range camera(s) 668, and / or other camera types. The cameras may be used to capture image data around an entire periphery of the vehicle 600. The camera types used depend on the embodiments and requirements for the vehicle 600, and any combination of camera types may be used to provide the necessary coverage around the vehicle 600. Additionally, the number of cameras may vary depending on the embodiment. For example, the vehicle may include six cameras, seven cameras, ten cameras, twelve cameras, and / or another number of cameras. The cameras may support Gigabit Multimedia Serial Link (GMSL) and / or Gigabit Ethernet, by way of example and without limitation.Each of the camera(s) is referred to herein in relation to . Fig. 6A and Fig. 6B is described in more detail.

[0149] The vehicle 600 may further include one or more vibration sensors 642. The vibration sensor(s) 642 may measure vibrations from components of the vehicle, such as the axle(s). For example, changes in vibration may indicate a change in the road surfaces. In another example, when two or more vibration sensors 642 are used, the differences between the vibrations may be used to determine friction or slippage of the road surface (e.g., when the difference in vibration is between a driven axle and a free-spinning axle).

[0150] The vehicle 600 may include an ADAS system 638. The ADAS system 638 may include an SoC in some examples. The ADAS system 638 may include autonomous / adaptive / automatic cruise control (ACC), cooperative adaptive cruise control (CACC), forward collision warning (FCW), automatic emergency braking (AEB), lane departure warning (LDW), lane keeping assistance (LKA), blind spot warning (BSW), rear cross-traffic alert (RCTW), collision warning systems (CWS), lane centering (LC), and / or other features and functionality.

[0151] The ACC systems may use RADAR sensor(s) 660, LIDAR sensor(s) 664, and / or camera(s). The ACC systems may include longitudinal ACC and / or lateral ACC. Longitudinal ACC monitors and controls the distance to the vehicle immediately ahead of the vehicle 600 and automatically adjusts the vehicle speed to maintain a safe distance to vehicles ahead of the vehicle. Lateral ACC performs follow-through and notifies the vehicle 600 to change lanes if necessary. Lateral ACC refers to other ADAS applications, such as LCA and CWS.

[0152] CACC utilizes information from other vehicles, which may be received via the network interface 624 and / or the wireless antenna(s) 626 from other vehicles over a wireless connection or indirectly via a network connection (e.g., over the Internet). Direct connections may be provided through a vehicle-to-vehicle (V2V) communication link, while indirect connections may be infrastructure-to-vehicle (I2V) communication links. In general, the V2V communication concept provides information about the immediately preceding vehicles (e.g., vehicles immediately in front of and in the same lane as vehicle 600), while the I2V communication concept provides information about traffic further ahead of the vehicle. CACC systems may incorporate one or both I2V and V2V information sources.Given the information from the vehicles ahead of vehicle 600, CACC can be more reliable and has the potential to improve traffic flow smoothness and reduce congestion on the road.

[0153] FCW systems are designed to warn the driver of a hazard so the driver can take corrective action. FCW systems utilize a forward-facing camera and / or radar sensor(s) 660 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is / are electrically coupled to driver feedback, such as a display, speaker, and / or vibration component. FCW systems can provide a warning, such as a sound, a visual warning, a vibration, and / or a rapid braking pulse.

[0154] AEB systems detect an impending forward collision with another vehicle or object and can automatically apply the brakes if the driver does not take corrective action within a specified time or distance parameter. AEB systems may utilize forward-facing camera(s) and / or radar sensor(s) 660 coupled with a dedicated processor, DSP, FPGA, and / or ASIC. When the AEB system detects a hazard, it typically first alerts the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system can automatically apply the brakes in an effort to prevent or at least mitigate the effects of the predicted collision. AEB systems may incorporate techniques such as dynamic brake support and / or imminent collision braking.

[0155] LDW systems provide visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle crosses lane markings. An LDW system will not activate if the driver indicates an intended lane departure by activating a turn signal. LDW systems may utilize forward-facing cameras coupled with a dedicated processor, DSP, FPGA, and / or ASIC, which is / are electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0156] LKA systems are a variation of LDW systems. LKA systems provide steering input or braking to correct the vehicle 600 when the vehicle 600 begins to depart from the lane.

[0157] BSW systems detect and warn the driver of vehicles in an automobile's blind spot. BSW systems may provide a visual, audible, and / or tactile warning to indicate that merging or changing lanes is unsafe. The system may provide an additional warning when the driver uses a turn signal. BSW systems may utilize rear-facing camera(s) and / or radar sensor(s) 660 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0158] RCTW systems may provide visual, audible, and / or tactile notification when an object is detected outside the range of the rear camera when the vehicle 600 is reversing. Some RCTW systems include AEB to ensure the vehicle brakes are applied to avoid a collision. RCTW systems may utilize one or more rear-facing RADAR sensors 660 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is / are electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0159] Conventional ADAS systems can be prone to false positives, which can be annoying and distracting for a driver, but are typically not catastrophic because the ADAS systems warn the driver and allow the driver to decide whether a safety condition actually exists and act accordingly. However, in an autonomous vehicle 600, even in the case of conflicting results, the vehicle 600 must decide whether to honor the result from a primary computer or a secondary computer (e.g., a first controller 636 or a second controller 636). For example, in some embodiments, the ADAS system 638 may be a backup and / or secondary computer for providing perception information to a backup computer rationality module.The backup computer rationality monitor can run redundant, diverse software on hardware components to detect errors in perception and dynamic driving tasks. Outputs from the ADAS system 638 can be provided to a monitoring MCU. If outputs from the primary computer and the secondary computer conflict, the monitoring MCU must determine how to reconcile the conflict to ensure safe operation.

[0160] In some examples, the primary computer may be configured to provide the monitoring MCU with a confidence value indicating the primary computer's confidence in the selected outcome. If the confidence value exceeds a threshold, the monitoring MCU may follow the primary computer's instruction regardless of whether the secondary computer provides a conflicting or inconsistent outcome. If the confidence value does not meet the threshold and if the primary and secondary computers indicate different outcomes (e.g., conflict), the monitoring MCU may arbitrate between the computers to determine the appropriate outcome.

[0161] The monitoring MCU may be configured to run a neural network(s) trained and configured to determine, based on outputs from the primary computer and the secondary computer, conditions under which the secondary computer provides false alarms. Thus, the neural network(s) in the monitoring MCU can learn when the output of the secondary computer can be trusted and when it cannot. For example, if the secondary computer is a radar-based FCW system, a neural network(s) in the monitoring MCU can learn when the FCW system identifies metallic objects that are not actually hazards, such as a drainage grate or manhole cover, which triggers an alarm.Similarly, if the secondary computer is a camera-based LDW system, a neural network in the monitoring MCU can learn to override the LDW when cyclists or pedestrians are present and lane departure is actually the safest maneuver. In embodiments including neural network(s) executing on the monitoring MCU, the monitoring MCU can include a DLA and / or a GPU suitable for executing the neural network(s) with associated memory. In preferred embodiments, the monitoring MCU can include and / or be included as a component of the SoC(s) 604.

[0162] In other examples, the ADAS system 638 may include a secondary computer that performs ADAS functionality using conventional computer vision rules. Thus, the secondary computer can use classic computer vision rules (if-then), and the presence of a neural network(s) in the monitoring MCU can improve reliability, safety, and performance. For example, the diverse implementation and intended non-identity makes the overall system more fault-tolerant, particularly against errors caused by software (or software-hardware interface) functionality.For example, if there is a software bug or error in the software running on the primary computer, and the non-identical software code running on the secondary computer provides the same overall result, the monitoring MCU can have greater confidence that the overall result is correct, and the software or hardware bug on the primary computer does not cause a significant error.

[0163] In some examples, the output of the ADAS system 638 may be fed into the perception block of the primary computer and / or the dynamic driving task block of the primary computer. For example, if the ADAS system 638 indicates a forward collision warning due to an object immediately ahead, the perception block may use this information when identifying objects. In other examples, the secondary computer may have its own neural network trained, thus reducing the risk of false positives, as described herein.

[0164] The vehicle 600 may further include the infotainment SoC 630 (e.g., an in-vehicle infotainment (IVI) system). Although illustrated and described as an SoC, the infotainment system may not be an SoC and may include two or more discrete components. The infotainment SoC 630 may include a combination of hardware and software that can be used to provide the vehicle 600 with audio (e.g., music, a personal digital assistant, navigation directions, news, radio, etc.), video (e.g., television, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., navigation systems, backup assist, a radio data system, vehicle-related information such as fuel level, total distance traveled, brake fuel level, oil level, door opening / closing, air filter information, etc.).For example, the infotainment SoC 630 may include radios, record players, navigation systems, video players, USB and Bluetooth connectivity, car stereos, in-vehicle entertainment, Wi-Fi, steering wheel audio controls, hands-free voice control, a heads-up display (HUD), an HMI display 634, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. The infotainment SoC 630 may further be used to provide information (e.g., visual and / or audible) to a user(s) of the vehicle, such as information from the ADAS system 638, autonomous driving information such as planned vehicle maneuvers, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0165] The infotainment SoC 630 may include GPU functionality. The infotainment SoC 630 may communicate with other devices, systems, and / or components of the vehicle 600 via the bus 602 (e.g., CAN bus, Ethernet, etc.). In some examples, the infotainment SoC 630 may be coupled to a supervisory MCU so that the infotainment system's GPU may perform some self-driving functions in the event that the primary controller(s) 636 (e.g., the primary and / or backup computers of the vehicle 600) fail). In such an example, the infotainment SoC 630 may place the vehicle 600 into a chauffeur-in-safe-stop mode, as described herein.

[0166] The vehicle 600 may further include an instrument cluster 632 (e.g., a digital instrument cluster, an electronic instrument cluster, a digital dashboard, etc.). The instrument cluster 632 may include a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). The instrument cluster 632 may include a set of instruments, such as a speedometer, fuel level, oil pressure, tachometer, odometer, turn signals, gear shift position indicator, seat belt warning light(s), parking brake warning light(s), engine failure light(s), airbag (SRS) system information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared on the infotainment SoC 630 and the instrument cluster 632. In other words, the instrument cluster 632 may be included as part of the infotainment SoC 630, or vice versa.

[0167] Fig. 6D is a system diagram for communication between one or more cloud-based servers and the example autonomous vehicle 600 of Fig. 6A, according to some embodiments of the present disclosure. The system 676 may include one or more servers 678, one or more networks 660, and vehicles, including the vehicle 600. The server(s) 678 may include a plurality of GPUs 684(A)-684(H) (collectively referred to herein as GPUs 684), PCIe switches 682(A)-682(H) (collectively referred to herein as PCIe switches 682), and / or CPUs 680(A)-680(B) (collectively referred to herein as CPUs 680). The GPUs 684, the CPUs 680, and the PCIe switches may be connected to high-speed interconnects, such as, without limitation, NVLink interfaces 688 developed by NVIDIA and / or PCIe interconnects 686. In some examples, the GPUs 684 are connected via NVLink and / or NVSwitch SoC, and the GPUs 684 and the PCIe switches 682 are connected via PCIe links.Although eight GPUs 684, two CPUs 680, and two PCIe switches are illustrated, this is not intended to be limiting. Depending on the embodiment, each of the server(s) 678 may include any number of GPUs 684, CPUs 680, and / or PCIe switches. For example, the server(s) 678 may include eight, sixteen, thirty-two, and / or more GPUs 684, respectively.

[0168] The server(s) 678 may receive, via the network(s) 660 and from the vehicles, image data representative of images depicting unexpected or changed road conditions, such as recently commenced roadwork. The server(s) 678 may transmit, via the network(s) 660 and to the vehicles, neural networks 662, updated neural networks 662, and / or map information 664, including information related to traffic and road conditions. The updates to the map information 664 may include updates to the HD map 622, such as information related to construction, potholes, detours, flooding, and / or other obstacles.In some examples, the neural networks 662, the updated neural networks 662, and / or the map information 664 may result from new training and / or experience represented in data received from any number of vehicles in the area and / or based on training performed in a data center (e.g., using the server(s) 678 and / or other servers).

[0169] The server(s) 678 may be used to train machine learning models (e.g., neural networks) based on training data. The training data may be generated by the vehicles and / or may be generated in a simulation (e.g., using a game engine). In some examples, the training data is labeled (e.g., where the neural network benefits from supervised learning) and / or subjected to other preprocessing, while in other examples, the training data is unlabeled and / or preprocessed (e.g., where the neural network does not require supervised learning).Training may be performed according to any one or more classes of machine learning techniques, including, without limitation, classes such as: supervised training, semi-supervised training, unsupervised training, self-learning, reinforcement learning, federated learning, transfer learning, feature learning (including principal component and cluster analysis), multilinear subspace learning, manifold learning, representation learning (including free dictionary learning), rule-based machine learning, anomaly detection, and any variations or combinations thereof. Once the machine learning models are trained, the machine learning models may be used by the vehicles (e.g., transmitted to the vehicles via the network(s) 660) and / or the machine learning models may be used by the server(s) 678 to remotely monitor the vehicles.

[0170] In some examples, the server(s) 678 may receive data from the vehicles and apply the data to real-time neural networks for intelligent real-time inference. The server(s) 678 may include deep learning supercomputers and / or dedicated AI computers powered by the GPU(s) 684, such as DGX and DGX Station machines developed by NVIDIA. However, in some examples, the server(s) 678 may include deep learning infrastructure using only CPU-powered data centers.

[0171] The deep learning infrastructure of server(s) 678 may be capable of rapid, real-time inference formation and may use this capability to evaluate and verify the health of the processors, software, and / or associated hardware in vehicle 600. For example, the deep learning infrastructure may receive periodic updates from vehicle 600, such as a sequence of images and / or objects that vehicle 600 has been located in that sequence of images (e.g., via computer vision and / or other machine learning object classification techniques).The deep learning infrastructure may run its own neural network to identify the objects and compare them to the objects identified by the vehicle 600, and if the results do not match and the infrastructure concludes that the AI ​​in the vehicle 600 is malfunctioning, the server(s) 678 may transmit a signal to the vehicle 600 instructing a fail-safe computer of the vehicle 600 to assume control, notify the passengers, and complete a safe parking maneuver.

[0172] For inference, the server(s) 678 may include the GPU(s) 684 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT). The combination of GPU-powered servers and inference acceleration may enable real-time responsiveness. In other examples, such as when performance is less critical, servers powered by CPUs, FPGAs, and other processors may be used for inference. Example computing device

[0173] Fig. 7 is a block diagram of exemplary computing device(s) 700 suitable for use in implementing some embodiments of the present disclosure. Computing device 700 may include an interconnect system 702 that directly or indirectly couples the following devices: memory 704, one or more central processing units (CPUs) 706, one or more graphics processing units (GPUs) 708, a communications interface 710, input / output (I / O) ports 712, input / output components 714, a power supply 716, one or more presentation components 718 (e.g., display(s)), and one or more logic units 720. In at least one embodiment, computing device(s) 700 may include one or more virtual machines (VMs), and / or any of the components thereof may include virtual components (e.g., virtual hardware components).For non-limiting examples, one or more of the GPUs 708 may include one or more vGPUs, one or more of the CPUs 706 may include one or more vCPUs, and / or one or more of the logic units 720 may include one or more virtual logic units. Accordingly, a computing device(s) 700 may include discrete components (e.g., an entire GPU dedicated to the computing device 700), virtual components (e.g., a portion of a GPU dedicated to the computing device 700), or a combination thereof.

[0174] Although the different blocks of Fig. 7 are shown as being connected with lines via the interconnect system 702, this is not intended to be limiting and is for clarity only. For example, in some embodiments, a presentation component 718, such as a display device, may be considered an I / O component 714 (e.g., if the display is a touchscreen). As another example, the CPUs 706 and / or GPUs 708 may include memory (e.g., memory 704 may be representative of a memory device in addition to the memory of the GPUs 708, the CPUs 706, and / or other components). In other words, the computing device of Fig. 7 is merely illustrative. No distinction is made between categories such as "workstation", "server", "laptop", "desktop", "tablet", "client device", "mobile device", "handheld device", "game console", "electronic control unit (ECU)", "virtual reality system" and / or other device or system types, since all fall within the scope of the computing device Fig. 7 should be taken into consideration.

[0175] The interconnect system 702 may represent one or more connections or buses, such as an address bus, a data bus, a control bus, or a combination thereof. The interconnect system 702 may include one or more bus or connection types, such as an industry standard architecture (ISA) bus, an extended industry standard architecture (EISA) bus, a video electronics standards association (VESA) bus, a peripheral component interconnect (PCI) bus, a peripheral component interconnect express (PCIe) bus, and / or another type of bus or connection. In some embodiments, there are direct connections between components. As one example, the CPU 706 may be directly connected to the memory 704. Further, the CPU 706 may be directly connected to the GPU 708. If there is a direct or point-to-point connection between components, the interconnect system 702 may include a PCIe connection to implement the connection.In these examples, a PCI bus need not be included in the computing device 700.

[0176] Storage 704 may include any of a variety of computer-readable media. The computer-readable media may be any available media accessible by the computing device 700. The computer-readable media may include both volatile and non-volatile media, as well as removable and non-removable media. By way of example and not limitation, the computer-readable media may include computer storage media and communication media.

[0177] The computer storage media may include both volatile and non-volatile media and / or removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, and / or other data types. For example, memory 704 may store computer-readable instructions (e.g., representing a program(s) and / or a program element(s)), such as an operating system.Computer storage media may include, but is not limited to, RAM, ROM, EEPROM, flash memory or other storage technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and that can be accessed by the computing device 700. As used herein, computer storage media does not include signals per se.

[0178] The computer storage media may embody computer-readable instructions, data structures, program modules, and / or other data types in a modulated data signal, such as a carrier wave or other transport mechanism, and include any information transmission media. The term "modulated data signal" may refer to a signal having one or more of its properties adjusted or altered in such a way as to encode information in the signal. By way of example and not limitation, the computer storage media may include wired media, such as a wired network or a direct-wired connection, and wireless media, such as acoustic, RF, infrared, and other wireless media. Combinations of any of the foregoing should also be included within the scope of computer-readable media.

[0179] The CPU(s) 706 may be configured to execute at least some of the computer-readable instructions to control one or more components of the computing device 700 to perform one or more of the methods and / or processes described herein. The CPU(s) 706 may each include one or more cores (e.g., one, two, four, eight, twenty-eight, seventy-two, etc.) capable of handling a plurality of software threads concurrently. The CPU(s) 706 may include any type of processor and may include different types of processors depending on the type of computing device 700 implemented (e.g., processors with fewer cores for mobile devices and processors with more cores for servers).For example, depending on the type of computing device 700, the processor may be an advanced RISC machine (ARM) processor implemented using reduced instruction set computing (RISC) or an x86 processor implemented using complex instruction set computing (CISC). Computing device 700 may include one or more CPUs 706 in addition to one or more microprocessors or supplemental coprocessors, such as math coprocessors.

[0180] In addition to or alternatively to the CPU(s) 706, the GPU(s) 708 may be configured to execute at least some of the computer-readable instructions to control one or more components of the computing device 700 to perform one or more of the methods and / or processes described herein. One or more of the GPU(s) 708 may be an integrated GPU (e.g., with one or more of the CPU(s) 706) and / or one or more of the GPU(s) 708 may be a discrete GPU. In embodiments, one or more of the GPU(s) 708 may be a coprocessor of one or more of the CPU(s) 706. The GPU(s) 708 may be used by the computing device 700 to render graphics (e.g., 3D graphics) or to perform general purpose computations. For example, the GPU(s) 708 can be used for general purpose computing on GPUs (GPGPU).The GPU(s) 708 may include hundreds or thousands of cores capable of handling hundreds or thousands of software threads simultaneously. The GPU(s) 708 may generate pixel data for output images in response to rendering commands (e.g., rendering commands from the CPU(s) 706 received via a host interface). The GPU(s) 708 may include graphics memory, such as display memory, for storing pixel data or any other suitable data, such as GPGPU data. The display memory may be included as part of the memory 704. The GPU(s) 708 may include two or more GPUs operating in parallel (e.g., via an interconnect). The interconnect may connect the GPUs directly (e.g., using NVLINK) or may connect the GPUs through a switch (e.g., using NVSwitch).When combined, each GPU can generate 708 pixel data or GPGPU data for different parts of an output or for different outputs (e.g., a first GPU for a first image and a second GPU for a second image). Each GPU can contain its own memory or can share memory with other GPUs.

[0181] In addition to or alternatively to the CPU(s) 706 and / or the GPU(s) 708, the logic unit(s) 720 may be configured to execute at least some of the computer-readable instructions to control one or more components of the computing device 700 to perform one or more of the methods and / or processes described herein. In embodiments, the CPU(s) 706, the GPU(s) 708, and / or the logic unit(s) 720 may discretely or jointly perform any combination of the methods, processes, and / or portions thereof. One or more of the logic units 720 may be part of and / or integrated with one or more of the CPU(s) 706 and / or the GPU(s) 708, and / or one or more of the logic units 720 may be discrete components or otherwise external to the CPU(s) 706 and / or the GPU(s) 708.In embodiments, one or more of the logic units 720 may be a coprocessor of one or more of the CPU(s) 706 and / or one or more of the GPU(s) 708.

[0182] Examples of the logic unit(s) 720 include one or more processing cores and / or components thereof, such as data processing units (DPUs), tensor cores (TCs), tensor processing units (TPUs), visual pixel cores (PVCs), vision processing units (VPUs), graphics processing clusters (GPCs), texture processing clusters (TPCs), streaming multiprocessors (SMs), tree traversal units (TTUs), artificial intelligence accelerators (AIAs), deep learning accelerators (DLAs), arithmetic logic units (ALUs), application-specific integrated circuits (ASICs), floating-point units (FPUs), input / output (I / O) elements, peripheral component interconnect (PCI) or peripheral component interconnect express (PCIe) elements, and / or the like.

[0183] The communication interface 710 may include one or more receivers, transmitters, and / or transceivers that enable the computing device 700 to communicate with other computing devices over an electronic communication network, including wired and / or wireless communication. The communication interface 710 may include components and functionality for enabling communication over any of a number of different networks, such as wireless networks (e.g., Wi-Fi, Z-Wave, Bluetooth, Bluetooth LE, ZigBee, etc.), wired networks (e.g., communicating over Ethernet or InfiniBand), low-power wide area networks (e.g., LoRaWAN, SigFox, etc.), and / or the Internet.In one or more embodiments, the logic unit(s) 720 and / or the communication interface 710 may include one or more data processing units (DPUs) for transferring data received over a network and / or through the interconnect system 702 directly to (e.g., a memory of) one or more GPU(s) 708.

[0184] The I / O ports 712 may enable the computing device 700 to be logically coupled to other devices, including the I / O components 714, the presentation component(s) 718, and / or other components, some of which may be built into (e.g., integrated) the computing device 700. Illustrative I / O components 714 include a microphone, a mouse, a keyboard, a joystick, a game pad, a game controller, a satellite dish, a scanner, a printer, a wireless device, etc. The I / O components 714 may provide a natural user interface (NUI) that processes air gestures, speech, or other physiological inputs generated by a user. In some cases, inputs may be transmitted to a suitable network element for further processing.An NUI may implement any combination of speech recognition, stylus recognition, facial recognition, biometric recognition, both on-screen and off-screen gesture recognition, air gestures, head and eye tracking, and touch detection (as described in more detail below) associated with a display of the computing device 700. The computing device 700 may include depth cameras, such as stereoscopic camera systems, infrared camera systems, RGB camera systems, touchscreen technology, and combinations thereof for gesture detection and recognition. Additionally, the computing device 700 may include accelerometers or gyroscopes (e.g., as part of an inertial measurement unit (IMU)) that enable the detection of motion. In some examples, the output of the accelerometers or gyroscopes may be used by the computing device 700 to render immersive augmented reality or virtual reality.

[0185] The power supply 716 may include a hardwired power supply, a battery power supply, or a combination thereof. The power supply 716 may provide power to the computing device 700 to enable the components of the computing device 700 to function.

[0186] The presentation component(s) 718 may include a display (e.g., a monitor, a touchscreen, a television monitor, a heads-up display (HUD), other display types, or a combination thereof), speakers, and / or other presentation components. The presentation component(s) 718 may receive data from other components (e.g., the GPU(s) 708, the CPU(s) 706, DPUs, etc.) and output the data (e.g., as an image, video, audio, etc.). Example data center

[0187] Fig. Figure 8 illustrates an exemplary data center 800 that may be used in at least one embodiment of the present disclosure. Data center 800 may include a data center infrastructure layer 810, a framework layer 820, a software layer 830, and / or an application layer 840.

[0188] As in Fig. 8, the data center infrastructure layer 810 may include a resource orchestrator 812, clustered compute resources 814, and node compute resources ("node CRs") 816(1)-816(N), where "N" represents any whole positive integer. In at least one embodiment, the node CRs 816(1)-816(N) may include, but are not limited to, any number of central processing units (CPUs) or other processors (including DPUs, accelerators, field-programmable gate arrays (FPGAs), graphics processors or graphics processing units (GPUs), etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state or disk drives), network input / output (NW I / O) devices, network switches, virtual machines (VMs), power modules, and / or cooling modules, etc. In some embodiments, one or more Node CRs may be selected from the Node CRs 816(1)-816(N) may correspond to a server having one or more of the above-mentioned computing resources. Additionally, in some embodiments, the node CRs 816(1)-816(N) may include one or more virtual components, such as vGPUs, vCPUs, and / or the like, and / or one or more of the node CRs 816(1)-816(N) may correspond to a virtual machine (VM).

[0189] In at least one embodiment, the grouped computing resources 814 may include separate groupings of node CRs 816 housed in one or more racks (not shown) or multiple racks housed in data centers in different geographic locations (also not shown). Separate groupings of node CRs 816 within the grouped computing resources 814 may include grouped computing, networking, storage, or memory resources that may be configured or assigned to support one or more workloads. In at least one embodiment, multiple node CRs 816, including CPUs, GPUs, DPUs, and / or other processors, may be grouped in one or more racks to provide computing resources to support one or more workloads.The one or more racks may also contain any number of power modules, cooling modules, and / or network switches in any combination.

[0190] The resource orchestrator 812 may configure or otherwise control one or more node CRs 816(1)-816(N) and / or grouped computing resources 814. In at least one embodiment, the resource orchestrator 812 may include a software design infrastructure (SDI) management entity for the data center 800. The resource orchestrator 812 may include hardware, software, or a combination thereof.

[0191] In at least one embodiment, as in Fig. 8, the framework layer 820 may include a job scheduler 833, a configuration manager 834, a resource manager 836, and / or a distributed file system 838. The framework layer 820 may include a framework to support software 832 of the software layer 830 and / or one or more applications 842 of the application layer 840. The software 832 or application(s) 842 may each include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. The framework layer 820 may be some type of free and open source software web application framework, such as, but not limited to, Apache Spark™ (hereinafter "Spark"), which may utilize the distributed file system 838 for large-scale data processing (e.g., "Big Data").In at least one embodiment, the job scheduler 833 may include a Spark driver to enable scheduling of workloads supported by various layers of the data center 800. The configuration manager 834 may be capable of configuring various layers, such as the software layer 830 and the framework layer 820, which include Spark and the distributed file system 838, to support large-scale computing. The resource manager 836 may be capable of managing clustered or grouped computing resources mapped to or allocated to support the distributed file system 838 and the job scheduler 833. In at least one embodiment, clustered or grouped computing resources may include the clustered computing resource 814 in the data center infrastructure layer 810.The resource manager 836 may coordinate with the resource orchestrator 812 to manage these mapped or allocated computing resources.

[0192] In at least one embodiment, the software 832 included in the software layer 830 may include software used by at least portions of the node CRs 816(1)-816(N), the clustered computing resources 814, and / or the distributed file system 838 of the framework layer 820. One or more types of software may include, among others, internet website search software, email virus scanning software, database software, and streaming video content software.

[0193] In at least one embodiment, the application(s) 842 included in the application layer 840 may include one or more types of applications used by at least portions of the node CRs 816(1)-816(N), the clustered computing resources 814, and / or the distributed file system 838 of the framework layer 820. One or more types of applications may include any number of a genomic application, a cognitive computing application, and a machine learning application, including, but not limited to, training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), and / or other machine learning applications used in connection with one or more embodiments.

[0194] In at least one embodiment, any of the configuration manager 834, the resource manager 836, and the resource orchestrator 812 may implement any number and type of self-modifying actions based on any amount and type of data collected in any technically feasible manner. Self-modifying actions may relieve a data center operator of the data center 800 from making potentially poor configuration decisions and potentially avoid underutilized and / or poorly performing portions of a data center.

[0195] Data center 800 may include tools, services, software, or other resources to train one or more machine learning models or to predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, machine learning model(s) may be trained by calculating weight parameters according to a neural network architecture using software and / or computational resources described above with respect to data center 800.In at least one embodiment, trained or deployed machine learning models corresponding to one or more neural networks may be used to infer or predict information using resources described above with respect to data center 800 by using weight parameters calculated by one or more training techniques, such as, but not limited to, those described herein.

[0196] In at least one embodiment, the data center 800 may utilize CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, and / or other hardware (or virtual computing resources corresponding thereto) to perform training and / or inference using resources described above. Furthermore, one or more of the software and / or hardware resources described above may be configured as a service to enable users to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services. Example network environments

[0197] Network environments suitable for use in implementing embodiments of the disclosure may include one or more client devices, servers, network-attached storage (NAS), other backend devices, and / or other device types. The client devices, servers, and / or other device types (e.g., each device) may be based on one or more instances of the computing device(s) 700 of Fig. 7 - e.g., each device may include similar components, features, and / or functionality of the computing device(s) 700. Additionally, if backend devices (e.g., servers, NAS, etc.) are implemented, the backend devices may be included as part of a data center 800, an example of which is described herein with respect to Fig. 8 is described in more detail.

[0198] Components of a network environment can communicate with each other over one or more networks, which can be wired, wireless, or both. The network can include multiple networks or a network of networks. For example, the network can include one or more wide area networks (WANs), one or more local area networks (LANs), one or more public networks such as the Internet and / or a public switched telephone network (PSTN), and / or one or more private networks. If the network includes a wireless telecommunications network, components such as a base station, a communications tower, or even access points (as well as other components) can provide wireless connectivity.

[0199] Compatible network environments may include one or more peer-to-peer network environments—in which case, a server may not be included in a network environment—and one or more client-server network environments—in which case, one or more servers may be included in a network environment. In peer-to-peer network environments, the functionality described herein with respect to one or more servers may be implemented on any number of client devices.

[0200] In at least one embodiment, a network environment may include one or more cloud-based network environments, a distributed computing environment, a combination thereof, etc. A cloud-based network environment may include a framework layer, a job scheduler, a resource manager, and a distributed file system implemented on one or more servers, which may include one or more core network servers and / or edge servers. A framework layer may include a framework to support software of a software layer and / or one or more applications of an application layer. The software or application(s) may each include web-based service software or applications. In embodiments, one or more of the client devices may use the web-based service software or applications (e.g.,by accessing the service software and / or applications through one or more application programming interfaces (APIs). The framework layer may be some type of free and open-source software web application framework, such as, but not limited to, a distributed file system for large-scale data processing (e.g., "Big Data").

[0201] A cloud-based network environment may provide cloud computing and / or cloud storage performing any combination of computing and / or data storage functions (or one or more portions thereof) described herein. Each of these various functions may be distributed across multiple locations of central or core servers (e.g., one or more data centers that may be distributed across a state, region, country, globe, etc.). When a connection to a user (e.g., a client device) is relatively close to one or more edge servers, one or more core servers may designate at least a portion of the functionality for the edge server(s). A cloud-based network environment may be private (e.g., limited to a single organization), public (e.g., available to many organizations), and / or a combination thereof (e.g., a hybrid cloud environment).

[0202] The client device(s) may include at least some of the components, features, and functionality of the devices described herein with respect to Fig.7, exemplary computing device(s) 700 described.By way of example, and not limitation, a client device may be embodied as a personal computer (PC), a laptop, a mobile device, a smartphone, a tablet computer, a smartwatch, a wearable computer, a personal digital assistant (PDA), an MP3 player, a virtual reality headset, a global positioning system (GPS) or device, a video player, a video camera, a surveillance device or system, a vehicle, a boat, a flying vessel, a virtual machine, a drone, a robot, a handheld communication device, a hospital device, a gaming device or system, an entertainment system, a vehicle computing system, an embedded system controller, a remote controller, an appliance, a consumer electronics device, a workstation, an edge device, any combination of these delineated devices, or any other suitable device.

[0203] The disclosure may be described in the general context of computer code or machine-usable instructions, including computer-executable instructions, such as program modules, executed by a computer or other machine, such as a personal data assistant or other handheld device. In general, program modules, including routines, programs, objects, components, data structures, etc., refer to code that performs specific tasks or implements specific abstract data types. The disclosure may be implemented in a variety of system configurations, including handheld devices, consumer electronics, general-purpose computers, specialized computing devices, etc. The disclosure may also be implemented in distributed computing environments where tasks are performed by remote processing devices connected by a communications network.

[0204] As used herein, a recitation of "and / or" with reference to two or more elements should be interpreted to mean only one element or a combination of elements. For example, "Element A, Element B, and / or Element C" may include only Element A, only Element B, only Element C, Element A and Element B, Element A and Element C, Element B and Element C, or Elements A, B, and C. Additionally, "at least one of Element A or Element B" may include at least one of Element A, at least one of Element B, or at least one of Element A and at least one of Element B. Further, "at least one of Element A and Element B" may include at least one of Element A, at least one of Element B, or at least one of Element A and at least one of Element B.

[0205] The subject matter of the present disclosure is specifically described herein to satisfy legal requirements. However, the description itself is not intended to limit the scope of this disclosure. Rather, the inventors have contemplated that the claimed subject matter may be embodied in other ways to include various steps or combinations of steps similar to those described herein, in conjunction with other present or future technologies. Furthermore, although the terms "step" and / or "block" may be used herein to refer to various elements of methods employed, the terms should not be interpreted to imply any particular ordering between or among different steps disclosed herein, unless and until the order of individual steps is explicitly described. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 16 / 101,232

[0108] Cited non-patent literature

[0000] Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (Standard No. J3016-201806, published on 15 June 2018, Standard No. J3016-201606, published on 30 September 2016

[0066]

Claims

[1] Method comprising: Receiving one or more sampled sets of correlated timestamps, including one or more first timestamps related to one or more first clock sources and one or more second timestamps related to one or more second clock sources; Calculating, using the one or more sampled sets of correlated timestamps, one or more offsets between the one or more first clock sources and the one or more second clock sources; translating, using the one or more offsets, one or more timestamps of one or more sensor measurements into a reference time range; and Performing one or more operations for a machine using the one or more sensor measurements and the one or more timestamps translated into the reference time domain. [2] The method of claim 1, further comprising frequency locking the one or more first clock sources to the one or more second clock sources, wherein the one or more sampled sets of correlated timestamps are generated based on at least the frequency locking. [3] The method of claim 1, wherein calculating the one or more offsets includes calculating one or more differences between the correlated timestamps within at least one of the one or more sampled sets of correlated timestamps. [4] The method of claim 1, wherein the one or more sampled sets of correlated timestamps include a plurality of sampled sets of correlated timestamps, and translating is based at least on calculating one or more rates of change for the one or more first clock sources and the one or more second clock sources using the plurality of sampled sets of correlated timestamps. [5] The method of claim 1, wherein the one or more first clock sources include a time stamp counter (TSC) clock source, the one or more second clock sources include a pulse-per-second hardware clock (PHC) clock source, and the reference time domain includes a system time domain. [6] The method of claim 1, wherein translating is responsive to receiving the one or more timestamps from one or more sensor drivers corresponding to the one or more sensor measurements. [7] The method of claim 1, further comprising synchronizing the one or more first clock sources and the one or more second clock sources using one or more real-time hardware clock (RTC) clock sources based on at least one boot sequence corresponding to the machine. [8] System comprising: one or more processing units for performing operations, including: Performing one or more operations for a machine based on at least one or more sensor measurements and one or more timestamps translated into a reference time domain, wherein the one or more timestamps are translated using one or more offsets between a plurality of clock sources, wherein the one or more offsets are calculated using one or more sets of correlated samples of the plurality of clock sources. [9] The system of claim 8, wherein the one or more sets of correlated samples are generated based on at least frequency locking of the plurality of clock sources. [10] The system of claim 8, wherein the one or more offsets are calculated based on at least calculating one or more differences between the correlated samples within at least one of the one or more sets of correlated samples. [11] The system of claim 8, wherein the one or more sets of correlated samples include a plurality of sampled sets of correlated timestamps, and translating is based at least on calculating one or more rates of change for the plurality of clock sources using the plurality of sampled sets of correlated timestamps. [12] The system of claim 8, wherein the plurality of clock sources include a time stamp counter (TSC) clock source and a pulse-per-second hardware clock (PHC) clock source. [13] The system of claim 8, wherein the one or more timestamps are translated in response to receiving the one or more timestamps from one or more sensor drivers corresponding to the one or more sensor measurements. [14] The system of claim 8, wherein the system comprises at least one of the following: a control system for an autonomous or semi-autonomous machine; a perception system for an autonomous or semi-autonomous machine; a system for performing simulation operations; a system for performing digital twin operations; a system for performing light transport simulation; a system for performing collaborative content creation for 3D assets; a system for performing deep learning operations; a system implemented using an edge device; a system implemented using a robot; a system for performing generative AI operations; a system for performing operations using a large language model; a system for performing conversational AI operations; a system for generating synthetic data; a system for displaying at least one of virtual reality content, augmented reality content, or mixed reality content; a system that contains one or more virtual machines (VMs); a system that is at least partially implemented in a data center; or a system implemented at least in part using cloud computing resources. [15] Processor comprising: one or more circuits: sampling a plurality of clock sources to generate one or more sets of correlated samples of the plurality of clock sources; Calculating, using the one or more sets of correlated samples, one or more offsets between the plurality of clock sources; Converting, using the one or more offsets, time data for one or more sensor measurements into a reference time range; and Performing one or more operations for a machine using the one or more sensor measurements and the time data converted to the reference time domain. [16] The processor of claim 15, wherein the one or more sets of correlated samples are generated based on at least frequency locking of the plurality of clock sources. [17] The processor of claim 15, wherein the calculating is based at least on calculating one or more differences between the correlated samples within at least one of the one or more sets of correlated samples. [18] The processor of claim 15, wherein the one or more sets of correlated samples include a plurality of sampled sets of correlated timestamps, and the converting is based at least on calculating one or more rates of change for the plurality of clock sources using the plurality of sampled sets of correlated timestamps. [19] The processor of claim 15, wherein the plurality of clock sources include a timestamp counter (TSC) clock source and a pulse-per-second hardware clock (PHC) clock source. [20] The processor of claim 15, wherein the processor is comprised in at least one of the following: a control system for an autonomous or semi-autonomous machine; a perception system for an autonomous or semi-autonomous machine; a system for performing simulation operations; a system for performing digital twin operations; a system for performing light transport simulation; a system for performing collaborative content creation for 3D assets; a system for performing generative AI operations; a system for performing operations using a large language model; a system for performing deep learning operations; a system implemented using an edge device; a system implemented using a robot; a system for performing conversational AI operations; a system for generating synthetic data; a system for displaying at least one of virtual reality content, augmented reality content, or mixed reality content; a system that contains one or more virtual machines (VMs); a system that is at least partially implemented in a data center; or a system implemented at least in part using cloud computing resources.

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