DISPLAY DEVICE THAT FEATURES A PIXEL CIRCUIT

Abstract

A display device (100) comprises: a mode control device configured to generate a first control signal (S(k)) and a second control signal (P(k)), a gate driver circuit (GD) configured to generate a light emission signal (EM(N)), a first scan signal (Scan(N)) and a second scan signal (Scan(N-1)), a common circuit (701) connected to a reference voltage line (711) configured to provide a reference voltage (Vref), the common circuit (701) comprising: a first transistor (T1) configured to operate based on the first scan signal (Scan(N)), and a second transistor (T2) connected in series with the first transistor (T1) and configured to operate based on the second scan signal (Scan(N-1)), and a first pixel circuit (702).which is connected to the mode control device and the gate driver circuit (GD), wherein the first pixel circuit (702) comprises: a driver transistor (DT), a third transistor (T3) configured to operate based on the light emission signal (EM(N)) and connected to the second transistor (T2), a fourth first transistor (T41) configured to operate based on the first control signal (S(k)), a fourth second transistor (T42) configured to operate based on the second control signal (P(k)), a first light emission element (ED1) connected to the fourth first transistor (T42), a second light emission element (ED2) connected to the fourth second transistor (T42), and a capacitor (Cst) connected to the first transistor (T1), the second transistor (T2), the third transistor (T3), and the driver transistor (DT).

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to Korean Patent Application No. 10-2023-0085177, filed on June 30, 2023. BACKGROUNDArea of ​​Revelation

[0002] The present disclosure relates to a display device having a pixel circuit. Description of the background

[0003] Display devices include organic light-emitting diodes (OLEDs) configured to emit light autonomously. These display devices are widely used because of their high response speed, high luminous efficiency, high brightness, and wide viewing angle. The display device adjusts the organic light-emitting element by adjusting the gradation of pixels arranged in a matrix according to the video data. The pixel may include a pixel circuit, and various voltages can be input to the pixel circuit to drive the pixel.

[0004] The voltage input to the pixel circuit forms a path for an electric current in the pixel circuit. In some cases, various situations may occur on the path of the electric current flow, such as leakage of the electric current. For example, a reference voltage in the pixel circuit may be provided to a light-emitting element via a switching transistor connected to an anode of the light-emitting element. In this case, a range of a voltage that can be used as a reference voltage can be restricted to suppress leakage current to the light-emitting element. The expression quality of black gradation can be improved as the usable range of the reference voltage increases. Accordingly, there is a need for a solution for suppressing leakage current to the light-emitting element while improving the usable range of the reference voltage. OVERVIEW

[0005] Accordingly, the present disclosure is directed to a display device having a pixel circuit that substantially obviates one or more of the problems due to the limitations and disadvantages described above.

[0006] More specifically, the present disclosure is intended to provide a display device that can use a common circuit to enlarge a usable range of a reference voltage and minimize a leakage current to a light emitting element.

[0007] The present disclosure is not limited to the above-mentioned, and other features not mentioned above can be clearly understood by those skilled in the art from the following descriptions.

[0008] Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the disclosure. Other advantages of the present disclosure will be realized and attained by the structure particularly pointed out in the written description and claims as well as the accompanying drawings.

[0009] To achieve these and other advantages, and in accordance with the present disclosure, as embodied and broadly described, a display device according to claim 1 and a display device according to claim 16 are provided. Further embodiments are described in the subclaims. In one aspect of the present disclosure, a display device comprises: a mode controller configured to generate a first control signal and a second control signal, a gate driver circuit configured to generate a light emission signal, a first scan signal, and a second scan signal, a common circuit connected to a reference voltage line configured to provide a reference voltage, the common circuit comprising: a first transistor configured to operate based on the first scan signal, and a second transistor,which is connected in series with the first transistor and configured to operate based on the second scan signal, and a first pixel circuit connected to the mode controller and the gate driver circuit, the first pixel circuit comprising: a driver transistor, a third transistor configured to operate based on the light emission signal and connected to the second transistor, a fourth first transistor configured to operate based on the first control signal, a fourth second transistor configured to operate based on the second control signal, a first light emission element connected to the fourth first transistor, a second light emission element connected to the fourth second transistor, and a capacitor connected to the first transistor, the second transistor,the third transistor and the driver transistor.,

[0010] In another aspect of the present disclosure, a display device comprises: a common circuit providing a reference voltage Vref, configured to operate based on a first scan signal and a second scan signal, and having a first node N1; and first, second, and third pixel circuits electrically connected to the common circuit, wherein the second pixel circuit is adjacent to at least one of the first and third pixel circuits and has at least two light-emitting elements configured to emit light of a different color than the light emitted by the first and second light-emitting elements of the first pixel circuit, wherein the third pixel circuit is adjacent to at least one of the first and second pixel circuits and has at least two light-emitting elements configured to emit light of a different color than light,emitted by a first and second light-emitting element of the first pixel circuit and a first and second light-emitting element of the second pixel circuit, and wherein the common circuit and the first, second, and third pixel circuits are electrically connected via the first node N1 to receive at least one of the reference voltage Vref, a high-potential voltage VDD, a low-potential voltage VSS, a light-emitting signal EM(N), a data voltage Vdata, and an initialization voltage Vini.

[0011] Further details on the exemplary aspects are shown in the detailed description and drawings.

[0012] According to the display device of the present disclosure, it is possible to provide the reference voltage using the common circuit, thereby increasing the usable range of the reference voltage and minimizing a leakage current to the light emitting element.

[0013] The effects according to the present disclosure are not limited to the contents exemplified above, and the present disclosure has other various effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a view showing an example of a display device according to an aspect of the present disclosure; Fig. 2 is a functional block diagram of the display device according to the aspect of the present disclosure; Fig. 3 is a view showing an example of a pixel circuit of the display device according to the aspect of the present disclosure; Fig. 4 is a view showing an example of the arrangement of lenses included in the display device according to the aspect of the present disclosure; Fig. 5 is a view showing an example of a cross section along the line II' in Fig. 4 shows; Fig. 6 is a view showing an example of a cross-section along the line II-II' in Fig. 4 shows; Fig. 7 is a view showing a common circuit and the pixel circuit of the display device according to the aspect of the present disclosure; Fig. 8 is a view showing an implementation example of the common circuit and the pixel circuit of the display device according to the aspect of the present disclosure; Fig. 9 is a view for explaining signal timing of the display device according to the aspect of the present disclosure; Fig. 10 is a view for explaining an operation of the pixel circuit in an initialization section of the display device according to the aspect of the present disclosure; Fig. 11 is a view for explaining an operation of the pixel circuit in a scanning section of the display device according to the aspect of the present disclosure; Fig. 12 and Fig. 13 are views for explaining an operation of the pixel circuit in a light emitting section of the display device according to the aspect of the present disclosure; Fig. 14 is a view showing a common circuit and a pixel circuit of a display device according to another aspect of the present disclosure; and Fig. 15 is a view showing a common circuit and a pixel circuit of a display device according to another aspect of the present disclosure. DETAILED DESCRIPTION

[0015] Advantages and features of the present disclosure, and a method for achieving the advantages and features, will become apparent by reference to exemplary aspects described in detail below together with the accompanying drawings. However, the present disclosure is not limited to the exemplary aspects disclosed herein, but may be embodied in various forms. The exemplary aspects are provided by way of example only so that those skilled in the art can fully understand the spirit and scope of the present disclosure. Therefore, the present disclosure is defined only by the scope of the appended claims.

[0016] The shapes, sizes, ratios, angles, numbers, and the like shown in the accompanying drawings to describe the exemplary aspects of the present disclosure are merely examples, and the present disclosure is not limited thereto. Like reference numerals generally designate like elements throughout the disclosure. Furthermore, in the following description of the present disclosure, detailed explanation of known related technologies may be omitted in order not to unnecessarily obscure the subject matter of the present disclosure. The terms "including," "having," and "formed of" as used herein are generally understood to include other components unless the terms are used with the term "only." Any reference to the singular form may include the plural form unless expressly stated otherwise.

[0017] In describing components of the exemplary aspect of the present disclosure, terms such as first, second, A, B, (a), (b), and the like may be used. These terms are used to distinguish one component from another component, but the type, order, or number of components is not limited by the terms. When a component is "linked," "coupled," or "connected" to another component, the component may be directly linked or connected to the other component. However, unless expressly stated otherwise, it is understood that a third component may be disposed between the components and may be indirectly connected or connected.

[0018] When the positional relationship between two parts is described with terms such as "on", "above", "below" and "next to", one or more parts may be located between the two parts unless the terms are used with the term "immediate" or "direct".

[0019] Although the terms "first," "second," and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from the other components. Therefore, a first component mentioned below may be a second component in a technical concept of the present disclosure.

[0020] The features of various aspects of the present disclosure may be partially or fully interconnected or combined with each other and may interact and operate in technically different ways, and the aspects may be practiced independently of each other or in conjunction with each other.

[0021] The following aspects are described with a focus on the organic light-emitting display device. However, the aspects of the present disclosure are not limited to organic light-emitting display devices and can be applied to various electroluminescent displays. For example, the electroluminescent display device can use an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode display device, or an inorganic light-emitting diode display device.

[0022] Hereinafter, exemplary aspects of the present disclosure will be described in detail with reference to the accompanying drawings.

[0023] Fig. 1 is a view showing an example of a display device according to an aspect of the present disclosure.

[0024] In this aspect, a display device 100 may be disposed on at least a portion of a vehicle's dashboard. The vehicle's dashboard has a configuration disposed at a front side of a front seat (e.g., a driver's seat or a passenger seat) of the vehicle. For example, the vehicle's dashboard may be equipped with an input configuration for operating various functions (e.g., an air conditioning system, an audio system, and a navigation system) in the vehicle.

[0025] In this aspect, the display device 100 may be disposed on the dashboard of the vehicle and function as an input for operating at least some of the various functions of the vehicle. The display device 100 may provide various types of information related to the vehicle, such as driving information of the vehicle (e.g., a current speed of the vehicle, a remaining amount of fuel, and a traveled distance) and information about components of the vehicle (e.g., a degree of damage to a vehicle tire).

[0026] In this aspect, the display device 100 may be arranged transversely to the driver's seat and the passenger's seat, which are arranged as the front seats of the vehicle. Users of the display device 100 may include a driver of the vehicle and a passenger in the passenger seat. Both the driver and the passenger in the vehicle may use the display device 100.

[0027] In the aspect, only a part of the display device 100 may be Fig. 1. The Fig. The display device 100 shown in Figure 1 may be represented as a display panel among various components included in the display device 100. For example, the display panel shown in Fig. 6 may be represented as at least a part of a display area and at least a part of a non-display area of ​​the display panel. The components that form the Fig. 1 among the components of the display device 100 may be mounted in the vehicle (or at least a part of the vehicle).

[0028] Fig. 2 is a functional block diagram of the display device according to the aspect of the present disclosure.

[0029] An electroluminescent display device may be used as the display device according to the aspect of the present disclosure. An organic light-emitting diode display device, a quantum dot light-emitting diode display device, or an inorganic light-emitting diode display device may be used as the electroluminescent display device.

[0030] With reference to Fig. 2, the display device may include a display panel DP, a data driver (or data driver circuit) DD, a gate driver (or gate driver circuit) GD, a timer controller TC, and a power source unit PU.

[0031] In this aspect, the display panel DP can generate an image to be provided to the user. For example, the display panel DP can generate and display an image to be provided to the user via a pixel area PA in which a pixel circuit is arranged.

[0032] The data driver DD, the gate driver GD, the timing controller TC, and the power source unit PU can provide signals for operating the pixel areas PA via signal lines. The signal lines can include, for example, data lines DL, gate lines GL, and power supply lines PL, which are arranged in Fig. 3 are shown.

[0033] For example, the data driver DD can be connected to the data lines DL in Fig. 3 Apply data signals to the pixel areas PA, the gate driver GD can apply gate signals to the pixel areas PA via the gate lines GL, and the power source unit PU can apply supply voltages to the pixel areas PA via the supply voltage supply lines PL.

[0034] The timing controller TC can control the data driver DD and the gate driver GD. For example, the timing controller TC can adapt digital video data input from the outside to the resolution of the display panel DP and supply the video data to the data driver DD.

[0035] The data driver DD can convert digital video data input from the timing controller TC into analog data voltages in response to the data control signal and supply the analog data voltages to the plurality of data lines.

[0036] The gate driver GD can generate a scan signal and a light emission signal (or a light emission control signal) in response to the gate control signal. The gate driver GD can include a scan signal driving part and a light emission signal driving part. The scan driver part can generate scan signals in a row-sequential manner to drive at least one scan line connected to each pixel row and supply the scan signals to the scan lines. The light emission signal driving part can generate light emission signals in a row-sequential manner to drive at least one light emission signal line connected to each pixel row and supply the light emission signals to the light emission signal lines.

[0037] The gate driver (or gate driver circuit) GD can generate multiple scan signals and a light emission signal. For example, the gate driver GD can generate a first scan signal (e.g., a first scan signal Scan(N) in Fig. 7), a second scan signal (e.g. a second scan signal Scan(N-1) in Fig. 7) and a light emission signal (e.g. a light emission signal EM(N) in Fig. 7) generate.

[0038] According to the aspect, the gate driver GD can be arranged on the display panel DP in a gate driver-in-panel (GIP) manner. For example, the gate driver GD can be divided into multiple gate drivers and arranged on at least two side surfaces of the display panel DP.

[0039] A display area AA of the display panel DP can have several pixel areas (or pixels or pixel circuits) PA. In the pixel areas PA, the several data lines (e.g., the data lines DL in Fig. 3) and the multiple gate lines (e.g. the gate lines GL in Fig. 3), and subpixels may be arranged in each intersection region. The subpixels included in a pixel region PA may emit light of different colors. For example, the pixel region PA may emit blue, red, and green using three subpixels. However, the present disclosure is not limited to this. In some cases, the pixel region PA may further include a subpixel to implement a specific color (e.g., white).

[0040] In the pixel area PA, the area for implementing blue may be called a blue subpixel area, an area for implementing red may be called a red subpixel area, and an area for implementing green may be called a green subpixel area.

[0041] In this aspect, the pixel region PA may include a plurality of subpixels. The plurality of subpixels may each be divided into a first and a second lens region that provide different viewing angles. For example, the pixel region PA may include: a first lens region configured to define a first viewing angle by providing light within a first region, and a second lens region configured to define a second viewing angle by providing light within a second region. The first region may be an area larger than the second region.

[0042] A non-display area BZ may be arranged along a periphery of the display area AA. Various components for operating the pixel circuitry arranged in the pixel area PA may be arranged in the non-display area BZ. For example, at least part of the gate driver circuit GD may be arranged in the non-display area BZ. The non-display area BZ may be referred to as an aperture area.

[0043] Fig. Figure 3 shows an example of the pixel circuit of the display device according to the aspect of the present disclosure. The pixel region PA may include the plurality of subpixels for implementing different colors, and the pixel circuits correspond in an associated manner to the plurality of subpixels. Fig. 3 shows an example of the pixel circuit of a subpixel arranged in the pixel area PA.

[0044] With reference to Fig. 3, the pixel circuit may include a plurality of transistors DT, ST, ET1 and ET2, a capacitor Cst and a plurality of light emitting elements 310 and 320.

[0045] A driver transistor DT and the capacitor Cst may be connected to a switching transistor ST. A first electrode of the driver transistor DT may be connected to the supply voltage supply line PL.

[0046] The switching transistor ST can be connected to the gate line GL and supplied with the gate signal. The switching transistor ST can be turned on or off by the gate signal. The first electrode of the switching transistor ST can be connected to the data line DL. A second electrode of the switching transistor ST can be connected to a gate electrode of the driver transistor DT. In this case, the data signal can be supplied to the gate electrode of the driver transistor DT via the switching transistor ST based on the switching transistor ST being turned on.

[0047] The capacitor Cst can be arranged between a gate electrode and the second electrode of the driver transistor DT. The capacitor Cst can maintain a signal applied to the gate electrode of the driver transistor DT, e.g., maintain the data signal during a frame.

[0048] According to the aspect, the driver transistor DT, the switching transistor ST, and the capacitor Cst may be components for driving light-emitting operations of the light-emitting elements (e.g., a first light-emitting element 310 and a second light-emitting element 320) and may be referred to as a driver part DC. However, the present disclosure is not limited by these terms.

[0049] The first light-emitting element 310 may be connected to a first transistor ET1, which is switched on or off by a first control signal S(k). The second light-emitting element 320 may be connected to a second transistor ET2, which is switched on or off by a second control signal P(k). The first control signal S(k) and the second control signal P(k) are generated by a mode control device, which is configured in the Fig. 2 shown data driver DD may be included.

[0050] In this case, the first light-emitting element 310 or the second light-emitting element 320 may be connected to other components of the pixel circuit, e.g., the driver transistor DT, in accordance with a mode. The mode may be determined when a condition specified by user input or in advance is met. For example, if a predetermined first condition is met, the first light-emitting element 310 emits light based on the supply of the first control signal S(k). If a predetermined second condition is met, the second light-emitting element 320 may emit light based on the supply of the second control signal P(k). The first condition may include a predefined condition for operation in a first mode. The second condition may include a predetermined condition for operation in a second mode.

[0051] The multiple transistors DT, ST, ET1 and ET2 in Fig. 3 may comprise at least one of oxide semiconductors, such as amorphous silicon, polycrystalline silicon, and IGZO. The first or second electrode of the transistor may be a source electrode or a drain electrode. For example, the first electrode may be a source electrode, or the second electrode may be a drain electrode. As another example, the first electrode may be a drain electrode and the second electrode may be a source electrode.

[0052] Fig. 4 shows a planar surface of a portion of the display device according to the aspect of the present disclosure. Fig. 4 shows a flat surface of the pixel area PA in the case where three subpixels are arranged in the pixel area PA. Fig. Figure 5 shows a cross section along the line II' in Fig. 4, and Fig. Figure 6 shows a cross section along the line II-II' in Fig. 4. Hereinafter, the present disclosure will be described with reference to the Fig. 4 to 6.

[0053] In Fig. 4, the pixel region PA may include: a blue subpixel region BPA configured to implement blue, a red subpixel region RPA configured to implement red, and a green subpixel region GPA configured to implement green. According to the aspect, the blue subpixel region BPA may correspond to a first subpixel, the red subpixel region RPA may correspond to a second subpixel, and the green subpixel region GPA may correspond to a third subpixel. The pixel circuit may correspond to a respective one of the subpixels. The pixel circuit may be arranged to correspond to a respective one of the subpixels.

[0054] The pixel area PA may include first lens areas BWE, RWE, and GWE and second lens areas BNE, RNE, and GNE that provide different viewing angles. The second lens areas BNE, RNE, and GNE in each of the pixel areas PA may operate independently of the first lens areas BWE, RWE, and GWE in the corresponding pixel area PA. For example, the pixel areas PA may each include: the first light-emitting elements 310 (e.g., the light-emitting elements 310 shown in Fig. 2) arranged in the first lens areas BWE, RWE and GWE in the corresponding pixel area PA, and the second light emitting elements 320 (e.g. the first light emitting elements 310 shown in Fig. 2) arranged in the second lens regions BNE, RNE and GNE in the corresponding pixel region PA.

[0055] The first light-emitting element 310 can emit light of a specific color. For example, the first light-emitting element 310 can include a first lower electrode 311, a first light-emitting layer 312, and a first upper electrode 313, which are sequentially stacked on a substrate 10. The substrate 10 can include an insulating material. The substrate 10 can include a transparent material. For example, the substrate 10 can include glass or plastic.

[0056] The first lower electrode 311 may comprise an electrically conductive material. The first lower electrode 311 may comprise a material having a high reflectance. For example, the first lower electrode 311 may comprise a metal such as aluminum (Al) and silver (Ag). The first lower electrode 311 may have a multilayer structure. For example, the first lower electrode 311 may have a structure in which a reflective electrode formed of metal is sandwiched between transparent electrodes made of a transparent conductive material such as ITO and IZO.

[0057] The first light-emitting layer 312 can generate light with a brightness corresponding to a voltage difference between the first lower electrode 311 and the first upper electrode 313. For example, the first light-emitting layer 312 can include an emissive material layer (EML) containing a light-emitting material. The light-emitting material can include an organic material, an inorganic material, or a hybrid material.

[0058] The first light-emitting layer 312 may have a multilayer structure. For example, the first light-emitting layer 312 may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0059] The first upper electrode 313 may comprise an electrically conductive material. The first upper electrode 313 may comprise a material that is different from the material of the first lower electrode 311. A transmittance of the first upper electrode 313 may be higher than a transmittance of the first lower electrode 311. For example, the first upper electrode 313 may be formed as a transparent electrode made of a transparent conductive material, such as ITO and IZO. Therefore, in the display device according to the aspect of the present disclosure, the light generated by the first light-emitting layer 312 may be emitted through the first upper electrode 313.

[0060] The second light-emitting element 320 may implement the same color as the first light-emitting element 310. The second light-emitting element 320 may have the same structure as the first light-emitting element 310. For example, the second light-emitting element 320 may include a second lower electrode 321, a second light-emitting layer 322, and a second upper electrode 323 stacked sequentially on the substrate 10.

[0061] The second lower electrode 321 may correspond to the first lower electrode 311, the second light-emitting layer 322 may correspond to the first light-emitting layer 312, and the second upper electrode 323 may correspond to the first upper electrode 313. For example, the second lower electrode 321 may be formed for the second light-emitting element 320 and have the same structure as the first lower electrode 311. The same may apply to the second light-emitting layer 322 and the second upper electrode 323. For example, the first light-emitting element 310 and the second light-emitting element 320 may be formed to have the same structure. However, the present disclosure is not limited thereto. In some cases, the first light-emitting element 310 and the second light-emitting element 320 may be formed to differ from each other in at least some configurations.

[0062] In this aspect, the second light-emitting layer 322 may be spaced apart from the first light-emitting layer 312. Therefore, in the display device according to the aspect of the present disclosure, it is possible to suppress light emission caused by a leakage current.

[0063] According to the aspect of the present disclosure, in the display device, only one of the first light-emitting layer 312 and the second light-emitting layer 322 can generate light in accordance with the user's selection or a predetermined condition.

[0064] In the aspect, the first light emitting element 310 and the second light emitting element 320 in the pixel region PA may be formed on a driving part (e.g., a driving part DC in Fig. 3) be disposed in the corresponding pixel region PA. For example, at least one insulating film (e.g., an element buffer film 110, a gate insulating film 120, an interlayer insulating film 130, a lower protective film 140, and an overcoat layer 150) may be disposed on the substrate 10, and the first light-emitting element 310 and the second light-emitting element 320 in each of the pixel regions PA may be disposed on one of the insulating films. Therefore, in the display device according to the aspect of the present disclosure, the first light-emitting element 310 and the second light-emitting element 320 in each of the pixel regions PA can be prevented from being unnecessarily connected to the driving part DC of the corresponding pixel region PA.

[0065] In this aspect, the buffer film 110, the gate insulating film 120, the interlayer insulating film 130, the lower protective film 140, and the overcoat layer 150 may be stacked on the substrate 10. The buffer film 110 may include an insulating material. For example, the buffer film 110 may include an inorganic insulator such as silicon oxide (SiOx) and silicon nitride (SiNx). The buffer film 110 may have a multilayer structure. For example, the buffer film 110 may have a stacked structure including a film made of silicon nitride (SiNx) and a film made of silicon oxide (SiOx).

[0066] In this aspect, the buffer film 110 may be disposed between the element substrate 10 and the driving part DC in each of the pixel regions PA. The buffer film 110 may suppress contamination caused by the substrate 10 during the process of forming the driving part DC. For example, an upper surface of the substrate 10 facing the driving part DC in each of the pixel regions PA may be covered by the buffer film 110. The driving part DC may be disposed on the buffer film 110 in each of the pixel regions PA.

[0067] The gate insulating film 120 may comprise an insulating material. For example, the gate insulating film 120 may comprise an inorganic insulating material, such as silicon oxide (SiO) and silicon nitride (SiN). The gate insulating film 120 may comprise a material having a high permittivity. For example, the gate insulating film 120 may comprise a high-K material, such as hafnium oxide (HfO). The gate insulating film 120 may have a multilayer structure.

[0068] The gate insulating film 120 may be disposed on the buffer film 110. The gate insulating film 120 may extend between the semiconductor layer and the gate electrode of the transistor. For example, the gate electrodes of the switching transistor ST and the driver transistor DT may be insulated from the semiconductor layers of the switching transistor ST and the driver transistor DT by the gate insulating film 120. The gate insulating film 120 may cover a first and second semiconductor layer in a respective one of the pixel regions PA. The gate electrodes of the switching transistor ST and the driver transistor DT may be disposed on the gate insulating film 120.

[0069] The interlayer insulating film 130 may comprise an insulator material. The interlayer insulating film 130 may comprise, for example, an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The interlayer insulating film 130 may be disposed on the gate insulating film 120. The interlayer insulating film 130 may extend between the gate electrodes and the source electrodes, and between the gate electrodes and the drain electrodes of the driver transistor DT and the switching transistor ST. For example, the source electrodes and the drain electrodes of the driver transistor DT and the switching transistor ST may be insulated from the gate electrodes by the interlayer insulating film 130. The interlayer insulating film 130 may cover the gate electrodes of the switching transistor ST and the driver transistor DT. The source electrode and the drain electrode in each of the pixel regions PA may be arranged on the interlayer insulating film 130.The gate insulating film 120 and the interlayer insulating film 130 may expose source and drain regions of each semiconductor pattern arranged in each of the pixel regions PA.

[0070] In this aspect, the lower protective film 140 may include an insulating material. For example, the lower protective film 140 may include an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The lower protective film 140 may be disposed on the interlayer insulating film 130. The lower protective film 140 may prevent damage to the driving part DC caused by external moisture and impact. The lower protective film 140 may extend along a surface of the driving transistor DT and a surface of the switching transistor ST that are opposite to the substrate 10. The lower protective film 140 may be in contact with the interlayer insulating film 130 outside the driving part DC, which is disposed in each of the pixel regions PA.

[0071] The overcoat layer 150 may include an insulating material. The overcoat layer 150 may include a material different from the material of the lower protective film 140. For example, the overcoat layer 150 may include an organic insulating material. The overcoat layer 150 may be disposed on the lower protective film 140. The overcoat layer 150 may eliminate a level difference caused by the driving part 205 in each of the pixel regions PA. For example, an upper surface of the overcoat layer 150, which faces the element substrate 10, may be a flat surface.

[0072] In this aspect, the first transistor ET1 may be electrically connected between the drain electrode of the driver transistor DT and the first lower electrode 311 of the first light-emitting element 310. The second transistor ET2 may be electrically connected between the drain electrode of the driver transistor DT and the second lower electrode 321 of the second light-emitting element 320.

[0073] The first transistor ET1 may include a first semiconductor layer 211, a first gate electrode 213, a first source electrode 215, and a first drain electrode 217. A first transistor T1 may have the same structure as the switching transistor ST and the driver transistor DT. For example, the first semiconductor layer 211 may be disposed between the buffer film 110 and the gate insulating film 120, and the first gate electrode 213 may be disposed between the gate insulating film 120 and the interlayer insulating film 130. The first source electrode 215 and the first drain electrode 217 may be disposed between the interlayer insulating film 130 and the lower protective film 140. The first gate electrode 213 may overlap a channel region of the first semiconductor layer 211. The first source electrode 215 may be electrically connected to a source region of the first semiconductor layer 211.The first drain electrode 217 may be electrically connected to a drain region of the first semiconductor layer 211.

[0074] In this aspect, the second transistor ET2 may include a second semiconductor layer 221, a second gate electrode 223, a second source electrode 225, and a second drain electrode 227. For example, the second semiconductor layer 221 may be disposed on the same layer as the first semiconductor layer 211, the second gate electrode 223 may be disposed on the same layer as the first gate electrode 213, and the second source electrode 225 and the second drain electrode 227 may be disposed on the same layer as the first source electrode 215 and the first drain electrode 217.

[0075] In this aspect, the first transistor ET1 may be formed simultaneously with the switching transistor ST and the driver transistor DT. The first transistor ET1 may be formed simultaneously with the second transistor ET2.

[0076] The first light-emitting element 310 and the second light-emitting element 320 in each of the pixel regions PA may be disposed on the cladding layer 150 in the corresponding pixel region PA. For example, the first lower electrode 311 of the first light-emitting element 310 may be electrically connected to the first drain electrode 217 (or the first source electrode 215) of the first transistor ET1 through contact holes formed by the lower protective film 140 and the cladding layer 150, and the second lower electrode 321 of the second light-emitting element 320 may be electrically connected to the second drain electrode 227 (or the second source electrode 225) of the second transistor ET2 through contact holes formed by the lower protective film 140 and the cladding layer 150.

[0077] The second lower electrode 321 in each of the pixel regions PA may be spaced apart from the first lower electrode 311 in the corresponding pixel region PA. For example, a bank insulating film 160 may be disposed between the first lower electrode 311 and the second lower electrode 321 in each of the pixel regions PA. The bank insulating film 160 may comprise an insulating material. The bank insulating film 160 may comprise, for example, an organic insulating material. The bank insulating film 160 may comprise a material that is different from the material of the cladding layer 150.

[0078] The second lower electrode 321 in each of the pixel regions PA may be insulated from the first lower electrode 311 in the corresponding pixel region PA by the bank insulating film 160. For example, the bank insulating film 160 may cover an edge of the first lower electrode 311 and an edge of the second lower electrode 321 located in each of the pixel regions PA. Therefore, the display device can provide the user with images generated by the first lens regions BWE, RWE, and GWE in each of the pixel regions PA where the first light-emitting element 310 is located, or images generated by the second lens regions BNE, RNE, and GNE in each of the pixel regions PA where the second light-emitting element 320 is located.

[0079] The first light-emitting layer 312 and the first upper electrode 313 of the first light-emitting element 310, which is arranged in each of the pixel regions PA, may be stacked in a portion of the corresponding first lower electrode 311 exposed through the bank insulating film 160. The second light-emitting layer 322 and the second upper electrode 323 of the second light-emitting element 320, which are arranged in each of the pixel regions PA, may be stacked in a portion of the corresponding second lower electrode 321 exposed through the bank insulating film 160. For example, the bank insulating film 160 in each of the pixel regions PA may be divided into first light-emitting regions BE1, RE1, and GE1 in which the first light-emitting element 310 emits light, and second light-emitting regions BE2, RE2, and GE2 in which the second light-emitting element 320 emits light.In each of the pixel regions PA, a size of each of the second light emission regions BE2, RE2 and GE2 may be smaller than a size of each of the first light emission regions BE1, RE1 and GE1.

[0080] In each of the pixel regions PA, the second upper electrode 323 may be electrically connected to the first upper electrode 313 in the corresponding pixel region PA. For example, a voltage applied to the second upper electrode 323 of the second light-emitting element 320 arranged in a respective one of the pixel regions PA may be equal to a voltage applied to the first upper electrode 313 of the first light-emitting element 310 arranged in the corresponding pixel region PA. The second upper electrode 323 in a respective one of the pixel regions PA may comprise the same material as the first upper electrode 313 in the corresponding pixel region PA. For example, the second upper electrode 323 in a respective one of the pixel regions PA may be formed simultaneously with the first upper electrode 313 in the corresponding pixel region PA.The second upper electrode 323 in each of the pixel regions PA may extend on the bank insulating film 160 and be in direct contact with the first upper electrode 313 in the corresponding pixel region PA. The brightness in the first lens regions BWE, RWE, and GWE arranged in each of the pixel regions PA, and the brightness in the second lens regions BNE, RNE, and GNE may be controlled by a drive current generated in the corresponding pixel region PA.

[0081] An encapsulation element 800 may be disposed on the first light-emitting element 310 and the second light-emitting element 320 in each of the pixel regions PA. The encapsulation element 800 may prevent damage to the light-emitting elements 310 and 320 due to moisture and external impact. The encapsulation element 800 may have a multi-layer structure. For example, the encapsulation element 800 may include a first encapsulation layer 810, a second encapsulation layer 820, and a third encapsulation layer 830 that are sequentially stacked. However, aspects of the present disclosure are not limited thereto. For example, the encapsulation element 800 may include a first encapsulation layer 810, a second encapsulation layer 820, and a third encapsulation layer 830 that are sequentially stacked. However, aspects of the present disclosure are not limited thereto.The second encapsulation layer 820 may comprise a material different from the material of the first encapsulation layer 810 and the third encapsulation layer 830. For example, the first encapsulation layer 810 and the third encapsulation layer 830 are inorganic encapsulation layers comprising an inorganic insulating material, and the second encapsulation layer 820 may comprise an organic encapsulation layer comprising an organic insulating material. Therefore, damage to the light-emitting elements 310 and 320 of the display device caused by moisture and external impacts can be more effectively suppressed.

[0082] First lenses 510 and second lenses 520 may be arranged on the encapsulation element 800 in a respective one of the pixel regions PA.

[0083] The first lenses 510 may be arranged on the first lens regions BWE, RWE, and GWE in each of the pixel regions PA. For example, the light generated by the first light-emitting element 310 in each of the pixel regions PA may be emitted into the corresponding pixel region PA through the first lens 510. The first lens 510 may have a shape in which at least the light cannot be restricted in one direction. For example, a planar shape of the first lens 510 arranged in each of the pixel regions PA may be a bar shape extending in a first direction.

[0084] In this case, the propagation direction of the light emitted by the first lens regions BWE, RWE, and GWE in the pixel region PA is not limited to the first direction. For example, the content (or images) provided by the first lens regions BWE, RWE, and GWE in the pixel region PA may be shared with people around the user in the first direction. The case where the content is provided by the first lens regions BWE, RWE, and GWE is a mode in which the content is provided within a first viewing angle range that is larger than a second viewing angle range in which the second lens regions BNE, RNE, and GNE are provided, and this mode may be referred to as a first mode.

[0085] The second lenses 520 may be arranged on the second lens regions BNE, RNE, and GNE in each of the pixel regions PA. The light generated by the second light-emitting element 320 in the pixel region PA may be emitted by the second lens 520 in the corresponding pixel region PA. The second lens 520 may restrict the propagation direction in which the light passes through the second lens 520 to the first direction and / or the second direction. For example, a planar shape of the second lens 520 arranged in the pixel region PA may be a circular shape. In this case, the propagation direction of the light emitted by the second lens regions BNE, RNE, and GNE in the pixel region PA may be restricted to the first and second directions. For example, the content provided by the second lens regions BNE, RNE, and GNE in the pixel region PA may not be shared with people around the user.The case where the content is provided by the second lens areas BNE, RNE, and GNE is a mode in which the content is provided within the second viewing angle range that is smaller than the first viewing angle range in which the first lens areas BWE, RWE, and GWE are provided, and this mode may be referred to as a second mode.

[0086] The first light-emitting regions BE1, RE1, and GE1 included in the first lens regions BWE, RWE, and GWE in each of the pixel regions PA may have shapes corresponding to the first lenses 510 arranged in the first lens regions BWE, RWE, and GWE in the corresponding pixel region PA. For example, the planar shapes of the first light-emitting regions BE1, RE1, and GE1 defined in the first lens regions BWE, RWE, and GWE in each of the pixel regions PA may each have a bar shape extending in the first direction. The first lenses 510 arranged in the first lens regions BWE, RWE, and GWE in the pixel region PA may have larger sizes than the first light-emitting regions BE1, RE1, and GE1 included in the first lens regions BWE, RWE, and GWE in the corresponding pixel region PA.Therefore, it is possible to improve the efficiency of the light emitted from the first light emitting areas BE1, RE1 and GE1 in the pixel area PA.

[0087] The second light-emitting regions BE2, RE2, and GE2 included in the second lens regions BNE, RNE, and GNE in each of the pixel regions PA may have shapes corresponding to the second lenses 520 arranged in the second lens regions BNE, RNE, and GNE in the corresponding pixel region PA. For example, planar shapes of the second light-emitting regions BE2, RE2, and GE2 included in the second lens regions BNE, RNE, and GNE in the pixel region PA may each have a circular shape. The second lenses 520 arranged in the second lens regions BNE, RNE, and GNE in the pixel region PA may have larger dimensions than the second light-emitting regions BE2, RE2, and GE2 included in the second lens regions BNE, RNE, and GNE in the corresponding pixel region PA.For example, the planar shapes of the second light-emitting regions BE2, RE2, and GE2 arranged in the second lens regions BNE, RNE, and GNE in each of the pixel regions PA may be circular shapes concentric with the planar shapes of the second lenses 520 arranged in the second lens regions BNE, RNE, and GNE in the corresponding pixel region PA. In this case, it is possible to improve the efficiency of the light emitted by the second light-emitting regions BE2, RE2, and GE2 in the pixel region PA.

[0088] In this aspect, the first lens region BWE, RWE, or GWE in the pixel region PA may include a first light-emitting region BE1, RE1, or GE1. The second lens regions BNE, RNE, and GNE in the pixel region PA may include the plurality of second light-emitting regions BE2, RE2, and GE2.

[0089] In this aspect, a first lens 510 may be arranged in the first lens region BWE, RWE, or GWE in the pixel region PA. The plurality of second lenses 520 may be arranged in the second lens regions BNE, RNE, and GNE in the pixel region PA.

[0090] In this aspect, the second light-emitting regions BE2, RE2, and GE2 included in the second lens regions BNE, RNE, and GNE in the pixel region PA can operate for the respective sub-pixel regions. The second light-emitting regions (e.g., the second light-emitting regions BE2, the second light-emitting regions RE2, or the second light-emitting regions GE2) included in a sub-pixel region can operate simultaneously.

[0091] In this aspect, a second lower electrode 321 may be disposed in the second lens region BNE, RNE, or GNE in each of the pixel regions PA. The bank insulating film 160 between the second light-emitting regions BE2, RE2, and GE2 may be disposed between the second lower electrode 321 and the second light-emitting layer 322. The bank insulating film 160 disposed between the second light-emitting regions BE2, between the second light-emitting regions RE2, and / or between the second light-emitting regions GE2 may be disposed between the second lower electrode 321 and the second light-emitting layer 322. The second light-emitting layer 322 disposed between the second light-emitting regions BE2, RE2, and GE2 in the second lens regions BNE, RNE, and GNE may be spaced from the second lower electrode 321 by the bank insulating film 160.In this case, it is possible to improve the luminous efficacy of the second light emission areas BE2, RE2 and GE2.

[0092] In this aspect, areas of the second light-emitting regions BE2, RE2, and GE2 located in the second lens regions BNE, RNE, and GNE in the pixel region PA may be designated as specific values. For example, the areas of the second light-emitting regions BE2, RE2, and GE2 located in the second lens regions BNE, RNE, and GNE may be implemented to be equal to each other. The area of ​​each of the second light-emitting regions BE2, RE2, and GE2 located in the second lens regions BNE, RNE, and GNE in the pixel region PA may be equal to the area of ​​each of the second light-emitting regions BE2, RE2, and GE2 included in the second lens regions BNE, RNE, and GNE in the adjacent pixel region PA.

[0093] In this aspect, the number of second light-emitting regions may vary depending on the subpixel regions RPA, GPA, and BPA. For example, the number of second light-emitting regions BE2 defined in the second lens region BNE in the blue subpixel region BPA may be greater than the number of second light-emitting regions RE2 defined in the second lens region RNE in the red subpixel region RPA. The number of second light-emitting regions RE2 defined in the second lens region RNE in the red subpixel region RPA may be greater than the number of second light-emitting regions GE2 defined in the second lens region GNE in the green subpixel region GPA.In this case, the efficiency deviation between the second light-emitting elements 320 arranged in the second lens regions BNE, RNE and GNE in the pixel region PA can be compensated by the number of the second light-emitting regions BE2, RE2 and GE2 defined in the second lens regions BNE, RNE and GNE in each of the pixel regions PA.

[0094] In this aspect, the sizes of the first light-emitting regions BE1, RE1, and GE1 for the respective subpixel regions RPA, GPA, and BPA may be different from each other. For example, the first light-emitting region BE1 in the blue subpixel region BPA may have a different size than the first light-emitting region RE1 in the red subpixel region RPA and a different size than the first light-emitting region GE1 in the green subpixel region GPA. The size of the first light-emitting region BE1 in the blue subpixel region BPA may be larger than the size of the first light-emitting region RE1 in the red subpixel region RPA. The size of the first light-emitting region RE1 in the red subpixel region RPA may be larger than the size of the first light-emitting region GE1 in the green subpixel region GPA.Therefore, in the display device according to the aspect of the present disclosure, the efficiency deviation between the first light-emitting elements 310 arranged in the first lens regions BWE, RWE, and GWE in each of the pixel regions PA can be compensated by the sizes of the first light-emitting regions BE1, RE1, and GE1 defined in the first lens regions BWE, RWE, and GWE in each of the pixel regions PA.

[0095] In the aspect, a lens protection film 600 may be attached to the first lens 510 and the second lens 520 in the pixel region PA. The lens protection film 600 may include an insulator material. For example, the lens protection film 600 may include an organic insulator. A refractive index of the lens protection film 600 may be smaller than a refractive index of the first lens 510 and a refractive index of the second lens 520 disposed in each of the pixel regions PA. Therefore, in the display device according to the aspect of the present disclosure, the light that has passed through the first lens 510 and the second lens 520 in each of the pixel regions PA may not be reflected toward the substrate 10 due to a difference from the refractive index of the lens protection film 600.

[0096] Fig. 7 is a view showing a common circuit and the pixel circuit of the display device according to the aspect of the present disclosure. Fig. 7 shows an example of a circuit constituting a subpixel, and the subpixel may include a common circuit and a pixel circuit.

[0097] With reference to Fig. 7, a common circuit 701 and a pixel circuit 702 may be connected. In the present disclosure, the common circuit 701 and the pixel circuit 702 are described as being different from each other for the sake of simplicity. However, the present disclosure is not limited thereto. It goes without saying that according to the aspect, at least a part of the common circuit 701 may include the pixel circuit 702. Furthermore, according to one aspect, the common circuit 701 may be referred to, for example, as a reference voltage circuit or a reference voltage driving part. However, the present disclosure is not limited by these terms.

[0098] At least a portion of the common circuit 701 may be connected to the pixel circuit 702. Furthermore, at least a portion of the common circuit 701 may also be connected to another pixel circuit. For example, the common circuit 701 may be connected to at least two pixel circuits that emit light of different colors. Therefore, a reference voltage Vref may be provided for at least two pixel circuits.

[0099] At least one component included in the common circuit 701 and the pixel circuit 702 may receive at least one of: the reference voltage Vref, a high potential voltage VDD, a low potential voltage VSS, the light emission signal EM(N), a data voltage Vdata, and an initialization voltage Vini.

[0100] The reference voltage Vref may have a predetermined voltage value and be provided via a reference voltage line 711. For example, the reference voltage Vref may have a value predetermined in a range of 0 V or higher and lower than 3.5 V. The range of 0 V or higher and lower than 3.5 V may correspond to a reference voltage range. The initialization voltage Vini may have a predefined voltage value and be provided via an initialization voltage line 712. The initialization voltage Vini may have a predefined voltage value equal to or lower than the reference voltage Vref.

[0101] The high-potential voltage VDD may have a voltage value higher than a certain value and is provided via a high-potential voltage line 717. The low-potential voltage VSS may have a voltage value lower than a certain value and is provided via a low-potential voltage line 714. The light-emitting signal EM(N) may have a voltage value at a first or second level and is provided via a light-emitting signal line 715. The data voltage Vdata may be determined in accordance with the input data and provided via a data voltage line 716.

[0102] The source electrode of the transistor to be described below may be used as the drain electrode, and the drain electrode may be used as the source electrode. Furthermore, in one aspect, the source electrode may be referred to as a first electrode and the drain electrode as a second electrode. However, the present disclosure is not limited by these terms.

[0103] Furthermore, aspects of voltages are described below using the terms "first level" and "second level." However, the present disclosure is not limited by these terms. According to the aspect, the first level may be referred to as a high level, and the second level may be referred to as a low level. In this case, the first level may have a larger voltage value than the second level. The voltage of the first level may belong to a range of voltage values ​​that can turn off a p-type TFT or turn on an n-type TFT. For example, the voltage at the first level may have a voltage corresponding to a range of 6 V to 16 V. The voltage at the second level may belong to a range of voltage values ​​that can turn on the p-type TFT or turn off the n-type TFT.For example, the voltage at the second level may have a voltage corresponding to a range of -8 V to -12 V. However, the aspect of the present disclosure is not limited thereto.

[0104] The common circuit 701 may include the first transistor T1 and / or a second transistor T2. The first transistor T1 may operate based on the first scan signal Scan(N). A first electrode of the first transistor T1 may be connected to the reference voltage line 711, which provides the reference voltage Vref. A second electrode of the first transistor T1 may be connected to at least one of: the second transistor T2, a third transistor T3, and the capacitor Cst. For example, the second electrode of the first transistor T1 may be connected to the second transistor T2. In another example, the second electrode of the first transistor T1 may be connected to a first node N1 and connected to the second transistor T2, the third transistor T3, and the capacitor Cst connected to the first node N1. The first transistor T1 may provide the reference voltage Vref to the first node N1.

[0105] The second transistor T2 may be connected in series with the first transistor T1. The second transistor T2 may operate based on the second scan signal Scan(N-1). A first electrode of the second transistor T2 may be connected to at least one of the first transistor T1, the third transistor T3, and the capacitor Cst. For example, the first electrode of the second transistor T2 may be connected to the first transistor T1, the third transistor T3, and the capacitor Cst via the first node N1. A second electrode of the second transistor T2 may be connected to at least one of the high-potential voltage line 717, the third transistor T3, and a ninth transistor T9. For example, the second electrode of the second transistor T2 may be connected to the high-potential voltage line 717 and the third transistor T3.In another example, the second electrode of the second transistor T2 may be connected to the high potential voltage line 717, the third transistor T3 and the ninth transistor T9.

[0106] The third transistor T3 may be connected between the first node N1 and the high-potential voltage line 717. The third transistor T3 may be connected between the first electrode and the second electrode of the second transistor T2. For example, the third transistor T3 may be connected in parallel with the second transistor T2.

[0107] In this aspect, the third transistor T3 may be connected to at least one of the second transistor T2, the high-potential voltage line 717, and the ninth transistor T9. For example, a first electrode of the third transistor T3 may be connected to at least one of the second electrode of the second transistor T2, the high-potential voltage line 717, and a first electrode of the ninth transistor T9. The third transistor T3 may be connected to the first transistor T1, the second transistor T2, and the capacitor Cst via the first node N1. For example, a second electrode of the third transistor T3 may be connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the capacitor Cst via the first node N1.

[0108] The first node N1 may be connected to the pixel circuit 702. In this aspect, the first node N1 may be further connected to another pixel circuit. For example, in the case where the light-emitting elements included in the pixel circuit 702 (e.g., a first light-emitting element ED1 and a second light-emitting element ED2) emit light having a first color, the first node N1 may be further connected to another pixel circuit having light-emitting elements that emit light having a second color. In this case, the common circuit 701 may be connected to the plurality of pixel circuits via the first node N1. A more specific example of the above configuration will be described with reference to Fig. 8 described.

[0109] The pixel circuit 702 includes the plurality of light-emitting elements ED1 and ED2, the driver transistor DT, the first to tenth transistors T1 to T10, and the capacitor Cst. The first to tenth transistors T1 to T10 may include the first transistor T1, the second transistor T2, the third transistor T3, a fourth first transistor T41, a fourth second transistor T42, a fifth transistor T5, a sixth transistor T6, a seventh first transistor T71, a seventh second transistor T72, an eighth transistor T8, the ninth transistor T9, and a tenth transistor T10.

[0110] The plurality of light-emitting elements ED1 and ED2 include the first light-emitting element ED1 and the second light-emitting element ED2. Furthermore, the first light-emitting element ED1 and the second light-emitting element ED2 emit light by being supplied with driving currents from the driving transistor DT. Specifically, an anode electrode of the first light-emitting element ED1 may be connected to the fourth-first transistor T41, and a cathode electrode of the first light-emitting element ED1 may be connected to an input terminal (or the low-potential voltage line 714) of the low-potential driving voltage VSS, so that the first light-emitting element ED1 can emit light using a first driving current.Further, an anode electrode of the second light-emitting element ED2 may be connected to the fourth-second transistor T42, and a cathode electrode of the second light-emitting element ED2 may be connected to the input terminal of the low-potential driving voltage VSS, so that the second light-emitting element ED2 can emit light by means of a second driving current.

[0111] The driver transistor DT controls the drive currents to be applied to the plurality of light-emitting elements ED1 and ED2 in response to a source-gate voltage Vgs thereof. The drive currents include the first drive current and the second drive current. In this aspect, the first electrode of the driver transistor DT may be connected to the fifth transistor T5 and the ninth transistor T9. The second electrode of the driver transistor DT may be connected to the sixth transistor T6 and the tenth transistor T10. The gate electrode of the driver transistor DT may be connected to a second node N2. The gate electrode of the driver transistor DT may be connected to a first capacitor Cst, the sixth transistor T6, and the eighth transistor T8.

[0112] The fourth-first transistor T41 may be connected to at least one of the tenth transistor T10, the fourth-second transistor T42, the seventh-first transistor T71, and the first light-emitting element ED1. In this aspect, the fourth-first transistor T41 may include a source electrode connected to the tenth transistor T10, a drain electrode connected to the anode electrode of the first light-emitting element ED1, and a gate electrode connected to a first control signal line 710 configured to provide the first control signal S(k). The fourth-first transistor T41 may be turned on or off in response to the first control signal S(k).The fourth-first transistor T41 defines a current path between the first light-emitting element ED1 and the tenth transistor T10 connected to a source electrode of the fourth-first transistor T41 in response to the first control signal S (k) at a low level, ie, a turn-on level.

[0113] The fourth-second transistor T42 may be connected to at least one of the tenth transistor T10, the fourth-first transistor T41, the seventh-second transistor T72, and the second light-emitting element ED2. In this aspect, the fourth-second transistor T42 may include a source electrode connected to the tenth transistor T10, a drain electrode connected to the anode electrode of the second light-emitting element ED2, and a gate electrode connected to a second control signal line 720 configured to provide the second control signal P(k). The fourth-second transistor T42 may be turned on or off in response to the second control signal P(k).The fourth-second transistor T42 defines a current path between the second light-emitting element ED2 and the tenth transistor T10 connected to a source electrode of the fourth-second transistor T42 in response to the second control signal P(k) at a low level, i.e., a turn-on level.

[0114] The fifth transistor T5 may be connected to at least one of the data voltage line 716 transmitting the data voltage Vdata, the driver transistor DT, and the ninth transistor T9. The fifth transistor T5 includes a first electrode connected to the data voltage line 716, a second electrode connected to the first electrode of the driver transistor DT, and a gate electrode connected to a first scan line 718 configured to transmit the first scan signal Scan(N). The fifth transistor T5 may apply the data voltage Vdata to the first electrode of the driver transistor DT. For example, the fifth transistor T5 may apply the data voltage Vdata to the first electrode of the driver transistor DT in response to the first scan signal Scan(N) at a low level, i.e., a turn-on level.

[0115] The sixth transistor T6 connects the gate electrode and the second electrode (e.g., the drain electrode) of the driver transistor DT as a diode. The sixth transistor T6 has a first electrode connected to the second node N2, a second electrode connected to a third node N3, and a gate electrode connected to the first scan signal line 718 configured to transmit the first scan signal Scan(N). The sixth transistor T6 connects the gate electrode and the drain electrode of the driver transistor DT as a diode in response to the first scan signal Scan(N) at a low level, i.e., a turn-on level.

[0116] The seventh-first transistor T71 may be connected to at least one of the initialization voltage line 712 transmitting the initialization voltage Vini, the first light-emitting element ED1, the seventh-second transistor T72, the eighth transistor T8, and the first scanning signal line 718. The seventh-first transistor T71 applies the initialization voltage Vini to the anode electrode of the first light-emitting element ED1. The fourth-first transistor T41 may include a first electrode connected to an initialization voltage line 717 configured to transmit the initialization voltage Vini, a second electrode connected to the anode electrode of the first light-emitting element ED1, and a gate electrode connected to the first scanning signal line 718.The seventh-first transistor T71 may apply the initialization voltage Vini to the anode electrode of the first light emitting element ED1 in response to the first scan signal Scan(N) at a low level, ie, a turn-on level.

[0117] The seventh-second transistor T72 may be connected to at least one of the initialization voltage line 712, the second light-emitting element ED2, the seventh-first transistor T71, the eighth transistor T8, and the first scan signal line 718. The seventh-second transistor T72 applies the initialization voltage Vini to the anode electrode of the second light-emitting element ED2. The seventh-second transistor T72 includes a first electrode connected to the initialization voltage line 712 and configured to transmit the initialization voltage Vini, a second electrode connected to the anode electrode of the second light-emitting element ED2, and a gate electrode connected to the first scan signal line 718 and configured to transmit the first scan signal Scan(N).The seventh-second transistor T72 applies the initialization voltage Vini to the anode electrode of the second light-emitting element ED2 in response to the first scan signal Scan(N) at a low level, ie, a turn-on level.

[0118] The eighth transistor T8 may be connected to at least one of the initialization voltage line 712, the capacitor Cst, the second transistor T2, the sixth transistor T6, the seventh-first transistor T71, the seventh-second transistor T72, the driver transistor DT, and the first scan signal line 718. The eighth transistor T8 applies the initialization voltage Vini to the second node N2. The eighth transistor T8 includes a first electrode connected to the initialization voltage line 712 and configured to transmit the initialization voltage Vini, a second electrode connected to the second node N2, and a gate electrode connected to a second scan signal line 713 configured to transmit the second scan signal Scan(N-1).The eighth transistor T8 applies the initialization voltage Vini to the anode electrode of the second node N2 in response to the second scan signal Scan(N-1) at a low level, ie, at a turn-on level.

[0119] The ninth transistor T9 may be connected to at least one of the second transistor T2, the third transistor T3, the fifth transistor T5, the driver transistor DT, the high-potential voltage line 717, and the light-emitting signal line 715 configured to provide the light-emitting signal EM(N). The ninth transistor T9 may include a first electrode connected to the high-potential voltage line 717 and the third transistor T3, a second electrode connected to the fifth transistor T5 and the driver transistor DT, and a gate electrode connected to the light-emitting signal line 715. The ninth transistor T9 may be turned on or off in response to the light-emitting signal EM(N). The ninth transistor T9 may respond to the light-emitting signal EM(N) at a low level, i.e., a turn-on level.

[0120] The tenth transistor T10 may be connected to at least one of the driver transistor DT, the sixth transistor T6, the fourth first transistor T41, the fourth second transistor T42, and the light-emitting signal line 715. The tenth transistor T10 may be connected to the driver transistor DT and the sixth transistor T6 via the third node N3. The tenth transistor T10 may include a first electrode connected to the third node N3, a second electrode connected to the fourth first transistor T41 and the fourth second transistor T42, and a gate electrode connected to the light-emitting signal line 715. The tenth transistor T10 may be turned on or off in response to the light-emitting signal EM(N). The tenth transistor T10 may respond to the light-emitting signal EM(N) at a low level, that is, at the turn-on level.The tenth transistor T10 may define a current path between the driver transistor DT, the fourth-first transistor T41 and the first light-emitting element ED1 or a current path between the driver transistor DT, the fourth-second transistor T42 and the second light-emitting element ED2.

[0121] In the aspect where active areas of the display device are arranged in N columns and M rows, the first scan signal Scan(N) may include a scan signal to be provided to the pixel circuits arranged in an N-th row. The second scan signal Scan(N-1) may include a scan signal to be provided to pixel circuits arranged in an (N-1)-th row. In the present disclosure, it is assumed that the first scan signal Scan(N) is a scan signal to be provided to the N-th row, and that the second scan signal Scan(N-1) is a scan signal to be provided to the (N-1)-th row. However, the present disclosure is not limited to this. The first scan signal Scan(N) and the second scan signal Scan(N-1) may be configured as different signals provided to the same row.

[0122] The capacitor (or storage capacitor) Cst has a first electrode connected to the first node N1 and a second electrode connected to the second node N2. The first electrode of the capacitor Cst may be connected to the first transistor T1 and the third transistor T3. The second electrode of the capacitor Cst may be connected to the gate electrode of the driver transistor DT, the sixth transistor T6, and the eighth transistor T8.

[0123] In this aspect, the reference voltage Vref and the initialization voltage Vini may have predetermined voltage values. The reference voltage Vref may have a higher voltage value than the initialization voltage Vini. For example, the reference voltage Vref may have a voltage value corresponding to a range of 2.0 V or higher and 2.5 V or lower. The initialization voltage Vini may have a voltage value corresponding to a range of 0 V or higher and 1.0 V or lower.

[0124] Fig. 8 is a view showing an implementation example of the common circuit and the pixel circuits of the display device according to an aspect of the present disclosure. Fig. 8 shows embodiments of a common circuit 701 and three pixel circuits 702, 802 and 812 connected to the common circuit 701. Fig. Figure 8 shows an example of one of the pixels arranged in the Nth row.

[0125] With reference to Fig. 8, a pixel may have multiple subpixels. The multiple subpixels may each be driven by the common circuit 701 and the pixel circuits 702, 802, and 812. Hereinafter, the pixel circuits 702, 802, and 812 constituting the pixel may be referred to interchangeably as a first pixel circuit 702, a second pixel circuit 802, and a third pixel circuit 812 for convenience.

[0126] In this aspect, the second pixel circuit 802 may include at least two light-emitting elements adjacent to at least one of the first pixel circuit 702 and the third pixel circuit 812 and configured to emit light that differs in color from the light emitted by the first and second light-emitting elements of the first pixel circuit 702. The third pixel circuit 812 may include at least two light-emitting elements adjacent to at least one of the first pixel circuit 702 and the second pixel circuit 802 and configured to emit light that differs in color from the light emitted by the first and second light-emitting elements of the first pixel circuit 702 and the light emitted by at least two light-emitting elements of the second pixel circuit 802.

[0127] In the aspect, a first subpixel emitting light with a first color may include common circuitry 701 and first pixel circuitry 702. A second subpixel emitting light with a second color may include common circuitry 701 and second pixel circuitry 802. A third subpixel emitting light with a third color may include common circuitry 701 and third pixel circuitry 812.

[0128] The first pixel circuit 702, the second pixel circuit 802, and the third pixel circuit 812 may share the common circuit 701. For example, as shown, if a common circuit 701 is included in the pixel circuit of a pixel, the common circuit 701 and the first pixel circuit 702 may be electrically connected while sharing the node, and the second pixel circuit 802 and the third pixel circuit 812 may be electrically connected while sharing the node.

[0129] In the aspect, the common circuit 701 may include the first transistor T1 (e.g., the first transistor T1 in Fig. 7), the second transistor T2 (e.g. the second transistor T2 in Fig. 7) and the third transistor T3 (e.g. the third transistor T3 in Fig. 7). The common circuit 701 may include the first node N1, and the first node N1 may be connected to the first pixel circuit 702, the second pixel circuit 802, and the third pixel circuit 812. Therefore, the common circuit 701 may enable the signal to be provided to the first node N1 to be provided jointly to the first pixel circuit 702, the second pixel circuit 802, and the third pixel circuit 812.

[0130] With reference to Fig. 8, lines for providing various signals may be arranged in the pixel. For example, the first scan signal line may be arranged to provide the first scan signal Scan(N) in a first direction (or x-axis), the second scan line may be arranged to provide the second scan signal Scan(N-1), the light emission signal line may be arranged to provide the light emission signal EM(N), and the high potential voltage line may be arranged to provide the high potential voltage VDD. The reference voltage line may be arranged to provide the reference voltage Vref in a second direction (or y-axis), the high potential voltage line may be arranged to provide the high potential voltage VDD, the data voltage line may be arranged to provide the data voltage Vdata, and the initialization voltage line may be arranged to provide the initialization voltage Vini.

[0131] For example, as shown, the second scanning signal line, the first scanning signal line, the light-emitting signal line, and the high-potential voltage line may be arranged sequentially. The first node N1 may be arranged between the first scanning signal line and the light-emitting signal line.

[0132] In the aspect, the high-potential voltage lines may be arranged in the first and second directions, thereby defining a mesh shape. The reference voltage line and the high-potential voltage line arranged in the second direction may be arranged to overlap at least a portion of the common circuit 701. The data voltage line and the initialization voltage line may be arranged in each of the sub-pixel circuits. For example, as shown, the data voltage line and the initialization voltage line may be arranged to overlap at least a portion of the first pixel circuit 702. The reference voltage line and the high-potential voltage line may be arranged in each of the plurality of pixel circuits (e.g., the first pixel circuit 702, the second pixel circuit 802, and the third pixel circuit 812) and overlap at least a portion of each of the pixel circuits.

[0133] According to the aspect, the design form of at least one of the first pixel circuit 702, the second pixel circuit 802, and the third pixel circuit 812 may be implemented to be different from the illustrated design form. The aspect of the present disclosure is not limited to this.

[0134] In this aspect, the common circuit 701 may be arranged on a first side, e.g., a left side of the pixel, and the pixel circuits may be arranged on a second side, e.g., a right side of the pixel. However, the present disclosure is not limited thereto. The common circuit 701 may be arranged between the pixel circuits.

[0135] Fig. 9 is a view for explaining a signal timing of the display device according to the aspect of the present disclosure.

[0136] With reference to Fig. 9, the pixel circuit may include multiple operating sections. The pixel circuit may operate in an initialization section (initial section) P1, a sensing section P2, a holding section P3, and a light-emitting section (emission section) P4. In some cases, the sections may be referred to by other names. For example, the initialization section P1 may be referred to as a first driving section, the sensing section P2 as a second driving section, the holding section P3 as a third driving section, and the light-emitting section P4 as a fourth driving section. However, the present disclosure is not limited by these terms.

[0137] In the aspect, the pixel circuit may be provided in each of the driving sections with the first scanning signal Scan (N), the second scanning signal Scan (N-1), the light emission signal EM (N), the data voltage Vdata, the reference voltage Vref, the initialization voltage Vini, the high potential voltage VDD, the low potential voltage VSS, the first control signal S (k), and the second control signal P (k).

[0138] The data voltage Vdata can be changed depending on the screens to be displayed on the display device. The data voltage Vdata can be an alternating voltage. The reference voltage Vref, the initialization voltage Vini, the high-potential voltage VDD, and the low-potential voltage VSS are voltages that have predetermined values ​​and can be supplied to the pixel circuit. At least one of the first scan signal Scan(N), the second scan signal Scan(N-1), and the light emission signal EM(N) can be changed depending on the driving sections.

[0139] In the aspect, the first control signal S(k) and the second control signal P(k) may be selectively provided in accordance with operating modes of the display device. For example, in the case that the display device is to be operated in a first mode, the first control signal S(k) may be provided as a value at a first level (or low-level voltage), and the second control signal P(k) may be provided as a value at a second level (or high-level voltage). In the case that the display device is to be operated in a second mode, the first control signal S(k) may be provided as a value at the second level, and the second control signal P(k) may be provided as a value at the first level.

[0140] In this aspect, the initialization section P1 may be performed before the data voltage Vdata is supplied. In the initialization section P1, the second scan signal Scan(N-1) may be input as a low-level voltage. In the initialization section P1, the first scan signal Scan(N) and the light emission signal EM(N) may be input as high-level voltages. Since the second scan signal Scan(N-1) is input as a low-level voltage, the second transistor T2 and the eighth transistor T8 may be turned on. In this case, the high-potential voltage VDD may be supplied to the first node N1 via the second transistor T2, and the initialization voltage Vini may be supplied to the second node N2 via the eighth transistor T8.

[0141] In this aspect, the initialization section P1 may be maintained for the time for which the light emission signal EM(N) and the first scanning signal Scan(N) are input as high-level voltages, and the second scanning signal Scan(N-1) is input as a low-level voltage. For example, the initialization section P1 may end when the first scanning signal Scan(N) transitions from the high-level voltage to the low-level voltage, and the second scanning signal Scan(N-1) transitions from the low-level voltage to the high-level voltage. The time (or point) at which the signal transitions from the low-level voltage to the high-level voltage may be referred to as the rising time. The time at which the signal transitions from the high-level voltage to the low-level voltage may be referred to as the falling time. A more specific example of the initialization section P1 will be described with reference to Fig. 10 described.

[0142] In this aspect, the first scan signal Scan (N) may be input as a low-level voltage on the basis that the initialization section P1 ends. The second scan signal Scan (N-1) may be input as a high-level voltage on the basis that the initialization section P1 ends.

[0143] In this aspect, the scanning section P2 may be performed while the data voltage Vdata is supplied to the pixel circuit. In the scanning section P2, the light emission signal EM(N) may be input as a high-level voltage. In the scanning section P2, the first scan signal Scan(N) may be input as a low-level voltage, and the second scan signal Scan(N-1) may be input as a high-level voltage.

[0144] According to the aspect, when the first scan signal Scan (N) is input as a low-level voltage to the scanning section P2, the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh-first transistor T71, and the seventh-second transistor T72 can be turned on. A more specific example of the scanning section P2 will be described with reference to Fig. 11 described.

[0145] In this aspect, the rise time of the light emission signal EM(N) may be a predetermined time before a start time of the initialization section P1. This is intended to enable stable operation of the initialization section P1. The fall time of the light emission signal EM(N) may be a predetermined time after an end time of the sampling section P2. This enables stable operation of the sampling section P2. However, the present disclosure is not limited to this. In some cases, the rise time may correspond to the end time of the sampling section P2.

[0146] In this aspect, the holding section P3 may be a section for holding a state of a starting point of the holding section P3 or a state of an end point of the scanning section P2. The pixel circuit may be held in a constant state for the holding section P3. For example, in the holding section P3, a state established immediately after the scanning section P2, that is, a state in which no voltage is applied to the pixel circuit, as if the voltage application is stopped for a moment, may be held constant.

[0147] According to the aspect, in the holding section P3, the light emission signal EM (N), the first scanning signal Scan (N) and the second scanning signal Scan (N-1) can be input as high level voltages.

[0148] In the aspect, the light-emitting section P4 may be initiated based on the light-emitting signal EM(N) transitioning from the high-level voltage to the low-level voltage. In the light-emitting section P4, the first light-emitting element ED1 and / or the second light-emitting element ED2 may emit light. In the light-emitting section P4, the first scanning signal Scan(N) and the second scanning signal Scan(N-1) may be input as high-level voltages. In the light-emitting section P4, the light-emitting signal EM(N) may be input as a low-level voltage. A more specific example of the light-emitting section P4 will be described with reference to Fig. 12 and / or Fig. 13 described.

[0149] In this aspect, the initialization section P1, the scanning section P2, the holding section P3, and the light emission section P4 may be executed sequentially. However, the present disclosure is not limited to this. In some cases, another section may be added between at least two sections, or at least one section may be excluded.

[0150] Fig. 10 is a view for explaining an operation of the pixel circuit in the initialization section of the display device according to the aspect of the present disclosure. The driving sections of the pixel circuit are described with reference to Fig. 9 described.

[0151] With reference to Fig. 10 can be in the initialization section (e.g. the initialization section P1 in Fig. 9), when the second scan signal Scan(N-1) is input as a low level voltage, the second transistor T2 and the eighth transistor T8 are turned on.

[0152] In this case, the high-potential voltage VDD can be input to the first node N1 via the second transistor T2. The initialization voltage Vini can be input to the second node N2 via the eighth transistor T8. Since the initialization voltage Vini is input to the second node N2, the voltage of the second node N2 can be changed to be close to a value of the initialization voltage Vini. In this case, the first node N1 can be connected to the first electrode of the capacitor Cst, and the second node N2 can be connected to the second electrode of the capacitor Cst.

[0153] In this case, the reference voltage Vref can be input to the third node N3 via the fifth transistor T5. The initialization voltage Vini can be input to the second node N2 via the fourth-second transistor T42, the second transistor T2, the third transistor T3, and a seventh transistor T7. When the initialization voltage Vini is input to the second node N2, the voltage of the second node N2 can be changed to be close to a value of the initialization voltage Vini.

[0154] In this aspect, in the initialization section, the first control signal S(k) and the second control signal P(k) may be input as high-level voltages. In this case, the fourth first transistor T41 and the fourth second transistor T42 may be in an off state.

[0155] Fig. 11 is a view for explaining an operation of the pixel circuit in the scanning section of the display device according to the aspect of the present disclosure.

[0156] With reference to Fig. 11 can be in the scanning section (e.g. the scanning section P2 in Fig. 9) The first scan signal Scan(N) can be input as a low-level voltage. The second scan signal Scan(N-1) and the light emission signal EM(N) can be input as high-level voltages. In this case, the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh first transistor T71, and the seventh second transistor T72 can be turned on in the scanning section.

[0157] In this aspect, when the seventh-first transistor T71 and the seventh-second transistor T72 are turned on, the initialization voltage Vini can be supplied to the anode electrode of the first light-emitting element ED1 and the anode electrode of the second light-emitting element ED2 via the seventh-first transistor T71 and the seventh-second transistor T72. When the first transistor T1 is turned on, the reference voltage Vref can be supplied to the first node N1 via the first transistor T1. When the fifth transistor T5 and the sixth transistor T6 are turned on, the data voltage Vdata can be supplied to the second node N2 via the fifth transistor T5 and the sixth transistor T6. The first electrode of the capacitor Cst can be charged with the reference voltage Vref, and the second electrode of the capacitor Cst can be charged with the data voltage Vdata.In this case, writing data can be performed.

[0158] In the aspect, the voltage of the second node N2 may gradually increase to a value corresponding to a difference between the high potential voltage VDD and a threshold voltage Vth.

[0159] The holding section (e.g. the holding section P3 in Fig. 9) can be after the scanning section (e.g. the scanning section P2 in Fig. 9) in Fig. 11. In the holding section, the first scanning signal Scan(N), the second scanning signal Scan(N-1), and the light emission signal EM(N) can be provided as high-level voltages. In this case, the transistors, e.g., the driver transistor DT and the first to tenth transistors T1 to T10 included in the pixel circuit, can be turned off. Therefore, the state of the scanning section can be maintained without a separate electric current flowing in the pixel circuit.

[0160] Fig. 12 and Fig. 13 are views for explaining an operation of the pixel circuit in the light emitting section of the display device according to the aspect of the present disclosure.

[0161] Fig. 12 may show a case where the first control signal S(k) is provided as a low-level voltage. Fig. Figure 13 may show a case where the second control signal P(k) is provided as a low-level voltage. The first control signal S(k) and the second control signal P(k) are signals that are provided individually. The two signals, which have low-level voltages, may be provided simultaneously or at different times.

[0162] With reference to Fig. 12, in the light-emitting section, the light-emitting signal EM(N) and the first control signal S(k) can be input as low-level voltages. The first scan signal Scan(N) and the second scan signal Scan(N-1) can be input as high-level voltages. In this case, the third transistor T3, the ninth transistor T9, the tenth transistor T10, and the fourth-first transistor T41 can be turned on.

[0163] In the aspect, the first control signal S(k) having the low-level voltage may be provided based on the pixel circuit operating in the first mode. The first mode may include a mode in which the content is provided to both the driver's seat and the passenger's seat. The second mode described below may include a mode in which the field of view of the driver's seat is restricted and the content is provided to the passenger's seat. The viewing angle in the first mode may be larger than the viewing angle in the second mode.

[0164] In the aspect where the pixel circuit operates in the first mode, the driver transistor DT, the third transistor T3, the ninth transistor T9, the tenth transistor T10, and the fourth-first transistor T41 can be turned on to define the current path. The high-potential voltage VDD can be input to the anode electrode of the first light-emitting element ED1. Therefore, the first light-emitting element ED1 can emit light.

[0165] With reference to Fig. 13, in the light-emitting section, the light-emitting signal EM(N) and the second control signal P(k) can be input as low-level voltages. The first scan signal Scan(N) and the second scan signal Scan(N-1) can be input as high-level voltages. In this case, the third transistor T3, the ninth transistor T9, the tenth transistor T10, and the fourth-second transistor T42 can be turned on.

[0166] In the aspect where the pixel circuit operates in the second mode, the driver transistor DT, the third transistor T3, the ninth transistor T9, the tenth transistor T10, and the fourth-second transistor T42 can be turned on to define the current path. The high-potential voltage VDD can be input to the anode electrode of the second light-emitting element ED2. Therefore, the second light-emitting element ED2 can emit light.

[0167] Fig. 14 is a view showing a pixel circuit of a display device according to another aspect of the present disclosure. A common circuit 1401 in Fig. 14 is an aspect different from the common circuit 701 in Fig. 7. A pixel circuit 1402 in Fig. 14 can be connected to the pixel circuit 702 in Fig. 7 be identical.

[0168] With reference to Fig. 14, the pixel may include common circuit 1401 and pixel circuit 1402. In this aspect, common circuit 1401 may include first transistor T1 and second transistor T2 connected in parallel. For example, the first transistor T1 and second transistor T2 of a common circuit 1501 may be connected in parallel between the reference voltage line and first node N1.

[0169] The first electrode of the first transistor T1 and the first electrode of the second transistor T2 may be connected to the reference voltage line configured to provide the reference voltage Vref. The second electrode of the first transistor T1 and the second electrode of the second transistor T2 may be connected to the third transistor T3. The first transistor T1 may be controlled by the first scan signal Scan(N), and the second transistor T2 may be controlled by the second scan signal Scan(N-1).

[0170] The circuit in Fig. 14 may include the initialization section, the sampling section, the holding section, and the light emission section. The signal timing in each of the sections may function in the same manner as in Fig. 9. However, the present disclosure is not limited thereto.

[0171] Fig. 15 is a view showing a common circuit and a pixel circuit of a display device according to another aspect of the present disclosure. An aspect will be described in which the common circuit 1501 is Fig. 15 with the common circuit 1401 in Fig. 14 is identical and a pixel circuit 1502 has a different shape than the pixel circuit 1402 in Fig. 14 and / or the pixel circuit 702 in Fig. 7.

[0172] With reference to Fig. 15, the first transistor T1 and the second transistor T2 of the common circuit 1501 may be connected in parallel between the reference voltage line and the first node N1. Compared to the pixel circuit 702 in Fig. 7, the pixel circuit 1502 may further include an additional capacitor Cbsm connected between the gate electrode and the first electrode of the driver transistor DT.

[0173] In this aspect, the sixth transistor T6 and / or the eighth transistor T8 may each comprise a transistor configured as a double gate. In this case, a leakage current in the sixth transistor T6 and / or the eighth transistor T8 is blocked, allowing the pixel circuit to operate more stably.

[0174] Although not shown, the pixel circuit 702 may be Fig. 7 may be configured in the same way as the pixel circuit 1502 in Fig. 15. In this case too, the signal timing can be Fig. 9 should be retained.

[0175] A pixel circuit and a display device according to exemplary aspects of the present disclosure may also be described as follows: A display device according to an exemplary aspect of the present disclosure comprises: a mode controller configured to generate a first control signal and a second control signal, a gate driver circuit configured to generate a light emission signal, a first scanning signal, and a second scanning signal, a common circuit connected to a reference voltage line configured to provide a reference voltage, the common circuit comprising: a first transistor configured to operate based on the first scanning signal, and a second transistor connected in series with the first transistor and configured to operate based on the second scanning signal, and a first pixel circuit connected to the mode controller and the gate driver circuit,wherein the first pixel circuit comprises: a driver transistor, a third transistor configured to operate based on the light emission signal and connected to the second transistor, a fourth first transistor configured to operate based on the first control signal, a fourth second transistor configured to operate based on the second control signal, a first light emission element connected to the fourth first transistor, a second light emission element connected to the fourth second transistor, and a capacitor connected to the first transistor, the second transistor, the third transistor, and the driver transistor.

[0176] In the aspects, the display device may further include a second pixel circuit having at least two light emitting elements adjacent to the first pixel circuit and configured to emit light having a different color than the light emitted by the first and second light emitting elements, wherein the second pixel circuit is connected to the common circuit.

[0177] In the aspects, a first electrode of the third transistor may be connected to a high potential voltage line and a second electrode of the second transistor, and a second electrode of the third transistor may be connected to a first electrode of the second transistor and the capacitor.

[0178] In the aspects, a first electrode of the first transistor may be connected to the reference voltage line, and a second electrode of the first transistor may be connected to the second transistor.

[0179] In the aspects, a first electrode of the second transistor may be connected to at least one of the first transistor, the third transistor, and the capacitor, and a second electrode of the second transistor may be connected to at least one of a high-potential voltage line and the third transistor.

[0180] In the aspects, a first electrode of the third transistor may be connected to the high potential voltage line and the second electrode of the second transistor, and a second electrode of the third transistor may be connected to the first electrode of the second transistor and the capacitor.

[0181] In the aspects, the display device may further include: a fifth transistor connected to the driver transistor and a data voltage line and configured to operate based on the first scan signal, and a sixth transistor connected to a gate electrode of the driver transistor and configured to operate based on the first scan signal.

[0182] In the aspects, the display device may further include: a seventh-first transistor connected to an initialization voltage line, the fourth-first transistor, and the first light-emitting element and configured to operate based on the first scan signal; and a seventh-second transistor connected to the initialization voltage line, the fourth-second transistor, and the second light-emitting element and configured to operate based on the first scan signal.

[0183] In the aspects, the display device may further include an eighth transistor connected to a gate electrode of the driver transistor, the seventh first transistor, the seventh second transistor, and the initialization voltage line, and configured to operate based on the second scanning signal.

[0184] In the aspects, the display device may further include a ninth transistor connected to a high potential voltage line, the second transistor, the third transistor, and the driver transistor and configured to operate based on the light emission signal.

[0185] In the aspects, a first electrode of the fourth first transistor and a first electrode of the fourth second transistor may be connected to the driver transistor, a second electrode of the fourth first transistor may be connected to the first light emitting element, and a second electrode of the fourth second transistor may be connected to the second light emitting element.

[0186] In the aspects, the display device may further include a tenth transistor connected between the driver transistor and the fourth-first transistor or between the driver transistor and the fourth-second transistor and configured to operate based on the light emission signal.

[0187] In the aspects, the first pixel circuit may operate in an initialization section, a scanning section, a holding section, or a light emission section.

[0188] In the aspects, in the initialization section, the first scan signal and the light emission signal have a first level and the second scan signal has a second level, wherein in the sampling section, the first scan signal has the second level and the second scan signal and the light emission signal have the first level, wherein in the holding section, the first scan signal, the second scan signal, and the light emission signal have the first level, and wherein in the light emission section, the first scan signal and the second scan signal have the first level and the light emission signal has the second level.

[0189] In aspects, the first level may be higher than the second level.

[0190] Although the exemplary aspects of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary aspects of the present disclosure are provided for illustration only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. It should therefore be understood that the exemplary aspects described above are illustrative in all respects and do not limit the present disclosure. The scope of the present disclosure should be interpreted based on the following claims. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2023-0085177

[0001]

Claims

[1] Display device (100) comprising: a mode controller configured to generate a first control signal (S(k)) and a second control signal (P(k)); a gate driver circuit (GD) configured to generate a light emission signal (EM(N)), a first scan signal (Scan(N)) and a second scan signal (Scan(N-1)); a common circuit (701) connected to a reference voltage line (711) and configured to provide a reference voltage (Vref), the common circuit (701) comprising: a first transistor (T1) configured to operate based on the first scan signal (Scan(N)), and a second transistor (T2) connected in series with the first transistor (T1) and configured to operate based on the second scan signal (Scan(N-1)); and a first pixel circuit (702) connected to the mode control device and the gate driver circuit (GD), wherein the first pixel circuit (702) comprises: a driver transistor (DT); a third transistor (T3) configured to operate based on the light emission signal (EM(N)) and connected to the second transistor (T2); a fourth-first transistor (T41) configured to operate based on the first control signal (S(k)); a fourth-second transistor (T42) configured to operate based on the second control signal (P(k)); a first light emitting element (ED1) connected to the fourth-first transistor (T41); a second light-emitting element (ED2) connected to the fourth-second transistor (T42); and a capacitor (Cst) connected to the first transistor (T1), the second transistor (T2), the third transistor (T3) and the driver transistor (DT). [2] The display device (100) according to claim 1, further comprising a second pixel circuit (802) having at least two light emitting elements adjacent to the first pixel circuit (702) and configured to emit light having a different color than the light emitted by the first and second light emitting elements (ED1, ED2), the second pixel circuit (802) being connected to the common circuit (701). [3] The display device (100) according to claim 2, wherein a first electrode of the third transistor (T3) is connected to a high potential voltage line (717) and a second electrode of the second transistor (T2), and a second electrode of the third transistor (T3) is connected to a first electrode of the second transistor (T2) and the capacitor (Cst). [4] The display device (100) according to any one of claims 1 to 3, wherein a first electrode of the first transistor (T1) is connected to the reference voltage line (711) and a second electrode of the first transistor (T1) is connected to the second transistor (T2). [5] The display device (100) according to claim 1 or 2, wherein a first electrode of the second transistor (T2) is connected to at least one of the first transistor (T1), the third transistor (T3) and the capacitor (Cst), and a second electrode of the second transistor (T2) is connected to at least one of a high-potential voltage line (717) and the third transistor (T3). [6] The display device (100) according to claim 5, wherein a first electrode of the third transistor (T3) is connected to the high potential voltage line (717) and the second electrode of the second transistor (T2), and a second electrode of the third transistor (T3) is connected to the first electrode of the second transistor (T2) and the capacitor (Cst). [7] The display device (100) according to any one of claims 1 to 6, further comprising a fifth transistor (T5) connected to the driver transistor (DT) and a data voltage line (716) and configured to operate based on the first scan signal (Scan(N)); and a sixth transistor (T6) connected to a gate electrode of the driver transistor (DT) and configured to operate based on the first scan signal (Scan(N)). [8] The display device (100) according to any one of claims 1 to 7, further comprising a seventh-first transistor (T71) connected to an initialization voltage line (712), the fourth-first transistor (T41) and the first light-emitting element (ED1) and configured to operate based on the first scan signal (Scan(N)); and a seventh-second transistor (T72) connected to the initialization voltage line (712), the fourth-second transistor (T42) and the second light-emitting element (ED2) and configured to operate based on the first scan signal (Scan(N)). [9] The display device (100) according to claim 8, further comprising an eighth transistor (T8) connected to a gate electrode of the driver transistor (DT), the seventh-first transistor (T71), the seventh-second transistor (T72) and the initialization voltage line (712) and configured to operate based on the second scan signal (Scan(N-1)). [10] The display device (100) according to any one of claims 1 to 9, further comprising a ninth transistor (T9) connected to a high potential voltage line (717), the second transistor (T2), the third transistor (T3) and the driver transistor (DT) and configured to operate based on the light emission signal (EM(N)). [11] The display device (100) according to any one of claims 1 to 10, wherein a first electrode of the fourth-first transistor (T41) and a first electrode of the fourth-second transistor (T42) are connected to the driver transistor (DT), a second electrode of the fourth-first transistor (T41) is connected to the first light-emitting element (ED1), and a second electrode of the fourth-second transistor (T42) is connected to the second light-emitting element (ED2). [12] The display device (100) according to claim 11, further comprising a tenth transistor (T10) connected between the driver transistor (DT) and the fourth-first transistor (T41) or between the driver transistor (DT) and the fourth-second transistor (T42) and configured to operate based on the light emission signal (EM(N)). [13] The display device (100) according to claim 11 or 12, wherein the first pixel circuit (702) operates in an initialization section (P1), a scanning section (P2), a holding section (P3) or a light emitting section (P4). [14] The display device (100) according to claim 13, wherein in the initialization section (P1), the first scanning signal (Scan(N)) and the light emission signal (EM(N)) have a first level and the second scanning signal (Scan(N-1)) has a second level, wherein in the scanning section (P2) the first scanning signal (Scan(N)) has the second level, and the second scanning signal (Scan(N-1)) and the light emission signal (EM(N)) have the first level, wherein in the holding section (P3) the first scanning signal (Scan(N)), the second scanning signal (Scan(N-1)) and the light emission signal (EM(N)) have the first level, and wherein in the light emission section (P4), the first scanning signal (Scan(N)) and the second scanning signal (Scan(N-1)) have the first level and the light emission signal (EM(N)) has the second level. [15] The display device (100) of claim 14, wherein the first level is higher than the second level. [16] Display device (100) comprising: a common circuit (701) providing a reference voltage (Vref), configured to operate based on a first scan signal (Scan(N)) and a second scan signal (Scan(N-1)), and having a first node (N1); and a first, second and third pixel circuit (702, 802, 812) which share the common circuit (701) during operation, wherein the second pixel circuit (802) is adjacent to at least one of the first and third pixel circuits (702, 812) and has at least two light-emitting elements configured to emit light of a different color than the light emitted by the first and second light-emitting elements (ED1, ED2) of the first pixel circuit (702), wherein the third pixel circuit (812) is adjacent to at least one of the first and second pixel circuits (702, 802) and has at least two light-emitting elements configured to emit light of a different color than the light emitted by the first and second light-emitting elements (ED1, ED2) of the first pixel circuit (702) and the first and second light-emitting elements of the second pixel circuit (802), and wherein the common circuit (701) and the first, second and third pixel circuits (702, 802, 812) are electrically connected via the first node (N1) to receive at least one of the reference voltage (Vref), a high potential voltage (VDD), a low potential voltage (VSS), a light emission signal (EM(N)), a data voltage (Vdata) and an initialization voltage (Vini). [17] The display device (100) of claim 16, further comprising: a first scan signal line (718) providing the first scan signal (Scan(N)) in a first direction; a second scan signal line (713) providing the second scan signal (Scan(N-1)) in the first direction; a light emission signal line (715) providing the light emission signal (EM(N)) in the first direction; and a high potential voltage line (717) providing the high potential voltage (VDD) in the first direction. [18] The display device (100) of claim 17, further comprising: a reference voltage line (711) providing the reference voltage (Vref) in a second direction; a high potential voltage line (717) providing the high potential voltage (VDD) in the second direction; a data voltage line (716) providing the data voltage (Vdata) in the second direction; and an initialization voltage line (712) for providing the initialization voltage (Vini) in the second direction. [19] The display device (100) according to claim 17 or 18, wherein the first node (N1) is arranged between the first scanning signal line (718) and the light emission signal line (715). [20] The display device (100) according to claim 18, wherein the reference voltage line (711) and the high potential voltage line (717) are arranged to overlap at least a part of the common circuit (701). [21] The display device (100) of claim 17, further comprising a high potential voltage line (717) arranged in the first and second directions to define a mesh shape. [22] The display device (100) of claim 18, wherein the data voltage line (716) and the initialization voltage line (712) overlap at least a portion of the first pixel circuit (702). [23] The display device (100) according to claim 18, wherein the reference voltage line (711) and the high potential voltage line (717) are arranged in the first, second and third pixel circuits (702, 802, 812) and overlap at least a part of the first, second and third pixel circuits (702, 802, 812).

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