Application programming interface for specifying memory

Abstract

Devices, systems, and techniques for indicating whether one or more memories correspond to one or more non-unitary memory (NUMA) memories. In at least one embodiment, one or more circuits execute an application programming interface (API) to indicate whether one or more memories specified by one or more users of the API correspond to one or more NUMA memories or one or more graphics processing unit (GPU) memories.

Description

TECHNICAL FIELDAt least one embodiment relates to processing resources used to perform one or more programs written for a parallel computing platform and application interface. For example, at least one embodiment relates to processors or computing systems that perform an application programming interface (API) according to various novel techniques described herein.BACKGROUNDPerforming memory management operations may use significant time, power, or compute resources. The amount of time, power, or computational resources may be improved.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a block diagram illustrating a computing environment, according to at least one embodiment; FIG. 2 illustrates performing an API to access one or more non-uniform memory access (NUMA) nodes, according to at least one embodiment; FIG. 3 illustrates performing an API to store information in one or more NUMA memories, according to at least one embodiment; FIG. 4 illustrates performing an API to indicate whether one or more memories correspond to one or more NUMA memories, according to at least one embodiment; FIG. 5 is a flow diagram of a technique for accessing one or more NUMA nodes, according to at least one embodiment; FIG. 6 is a flow diagram of a technique for storing information in one or more NUMA memories, according to at least one embodiment; FIG. 7 is a flow diagram of a technique for indicating whether one or more memories correspond to one or more NUMA memories, according to at least one embodiment; FIG. 8 is a block diagram illustrating an example of a processor according to at least one embodiment; FIG. 9 is a block diagram illustrating a driver and / or runtime environment, according to at least one embodiment; FIG. 10 illustrates an example data center, according to at least one embodiment; FIG. 11 illustrates a processing system according to at least one embodiment; FIG. 12 illustrates a computer system according to at least one embodiment; FIG. 13 illustrates a system according to at least one embodiment; FIG. 14 illustrates an example integrated circuit according to at least one embodiment; FIG. 15 illustrates a computer system according to at least one embodiment; FIG. 16 illustrates an APU according to at least one embodiment; FIG. 17 illustrates a CPU according to at least one embodiment; FIG. 18 illustrates an example accelerator integration slice, according to at least one embodiment; FIGS. 19A-19B illustrate example graphics processors, according to at least one embodiment; FIG. 20A illustrates a graphics core according to at least one embodiment; FIG. 20B illustrates a GPGPU according to at least one embodiment; FIG. 21A illustrates a parallel processor according to at least one embodiment; FIG. 21B illustrates a processing cluster according to at least one embodiment; FIG. 21C illustrates a graphics multiprocessor according to at least one embodiment; FIG. 22 illustrates a graphics processor according to at least one embodiment; FIG. 23 illustrates a processor according to at least one embodiment; FIG. 24 illustrates a processor according to at least one embodiment; FIG. 25 illustrates a graphics processor core, according to at least one embodiment; FIG. 26 illustrates a PPU according to at least one embodiment; FIG. 27 illustrates a GPC, according to at least one embodiment; FIG. 28 illustrates a streaming multiprocessor according to at least one embodiment; FIG. 29 illustrates a software stack of a programming platform, according to at least one embodiment; FIG. 30 illustrates a CUDA implementation of a software stack of FIG. 29, in accordance with at least one embodiment; FIG. 31 illustrates a ROCm implementation of a software stack of FIG. 29, in accordance with at least one embodiment; FIG. 32 illustrates an OpenCL implementation of a software stack of FIG. 29, according to at least one embodiment; FIG. 33 illustrates software supported by a programming platform, according to at least one embodiment; FIG. 34 illustrates compilation code for execution on programming platforms of FIGS. 29-32, in accordance with at least one embodiment; FIG. 35 illustrates in more detail compilation code for execution on programming platforms of FIGS. 29-32, in accordance with at least one embodiment; FIG. 36 illustrates translating source code prior to compiling source code, in accordance with at least one embodiment; FIG. 37A illustrates a system configured to compile and execute CUDA source code using various types of processing units, according to at least one embodiment; FIG. 37B illustrates a system configured to compile and execute CUDA source code of FIG. 37A using a CPU and a CUDA-capable GPU, according to at least one embodiment; FIG. 37C illustrates a system configured to compile and execute CUDA source code of FIG. 37A using a CPU and a non-CUDA-capable GPU, according to at least one embodiment; FIG. 38 illustrates an example kernel translated by the CUDA to HIPUsetzungs tool of FIG. 37C, according to at least one embodiment; FIG. 39 illustrates a non-CUDA-capable GPU of FIG. 37C in more detail according to at least one embodiment; FIG. 40 illustrates how threads of an example CUDA grid are mapped to different compute units of FIG. 39, in accordance with at least one embodiment; FIG. 41 illustrates how existing CUDA code is migrated to data parallel C++ code, according to at least one embodiment; and FIG. 42 illustrates components of a system for accessing a large language model, according to at least one embodiment.DETAILED DESCRIPTIONIn the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, it will be apparent to those skilled in the art that the inventive concepts may be practiced without one or more of these specific details.FIG. 1 is a block diagram illustrating a computing environment 100, according to at least one embodiment. In at least one embodiment, a computer system 102 includes a set of non-uniform memory access (NUMA) nodes 104 and a set of parallel processing units (PPUs) 106 (e.g., one or more accelerators, such as a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and / or another suitable device). In at least one embodiment, set of PPUs 106 includes a set of graphics processing units (GPUs). In at least one embodiment, set of NUMA nodes 104 includes a NUMA node 108 that includes a processor 110 and a memory 112. In at least one embodiment, set of NUMA nodes 104 includes a NUMA node 114 that includes a processor 116 and a memory 118. In at least one embodiment, set of NUMA nodes 104 are host NUMA nodes and GPUs in set of PPUs 106 are devices.In at least one embodiment, a NUMA node includes a set of hardware components (e.g., one or more processors, one or more memories, such as memory, one or more other types of memory devices, one or more networking components, and / or other suitable components). In at least one embodiment, in a system having a NUMA node architecture and / or that allows sets of hardware to be treated as NUMA nodes, NUMA nodes may access memory in other NUMA nodes and / or GPUs, but have faster access with less latency to memory within NUMA node. In at least one embodiment, computer system 102 is a server platform having more than one system bus. In at least one embodiment, different processor sockets are located on a multi-socket motherboard in different NUMA nodes.In at least one embodiment, set of PPUs 106 includes a GPU 120 and a GPU 122. In at least one embodiment, set of GPUs 106 includes a different number of GPUs (e.g., less than or more than two GPUs). In at least one embodiment, GPU 120 includes GPU memory 124, and GPU 122 includes GPU memory 126. In at least one embodiment, GPU memory 124 and / or GPU memory 126 includes more than one level and / or type of memory (e.g., global memory that is accessible by entire GPU, memory that is accessible by a subset of processors on GPU, cache memory that is accessible by a single processor on GPU, shared memory that is accessible by a particular group of threads).In at least one embodiment, GPU 120 includes one or more processors 128. In at least one embodiment, GPU 122 includes one or more processors, which are not shown for clarity. In at least one embodiment, a different number of processors (e.g., more than one processor 110 and / or processor 116) and / or a different number of memories (e.g., more than one memory 112 and / or memory 118) are included in computer system 102. In at least one embodiment, one or more of processor 110 and processor 116 are a central processing unit (CPU). In at least one embodiment, both processor 110 and processor 116 are CPUs. In at least one embodiment, computer system 102 includes one or more other components not shown for clarity (e.g., a network interface card, a persistent storage device, one or more input devices, one or more output devices, and / or one or more other suitable components). In at least one embodiment, computer system 102 includes a different number of NUMA nodes. In at least one embodiment, NUMA node 108 and / or NUMA node 114 include one or more other components, which are not shown for clarity. In at least one embodiment, NUMA node 108 and / or NUMA node 114 includes a different number of processors and / or memories.In at least one embodiment, one or more of processor 110 and processor 116 is a single core processor. In at least one embodiment, one or more of processor 110 and processor 116 is a multi-core processor. In at least one embodiment, one or more of processor 110 and processor 116 is an element of a processing system, such as processing system 1100 described herein. In at least one embodiment, one or more of processor 110 and processor 116 is an element of a computer system, such as computer system 1200 described herein. In at least one embodiment, one or more of processor 110 and processor 116 is an element of a system, such as system 1300 described herein. In at least one embodiment, one or more of processor 110 and processor 116 is an element of a computing system, such as computing system 1500 described herein. In at least one embodiment, one or more of processor 110 and processor 116 is an element of a computing device, such as computing device 3940 described herein. In at least one embodiment, one or more of processor 110 and processor 116 is another processor shown and / or described herein.In at least one embodiment, one or more GPUs (e.g., GPU 120) in set of PPUs 106 is a graphics processor 1910 described herein. In at least one embodiment, one or more GPUs (e.g., GPU 120) in set of PPUs 106 is a graphics processor 1940 described herein. In at least one embodiment, one or more GPUs (e.g., GPU 120) in set of PPUs 106 is a graphics multiprocessor 2134. In at least one embodiment, one or more GPUs (e.g., GPU 120) in set of PPUs 106 is a graphics processor 2200 described herein. In at least one embodiment, one or more GPUs (e.g., GPU 120) in set of PPUs 106 is a graphics processor 2408. In at least one embodiment, one or more GPUs (e.g., GPU 120) in set of PPUs 106 is a GPU 3792 described herein. In at least one embodiment, one or more GPUs (e.g., GPU 120) in set of PPUs 106 is another GPU shown and / or described herein. In at least one embodiment, computer system 102 includes one or more accelerators (e.g., one or more parallel processing units (PPUs), FPGAs, ASICs, and / or other suitable accelerators) instead of or in addition to GPUs in set of PPUs 106.In at least one embodiment, computer system 102 includes a set of APIs 130. In at least one embodiment, when one or more APIs are referred to as performing an action or aspect of a technique, one or more hardware components (e.g., a CPU, a GPU, and / or other hardware component) of a computer system executing an API perform that action or aspect of technique. In at least one embodiment, set of APIs 130 is a set of APIs for GPUs in set of PPUs 106 and / or one or more NUMA nodes of set of NUMA nodes 104. In at least one embodiment, one or more operations described with respect to GPUs in set of PPUs 106 and / or APIs in set of APIs 130 are performed by one or more accelerators, not shown for clarity, that are not GPUs. In at least one embodiment, set of APIs 130 is referred to as an API (e.g., a driver API) that includes multiple callable functions. In at least one embodiment, set of APIs 130 is implemented in a dynamic library. In at least one embodiment, set of APIs 130 is a handle-based, imperative API. In at least one embodiment, set of APIs 130 is a parallel processing framework API (e.g., a CUDA driver API (CUDA= Comp Unified Device Architecture), a HIP API (HIP= Heterogene-Compute Interface for Portability), or another API).In at least one embodiment, one or more APIs in set of APIs 130 are high-level APIs (e.g., accessed using a high-level programming language such as C++, Python, Java, Fortran, C, or other suitable language). In at least one embodiment, one or more APIs in set of APIs 130 are low-level APIs (e.g., that are accessed using instructions of a programming framework, such as CUDA PTX instructions or other suitable intermediate representation that can be compiled to a machine-level binary representation for a particular hardware architecture). In at least one embodiment, one or more APIs of set of APIs 130 may also be implemented as instructions such as PTX, assembly, x86, GPU instruction set architecture (ISA), machine level, or other suitable type of instructions.In at least one embodiment, set of APIs 130 is a set of APIs for a programming platform. In at least one embodiment, a programming platform may be, but is not limited to, CUDA, Radon open compute platform ("ROCm"), OpenCL (OpenCL™ is developed by Khronos Group), SYCL, or Intel One API. Although in at least one embodiment, some aspects of APIs and / or techniques for combining operations related to CUDA are discussed, including CUDA APIs and / or CUDA kernels, it should be appreciated that ROCm, OpenCL, SYCL, One API, and / or any other suitable APIs and / or kernels may be used. In at least one embodiment, one or more APIs in set of APIs 130 are at least partially accessed by including a header file in one or more portions of code defining one or more functions of one or more APIs. In at least one embodiment, one or more APIs in set of APIs are functions (e.g., defined in a function library).In at least one embodiment, one or more APIs in set of APIs 130 perform one or more actions with respect to a range of memory. In at least one embodiment, range of memory is a range of virtual memory accessible by one or more NUMA nodes (e.g., processors of one or more host NUMA nodes) and one or more GPUs. In at least one embodiment, range of memory is virtual memory managed by one or more drivers not shown for clarity and / or one or more memory managers not shown for clarity. In at least one embodiment, managed memory is referred to as unified memory. In at least one embodiment, managed memory is allocated using one or more functions and / or APIs (e.g., cuMemAlloMan) and / or declared using a particular declaration statement (e.g., using _managed_variants).In at least one embodiment, set of APIs 130 includes a storage location preference API 132. In at least one embodiment, storage location preference API 132 is referred to as a managed storage preference indication API. In at least one embodiment, storage location preference API 32 is referred to as cuMemIse_v2(), cudaMemAdvise_v2(), or by another suitable API name. In at least one embodiment, storage location preference API 132 is to set a preferred storage location of a range of managed virtual storage that can be accessed by one or more GPUs and one or more CPUs as a NUMA node based at least in part on an identifier of a NUMA node (e.g., a NUMA ID) provided as one or more inputs to storage location preference API 132. In at least one embodiment, storage location preference API 132 is to cause one or more NUMA nodes (e.g., memory 112 of NUMA node 108) or one or more physical addresses of memory associated with one or more GPUs (e.g., GPU memory 124) to be accessed based at least in part on one or more indicia within API. In at least one embodiment, one or more aspects of storage location preference API 132 are further described with respect to one or more of API 200 of FIG. 2, technique 500 of FIG. 5, managed storage preference display module 804 of FIG. 8, and / or managed storage preference location function 916 of FIG. 9.In at least one embodiment, set of APIs 130 includes a memory prefetch API 134. In at least one embodiment, memory prefetch API 134 is referred to as an asynchronous managed memory prefetch API. In at least one embodiment, memory prefetch API 134 is referred to as cuMemPrefetchAsync_v 2( ), cudaMemPrefetchAsync_v 2( ), or by another suitable API name. In at least one embodiment, memory prefetch API 134 is to cause data stored in a range of virtual memory that can be accessed by one or more CPUs and one or more GPUs to be prefetched into a memory of a NUMA node based at least in part on an identifier of a NUMA node (e.g., a NUMA ID) provided as one or more inputs to memory prefetch API 134. In at least one embodiment, memory prefetch API 134 is to cause information to be stored in one or more NMA memories (e.g., memory 112 of NUMA node 108) or one or more physical GPU memories (e.g., memory 124 of GPU 120), based at least in part on one or more indicators to be displayed by one or more users of memory prefetch API 134. In at least one embodiment, memory prefetch API 134 is to cause information to be read from one or more NUMA memories (e.g., memory 112 of NUMA node 108) or one or more physical GPU memories (e.g., memory 124 of GPU 120), based at least in part on one or more indicators to be displayed by one or more users of memory prefetch API 134. In at least one embodiment, one or more aspects of memory prefetch API 134 are further described with respect to one or more of API 300 of FIG. 3, technique 600 of FIG. 6, managed memory prefetch module 806 of FIG. 8, and / or managed prefetch memory function 918 of FIG. 9.In at least one embodiment, set of APIs 130 includes a Get Storage Attribute API 136. In at least one embodiment, get storage attribute API 136 is referred to as a get managed storage attribute API. In at least one embodiment, Get Storage Attribute API 136 is referred to as cuMemRangeGetAttribute( ) or by another suitable API name. In at least one embodiment, get memory attribute API 136 is to indicate, return, and / or otherwise provide an indication of a NUMA node that was previously specified (e.g., last specified by location preference API 132) as a preferred location of a range of managed virtual memory that can be accessed by one or more CPUs and one or more GPUs. In at least one embodiment, get memory attribute API 136 is to display, return, and / or otherwise provide an indication of a NUMA node that is pre-fetched (e.g., last pre-fetched using memory pre-fetch API 134) a range of managed virtual memory that is accessible to one or more CPUs and one or more GPUs. In at least one embodiment, get storage attribute API 136 is to indicate whether one or more memories indicated by one or more users of get storage attribute API 136 correspond to one or more NUMA memories or one or more GPU memories. In at least one embodiment, one or more aspects of get storage attribute API 136 are further described with respect to one or more of API 400 of FIG. 4, technique 700 of FIG. 7, managed storage attribute module 808 of FIG. 8, and / or managed storage attribute function 920 of FIG. 9. In at least one embodiment, set of APIs 130 includes one or more other APIs not shown for clarity (e.g., one or more memory allocation APIs for allocating managed memory that can be accessed by both CPUs and GPUs, one or more synchronization APIs, and / or other suitable APIs).In at least one embodiment, a compiler 138 translates requests received via APIs in set of APIs 130 into instructions (e.g., generates instructions that are part of an instruction set architecture for GPU 120) that may be executed on GPU 120 and / or one or more NUMA nodes in set of NUMA nodes 104. In at least one embodiment, generated instructions are stored as code 140 that is copied to one or more GPUs in set of PPUs 106 (e.g., GPU 120) to be executed. In at least one embodiment, one or more threads use one or more APIs in set of APIs 130, and may pass one or more arguments to APIs in set of APIs. In at least one embodiment, set of APIs 130 includes one or more APIs that can be used by code implemented at a higher level (e.g., C++ style implementation) and / or that can be used by code implemented at an intermediate level (e.g., PTX style instructions). In at least one embodiment, one or more APIs in set of APIs 130 provide at least one function that can be accessed by an application 142. In at least one embodiment, a user provides one or more parameters (e.g., information as one or more inputs) to APIs in set of APIs 130. In at least one embodiment, user is a program that invokes and / or uses one or more API functions.In at least one embodiment, computer system 102 includes a set of nodes 144. In at least one embodiment, set of nodes 144 includes a node 146, a node 148, and a node 150. In at least one embodiment, set of nodes 144 includes a different number of nodes. In at least one embodiment, nodes in set of nodes 144 include one or more GPUs and / or one or more NUMA nodes. In at least one embodiment, kernel information (e.g., based at least in part on code 140) is copied to one or more GPUs included in one or more nodes in set of nodes 144. In at least one embodiment, one or more components and / or aspects of computer system 102 and / or set of nodes 144 are implemented with one or more hardware components, one or more software components, one or more circuits, dedicated hardware such as fixed function circuits, and / or any other suitable type of hardware, software, or combination thereof.In at least one embodiment, as used in any implementation described herein, terms such as "module" and nominal verbs (e.g., compilers, drivers, managers, and / or other terms), unless otherwise clearly or expressly stated to the contrary from context, each refer to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide functionality described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein may include, for example, singly or in any combination, hardwired circuits, programmable circuits, state machine circuits, fixed function circuits, execution unit circuits, and / or firmware storing instructions executed by programmable circuits. In at least one embodiment, modules may be embodied jointly or individually as circuits forming part of a larger system, for example, an integrated circuit (IC), a system on chip (SoC), and so forth.FIG. 2 illustrates performing an API 200 to access one or more non-uniform memory access (NUMA) nodes (e.g., a node in the set of NUMA nodes 104 of FIG. 1 ), according to at least one embodiment. In at least one embodiment, performing API 200 to access one or more NUMA nodes includes causing a preferred location of a range of memory (e.g., virtual memory that can be accessed by one or more CPUs and one or more GPUs) to be set to a NUMA node. In at least one embodiment, one or more processors (e.g., processor 128, processor 110, and / or processor 116 of FIG. 1 ) are to perform API 200. In at least one embodiment, API 200 is to be performed using location preference API 132 of FIG. 1.In at least one embodiment, API 200 includes one or more parameters. In at least one embodiment, parameters of API 200 include one or more parameters to indicate a storage area. In at least one embodiment, API 200 parameters include a source parameter to indicate a pointer to a base memory address (e.g., in managed unified virtual memory that can be accessed by one or more CPUs and one or more GPUs), and a size parameter (e.g., a number in bytes) to indicate a size of memory area. In at least one embodiment, API 200 includes an information to be adjusted parameter to indicate a type of information to be adjusted (e.g., a preferred location). In at least one embodiment, rather than indicating that preferred location is a type of information to be set using a parameter, API 200 sets preferred location as a standard and / or is an API dedicated to setting preferred location type that does not include a parameter for information to be set. In at least one embodiment, API 200 includes a location parameter to indicate a preferred location (e.g., using a NUMA ID or an identifier of a GPU). In at least one embodiment, API 200 includes a different number and / or type of parameters. In at least one embodiment, a response 202 to performing API 200 includes an indication of whether performance of API 200 was successful (e.g., an operational status). In at least one embodiment, response 202 is not present (e.g., when API 200 has a Void Return Type).In at least one embodiment, an API signature and / or function prototype of API 200 (e.g., for use with a driver API) may be represented as: CUres cuMemAdvise_v2(CUdeviceptr dptr, size_t count, CUmem_advis advertisement CUmemLoc location); In at least one embodiment, CUdeviceptr dptr corresponds to source parameter, size_t count corresponds to size parameter, CUmem_advis advertisement information for setting parameter, and / or CUmemLoc location corresponds to location parameter. In at least one embodiment, an API signature and / or function prototype of API 200 (e.g., for use with a runtime API) may be referred to as: cudaError_t cudaMemAdv(constant void *dptr, size_t count, cudaMemoryAdv Adv Adv location); In at least one embodiment, constant void *dptr corresponds to source parameter, size_t count corresponds to size parameter, cudaMemory Adv Adv Adv information for setting parameter, and / or corresponding to cudaMem Location corresponds to location parameter. In at least one embodiment, an API signature and / or function prototype of API 200 is presented using another suitable API signature and / or function or interface prototype.In at least one embodiment, location parameter indicates a location type and a location identity (e.g., a NUMA node ID). In at least one embodiment, a NUMA node ID is information that uniquely identifies a NUMA node. In at least one embodiment, a NUMA node ID uniquely identifies a NUMA node for an operating system (OS). In at least one embodiment, location parameter is a data structure that includes a type field and an identifier field. In at least one embodiment, location type may be further understood with respect to CUmemLocType, which may be represented as: typedef enum CUmemLocationType_enum { CU_MEM_LOCATION_TYPE_INVALID = 0x0, CU_MEM_LOCATION_TYPE_DEVICE = 0x1, CU_MEM _LOCATION _TYPEHOST_NUMA = 0x2, CU_MEM_LOCATION_TYPE_HOST = 0x3, CU_MEM_LOCATIONTION_TYPE_HOST_NUMA_CURRENT = 0x4, CU_MEM_LOCATION_TYPE_MAX = 0x7FFFFF Cu12LocType,In at least one embodiment,CU_MEM_LOCATION_TYPE_DEVICE the location is a device location, and the id (e.g., the location identity) is a device ordinal. In at least one embodiment, with respect to CU_MEM_LOCATION_TYPE_HOST_NUMA location is a host NUMA node and id is a host NUMA node id. In at least one embodiment, with respect to CU_MEM_LOCATION_TYPE_HOST location is a host and id is ignored. In at least one embodiment,CU_MEM_LOCATION_TYPE HOST_NUMA_CURRENT the location a host NUMA node of the calling thread, and the id is ignored.In at least one embodiment, one or more APIs support host NUMA nodes. In at least one embodiment, host NUMA support for virtual memory manager (VMM) (e.g., CUDA-VMM) and memory pool assignments uses a driver (e.g., CUDA driver) CU_MEM _LOCATION_TYPE_HOST_NUMA as a enumeration type in CUmemLoc:: CUmemLocType. In at least one embodiment, CUmem::id specifies NUMA ID of a host CPU node when CUmemLoc::type is CU_MEM_LOCATION_TYPE_HOST_NUMA. In at least one embodiment, CUmem::id is ignored when CUmemLoc::type CU_MEM_LOCATION_TYPEHOSTist.In at least one embodiment, in some cases, NUMA node of current thread is a desired CPU NUMA node. In at least one embodiment, CU_MEM_LOCATION_TYPE_HOST_NUMA_CURRENT specifies a enumeration type of CUmemLocation::CUmemLocationType to specify usage of NUMA node of current thread. In at least one embodiment, CUmem::id is ignored if CUmemLoc::type is CU_MEM_LOCATION_TYPEHOST_NUMA_CURRENT. In at least one embodiment, corresponding cudaMemLocTypeHost and / or cudaMemLocationTypeHostNumaCurrent may also be used with cudaMemLocType.In at least one embodiment, location identifier (e.g., CUmemLoc::id) to be provided as input is a valid NUMA ID (e.g., a CPU NUMA ID) when information to be set (e.g., AdvantageParameter) is a set preferred location (e.g., CU_MEM_ADVISE_SET_PREFERRED_LOCATION) and location type (e.g., CUmemLocation::type) is a host NUMA node (e.g., CU_MEM_LOCATION_TYPE_HOST_NUMA). In at least one embodiment, CUmemLoc::id is a valid device ordinal when information to be set (e.g., Advertisement) is a set preferred location (e.g., CU_MEM_ADVISE_SET_PREFERRED_LOCATION) and location type (e.g., CUmemLocation::type) is a device (e.g., CU_MEM_LOCATION_TYPE_DEVICE). In at least one embodiment, CUmemLoc:id is ignored when information to be set (e.g., Advertisement) is a set preferred location (e.g., CU_MEM_ADVISE_SET_PREFERRED_LOCATION) and location type (e.g., CUmemLocation::type) is a host without specifying a NUMA node (e.g., CU_MEM_LOCATION_TYPE_HOST). In at least one embodiment, CUmemLoc::id is ignored when information to be set (e.g., Advertisement) is a set preferred location (e.g., CU_MEM_ADVISE_SET_PREFERRED_LOCATION) and location type (e.g., CUmemLocation::type) is a current host NUMA node (e.g., CU_MEM_LOCATION_TYPE_HOST_NUMA_CURRENT) and current thread's CPU NUMA node is set as preferred location of area. In at least one embodiment, argument CUmemLoc::type is ignored if Advance is one of CU_MEM_ADVISE_UNSET_PREFERRED_LOCATION CU_MEM_ADVISE_SET_READ_MOSTED or CU_MEM_ADVISE_UNSET_READ_MOSTED. In at least one embodiment, CUmemLoc::type is either CU_MEM_LOCATION_TYPE_DEVICE (e.g., with valid ordinal in CUmemLoc::id) or CU_MEM_LOCATION_TYPE_HOST (e.g., where CUmemLoc::id is ignored) when Advantage is CU_MEM_ADVISE_SET_ACCESSED_BY or CU_MEM_ ADVISE_UNSET_ACCESSED_BY.FIG. 3 illustrates performing an API 300 to store information in one or more NUMA memories (e.g., memory 112 of FIG. 1 ) according to at least one embodiment. In at least one embodiment, performing API 300 to store information in one or more NUMA memories includes pre-fetching data stored using a range of memory (e.g., virtual memory accessible to one or more CPUs and one or more GPUs) into physical memory in a NUMA node. In at least one embodiment, one or more processors (e.g., processor 128, processor 110, and / or processor 116 of FIG. 1 ) are to perform API 300. In at least one embodiment, API 300 is to be performed using memory prefetch API 134 of FIG. 1.In at least one embodiment, API 300 includes one or more parameters. In at least one embodiment, parameters of API 300 include one or more parameters to indicate a storage area. In at least one embodiment, API 300 parameters include a source parameter to indicate a pointer to a base memory address (e.g., in managed unified virtual memory that can be accessed by one or more CPUs and one or more GPUs), and a size parameter (e.g., a number in bytes) to indicate a size of memory area. In at least one embodiment, API 300 includes a destination parameter to the location to which data stored in a specified storage area is to be pre-fetched (e.g., a host NUMA node using a NUMA ID or a GPU using a GPU ID). In at least one embodiment, API 300 includes a stream identifier parameter to identify a stream for which prefetch applies. In at least one embodiment, API 300 includes a different number and / or type of parameters. In at least one embodiment, a response 302 to performing API 300 includes an indication of whether performance of API 300 was successful (e.g., an operational status). In at least one embodiment, response 302 is not present (e.g., when API 300 has a Void Return Type).In at least one embodiment, an API signature and / or function prototype of API 300 (e.g., for use with a driver API) may be represented as: CUres cuMemPrefetchAsync_v2(CUdevice dptr, size_t count, CUmemLoc location, CUstream stream); In at least one embodiment, CUdevice dptr corresponds to source parameter, size_t count corresponds to size parameter, CUmemLoc location corresponds to destination parameter, and / or CUstream stream corresponds to stream identifier parameter. In at least one embodiment, an API signature and / or function prototype of API 300 (e.g., for use with a runtime API) may be represented as: cudaError_t cudaMemPrefetchAsync_v2(const void *dptr, size_t count, cudaMemLoc location, cudaStream = 0); in at least one embodiment, constant void *dptr corresponds to source parameter, size_t count corresponds to size parameter, cudaMemLoc location corresponds to destination parameter, and / or cudaStream corresponds to stream identifier parameter. In at least one embodiment, an API signature and / or a function prototype of API 300 is presented using another suitable API signature and / or another suitable function or interface prototype.In at least one embodiment, one or more aspects of CUmemLocType, CUmemLoc Loc, and / or cudaMemLoc Loc shown and / or described with respect to API 200 of FIG. 2 also apply to API 300. In at least one embodiment, specifying CU_MEM_LOCATION_TYPE_HOST_NUMA memory (e.g., data stored using a range of managed virtual memory that can be accessed by one or more CPUs and one or more GPUs) is prefetched into a NUMA node specified by CUmemLoc::id. In at least one embodiment, upon pre-fetching an address range to a HOST NUMA node, if CU_MEM_ADVISE_SET_READ_MOSTED is set for each page of user forwarded in address range, a read duplicate copy is generated in targeted CPU NUMA node. In at least one embodiment, if these pages are already in another HOST NUMA node, unified memory driver will migrate them to destination NUMA node. In at least one embodiment, if CU_MEM_ADVISE_SET_READ_MOSTED is not set, pages are migrated to destination NUMA node. In at least one embodiment, specifying CUmemLoc::type = CU_MEM_LOCATION_TYPE_DEVICE memory will prefetch to GPU specified by device ordinal CUmemLoc::id. In at least one embodiment, users may also request prefetching memory to CPU NUMA node of current thread by specifying CUmemLoc::type = CU_MEM_LOCATION_TYPE_HOST_NUMA_CURRENT.FIG. 4 illustrates performing an API 400 to indicate whether one or more memories correspond to one or more NUMA memories (e.g., memory 112 of FIG. 1 ), according to at least one embodiment. In at least one embodiment, performing API 400 to indicate whether one or more memories correspond to one or more NUMA memories includes generating an indication of a NUMA node to which a range of memories was last pre-fetched. In at least one embodiment, performing API 400 to indicate whether one or more memories correspond to one or more NUMA memories includes generating an indication of a NUMA node set as a preferred location of a range of memories. In at least one embodiment, one or more processors (e.g., processor 128, processor 110, and / or processor 116 of FIG. 1 ) are to perform API 400. In at least one embodiment, API 400 is to be performed using Get Storage Attribute API 136 of FIG. 1.In at least one embodiment, API 400 includes one or more parameters. In at least one embodiment, parameters of API 400 include a result location parameter for indicating a storage location at which a result of an attribute query is written to API 400. In at least one embodiment, API 400 includes a result size parameter for indicating a size of data. In at least one embodiment, API 400 includes an attribute parameter for indicating an attribute to be queried (e.g., a last pre-called location or a preferred location set for a range of memory). In at least one embodiment, API 400 includes a storage header area parameter for indicating a header of an area to be queried. In at least one embodiment, API 400 includes a memory size range parameter for indicating a size of a range to be queried (e.g., a number in bytes). In at least one embodiment, API 400 includes a different number and / or type of parameters. In at least one embodiment, a response 402 to performing API 400 includes an indication of whether performance of API 400 was successful (e.g., an operational status). In at least one embodiment, response 402 is not present (e.g., when API 400 has a Void Return Type).In at least one embodiment, an API signature and / or function prototype of API 400 may be represented as: CUres cuMemRangeGetAttribute(void*data size_t dataSize, CUmem_range_bebnet attributes, CUdeviceptr devPtr, size_t count). In at least one embodiment, void*data corresponds to result location parameter, size_t dataSize corresponds to result size parameter, CUmem_range_be attribute corresponds to attribute parameter, CUdeviceptr devPtr corresponds to memory beginning range parameter, and / or size_t count corresponds to size of memory range parameter. In at least one embodiment, a region attribute parameter has a type that can be represented as: typedef enum CUmem_range_attribute_enum {CU_MEM_RANGE_ATTRIBUTE_READ_MOST = 1, CU_MEM_RANGE_ATTRIBUTE_PREFERRED_LOCATION = 2, CU_MEM_RANGE_ATTRIBUTE_ACCESSED_BY = 3, CU_MEM _RANGE_ATTRIBUTE_LAST_PREFETCH_LOCATION = 4, CU_MEM_RANGE_ATTRIBUTE_PREFERRED_LOCATION_v2 = 5, CU_MEM_RANGE_ATTRIBUTE_LAST_PREFETCH_LOCATION _v2 = 6, CUmem_range_benetistics;In at least one embodiment, CU_MEM_RANGE_ATTRIBUTE_READ_MOSTED is used to indicate attribute for return, whether area is largely read and written only occasionally. In at least one embodiment, CU_MEM _RANGE_ATTRIBUTE_PREFERRED_LOCATION is used to indicate attribute for return, is preferred location of range, but is not enabled for NUMA and cannot return NUMA ID. In at least one embodiment, CU_MEM_RANGE_ATTRIBUTE_ACCESSED_BY is used to indicate attribute for return whether storage area comprises: CU_MEM_ADVISE_SET_ACCESSED_BY specified for a specified device.In at least one embodiment, CU_MEM_RANGE_ATTRIBUTE_LAST _PREFETCH_LOCATION is used to indicate attribute for return, which is last prefetch location, but is not enabled for NUMA and cannot return NUMA ID. In at least one embodiment, CU_MEM_RANGE_ATTRIBUTE_PREFERRED_LOCATION_v2 is used to indicate attribute for return that is preferred CUmemLoc of range (e.g., which may include a preferred NUMA node). In at least one embodiment, CU _MEM_RANGE_ATTRIBUTE_LAST _PREFETCH_LOCATION_v2 is used to indicate attribute for return, last prefetch CUmemLoc is from range (which may be, e.g., a NUMA node to which range was pre-fetched).In at least one embodiment, API 400 enables user (e.g., using cuMemRangeGetAttribute( )) to query storage area attributes assigned by API 200 of FIG. 2 (e.g., preference set using cuMemIse) and / or API 300 of FIG. 3 (e.g., pre-called using cuMemPreAsync). In at least one embodiment, enumerations are used to retrieve CUmemLoc of last prefetch location and / or preferred location of address range. In at least one embodiment, if preferred location is specified as an attribute (e.g., using CU_MEM_RANGE_ATTRIBUTE_PREFERRED_LOCATION_v2), data argument is interpreted as a pointer to a CUmemLoc, and dataSize is at least sizeof(CUmemLocation). In at least one embodiment, returned location.type is CU_MEM_LOCATION_TYPE_DEVICE and location.id is device ID (e.g., GPU) if all pages in specified address range have same GPU device as its preferred location. In at least one embodiment, returned location.type is CU_MEM_LOCATION_TYPE_HOST_NUMA and location.id is CPU NUMA ID if all pages in specified address range have same CPU NUMA node as its preferred location. In at least one embodiment, if a CPU NUMA node ID was not specified as part of setting preferred location for hosts or pages of different CPUs as their preferred location, location.type is CU_MEM_LOCATION_TYPE_HOST.In at least one embodiment, if last prefetch location is specified as an attribute (e.g., using CU_MEM_RANGE_ATTRIBUTE_LAST_PREFETCH_LOCATION_v2), data argument is interpreted as a pointer to a CUmemLoc, and dataSize is at least sizeof(CUmemLocation). In at least one embodiment, returned location.type is CU_MEM_LOCATION_TYPE_DEVICE and location.id is device ID (e.g., GPU) when all pages in specified address range have been explicitly pre-fetched on a single GPU. In at least one embodiment, returned location.type is CU_MEM_LOCATION_TYPE_HOST_NUMA and location.id is CPU NUMA ID if all pages in specified address range have been explicitly pre-fetched on a single CPU NUMA node. In at least one embodiment, if a CPU NUMA node ID was not specified as part of host prefetch operation or pages were explicitly pre-fetched to different CPUs, then returned location.type is CU_MEM_LOCATION_TYPE_HOST.In at least one embodiment, one or more aspects of API 200, API 300, and / or API 400 are to be used with a NUMA-enabled system. In at least one embodiment, API 200, API 300, and API 400 are referred to as NUMA aware and / or take one or more indications of one or more NUMA nodes as one or more input parameters. In at least one embodiment, one or more aspects of API 200, API 300, and / or API 400 are to be used with a system that includes one or more CPUs and one or more GPUs interconnected with a high bandwidth chip-to-chip (C2C) connection. In at least one embodiment, the presence of a high bandwidth C2C connection between CPU and GPU and use of high capacity memory enables increasing amount of high bandwidth memory available to GPU. In at least one embodiment, enhancing GPU's ability to access CPU memory on a remote socket or node is referred to as extended GPU memory (EGM). In at least one embodiment, EGM enables, based at least in part on C2C connection, more rapid access to system memory (system memory) than PCIe. In at least one embodiment, one or more APIs enable creation of targeted assignments in and / or management of virtual memory in different CPU memory on different sockets (e.g., in different NUMA nodes) to better use EGM feature compared to legacy techniques that are not NUMA aware, and / or do not enable to specify particular NUMA nodes. In at least one embodiment, CPU nodes are enumerated as unique NUMA nodes within system. In at least one embodiment, passing GPU NUMA ID to API 200, API 300, and / or API 400 instead of a CPU results in an API error (e.g., with CUDA_ERROR_INVALID_VALUE). In at least one embodiment, a driver (e.g., CUDA driver) will pass user-specified NUMA ID to a unified virtual memory (UVM) driver.FIG. 5 is a flow diagram of a technique 500 for accessing one or more NUMA nodes, according to at least one embodiment. In at least one embodiment, one or more aspects of technique 500 are performed by one or more aspects shown or described with respect to FIG. 1 (e.g., processor 110, processor 116, GPU 120, GPU 122, and / or storage location preference API 132), and / or one or more components, techniques, and / or other aspects shown or described with respect to other figures herein. In at least one embodiment, technique 500 includes performing one or more aspects of API 200 of FIG. 2. in at least one embodiment, technique 500 includes, in a block 502, obtaining an attribute request for a managed storage set (e.g., via an API such as storage location preference API 132 of FIG. 1 ). In at least one embodiment, technique 500 includes, at a block 504, setting a managed storage attribute (e.g., performing storage location preference API 132 of FIG. 1 and / or API 200 of FIG. 2 ). In at least one embodiment, technique 500 includes, at a block 506, performing other actions (e.g., returning an indication that setting a preferred location of a managed storage area has been successfully performed, and / or returning to block 502 to obtain another attribute request for a managed storage set). In at least one embodiment, performing other actions at block 506 includes storing an indication of a preferred storage location (e.g., a NUMA ID) in association with one or more indications of a range of virtual storage (e.g., managed virtual storage that can be accessed by one or more CPUs and one or more GPUs).In at least one embodiment, at least one aspect of technique 500 includes performing an API (e.g., location preference API 132 of FIG. 1 and / or API 200 of FIG. 2 ) to cause one or more non-uniform memory access (NUMA) nodes or one or more physical addresses associated with one or more graphics processing units (GPUs) to be accessed based at least in part on one or more indications within API. In at least one embodiment, API is to cause a memory of a NUMA node to be set as a preferred memory location based at least in part on one or more indications. In at least one embodiment, one or more indicia includes information indicative of a range of virtual memory accessible by a central processing unit (CPU) and one or more GPUs. In at least one embodiment, one or more indicia includes information indicative of a NUMA node to be used as a preferred storage location. In at least one embodiment, API is to cause a NUMA node from a plurality of NUMA nodes to be used as a preferred storage location of data to be stored using one or more virtual memory addresses that can be accessed by a central processing unit (CPU) of a NUMA node and one or more GPUs. In at least one embodiment, API is to cause one or more indicia to be stored that contain information indicative of a NUMA node to be used as a preferred storage location of information to be stored using one or more virtual memory addresses that can be accessed by a central processing unit (CPU) of a NUMA node and one or more GPUs. In at least one embodiment, a non-transitory computer readable medium having stored thereon a set of instructions that, when executed by one or more processors, cause one or more processors to perform at least one or more aspects of technique 500.FIG. 6 is a flow diagram of a technique 600 for storing information in one or more NUMA memories, according to at least one embodiment. In at least one embodiment, one or more aspects of technique 500 are performed by one or more aspects shown or described with respect to FIG. 1 (e.g., processor 110, processor 116, GPU 120, GPU 122, and / or memory prefetch API 134), and / or one or more components, techniques, and / or other aspects shown or described with respect to other figures herein. In at least one embodiment, technique 600 includes performing one or more aspects of API 300 of FIG. 3. In at least one embodiment, technique 600 includes, at a block 602, obtaining a request for managed memory prefetch (e.g., via an API such as memory prefetch API 134 of FIG. 1 ). In at least one embodiment, technique 600 includes, at a block 604, performing managed memory prefetch (e.g., performing memory prefetch API 134 of FIG. 1 and / or API 300 of FIG. 3 ). In at least one embodiment, performing managed memory prefetch includes causing a driver and / or a memory manager to prefetch data into a NUMA node. In at least one embodiment, technique 600 includes, at a block 606, performing other actions (e.g., returning an indication that a memory prefetch operation was successfully performed and / or returning to block 602 to obtain another managed memory prefetch request).In at least one embodiment, at least one aspect of technique 600 includes performing an API (e.g., memory prefetch API 134 of FIG. 1 and / or API 400 of FIG. 4 ) to cause information to be stored within one or more non-uniform memory access (NUMA) memories or one or more physical graphics processor unit (GPU) memories based at least in part on one or more indicators to be indicated by one or more users of API. In at least one embodiment, API is to cause information accessible by one or more central processing units (CPUs) and one or more GPUs to be stored within a NUMA memory based at least in part on one or more indicators. In at least one embodiment, API is to prefetch information at a location indicated by one or more of one or more indicators. In at least one embodiment, API is to cause information to be pre-called into a NUMA node of a plurality of NUMA nodes. In at least one embodiment, information is in managed virtual memory accessible by one or more central processing units (CPUs) and one or more GPUs, and API is to cause information to be pre-fetched into a memory of a NUMA node that includes one or more of one or more CPUs. In at least one embodiment, information indicates a NUMA node in which information is to be stored. In at least one embodiment, a non-transitory computer readable medium having stored thereon a set of instructions that, when executed by one or more processors, cause one or more processors to perform at least one or more aspects of technique 600.In at least one embodiment, at least one aspect of technique 600 includes performing an API (e.g., memory prefetch API 134 of FIG. 1 and / or API 300 of FIG. 3 ) to cause information to be read from one or more non-uniform memory access (NUMA) memories or one or more physical graphics processor unit (GPU) memories based at least in part on one or more indicators to be indicated by one or more users of API. In at least one embodiment, information is stored using one or more virtual memory addresses accessible by one or more NUMA nodes and one or more GPUs, and API is to cause information to be stored within a particular NUMA node of one or more NUMA nodes. In at least one embodiment, information is stored using one or more virtual memory addresses accessible by one or more NUMA nodes and one or more GPUs, and one or more indicators indicate one or more virtual memory addresses and a location to which information is to be pre-called. In at least one embodiment, information is stored using one or more virtual memory addresses, and API is to store information within a NUMA memory of a NUMA node indicated by one or more of one or more indicators. In at least one embodiment, one or more indicators indicate a range of virtual memory and a NUMA node. In at least one embodiment, information is stored using virtual memory accessible by a plurality of NUMA nodes and one or more GPUs, and API is to cause information to be read from a memory of a NUMA node of a plurality of NUMA nodes. In at least one embodiment, a non-transitory computer readable medium having stored thereon a set of instructions that, when executed by one or more processors, cause one or more processors to perform at least one or more aspects of technique 600.FIG. 7 is a flow diagram of a technique 700 for indicating whether one or more memories correspond to one or more NUMA memories, according to at least one embodiment. In at least one embodiment, one or more aspects of technique 700 are performed by one or more aspects shown or described with respect to FIG. 1 (e.g., processor 110, processor 116, GPU 120, GPU 122, and / or get memory attribute API 136), and / or one or more components, techniques, and / or other aspects shown or described with respect to other figures herein. In at least one embodiment, technique 700 includes performing one or more aspects of API 400 of FIG. 4. In at least one embodiment, technique 700 includes, in a block 702, obtaining a request for managed storage retrieval (e.g., via an API such as get storage attributes API 136 of FIG. 1 ). In at least one embodiment, technique 700 includes, at a block 704, providing a requested storage attribute (e.g., performing Get storage attribute API 136 of FIG. 1 and / or API 400 of FIG. 4 ). In at least one embodiment, technique 700 includes, at a block 706, performing other actions (e.g., returning an indication that providing a requested memory attribute operation was successfully performed, and / or returning to block 702 to obtain another request for a managed memory fetch).In at least one embodiment, at least one aspect of technique 700 includes performing an API (e.g., get memory attribute API 136 of FIG. 1 and / or API 400 of FIG. 4 ) to indicate whether one or more memories indicated by one or more users of API correspond to one or more non-uniform memory access (NUMA) memories or one or more graphics processing unit (GPU) memories. In at least one embodiment, one or more memories indicated by one or more users of API are one or more managed memory locations indicated by information received as one or more inputs to API indicating a range of managed memory. In at least one embodiment, API is to indicate a preferred NUMA memory or GPU memory of one or more memories indicated by one or more users. In at least one embodiment, API is to indicate NUMA memory or GPU memory to which one or more memories were last pre-fetched. In at least one embodiment, one or more NUMA memories are physical memories included in one or more NUMA nodes each including one or more central processing units (CPUs). In at least one embodiment, one or more memories indicated by one or more users are one or more virtual memory addresses that can be accessed by one or more central processing units (CPUs) and one or more GPUs. In at least one embodiment, a non-transitory computer readable medium having stored thereon a set of instructions that, when executed by one or more processors, cause one or more processors to perform at least one or more aspects of technique 700.FIG. 8 is a block diagram illustrating an example of a processor 800 according to at least one embodiment. In at least one embodiment, a processor 802 performs one or more processes such as those described herein to set a NUMA node as a preferred storage location of data to be stored using a range of managed memory (e.g., virtual memory accessible to one or more CPUs and one or more GPUs). In at least one embodiment, processor 802 performs one or more processes, such as those described herein, to prefetch data stored using a range of managed memory into a NUMA node. In at least one embodiment, processor 802 performs one or more processes such as those described herein to obtain one or more attributes (e.g., a last location (e.g., NUMA node) to which a range of memory has been explicitly pre-fetched and / or an identifier of a location (e.g., NUMA node) that is specified as a preferred memory location of a range of memory).In at least one embodiment, processor 802 executes one or more aspects described with respect to processor 110, processor 116, processor 128, and / or one or more APIs of set of APIs 130 of FIG. 1, API 200 of FIG. 2, API 300 of FIG. 3, API 400 of FIG. 4, technique 500 of FIG. 5, technique 600 of FIG. 6, technique 700 of FIG. 7, and / or one or more APIs 910 of FIG. 9. In at least one embodiment, processor 802 performs one or more processes such as those described in connection with FIGS. 1-7.In at least one embodiment, processor 802 includes one or more processors such as those described in connection with one or more of FIGS. 25-40. In at least one embodiment, processor 802 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof. In at least one embodiment, processor 802 includes a management memory preference display module 804, a management memory prefetch module 806, and a get management memory attribute module 808. In at least one embodiment, management memory preference display module 804, management memory prefetch module 806, and / or get management memory attribute module 808 are part of processor 802 and / or one or more other processors. In at least one embodiment, management memory preference display module 804, management memory prefetch module 806, and / or get management memory attribute module 808 are distributed among multiple processors that communicate via a bus, network, by writing to shared memory, and / or any suitable communication process such as those described herein.In at least one embodiment, as used in any implementation described herein, unless otherwise clearly or expressly stated to the contrary from context, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide functionality described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein may include, for example, singly or in any combination, hardwired circuits, programmable circuits, state machine circuits, fixed function circuits, execution unit circuits, and / or firmware storing instructions executed and / or performed by programmable circuits. In at least one embodiment, modules may be embodied jointly or individually as circuits forming part of a larger system, for example, an integrated circuit (IC), a system on chip (SoC), and so forth. In at least one embodiment, a module performs one or more processes in connection with any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof.In at least one embodiment, management storage preference indication module 804 is a module that generates one or more wireless network metrics. In at least one embodiment, management storage preference display module 804 performs one or more processes, such as those described herein, by at least including or otherwise encoding (e.g., by processor 802) instructions that cause or otherwise may be used to perform at least one process. In at least one embodiment, management storage preference display module 804 sets a NUMA node as a preferred storage location of a range of managed storage based at least in part on receiving information specifying a NUMA node and a range of storage via an API. In at least one embodiment, management storage preference display module 804 performs one or more aspects shown or described with respect to storage location preference API 132 of FIG. 1, API 200 of FIG. 2, and / or technique 500 of FIG. 5.In at least one embodiment, management memory prefetch module 806 is a module that prefetches information stored using a range of virtual memory to a specified location (e.g., a NUMA node). In at least one embodiment, management memory prefetch module 806 performs one or more processes, such as those described herein, by at least including or otherwise encoding (e.g., by processor 802) instructions that cause or otherwise can be used to perform one or more processes. In at least one embodiment, managed memory prefetch module 806 performs one or more aspects shown or described with respect to memory prefetch API 134 of FIG. 1, API 300 of FIG. 3, and / or technique 600 of FIG. 6.In at least one embodiment, get management storage attribute module 808 is a module that creates, returns, and / or otherwise provides a last location (e.g., a NUMA node) to which a range of storage has been explicitly pre-called and / or a location (e.g., a NUMA node) that is designated as a preferred storage location of a range of storage. In at least one embodiment, get management storage attribute module 808 performs one or more processes, such as those described herein, by at least including or otherwise encoding (e.g., by processor 802) instructions that cause or otherwise may be used to perform at least one process. In at least one embodiment, get management storage attribute module 808 performs one or more aspects shown or described with respect to get management storage attribute API 136 of FIG. 1, API 400 of FIG. 4, and / or technique 700 of FIG. 7.In at least one embodiment, a processor (e.g., processor 110, processor 116, and / or processor 128 of FIG. 1 ) includes one or more circuits for performing an API (e.g., location preference indication API 132 of FIG. 1 and / or API 200 of FIG. 2 ) to cause one or more non-uniform memory access (NUMA) nodes (e.g., NUMA node 108 of FIG. 1 ) or one or more physical addresses (e.g., in memory 124 of FIG. 1 ) associated with one or more graphics processing units (GPUs) (e.g., GPU 120), at least partially accessed based on one or more indications (e.g., one or more parameters of the API 200) within the API. In at least one embodiment, API is to cause a memory of a NUMA node to be set as a preferred storage location of data to be stored at one or more virtual memory addresses. In at least one embodiment, API is to cause a memory of a NUMA node including a central processing unit (CPU) to be set as a preferred memory location. In at least one embodiment, API is to cause a NUMA node from a plurality of NUMA nodes to be used as a preferred storage location of data to be stored using one or more virtual memory addresses that can be accessed by a central processing unit (CPU) and one or more GPUs. In at least one embodiment, API is to cause a memory of a NUMA node to be accessed based at least in part on information contained in one or more indicia indicative of NUMA node. In at least one embodiment, one or more displays within API include information provided as input that displays a range of managed memory and a NUMA node. In at least one embodiment, one or more NUMA nodes include one or more central processing units (CPUs) and one or more indicia within API include information provided as input indicating a range of virtual memory addresses that can be accessed by one or more CPUs and one or more GPUs. In at least one embodiment, a processor includes one or more circuits for performing an API to indicate that physical memory corresponding to a subset of a set of CPUs is to be used to store data corresponding to one or more virtual memory addresses shared by subset of CPUs and one or more GPUs. In at least one embodiment, a processor includes one or more circuits for performing an API to indicate that physical memory in a NUMA node is to be used to store data stored using one or more virtual memory addresses shared by NUMA node and one or more GPUs. In at least one embodiment, a processor includes one or more circuitry for performing an API to cause a preferred managed storage location to be indicated based at least in part on an identifier of a NUMA node.In at least one embodiment, a system includes one or more processors (e.g., processor 110, processor 116, and / or processor 128 of FIG. 1 ) for performing an API (e.g., memory location preference indication API of FIG. 1 and / or API 200 of FIG. 2 ) to cause one or more non-uniform memory access (NUMA) nodes (e.g., NUMA node 108 of FIG. 1 ) or one or more physical addresses (e.g., in memory 124 of FIG. 1 ) associated with one or more GPUs (e.g., GPU 120), at least partially accessed based on one or more indications (e.g., one or more parameters of the API 200) within the API. In at least one embodiment, one or more indicia includes information indicative of a range of virtual memory addresses accessible by one or more central processing units (CPUs) and one or more GPUs. In at least one embodiment, API is to cause a memory of a NUMA node that includes a central processing unit (CPU) to be used as a preferred physical storage location of data to be stored using one or more virtual memory addresses that can be accessed by CPU and one or more GPUs. In at least one embodiment, one or more indicia includes information indicative of a NUMA node to be used as a storage location of data. In at least one embodiment, one or more indicia includes information indicative of a NUMA node to be used as a physical storage location of data and information indicative of a range of virtual memory addresses. In at least one embodiment, API is to cause an indication of a preferred physical storage location of a range of virtual storage addresses to be stored.In at least one embodiment, a processor (e.g., processor 110, processor 116, and / or processor 128 of FIG. 1 ) includes one or more circuits for performing an API (e.g., memory prefetch API 134 of FIG. 1 and / or API 300 of FIG. 3 ) to cause information within one or more non-uniform memory access (NUMA) memories (e.g., memory 118 of FIG. 1 ) or one or more physical graphics processor unit (GPU) memories (e.g., memory 124 of FIG. 1 ) based at least in part on one or more indicators (e.g., one or more parameters of API 300 of FIG. 3 ), which are to be specified by one or more users of the API. In at least one embodiment, API is to cause information to be pre-called into a memory of a NUMA node. In at least one embodiment, one or more indicators include information indicative of a storage location type and a storage location identifier. In at least one embodiment, API is to cause information to be stored within a NUMA memory of a NUMA node that includes a central processing unit (CPU) in response to one or more indicators indicating a memory location type of a host NUMA node. In at least one embodiment, API is to cause information to be pre-fetched into a memory of a host NUMA node indicated by one or more of one or more indicators. In at least one embodiment, information is stored using one or more virtual memory addresses that can be accessed by one or more GPUs and one or more central processing units (CPUs), and API is to cause information to be stored within a physical memory of a NUMA node. In at least one embodiment, one or more indicators include an indication of a NUMA node of a plurality of NUMA nodes, and API is to cause information to be stored within indicated NUMA node. In at least one embodiment, a processor includes one or more circuits for performing an API to cause physical memory corresponding to a subset of a set of CPUs to be used to store data corresponding to one or more virtual memory addresses shared by subset of CPUs and one or more GPUs. In at least one embodiment, a processor includes one or more circuits for performing an API to cause physical memory in a NUMA node to be used to store data stored using one or more virtual memory addresses shared by NUMA node and one or more GPUs. In at least one embodiment, a processor includes one or more circuitry to perform an API to cause a range of managed memory to be pre-called based at least in part on an identifier of a NUMA node.In at least one embodiment, a system includes one or more processors (e.g., processor 110, processor 116, and / or processor 128 of FIG. 1 ) for performing an API (e.g., memory prefetch API 134 of FIG. 1 and / or API 300 of FIG. 3 ) to cause information within one or more non-uniform memory access (NUMA) memories (e.g., memory 112 of FIG. 1 ) or one or more physical graphics processor unit (GPU) memories (e.g., memory 126 of FIG. 1 ) based at least in part on one or more indicators (e.g., one or more parameters of API 300 of FIG. 3 ), which are to be specified by one or more users of the API. In at least one embodiment, information is stored using virtual addresses accessible by one or more central processing units (CPUs) and one or more GPUs, and API is to cause information to be stored within a physical memory of a NUMA node. In at least one embodiment, one or more indicators include information indicating a range of memory accessible by one or more central processing units (CPUs) and one or more GPUs. In at least one embodiment, API is to cause information to be pre-called into a NUMA node that includes a central processing unit. In at least one embodiment, one or more indicators indicate a range of virtual memory and a NUMA node. In at least one embodiment, one or more indicators indicate a starting location and a size of information to be stored.In at least one embodiment, a processor (e.g., processor 110, processor 116, and / or processor 128 of FIG. 1 ) includes one or more circuits for performing an API (e.g., memory prefetch API 134 of FIG. 1 and / or API 300 of FIG. 3 ) to cause information from one or more non-uniform memory access (NUMA) memories (e.g., memory 112 and / or memory 118 of FIG. 1 ) or one or more physical graphics processor unit (GPU) memories (e.g., memory 124 of FIG. 1 ) to be generated based at least in part on one or more indicators (e.g., one or more parameters of API 300 of FIG. 3 ), which are to be specified by one or more users of the API. In at least one embodiment, API is to cause information to be read from a NUMA memory based at least in part on causing information to be pre-fetched into NUMA memory. In at least one embodiment, information is stored using one or more virtual memory addresses accessible by one or more central processing units (CPUs) and one or more GPUs, and API is to cause information to be read based at least in part on causing information to be stored within a NUMA memory. In at least one embodiment, one or more indicators include one or more indicators that indicate virtual memory accessible by one or more central processing units (CPUs) and one or more GPUs. In at least one embodiment, one or more indicators include one or more indicators indicating a NUMA node in which information is to be pre-called. In at least one embodiment, one or more indicators include: one or more indicators indicating virtual memory accessible by one or more central processing units (CPUs) and one or more GPUs; and one or more indicators indicating a particular NUMA node from among a plurality of NUMA nodes. In at least one embodiment, API is to cause information to be read from a NUMA memory based at least in part on causing information to be stored in a NUMA node indicated by one or more of one or more indicators.In at least one embodiment, a system includes one or more processors (e.g., processor 110, processor 116, and / or processor 128 of FIG. 1 ) for performing an API (e.g., memory prefetch API 134 of FIG. 1 and / or API 300 of FIG. 3 ) to cause information from one or more non-uniform memory access (NUMA) memories (e.g., memory 118 of FIG. 1 ) or one or more physical graphics processor unit (GPU) memories (e.g., memory 124 of FIG. 1 ) to be generated based at least in part on one or more indicators (e.g., one or more parameters of API 300 of FIG. 3 ), which are to be specified by one or more users of the API. In at least one embodiment, information is stored using one or more virtual memory addresses accessible by one or more central processing units (CPUs) and one or more GPUs, and API is to cause information to be read from a NUMA memory based at least in part on causing information to be stored in a NUMA memory. In at least one embodiment, information is stored using one or more virtual memory addresses, and one or more of one or more indicators indicate one or more virtual memory addresses. In at least one embodiment, one or more indicators include one or more indicators indicating a particular NUMA node from a plurality of NUMA nodes. In at least one embodiment, API is to cause information to be read from NUMA memory within a particular NUMA node of a plurality of NUMA nodes. In at least one embodiment, information is stored using one or more virtual memory addresses that can be accessed by a plurality of NUMA nodes and one or more GPUs.In at least one embodiment, a processor (e.g., processor 110, processor 116, and / or processor 128 of FIG. 1 ) includes one or more circuits for performing an API (e.g., get memory attribute API 136 of FIG. 1 and / or API 400 of FIG. 4 ) to indicate whether one or more memories indicated by one or more users of API (e.g., using one or more parameters of API 400 of FIG. 4 ), The processing units may be configured to correspond to one or more non-uniform memory access (NUMA) memories (e.g., memory 112 or memory 118 of FIG. 1 ) or one or more graphics processing unit (GPU) memories (e.g., memory 124 or memory 126 of FIG. 1 ). In at least one embodiment, API is to indicate a NUMA node to which data was last pre-called by another API. In at least one embodiment, API is to indicate a NUMA node that is set by an API other than a preferred location of one or more memory addresses. In at least one embodiment, API is to indicate a location type and identity of virtual memory that can be accessed by one or more central processing units (CPUs) and one or more GPUs. In at least one embodiment, API is to receive one or more inputs indicating a range of memory. In at least one embodiment, one or more memories indicated by one or more users are a range of virtual memory accessible by one or more central processing units (CPUs) and one or more GPUs. In at least one embodiment, API is to return an identifier of a location type and an identifier of a location identity based at least in part on one or more inputs indicating a range of memory. In at least one embodiment, a processor includes one or more circuits for performing an API to provide a user with an indication of a subset of a set of CPUs based at least in part on one or more virtual memory addresses shared between subset of CPUs and one or more GPUs. In at least one embodiment, a processor includes one or more circuits for performing an API to provide a user with an indication of a NUMA node based at least in part on one or more virtual memory addresses shared between NUMA node and one or more GPUs. In at least one embodiment, a processor includes one or more circuits for performing an API to obtain an indication of a NUMA node based at least in part on an input parameter indicating an attribute of a managed memory area to be obtained.In at least one embodiment, a system includes one or more processors (e.g., processor 110, processor 116, and / or processor 128 of FIG. 1 ) to perform an API (e.g., get memory attribute API 136 of FIG. 1 and / or API 400 of FIG. 4 ) to indicate whether one or more memories indicated by one or more users of API (e.g., using one or more parameters of API 400 of FIG. 4 ), The processing units may be configured to correspond to one or more non-uniform memory access (NUMA) memories (e.g., memory 112 of FIG. 1 ) or one or more graphics processing unit (GPU) memories (e.g., memory 126 of FIG. 1 ). In at least one embodiment, API is to indicate a NUMA node to which data stored using one or more virtual memory addresses was most recently explicitly pre-fetched. In at least one embodiment, API is to indicate a NUMA node that is set as a preferred storage location of a range of virtual storage addresses. In at least one embodiment, API is to indicate a NUMA node to which a range of virtual storage indicated by one or more users was last pre-called. In at least one embodiment, one or more memories indicated by one or more users of API are indicated using information as input to API indicating one or more virtual memory locations accessible by one or more NUMA nodes and one or more GPUs. In at least one embodiment, API is to indicate a NUMA node to which a range of virtual memory accessible by one or more NUMA nodes and one or more GPUs was last pre-called using an API.In at least one embodiment, an API (e.g., location preference API 132 of FIG. 1 and / or API 200 of FIG. 2 ) is to indicate a preference that physical storage of a subset of a set of CPUs is to be used for virtual addresses shared by subset of CPUs and a GPU. In at least one embodiment, this is a preference (e.g., expressed as an indication via API) and performing API causes a storage manager to use preference in determining where to locate physical storage, but may not satisfy preference (e.g., heuristics indicate that another location is better or if subset of CPUs have insufficient storage). In at least one embodiment, subset of CPUs is a NUMA node and API receives an identifier of NUMA node.In at least one embodiment, an API (e.g., memory prefetch API 134 of FIG. 1 and / or API 300 of FIG. 3 ) is to cause data stored at a virtual address shared by a subset of CPUs and a GPU to be pre-fetched into physical memory of a subset of a set of CPUs. In at least one embodiment, inputs to API specify virtual address and an identifier of subset of CPUs. In at least one embodiment, identifier is a NUMA node identifier. In at least one embodiment, performing API causes data stored at virtual address to be stored in physical memory of identified subset of CPUs.In at least one embodiment, an API (e.g., Get Storage Attribute API 136 of FIG. 1 and / or API 400 of FIG. 4 ) is to cause a preference (set using a different API such as API 200 of FIG. 2 ) to be displayed to user. In at least one embodiment, API allows a user to enter a virtual storage address into API and obtain an indication of which preference was set for physical storage location for that virtual storage. In at least one embodiment, input to API includes a virtual memory address shared between a set of CPUs and a GPU. In at least one embodiment, performing API causes an identifier of a subset of set of CPUs to be provided to user (e.g., to allow user to change preference).FIG. 9 is a block diagram illustrating a driver and / or runtime environment 900 that includes one or more libraries to provide one or more application programming interfaces (APIs), according to at least one embodiment. In at least one embodiment, a software program 902 is a software module. In at least one embodiment, a software program 902 includes one or more software modules, including, but not limited to, those described herein in connection with at least FIG. 8. Further, in at least one embodiment, a software module is not exclusively described in FIG. 8. In at least one embodiment, one or more APIs 910 are sets of software instructions that, when executed, cause one or more processors to perform one or more computational operations. In at least one embodiment, performing software instructions includes executing software instructions. In at least one embodiment, one or more aspects of one or more software modules shown or described in connection with FIG. 8 are included in part in software program 902 (e.g., instructions and / or code for invoking a function when performed by a processor) and in part in one or more APIs 910 and / or functions 912 (e.g., instructions and / or code that implements invoked function when performed by a processor).In at least one embodiment, one or more APIs 910 are distributed or otherwise provided as part of one or more libraries 906, drivers and / or runtimes 904, and / or any other collection of software, non-transitory computer readable instructions, and / or executable code further described herein. In at least one embodiment, one or more APIs 910 perform one or more computing operations in response to being called by software programs 902. In at least one embodiment, a software program 902 is a collection of software code, instructions, instructions, or other text sequences to direct a computing device to perform one or more computing operations and / or to invoke one or more other sets of instructions, such as APIs 910 or API functions 912, to be performed. In at least one embodiment, functionality provided by one or more APIs 910 includes software functions 912, such as those that can be used to accelerate one or more portions of software programs 902 using one or more parallel processing units (PPUs), such as graphics processing units (GPUs). In at least one embodiment, APIs 910 and / or API functions 912 include APIs and / or functions for performing one or more aspects shown or described with respect to one or more APIs of set of APIs 130 of FIG. 1, API 200 of FIG. 2, API 300 of FIG. 3, API 400 of FIG. 4, technique 500 of FIG. 5, technique 600 of FIG. 6, and / or technique 700 of FIG. 7.In at least one embodiment, APIs 910 are hardware interfaces to one or more circuits to perform one or more computing operations. In at least one embodiment, one or more software APIs 910 described herein are implemented as one or more circuits to perform one or more techniques described herein in connection with FIGS. 1-8. In at least one embodiment, one or more software programs 902 include instructions that, when executed, cause one or more hardware devices and / or circuits to perform one or more techniques described herein in connection with FIGS. 1-8. In at least one embodiment, one or more software programs 902 use one or more APIs 910 provided by a driver and / or runtime 904 to manage virtual storage and / or allocate or otherwise reserve one or more storage blocks 914 of one or more NUMA nodes and / or one or more PPUs, such as GPUs. In at least one embodiment, one or more software programs 902 use one or more APIs 910 provided by a driver and / or runtime 904 to manage virtual memory and / or allocate or otherwise reserve memory blocks.In at least one embodiment, software programs 902, such as user-implemented software programs (e.g., application 142 of FIG. 1 ), use one or more application programming interfaces (APIs) 910 to perform various computational operations, such as memory reservation, matrix multiplication, arithmetic operations, or any computational operation performed by parallel processing units (PPUs), such as graphics processing units (GPUs), as further described herein. In at least one embodiment, one or more APIs 910 provide a set of callable functions 912, referred to herein as APIs, API functions, and / or functions that individually perform one or more computational operations, such as computational operations related to parallel computing. In at least one embodiment, a processor uses an API that includes a preferred managed storage location display function 916. In at least one embodiment, preferred managed storage location display function 916 performs one or more aspects of storage location preference API 132 of FIG. 1, API 200 of FIG. 2, technique 500 of FIG. 5, and / or managed storage preference display module 804 of FIG. 8. In at least one embodiment, a processor uses an API that includes a managed prefetch memory function 918. In at least one embodiment, managed prefetch storage function 918 performs one or more aspects of storage prefetch API 134 of FIG. 1, API 300 of FIG. 3, technique 600 of FIG. 6, and / or managed storage prefetch module 806 of FIG. 8. In at least one embodiment, a processor uses an API that includes a get management storage attribute function 920. In at least one embodiment, get management storage attribute function 920 performs one or more aspects of get storage attribute API 136 of FIG. 1, API 400 of FIG. 4, technique 700 of FIG. 7, and / or managed storage attribute module 808 of FIG. 8.In at least one embodiment, one or more software programs 902 interact with or otherwise communicate with one or more APIs 910 to perform one or more computing operations using one or more NUMA nodes and one or more PPUs, such as GPUs. In at least one embodiment, one or more computational operations using one or more PPUs include at least one or more groups of computational operations to be expedited by performance at least in part by one or more PPUs. In at least one embodiment, one or more software programs 902 interact with one or more APIs 910 to enable parallel computing using a remote or local interface.In at least one embodiment, an interface is software instructions that, when performed, provide access to one or more functions 912 provided by one or more APIs 910. In at least one embodiment, a software program 902 uses a local interface when a software developer compiles one or more software programs 902 in conjunction with one or more libraries 906 that include or otherwise provide access to one or more APIs 910. In at least one embodiment, one or more software programs 902 are statically compiled in conjunction with precompilation libraries 906 or uncompilation source code comprising instructions for executing one or more APIs 910. In at least one embodiment, one or more software programs 902 are dynamically compiled and one or more software programs use a linker to link to one or more precompilation libraries 906 that include one or more APIs 910.In at least one embodiment, a software program 902 uses a remote interface when a software program uses or otherwise communicates with a library 906 comprising one or more APIs 910 over a network or other remote communication medium. In at least one embodiment, one or more libraries 906 comprising one or more APIs 910 are to be performed by a remote computing service, such as a computing resource service provider. In another embodiment, one or more libraries 906 comprising one or more APIs 910 are to be performed by any other computing host that provides the one or more APIs 910 to one or more software programs 902.In at least one embodiment, a processor executing or using one or more software programs 902 invokes, uses, executes, or otherwise implements one or more APIs 910 to allocate and otherwise manage memory to be used by software programs 902. In at least one embodiment, one or more software programs 902 use one or more APIs 910 to allocate and otherwise manage memory to be used by one or more portions of software programs 902 to be accelerated using one or more PPUs, such as GPUs or any other accelerator or processor further described herein.In at least one embodiment, an API of one or more APIs 910 is an API to enable parallel computing. In at least one embodiment, one or more APIs 910 include any other API further described herein. In at least one embodiment, one or more APIs 910 are provided by a driver and / or runtime 904. In at least one embodiment, an API of one or more APIs 910 is provided by a CUDA user mode driver. In at least one embodiment, an API of one or more APIs 910 is provided by a CUDA runtime. In at least one embodiment, a driver 904 is data values and software instructions that, when executed, perform or otherwise enable operation of one or more functions 912 of an API 910 during loading and execution of one or more portions of a software program 902. In at least one embodiment, drivers and / or runtimes 904 are data values and software instructions that, when executed, perform or otherwise enable operation of one or more functions 912 of an API 910 during execution of a software program 902. In at least one embodiment, one or more software programs 902 use one or more APIs 910 implemented or otherwise provided by a driver and / or runtime 904 to perform combined arithmetic operations by one or more software programs 902 during execution by one or more PPUs, such as GPUs.Data CenterThe following figure presents, without limitation, exemplary data center systems that may be used to implement at least one embodiment. In at least one embodiment, one or more data center components of following figure may implement one or more aspects of an embodiment described with respect to one or more of FIGS. 1-9. In at least one embodiment, one or more data center components include one or more components of computer system 102 of FIG. 1 (e.g., NUMA nodes 108, NUMA nodes 110, processor 110, processor 116, compiler 138, memory 112, memory 118, set of APIs 130, code 140, GPU 120, and / or one or more components of set of nodes 144). In at least one embodiment, one or more data center components perform one or more aspects of API 200 of FIG. 2, API 300 of FIG. 3, and / or API 400 of FIG. 4. In at least one embodiment, one or more data center components perform one or more aspects of technique 500 of FIG. 5, technique 600 of FIG. 6, and / or technique 700 of FIG. 7. In at least one embodiment, one or more data center components include processor 800 of FIG. 8 and / or one or more modules shown or described with reference to FIG. 8. In at least one embodiment, one or more data center components include and / or perform one or more aspects of environment 900 of FIG. 9 (e.g., drivers and / or runtimes 904, one or more APIs 910, and / or one or more functions of functions 912).FIG. 10 illustrates an example data center 1000, according to at least one embodiment. In at least one embodiment, data center 1000 includes, without limitation, a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.In at least one embodiment, as shown in FIG. 10, data center infrastructure layer 1010 may include resource orchestrator 1012, grouped computing resources 1014, and node computing resources ("node-C.R.s" 1016( 1)- 1016(N), where "N" represents any integer, positive integer. In at least one embodiment, node C.R.s 1016( 1)- 1016(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays ("FPGAs"), computing units ("DPUs") in network devices, graphics processors, etc.), memory devices (e.g., dynamic read only memories), memory devices (e.g., solid state or disk drives), network input / output devices ("NW I / O" devices), network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more node C.R.s from node C.R.s 1016( 1)- 1016(N) may be a server that includes one or more of above computing resources.In at least one embodiment, grouped computing resources 1014 may include separate groupings of node C.R.s residing in one or more racks (not shown) or many racks residing in data centers at different geographic locations (also not shown). Separate groupings of node C.R.s within the grouped computing resources 1014 may include grouped computing, network, storage, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, multiple node C.R.s including CPUs or processors may be grouped into one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.In at least one embodiment, resource orchestrator 1012 may configure or otherwise control one or more node C.R.s 1016( 1)- 1016(N) and / or grouped computing resources 1014. In at least one embodiment, resource orchestrator 1012 may include a software design infrastructure ("SDI") management entity for data center 1000. In at least one embodiment, resource orchestrator 1012 may include hardware, software, or any combination thereof.In at least one embodiment, as shown in FIG. 10, framework layer 1020 includes, without limitation, a job scheduler 1032, a configuration manager 1034, a resource manager 1036, and a distributed file system 1038. In at least one embodiment, framework layer 1020 may include a framework to support software 1052 of software layer 1030 and / or one or more application(s) 1042 of application layer 1040. In at least one embodiment, software 1052 or application(s) 1042 may each include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1020 may be any type of free and open source software web application framework, such as, but not limited to, Apache SparkTM (hereafter "Spark"), which distributed file system 1038 may use for big-attached data processing (e.g., "Big Data"). In at least one embodiment, job scheduler 1032 may include a spark driver to facilitate scheduling workloads supported by different layers of data center 1000. In at least one embodiment, configuration manager 1034 may be capable of configuring various layers, such as software layer 1030 and framework layer 1020, including spark and distributed file system 1038 to support customized data processing. In at least one embodiment, resource manager 1036 may be capable of managing clustered or grouped computing resources mapped to or assigned to support distributed file system 1038 and job scheduler 1032. In at least one embodiment, clustered or grouped computing resources may include grouped computing resource 1014 at data center infrastructure layer 1010. In at least one embodiment, resource manager 1036 may coordinate with resource orchestrator 1012 to manage these mapped or allocated computing resources.In at least one embodiment, software 1052 included in software layer 1030 may include software used by at least portions of node C.R.s 1016( 1)- 1016(N), grouped computing resources 1014, and / or distributed file system 1038 of framework layer 1020. One or more types of software may include, but are not limited to, Internet web page search software, email virus scan software, database software, and streaming video content software.In at least one embodiment, application(s) 1042 included in application layer 1040 may include one or more types of applications used by at least portions of node C.R.s 1016( 1)- 1016(N), grouped computing resources 1014, and / or distributed file system 1038 of framework layer 1020. In at least one or more types of applications, CUDA applications may include without limitation.In at least one embodiment, any of configuration manager 1034, resource manager 1036, and resource orchestrator 1012 may implement any number and type of self-modifying actions based on any amount and type of data captured in any technically possible manner. In at least one embodiment, self-modifying actions may offload a data center operator of data center 1000 from making potentially bad configuration decisions and avoiding potentially underutilized and / or poorly executing portions of a data center.Computer-Based SystemsThe following figures set forth, without limitation, example computer-based systems that may be used to implement at least one embodiment. In at least one embodiment, one or more computer-based systems of following figures implement one or more aspects of one or more embodiments described with respect to one or more of FIGS. 1-9. In at least one embodiment, one or more computer-based systems include one or more components of computer system 102 of FIG. 1 (e.g., NUMA nodes 108, NUMA nodes 110, processor 110, processor 116, compiler 138, memory 112, memory 118, set of APIs 130, code 140, GPU 120, and / or one or more components of set of nodes 144). In at least one embodiment, one or more computer-based systems perform one or more aspects of API 200 of FIG. 2, API 300 of FIG. 3, and / or API 400 of FIG. 4. In at least one embodiment, one or more computer-based systems perform one or more aspects of technique 500 of FIG. 5, technique 600 of FIG. 6, and / or technique 700 of FIG. 7. In at least one embodiment, one or more computer-based systems include processor 800 of FIG. 8 and / or one or more modules shown or described with reference to FIG. 8. In at least one embodiment, one or more computer-based systems include and / or perform one or more aspects of environment 900 of FIG. 9 (e.g., drivers and / or runtimes 904, one or more APIs 910, and / or one or more functions of functions 912).FIG. 11 illustrates a processing system 1100, according to at least one embodiment. In at least one embodiment, processing system 1100 includes one or more processors 1102 and one or more graphics processors 1108, and may be a single processor desktop system, multiprocessor workstation system, or a server system having a large number of processors 1102 or processor cores 1107. In at least one embodiment, processing system 1100 is a processing platform integrated into a system on a chip ("SoC") integrated circuit for use in mobile, handheld, or embedded devices. In at least one embodiment, a processor core 1107 is referred to as a computing device or computing device.In at least one embodiment, processing system 1100 may include or be incorporated into a server-based gaming platform, a gaming console, a media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In at least one embodiment, processing system 1100 is a mobile phone, a smartphone, a tablet computing device, or a mobile Internet device. In at least one embodiment, processing system 1100 may also include, be coupled to, or incorporated into a wearable device, such as a smart watch wearable device, smart glasses device, augmented reality device, or virtual reality device. In at least one embodiment, processing system 1100 is a television or set-top box device having one or more processors 1102 and a graphical interface generated by one or more graphics processors 1108.In at least one embodiment, one or more processors 1102 each include one or more processor cores 1107 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores 1107 is configured to process a specific instruction set 1109. In at least one embodiment, instruction set 1109 may enable complex instruction set computing ("CISC"), reduced instruction set computing ("RISC"), or computing via a very long instruction word ("VLIW"). In at least one embodiment, processor cores 1107 may each process a different instruction set 1109, which may include instructions to enable emulation of different instruction sets. In at least one embodiment, processor core 1107 may also include other processing devices, such as a digital signal processor ("DSP").In at least one embodiment, processor 1102 includes cache memories ("caches") 1104. In at least one embodiment, processor 1102 may include a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 1102. In at least one embodiment, processor 1102 also uses an external cache (e.g., a level 3 ("L3") cache or a last level ("LLC") cache) (not shown) that may be shared by processor cores 1107 using known cache coherency techniques. In at least one embodiment, register file 1106 is additionally included in processor 1102, which may include various types of registers for storing various types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). In at least one embodiment, register file 1106 may include general purpose registers or other registers.In at least one embodiment, one or more processor(s) 1102 are coupled to one or more interface bus(s) 1110 to transmit communication signals, such as address, data, or control signals, between processor 1102 and other components in processing system 1100. In at least one embodiment, interface bus 1110, in one embodiment, may be a processor bus, such as a version of a direct media interface ("DMI") bus. In at least one embodiment, interface bus 1110 is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., "PCI", PCI Express ("PCIe")), memory buses, or other types of interface buses. In at least one embodiment, processor(s) 1102 include an integrated memory controller 1116 and a platform controller hub 1130. In at least one embodiment, memory controller 1116 enables communication between a memory device and other components of processing system 1100 while platform controller hub ("PCH") 1130 provides connections to input / output ("I / O") devices via a local I / O bus. In at least one embodiment, one or more peripheral component interconnect buses include PCIe Gen 5 which provides an interface for processors.In at least one embodiment, memory device 1120 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, a phase change memory device, or other suitable performance memory device to serve as processor memory. In at least one embodiment, memory device 1120 may operate as system memory for processing system 1100 to store data 1122 and instructions 1121 for use when one or more processors 1102 execute an application or process. In at least one embodiment, memory controller 1116 also couples to an optional external graphics processor 1112, which may communicate with one or more graphics processors 1108 in processors 1102 to perform graphics and media operations. In at least one embodiment, a display device 1111 may connect to processor(s) 1102. In at least one embodiment, display device 1111 may include one or more of an internal display device, such as in a mobile electronic device or a laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, display device 1111 may include a head mounted display ("FIMIDE"), such as a stereoscopic display device, for use in virtual reality ("VR") applications or augmented reality ("AR") applications.In at least one embodiment, platform control hub 1130 allows peripheral devices to connect to memory device 1120 and processor 1102 via a high speed I / O bus. In at least one embodiment, I / O peripherals include, but are not limited to, an audio controller 1146, a network controller 1134, a firmware interface 1128, a wireless transceiver 1126, touch sensors 1125, a data storage device 1124 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage device 1124 may connect via a memory interface (e.g., SATA) or via a peripheral bus, such as PCI or PCIe. In at least one embodiment, touch sensors 1125 may include touch screen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver 1126 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or long term evolution ("LTE") transceiver. In at least one embodiment, firmware interface 1128 enables communication with system firmware and may be, for example, a unified extensible firmware interface ("UEFI"). In at least one embodiment, network controller 1134 may enable network connection to a wired network. In at least one embodiment, a high performance network controller (not shown) couples to interface bus 1110. In at least one embodiment, audio controller 1146 is a multi-channel high resolution audio controller. In at least one embodiment, processing system 1100 includes an optional legacy I / O controller 1140 for coupling legacy devices (e.g., personal system 2 ("PS / 2")) to processing system 1100. In at least one embodiment, platform controller hub 1130 may also be connected to one or more universal serial bus ("USB") controllers 1142 that connect input devices, such as keyboard and mouse combinations 1143, a camera 1144, or other USB input devices.In at least one embodiment, an instance of memory controller 1116 and platform controller hub 1130 may be integrated into a discrete external graphics processor, such as external graphics processor 1112. In at least one embodiment, platform controller hub 1130 and / or memory controller 1116 may be external to one or more processor(s) 1102. For example, in at least one embodiment, processing system 1100 may include an external memory controller 1116 and a platform controller hub 1130, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset in communication with processor(s) 1102.FIG. 12 illustrates a computer system 1200, according to at least one embodiment. In at least one embodiment, computer system 1200 may be a system having interconnected devices and components, an SOC, or any combination thereof. In at least one embodiment, computer system 1200 is formed with a processor 1202, which may include execution units for executing an instruction. In at least one embodiment, computer system 1200 may include, without limitation, a component, such as processor 1202, to use execution units that include logic to perform algorithms for processing data. In at least one embodiment, computer system 1200 may include processors, such as PENTIUM® family of processors, XeonTM, Itanium® XScaleTM, and / or StrongARMTM, Intel® Core™ or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, and the like) may also be used. In at least one embodiment, computer system 1200 may execute a version of WINDOWS operating system available from Microsoft Corporation of Redmond, California, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.In at least one embodiment, computer system 1200 may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (DSP), a SoC, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of performing one or more instructions.In at least one embodiment, computer system 1200 may include, without limitation, processor 1202, which may include, without limitation, one or more execution units 1208, which may be configured to execute a unified computing device architecture ("CUDA") program (CUDA® developed by NVIDIA Corporation of Santa Clara, California). In at least one embodiment, a CUDA program is at least a portion of a software application written in a CUDA programming language. In at least one embodiment, computer system 1200 is a single processor desktop or server system. In at least one embodiment, computer system 1200 may be a multiprocessor system. In at least one embodiment, processor 1202 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as, for example, a digital signal processor. In at least one embodiment, processor 1202 may be coupled to a processor bus 1210, which may transmit data signals between processor 1202 and other components in computer system 1200.In at least one embodiment, processor 1202 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1204. In at least one embodiment, processor 1202 may include a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may be external to processor 1202. In at least one embodiment, processor 1202 may also include a combination of both internal and external caches. In at least one embodiment, a register file 1206 may store various types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and instruction pointer registers.In at least one embodiment, execution unit 1208 is also located in processor 1202, including, without limitation, logic for performing integer and floating point operations. The processor 1202 may also include microcode ("ucode") read-only memory ("ROM") that stores microcode for certain microinstruction. In at least one embodiment, execution unit 1208 may include logic to handle a packed instruction set 1209. In at least one embodiment, by including packaged instruction set 1209 in an instruction set of a general purpose processor 1202, along with associated circuitry for executing instructions, operations used by many multimedia applications may be performed using packaged data in a general purpose processor 1202. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently using full width of a processor's data bus to perform operations on packed data, which may eliminate a need to transfer smaller units of data across a processor's data bus to perform one or more operations one data element at a time.In at least one embodiment, execution unit 1208 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuitry. In at least one embodiment, computer system 1200 may include, but is not limited to, memory 1220. In at least one embodiment, memory 1220 may be implemented as a DRAM device, an SRAM device, a flash memory device, or another memory device. The memory 1220 may store instruction(s) 1219 and / or data 1221 represented by data signals executable by the processor 1202.In at least one embodiment, a system logic chip may be coupled to processor bus 1210 and memory 1220. In at least one embodiment, system logic chip may include, but is not limited to, a memory control hub ("MCH") 1216, and processor 1202 may communicate with MCH 1216 via processor bus 1210. In at least one embodiment, MCH 1216 may provide a high bandwidth storage path 1218 to memory 1220 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1216 may route data signals between processor 1202, memory 1220, and other components in computer system 1200 and bridge data signals between processor bus 1210, memory 1220, and a system I / O 1222. In at least one embodiment, system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1216 may be coupled to memory 1220 through high bandwidth storage path 1218, and graphics / video card 1212 may be coupled to MCH 1216 through an accelerated graphics port ("AGP") connection 1214.In at least one embodiment, computer system 1200 may use system I / O 1222, which is a proprietary hub interface bus, to couple MCH 1216 to I / O controller hub ("ICH") 1230. In at least one embodiment, ICH 1230 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, local I / O bus may include, without limitation, a high speed I / O bus for connecting peripherals to memory 1220, a chipset, and processor 1202. Examples may include, without limitation, an audio controller 1229, a firmware hub ("flash BIOS") 1228, a wireless transceiver 1226, a data storage 1224, an legacy I / O controller 1223 including a user input interface 1225 and a keyboard interface, a serial expansion port 1227 such as a USB, and a network controller 1234. The data store 1224 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.In at least one embodiment, FIG. 12 may illustrate an example SoC. In at least one embodiment, devices illustrated in FIG. 12 may be connected to proprietary connections, standardized connections (e.g., PCIe), or any combination thereof. In at least one embodiment, one or more components of system 1200 are interconnected using CXL connections (CXL=compute express link).FIG. 13 illustrates a system 1300 according to at least one embodiment. In at least one embodiment, system 1300 is an electronic device that uses a processor 1310. In at least one embodiment, system 1300 may be, for example and without limitation, a notebook, a mast server, a rack server, a blade server, an edge device communicatively coupled to one or more on-premium or cloud service providers, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.In at least one embodiment, system 1300 may include, without limitation, processor 1310 communicatively coupled to any suitable number or type of components, peripheral devices, modules, or devices. In at least one embodiment, processor 1310 is coupled using a bus or interface, such as an I 2 C bus, a system management ("SM") bus, an LPC (Low Pin Count) bus, an SPI (SPI= Ser Peripheral Interface), an HDA (High Definition Audio) bus, a SATA (Serial Advance Technology Attachment) bus, a USB (Versions 1, 2, 3) bus, or a UART (Universal Asynchronous Receiver / Transmitter) bus. In at least one embodiment, FIG. 13 may illustrate an example SoC. In at least one embodiment, devices illustrated in FIG. 13 may be connected to proprietary connections, standardized connections (e.g., PCIe), or any combination thereof. In at least one embodiment, one or more components of FIG. 13 are interconnected using CXL connections.In at least one embodiment, FIG. 13 may include a display 1324, a touch screen 1325, a touchpad 1330, a near field communication unit ("NFC") 1345, a sensor hub 1340, a thermal sensor 1346, an express chipset ("EC") 1335, a trusted platform module ("TPM") 1338, BIOS / firmware / flash memory ("BIOS, FW flash") 1322, a DSP 1360, a solid state disk ("SSD") or a hard disk drive ("HDD") 1320, a wireless local area network unit ("WLAN") 1350, a Bluetooth unit 1352, a wireless wide area network ("WWAN") unit 1356; a global positioning system ("GPS") 1355, a camera ("USB 3.0 camera") 1354 such as a USB 3.0 camera; or a low power double data rate ("LPDDR") storage unit ("LPDDR3") 1315 implemented in the LPDDR3 standard, for example. These components may each be implemented in any suitable manner.In at least one embodiment, other components may be communicatively coupled to processor 1310 by components discussed above. In at least one embodiment, accelerometer 1341, ambient light sensor ("ALS") 1342, compass 1343, and gyroscope 1344 may be communicatively coupled to sensor hub 1340. In at least one embodiment, a thermal sensor 1339, a fan 1337, a keyboard 1336, and a touchpad 1330 may be communicatively coupled to EC 1335. In at least one embodiment, speaker 1363, earphone 1364, and microphone ("mic") 1365 may be communicatively coupled to audio unit ("audio codec and class D amplifier") 1362, which in turn may be communicatively coupled to DSP 1360. In at least one embodiment, audio unit 1362 may include, for example and without limitation, an audio coder / decoder ("codec") and a class D amplifier. In at least one embodiment, a SIM card ("SIM") 1357 may be communicatively coupled to WWAN unit 1356. In at least one embodiment, components such as WLAN unit 1350 and Bluetooth unit 1352, as well as WWAN unit 1356, may be implemented in a next generation form factor ("NGFF").FIG. 14 illustrates an example integrated circuit 1400, according to at least one embodiment. In at least one embodiment, example integrated circuit 1400 is a SoC that may be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 1400 includes one or more application processor(s) 1405 (e.g., CPUs, DPUs), at least one graphics processor 1410, and may additionally include an image processor 1415 and / or a video processor 1420, each of which may be a modular IP core. In at least one embodiment, integrated circuit 1400 includes peripheral or bus logic including a USB controller 1425, a UART controller 1430, an SPI / SDIO controller 1435, and an I 2 S / I 2 C controller 1440. In at least one embodiment, integrated circuit 1400 may include a display device 1445 coupled to one or more of a high definition multimedia interface ("HDMI") controller 1450 and a mobile industry processor interface ("MIPI") display interface 1455. In at least one embodiment, memory may be provided by a flash memory subsystem 1460 that includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1465 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1470.In at least one embodiment, computer system 1500 includes a processing subsystem 1501 having one or more processor(s) 1502 and a system memory 1504 that communicates via a connection path that may include a memory hub 1505. In at least one embodiment, storage hub 1505 may be a separate component within a chipset component or may be integrated within one or more processor(s) 1502. In at least one embodiment, storage hub 1505 is coupled to an I / O subsystem 1511 via a communication link 1506. In at least one embodiment, I / O subsystem 1511 includes an I / O hub 1507 that may enable computer system 1500 to receive input from one or more input device(s) 1508. In at least one embodiment, I / O hub 1507 may enable a display controller, which may be included in one or more processor(s) 1502, to provide output to one or more display device(s) 1510A. In at least one embodiment, one or more display device(s) 1510A coupled to I / O hub 1507 may include a local, internal, or embedded display device.In at least one embodiment, processing subsystem 1501 includes one or more parallel processor(s) 1512 coupled to memory hub 1505 via a bus or other communication link 1513. In at least one embodiment, communication link 1513 may be any of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCIe, or may be a proprietary communication interface or communication fabric. In at least one embodiment, one or more parallel processor(s) 1512 form a computationally focused parallel or vector processing system that may include a large number of processing cores and / or processing clusters, such as a multi-core processor or many computational units. In at least one embodiment, one or more parallel processor(s) 1512 form a graphics processing subsystem that can output pixels to one of one or more display device(s) 1510A coupled via I / O hub 1507. In at least one embodiment, one or more parallel processor(s) 1512 may also include a display controller and display interface (not shown) to enable direct connection to one or more display device(s) 1510B.In at least one embodiment, a system storage unit 1514 may connect to I / O hub 1507 to provide a storage mechanism for computing system 1500. In at least one embodiment, an I / O switch 1516 may be used to provide an interface mechanism to enable connections between I / O hub 1507 and other components, such as a network adapter 1518 and / or a wireless network adapter 1519 that may be integrated into a platform, and various other devices that may be added via one or more accessory device(s) 1520. In at least one embodiment, network adapter 1518 may be an Ethernet adapter or other wired network adapter. In at least one embodiment, wireless network adapter 1519 may include one or more of a Wi-Fi, Bluetooth, NFC, or other network device that includes one or more wireless radios.In at least one embodiment, computing system 1500 may include other components not explicitly shown, including USB or other connector connections, optical storage drives, video capture devices, and the like, which may also be connected to I / O hub 1507. In at least one embodiment, communication paths connecting various components in FIG. 15 may be implemented using any suitable protocols, such as PCI-based protocols (e.g., PCIe) or other bus or point-to-point communication interfaces and / or protocol(s) such as NVLink high-speed connection or connection protocols.In at least one embodiment, one or more parallel processor(s) 1512 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and represents a graphics processing unit ("GPU"). In at least one embodiment, one or more parallel processor(s) 1512 include circuitry optimized for general purpose processing. In at least one embodiment, components of computing system 1500 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processor(s) 1512, memory hub 1505, processor(s) 1502, and I / O hub 1507 may be integrated into a SoC integrated circuit. In at least one embodiment, components of computing system 1500 may be integrated into a single package to form a system-in-package ("SIP") configuration. In at least one embodiment, at least a portion of components of computing system 1500 may be integrated into a multi-chip module ("MCM"), which may be connected to other multi-chip modules to form a modular computing system. In at least one embodiment, I / O subsystem 1511 and display devices 1510B are omitted from computing system 1500. In at least one embodiment, one or more parallel processor(s) 1512 include one or more tensor storage accelerator (TMA) units that can transfer data blocks between global memory and shared memory. In at least one embodiment, one or more processors use or access one or more TMAs to perform bidirectional copy operations, e.g., global to shared memory, and vice versa.Processing SystemsThe following figures set forth, without limitation, example processing systems that may be used to implement at least one embodiment. In at least one embodiment, one or more processing systems of following figures implement one or more aspects of one or more embodiments described with respect to one or more of FIGS. 1-9. In at least one embodiment, one or more processing systems include one or more components of computer system 102 of FIG. 1 (e.g., NUMA nodes 108, NUMA nodes 110, processor 110, processor 116, compiler 138, memory 112, memory 118, set of APIs 130, code 140, GPU 120, and / or one or more components of set of nodes 144). In at least one embodiment, one or more processing systems perform one or more aspects of API 200 of FIG. 2, API 300 of FIG. 3, and / or API 400 of FIG. 4. In at least one embodiment, one or more processing systems perform one or more aspects of technique 500 of FIG. 5, technique 600 of FIG. 6, and / or technique 700 of FIG. 7. In at least one embodiment, one or more processing systems include processor 800 of FIG. 8 and / or one or more modules shown or described with reference to FIG. 8. In at least one embodiment, one or more processing systems include and / or perform one or more aspects of environment 900 of FIG. 9 (e.g., drivers and / or runtimes 904, one or more APIs 910, and / or one or more functions of functions 912).FIG. 16 illustrates an accelerated processing unit ("APU") 1600, according to at least one embodiment. In at least one embodiment, APU 1600 may be configured to execute an application program, such as a CUDA program. In at least one embodiment, APU 1600 includes, without limitation, a core complex 1610, a graphics complex 1640, a fabric 1660, I / O interfaces 1670, memory controllers 1680, a display controller 1692, and a multimedia engine 1694. In at least one embodiment, APU 1600 may include, without limitation, any number of core complexes 1610, any number of graphics complexes 1650, any number of display controllers 1692, and any number of multimedia engines 1694, in any combination. For purposes of explanation, multiple instances of like objects are referred to herein with reference numerals identifying the object and parenthetistic numbers identifying the instance where they are needed.In at least one embodiment, core complex 1610 is a CPU, graphics complex 1640 is a GPU, and APU 1600 is a processing unit that integrates 1610 and 1640 on a single chip without limitation. In at least one embodiment, some tasks may be assigned to core complex 1610 and other tasks may be assigned to graphics complex 1640. In at least one embodiment, core complex 1610 is configured to execute master control software associated with APU 1600, such as an operating system. In at least one embodiment, core complex 1610 is main processor of APU 1600 that controls and coordinates operations of other processors. In at least one embodiment, core complex 1610 issues commands that control operation of graphics complex 1640. In at least one embodiment, core complex 1610 may be configured to execute host executable code derived from CUDA source code, and graphics complex 1640 may be configured to execute device executable code derived from CUDA source code.In at least one embodiment, core complex 1610 includes, without limitation, cores 1620( 1)- 1620( 4) and an L3 cache 1630. In at least one embodiment, core complex 1610 may include, without limitation, any number of cores 1620 and any number and type of caches in any combination. In at least one embodiment, cores 1620 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1620 is a CPU core. In at least one embodiment, core 1620 is referred to as a computing device or computing device.In at least one embodiment, each core 1620 includes, without limitation, a fetch / decode unit 1622, an integer execution engine 1624, a floating point execution engine 1626, and an L2 cache 1628. In at least one embodiment, fetch / decode unit 1622 fetches instructions, decodes such instructions, generates micro-operations, and sends separate microinstructions to integer execution engine 1624 and floating point execution engine 1626. In at least one embodiment, fetch / decode unit 1622 may simultaneously dispatch one microinstruction to integer execution engine 1624 and another microinstruction to floating point execution engine 1626. In at least one embodiment, integer execution engine 1624 performs integer and memory operations without limitation. In at least one embodiment, floating point engine 1626 performs floating point and vector operations without limitation. In at least one embodiment, fetch / decode unit 1622 sends microinstructions to a single execution engine that replaces both integer execution engine 1624 and floating point execution engine 1626.In at least one embodiment, each core 1620(i), where i is an integer representing a particular instance of core 1620, may access L2 cache 1628(i) included in core 1620(i). In at least one embodiment, each core 1620 included in core complex 1610(j), each integer representing a particular instance of core complex 1610, is linked to other cores 1620 included in core complex 1610(j) via L3 cache 1630(j) included in core complex 1610(j). In at least one embodiment, cores 1620 included in core complex 1610(j), where j is an integer representing a particular instance of core complex 1610, may access entire L3 cache 1630(j) included in core complex 1610(j). In at least one embodiment, L3 cache 1630 may include, without limitation, any number of slices.In at least one embodiment, graphics complex 1640 may be configured to perform computational operations in a highly parallel manner. In at least one embodiment, graphics complex 1640 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometric computations, and other operations associated with rendering an image on a display. In at least one embodiment, graphics complex 1640 is configured to perform operations that do not relate to graphics. In at least one embodiment, graphics complex 1640 is configured to perform both operations related to graphics and operations not related to graphics.In at least one embodiment, graphics complex 1640 includes, without limitation, any number of compute units 1650 and an L2 cache 1642. In at least one embodiment, compute units 1650 share L2 cache 1642. In at least one embodiment, L2 cache 1642 is partitioned. In at least one embodiment, graphics complex 1640 includes, without limitation, any number of compute units 1650 and any number (including zero) and type of caches. In at least one embodiment, graphics complex 1640 includes, without limitation, any amount of dedicated graphics hardware.In at least one embodiment, each computing unit 1650 includes, without limitation, any number of SIMD units 1652 and shared memory 1654. In at least one embodiment, each SIMD unit 1652 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each compute unit 1650 may execute any number of thread blocks, but each thread block is executed on a single compute unit 1650. In at least one embodiment, a thread block includes, without limitation, any number of execution threads. In at least one embodiment, a working group is a thread block. In at least one embodiment, each SIMD unit 1652 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in warp belongs to a single thread block and is configured to process a different dataset based on a single instruction set. In at least one embodiment, prediction may be used to disable one or more threads in a warp. In at least one embodiment, a trace is a thread. In at least one embodiment, a work element is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize with each other and communicate via shared memory 1654. In at least one embodiment, each compute unit 1650 includes one or more thread block clusters, where a thread block cluster may enable programmatic control of locality at a granularity greater than a single thread block of a single streaming multiprocessor (SM). In at least one embodiment, thread block clusters (also referred to as "clusters") allow multiple thread blocks that concurrently pass over streaming multiprocessors to synchronize and shared fetch, exchange, or otherwise use data.In at least one embodiment, fabric 1660 is a system interconnect that enables data and control transfers via core complex 1610, graphics complex 1640, I / O interfaces 1670, memory controllers 1680, display controller 1692, and multimedia engine 1694. In at least one embodiment, APU 1600 may include, without limitation, any amount and type of system connection in addition to or in place of fabric 1660, which enables data and control transfers via any number and type of directly or indirectly connected components, which may be internal or external to APU 1600. In at least one embodiment, I / O interfaces 1670 are representative of any number and type of I / O interfaces (e.g., PCI, PCI extended ("PCI-X"), PCIe, gigabit Ethernet ("GBE"), USB, etc.). In at least one embodiment, peripheral devices coupled to I / O interfaces 1670 may include, without limitation, keyboards, mice, printers, scanners, joysticks, or other types of game controllers, media recording devices, external storage devices, network interface cards, and so forth.In at least one embodiment, display controller AMD 92 displays images on one or more display device(s), such as a liquid crystal display ("LCD") device. In at least one embodiment, multimedia engine 1694 includes, without limitation, any amount and type of circuitry related to multimedia, such as a video decoder, a video encoder, an image signal processor, etc. In at least one embodiment, memory controllers 1680 enable communications between APU 1600 and unified system memory 1690. In at least one embodiment, core complex 1610 and graphics complex 1640 share unified system memory 1690.In at least one embodiment, APU 1600 implements a storage subsystem that includes, without limitation, any set and type of storage controllers 1680 and storage devices (e.g., shared memory 1654) that may be dedicated to one component or shared among multiple components. In at least one embodiment, APU 1600 implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 caches 1728, L3 cache 1630, and L2 cache 1642), which may each be private or shared for any number of components (e.g., cores 1620, core complex 1610, SIMD units 1652, compute units 1650, and graphics complex 1640).FIG. 17 illustrates a CPU 1700, according to at least one embodiment. In at least one embodiment, CPU 1700 may be configured to execute an application program. In at least one embodiment, CPU 1700 is configured to execute master control software, such as an operating system. In at least one embodiment, CPU 1700 issues commands that control operation of an external GPU (not shown). In at least one embodiment, CPU 1700 may be configured to execute host executable code derived from CUDA source code, and an external GPU may be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, CPU 1700 includes, without limitation, any number of core complexes 1710, fabric 1760, I / O interfaces 1770, and memory controllers 1780.In at least one embodiment, core complex 1710 includes, without limitation, cores 1720( 1)- 1720( 4) and an L3 cache 1730. In at least one embodiment, core complex 1710 may include, without limitation, any number of cores 1720 and any number and type of caches in any combination. In at least one embodiment, cores 1720 are configured to execute instructions of a particular ISA. In at least one embodiment, each core 1720 is a CPU core.In at least one embodiment, each core 1720 includes, without limitation, a fetch / decode unit 1722, an integer execution engine 1724, a floating point execution engine 1726, and an L2 cache 1728. In at least one embodiment, fetch / decode unit 1722 fetches instructions, decodes such instructions, generates micro-operations, and sends separate microinstructions to integer execution engine 1724 and floating point execution engine 1726. In at least one embodiment, fetch / decode unit 1722 may simultaneously dispatch one microinstruction to integer execution engine 1724 and another microinstruction to floating point execution engine 1726. In at least one embodiment, integer execution engine 1724 performs integer and storage operations without limitation. In at least one embodiment, floating point engine 1726 performs floating point and vector operations without limitation. In at least one embodiment, fetch / decode unit 1722 sends microinstructions to a single execution engine that replaces both integer execution engine 1724 and floating point execution engine 1726.In at least one embodiment, each core 1720(i), where i is an integer representing a particular instance of core 1720, may access L2 cache 1728(i) included in core 1720(i). In at least one embodiment, each core 1720 included in core complex 1710(j), each integer representing a particular instance of core complex 1710, is connected to other cores 1720 in core complex 1710(j) via L3 cache 1730(j) included in core complex 1710(j). In at least one embodiment, cores 1720 included in core complex 1710(j), where j is an integer representing a particular instance of core complex 1710, may access entire L3 cache 1730(j) included in core complex 1710(j). In at least one embodiment, L3 cache 1730 may include, without limitation, any number of slices.In at least one embodiment, fabric 1760 is a system interconnect that enables data and control transfers via core complexes 1710( 1)- 1710(N) (N being an integer greater than zero), I / O interfaces 1770, and memory controllers 1780. In at least one embodiment, CPU 1700 may include, without limitation, any amount and type of system connection in addition to or in place of fabric 1760, which enables data and control transfers via any number and type of directly or indirectly connected components, which may be internal or external to CPU 1700. In at least one embodiment, I / O interfaces 1770 are representative of any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, peripheral devices coupled to I / O interfaces 1770 may include, without limitation, displays, keyboards, mice, printers, scanners, joysticks, or other types of game controllers, media recording devices, external storage devices, network interface cards, and so forth.In at least one embodiment, memory controllers 1780 enable communications between CPU 1700 and system memory 1790. In at least one embodiment, core complex 1710 and graphics complex 1740 share system memory 1790. In at least one embodiment, CPU 1700 implements a memory subsystem that includes, without limitation, any set and type of memory controllers 1780 and memory devices that may be dedicated to one component or shared among multiple components. In at least one embodiment, CPU 1700 implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 caches 1728 and L3 caches 1730), each of which may be private or shared for any number of components (e.g., cores 1720 and core complexes 1710).FIG. 18 illustrates an example accelerator integration slice 1890, according to at least one embodiment. As used herein, a "slice" includes a specified portion of processing resources of an accelerator integration circuit. In at least one embodiment, accelerator integration circuit provides cache management, memory access, context management, and interrupt management services to multiple graphics processing engines included in a graphics acceleration module. The graphics processing engines may each include a separate GPU. Alternatively, the graphics processing engines may include various types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, graphics processing engines may be single GPUs integrated on a common package, line card, or die.An application effective address space 1882 within system memory 1814 stores process elements 1883. In one embodiment, process elements 1883 are stored in response to GPU calls 1881 from applications 1880 executing on processor 1807. A process element 1883 includes a process state for the corresponding application 1880. A work descriptor ("WD") 1884 included in process element 1883 may be a single job requested by an application or may include a pointer to a queue of jobs. In at least one embodiment, WD 1884 is a pointer to a job request queue in application effective address space 1882.Graphics acceleration module 1846 and / or individual graphics processing engines may be shared among all or a subset of processes in a system. In at least one embodiment, an infrastructure to establish a process state and send WD 1884 to graphics acceleration module 1846 to start a job in a virtualized environment may be included.In at least one embodiment, a dedicated process programming model is implementation specific. In this model, a single process has graphics acceleration module 1846 or a single graphics processing engine. Because the graphics acceleration module 1846 is owned by a single process, a hypervisor initializes an accelerator integration circuit for an ownership partition and an operating system initializes an accelerator integration circuit for an ownership process when the graphics acceleration module 1846 is assigned.In operation, a WD fetch unit 1891 in the accelerator integration slice 1890 fetches the next WD 1884 that includes an indication of work to be done by one or more graphics processing engines of the graphics acceleration module 1846. Data from the WD 1884 may be stored in registers 1845 and used by a memory management unit ("MMU") 1839, an interrupt management circuit 1847, and / or a context management circuit 1848, as illustrated. For example, one embodiment of MMU 1839 includes segment / page run circuitry for accessing segment / page tables 1886 within OS virtual address space 1885. The interrupt management circuit 1847 may process interrupt events ("INT") 1892 received from the graphics acceleration module 1846. In performing graphics operations, an effective address 1893 generated by a graphics processing engine is translated by the MMU 1839 to a true address.In one embodiment, a same set of registers 1845 are duplicated for each graphics processing engine and / or graphics acceleration module 1846, and may be initialized by a hypervisor or operating system. Each of these duplicated registers may be included in the accelerator integration slice 1890. Example registers that may be initialized by a hypervisor are shown in Table 1. Table 1 - Hypervisor-Initialized Registers Table 1 - Hypervisor-Initialized Registers1Slice Control Register2Real Address (RA) Scheduled Processes Area Pointers3Authority Mask Override Register4Interrupt Vector Table Entry Offset5Interrupt Vector Table Entry Limit6State Register7Logical Partition ID8Real Address (RA) Hypervisor Accelerator Utilization Record Pointer9Storage Description RegisterExample registers that may be initialized by an operating system are shown in Table 2. Table 2 - Operating System Initialized Registers Table 2 - Operating System Initialized Registers1Process and Thread Identification2Effective Address (EA) Context Save / Restore Pointer3Virtual Address (VA) Accelerator Utilization Record Pointer4Virtual Address (VA) Storage Segment Table Pointer5Authority Mask6Work descriptorIn one embodiment, each WD 1884 is specific to a particular graphics acceleration module 1846 and / or a particular graphics processing engine. It contains all information needed by a graphics processing engine to do work, or it may be a pointer to a storage location where an application has set up a work to be done command queue.FIGS. 19A-19B illustrate example graphics processors, in accordance with at least one embodiment. In at least one embodiment, each of example graphics processors may be manufactured using one or more IP cores. In addition to what is illustrated, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores. In at least one embodiment, example graphics processors are for use within a SoC.FIG. 19A illustrates an example graphics processor 1910 of an SoC integrated circuit that may be fabricated using one or more IP cores, in accordance with at least one embodiment. FIG. 19B illustrates an additional example graphics processor 1940 of an SoC integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor 1910 of FIG. 19A is a low power graphics processor core. In at least one embodiment, graphics processor 1940 of FIG. 19B is a higher performance graphics processor core. In at least one embodiment, each of graphics processors 1910, 1940 may be variants of graphics processor 1410 of FIG. 14.In at least one embodiment, graphics processor 1910 includes a vertex processor 1905, and one or more fragment processor(s) 1915A- 1915N (e.g., 1915A, 1915B, 1915C, 1915D through 1915N- 1, and 1915N). In at least one embodiment, graphics processor 1910 may execute various shader programs via separate logic such that vertex processor 1905 is optimized to perform operations for vertex shader programs, while one or more fragment processor(s) 1915A- 1915N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1905 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, fragment processor(s) 1915A- 1915N use primitive and vertex data generated by vertex processor 1905 to generate a frame buffer that is displayed on a display device. In at least one embodiment, fragment processor(s) 1915A- 1915N are optimized to execute fragment shader programs as provided in an OpenGL API, which may be used to perform similar operations as a pixel shader program as provided in a Direct 3D API.In at least one embodiment, graphics processor 1910 additionally includes one or more MMU(s) 1920A- 1920B, cache(s) 1925A- 1925B, and circuit interconnect(s) 1930A- 1930B. In at least one embodiment, one or more MMU(s) 1920A- 1920B provide a virtual to physical address mapping for graphics processor 1910, including vertex processor 1905 and / or fragment processor(s) 1915A- 1915N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more cache(s) 1925A- 1925B. In at least one embodiment, one or more MMU(s) 1920A- 1920B may be synchronized with other MMUs within a system, including one or more MMUs associated with one or more application processor(s) 1405, image processors 1415, and / or video processors 1420 of FIG. 14, such that each processor 1405- 1420 may participate in a shared or unified virtual storage system. In at least one embodiment, one or more circuit connection(s) 1930A- 1930B enable graphics processor 1910 to interface with other IP cores within a SoC, either via an internal bus of SoC or via a direct connection.In at least one embodiment, graphics processor 1940 includes one or more MMU(s) 1920A- 1920B, caches 1925A- 1925B, and circuit interconnects 1930A- 1930B of graphics processor 1910 of FIG. 19A. In at least one embodiment, graphics processor 1940 includes one or more shader core(s) 1955A- 1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F through 1955N- 1, and 1955N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, a number of shader cores may vary. In at least one embodiment, graphics processor 1940 includes an inter-core task manager 1945 acting as a thread dispatcher to dispatch execution threads to one or more shader cores 1955A- 1955N, and a tiling unit 1958 to accelerate tiling operations for tile-based rendering, rendering operations for a scene being divided into image space to exploit local spatial coherence within a scene or optimize use of internal caches, for example.FIG. 20A illustrates a graphics core 2000, according to at least one embodiment. In at least one embodiment, graphics core 2000 may be included in graphics processor 1410 of FIG. 14. In at least one embodiment, graphics core 2000 may be a unified shader core 1955A- 1955N as in FIG. 19B. In at least one embodiment, graphics core 2000 includes a shared instruction cache 2002, a texture unit 2018, and a cache / shared memory 2020 that are shared with execution resources within graphics core 2000. In at least one embodiment, graphics core 2000 may include multiple slices 2001A- 2001N or partition for each core, and a graphics processor may include multiple instances of graphics core 2000. Slices 2001A- 2001N may include support logic including a local instruction cache 2004A- 2004N, a thread scheduler 2006A- 2006N, a thread dispatcher 2008A- 2008N, and a set of registers 2010A- 2010N. In at least one embodiment, slices 2001A- 2001N may include a set of additional functional units ("AFUs") 2012A- 2012N, floating point units ("FPUs") 2014A- 2014N, integer arithmetic logic units ("ALUs") 2016-2016N, address computational units ("ACUs") 2013A- 2013N, double precision floating point units ("DPFPUs") 2015A- 2015N, and matrix processing units ("MPUs") 2017A- 2017N. In at least one embodiment, a graphics core 2000 is referred to as a computing device or computing device.In at least one embodiment, FPUs 2014A- 2014N may perform single precision (32-bit) and half precision (16-bit) floating point operations while DPFPUs 2015A- 2015N may perform double precision (64-bit) floating point operations. In at least one embodiment, ALUs 2016A- 2016N may perform variable precision integer operations with 8-bit, 16-bit, and 32-bit precision, and may be configured for mixed precision operations. In at least one embodiment, MPUs 2017A- 2017N may also be configured for mixed precision matrix operations, including half precision floating point operations and 8-bit integer operations. In at least one embodiment, MPUs 2017-2017N may perform a variety of matrix operations to accelerate CUDA programs, including facilitating support for accelerated general matrix-matrix multiplication ("GEMM"). In at least one embodiment, AFUs 2012A-2012N may perform additional logic operations not supported by floating point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).FIG. 20B illustrates a general purpose graphics processing unit ("GPGPU") 2030 in accordance with at least one embodiment. In at least one embodiment, GPGPU 2030 is highly parallel and suitable for use on a multi-chip module. In at least one embodiment, GPGPU 2030 may be configured to allow highly parallel computational operations to be performed by an array of GPUs. In at least one embodiment, GPGPU 2030 may be directly associated with other instances of GPGPU 2030 to generate a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU 2030 includes a host interface 2032 to enable connection to a host processor. In at least one embodiment, host interface 2032 is a PCIe interface. In at least one embodiment, host interface 2032 may be a proprietary communication interface or communication fabric. In at least one embodiment, GPGPU 2030 receives instructions from a host processor and uses a global scheduler 2034 to distribute execution threads associated with these instructions to a set of compute clusters 2036A- 2036H. In at least one embodiment, compute clusters 2036A- 2036H share a cache memory 2038. In at least one embodiment, cache 2038 may serve as a higher level cache for caches within compute clusters 2036A- 2036H.In at least one embodiment, GPGPU 2030 includes memory 2044A- 2044B coupled to compute clusters 2036A- 2036H via a set of memory controllers 2042A- 2042B. In at least one embodiment, memory 2044A- 2044B may include various types of memory devices, including DRAM or graphics random access memory, such as synchronous graphics random access memory ("SGRAM"), including dual data rate graphics memory ("GDDR").In at least one embodiment, compute clusters 2036A- 2036Heach include a set of graphics cores, such as graphics core 2000 of FIG. 20A, which may include multiple types of integer and floating point logic units that may perform computational operations with a number of precisions, including suitable for computations associated with CUDA programs. For example, in at least one embodiment, at least a subset of floating point units in each of compute clusters 2036A- 2036H may be configured to perform 16-bit or 32-bit floating point operations, while another subset of floating point units may be configured to perform 64-bit floating point operations.In at least one embodiment, multiple instances of GPGPU 2030 may be configured to operate as a compute cluster. The compute clusters 2036A- 2036H may implement any technically possible communication techniques for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 2030 communicate via host interface 2032. In at least one embodiment, GPGPU 2030 includes an I / O hub 2039 that couples GPGPU 2030 to a GPU link 2040 that enables direct connection to other instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a dedicated GPU-to-GPU bridge that facilitates communication and synchronization between multiple instances of GPGPU 2030. In at least one embodiment, GPU link 2040 couples to a high speed link to transmit and receive data to other GPGPUs 2030 or parallel processors. In at least one embodiment, multiple instances of GPGPU 2030 reside in separate computing systems and communicate via a network device that can be accessed via host interface 2032. In at least one embodiment, GPU link 2040 may be configured to enable connection to a host processor in addition to or as an alternative to host interface 2032. In at least one embodiment, GPGPU 2030 may be configured to execute a CUDA program.FIG. 21A illustrates a parallel processor 2100, according to at least one embodiment. In at least one embodiment, various components of parallel processor 2100 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits ("ASICs"), or FPGAs.In at least one embodiment, parallel processor 2100 includes a parallel processing unit 2102. In at least one embodiment, parallel processing unit 2102 includes an I / O unit 2104 that enables communication with other devices, including other instances of parallel processing unit 2102. In at least one embodiment, I / O unit 2104 may be directly connected to other devices. In at least one embodiment, I / O unit 2104 connects to other devices via use of a hub or switch interface, such as storage hub 2105. In at least one embodiment, connections between storage hub 2105 and I / O unit 2104 form a communication link. In at least one embodiment, I / O unit 2104 connects to a host interface 2106 and a memory crossbar 2116, where host interface 2106 receives commands directed to performing processing operations and memory crossbar 2116 receives commands directed to performing memory operations.In at least one embodiment, when host interface 2106 receives a command buffer via I / O unit 2104, host interface 2106 may direct operational operations to perform these commands to a front end 2108. In at least one embodiment, front end 2108 couples to a scheduler 2110 configured to dispatch instructions or other work items to a processing array 2112. In at least one embodiment, scheduler 2110 ensures that processing array 2112 is properly configured and is in a valid state before tasks are distributed to processing array 2112. In at least one embodiment, scheduler 2110 is implemented via firmware logic executing on a microcontroller. In at least one embodiment, microcontroller-implemented scheduler 2110 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling fast preemption and context switching of threads executing on processing array 2112. In at least one embodiment, host software may detect workloads for scheduling on processing array 2112 via one of multiple graphics processing doorbell blades. In at least one embodiment, workloads may then be automatically distributed across processing array 2112 by scheduler 2110 logic within a microcontroller including scheduler 2110.In at least one embodiment, processing arrangement 2112 may include up to "N" clusters (e.g., cluster 2114A, cluster 2114B, to cluster 2114N). In at least one embodiment, each cluster 2114A- 2114N of processing array 2112 may execute a large number of simultaneous threads. In at least one embodiment, scheduler 2110 may assign work to clusters 2114A- 2114N of processing arrangement 2112 using various scheduling and / or work distribution algorithms, which may vary depending on workload incurred for each type of program or calculation. In at least one embodiment, scheduling may be dynamically managed by scheduler 2110 or may be partially supported by compiler logic during compilation of program logic configured for execution by processing arrangement 2112. In at least one embodiment, different clusters 2114A- 2114Nmay be assigned to processing arrangement 2112 for processing different types of programs or for performing different types of computations.In at least one embodiment, processing arrangement 2112 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing arrangement 2112 is configured to perform parallel general purpose computing operations. For example, in at least one embodiment, processing arrangement 2112 may include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physical operations, and performing data transformations.In at least one embodiment, processing arrangement 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, processing arrangement 2112 may include additional logic to assist in executing such graphics processing operations, including, but not limited to, texture sampling logic to perform texture operations, as well as tiling logic and other vertex processing logic. In at least one embodiment, processing arrangement 2112 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, tile shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 2102 may transfer data from system memory via I / O unit 2104 for processing. In at least one embodiment, data transferred during processing may be stored in on-chip memory (e.g., parallel processor memory 2122) during processing and then written back to system memory.In at least one embodiment, when parallel processing unit 2102 is used to perform graphics processing, scheduler 2110 may be configured to subdivide a processing workload into approximately equal sized tasks to better enable distribution of graphics processing operations among multiple clusters 2114A- 2114Nof processing array 2112. In at least one embodiment, portions of processing arrangement 2112 may be configured to perform various types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tile and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2114A- 2114N may be stored in buffers to allow intermediate data to be transferred between clusters 2114A- 2114N for further processing.In at least one embodiment, processing arrangement 2112 may receive processing tasks to be executed via scheduler 2110, which receives instructions defining processing tasks from front end 2108. In at least one embodiment, processing tasks may include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process data (e.g., which program to execute). In at least one embodiment, scheduler 2110 may be configured to retrieve indices corresponding to tasks or may receive indices from front end 2108. In at least one embodiment, front end 2108 may be configured to ensure that processing array 2112 is configured to a valid state before initiating a workload specified by incoming command buffers (e.g., stack buffers, push buffers, etc.).In at least one embodiment, each of one or more instances of parallel processing unit 2102 may couple to parallel processor memory 2122. In at least one embodiment, parallel processor memory 2122 may be accessed via memory crossbar 2116, which may receive memory requests from processing array 2112 as well as I / O unit 2104. In at least one embodiment, memory crossbar 2116 may access parallel processor memory 2122 via memory interface 2118. In at least one embodiment, memory interface 2118 may include multiple partition units (e.g., partition unit 2120A, partition unit 2120B, through partition unit 2120N), each of which may couple to a portion (e.g., memory unit) of parallel processor memory 2122. In at least one embodiment, a number of partition units 2120A- 2120N are configured to be equal to a number of memory units such that a first partition unit 2120A includes a corresponding first memory unit 2124A, a second partition unit 2120B includes a corresponding memory unit 2124B, and an Nth partition unit 2120N includes a corresponding Nth memory unit 2124N. In at least one embodiment, a number of partition units 2120A- 2120N may not be equal to a number of memory devices.In at least one embodiment, memory units 2124A- 2124N may include various types of memory devices, including DRAM or graphics random access memory, such as SGRAM, including GDDR memory. In at least one embodiment, memory units 2124A- 2124N may also include stacked 3D memories, including, but not limited to, high bandwidth memory ("HBM"). In at least one embodiment, render targets, such as frame buffers or texture maps, may be stored across memory units 2124A- 2124N, allowing partition units 2120A- 2120N to write portions of each render target in parallel to efficiently utilize available bandwidth of parallel processor memory 2122. In at least one embodiment, a local instance of parallel processor memory 2122 may be excluded in favor of a unified memory design that uses system memory in conjunction with local cache memory.In at least one embodiment, any of clusters 2114A- 2114N of processing array 2112 may process data written to any of memory units 2124A- 2124N within parallel processor memory 2122. In at least one embodiment, memory crossbar 2116 may be configured to transmit an output of each cluster 2114A- 2114N to any partition unit 2120A- 2120N or to another cluster 2114A- 2114N that can perform additional processing operations on an output. In at least one embodiment, each cluster 2114A- 2114N may communicate with memory interface 2118 via memory crossbar 2116 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 2116 includes a connection to memory interface 2118 to communicate with I / O unit 2104, as well as a connection to a local instance of parallel processor memory 2122, which allows processing units within different clusters 2114A- 2114N to communicate with system memory or other memory that is not local to parallel processing unit 2102. In at least one embodiment, memory crossbar 2116 may use virtual channels to separate traffic streams between clusters 2114A- 2114N and partition units 2120A- 2120N.In at least one embodiment, multiple instances of parallel processing unit 2102 may be provided on a single add-on card, or multiple add-on cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2102 may be configured to operate with each other even though different instances have a different number of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. In at least one embodiment, different instances of parallel processing unit 2102 may be configured to operate with one another even though different instances include a different number of processing cores, different amounts of local parallel processor memory, and / or different K For example, in at least one embodiment, some instances of parallel processing unit 2102 may include floating point units with higher precision compared to other instances. In at least one embodiment, systems including one or more instances of parallel processing unit 2102 or parallel processor 2100 may be implemented in a variety of configurations and form factors including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.FIG. 21B illustrates a processing cluster 2194, according to at least one embodiment. In at least one embodiment, processing cluster 2194 is included in a parallel processing unit. In at least one embodiment, processing cluster 2194 is one of processing clusters 2114A- 2114N of FIG. 21. In at least one embodiment, processing cluster 2194 may be configured to execute multiple threads in parallel, where term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single instruction multiple data ("SIMD") instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread ("SIMT") techniques are used to support parallel execution of a large number of generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster 2194.In at least one embodiment, operation of processing cluster 2194 may be controlled via a pipeline manager 2132 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager 2132 receives instructions from scheduler 2110 of FIG. 21 and manages execution of these instructions via graphics multiprocessor 2134 and / or texture unit 2136. In at least one embodiment, graphics multiprocessor 2134 is an example instance of a SIMT parallel processor. However, in at least one embodiment, different types of SIMT parallel processors of different architectures may be included in processing cluster 2194. In at least one embodiment, one or more instances of graphics multiprocessor 2134 may be included in processing cluster 2194. In at least one embodiment, graphics multiprocessor 2134 may process data and a data crossbar 2140 may be used to distribute processed data to one of several possible destinations, including other shader units. In at least one embodiment, pipeline manager 2132 may enable distribution of processed data by specifying processed data destinations to be distributed across data crossbar 2140.In at least one embodiment, each graphics multiprocessor 2134 in processing cluster 2194 may include an identical set of function execution logic (e.g., arithmetic logic units, load / store units ("LSUs"), etc.). In at least one embodiment, function execution logic may be configured in a pipelined manner in which new instructions may be issued before previous instructions are completed. In at least one embodiment, function execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, boolean operations, bit shifting, and computation of various algebraic functions. In at least one embodiment, same functional unit hardware may be employed to perform various operations, and any combination of functional units may be present.In at least one embodiment, instructions transmitted to processing cluster 2194 represent a thread. In at least one embodiment, a set of threads executing over a set of parallel processing engines is a group of threads. In at least one embodiment, a thread group executes a program on various input data. In at least one embodiment, each thread within a thread group may be assigned to a different processing engine within graphics multiprocessor 2134. In at least one embodiment, a thread group may include fewer threads than a number of processing engines within graphics multiprocessor 2134. In at least one embodiment, if a thread group includes fewer threads than a number of processing engines, one or more of processing engines may be idle during cycles in which that thread group is processed. In at least one embodiment, a thread group may also include more threads than a number of processing engines within graphics multiprocessor 2134. In at least one embodiment, if a thread group includes more threads than number of processing engines within graphics multiprocessor 2134, processing may be performed over successive clock cycles. In at least one embodiment, multiple thread groups may be executed simultaneously on graphics multiprocessor 2134.In at least one embodiment, graphics multiprocessor 2134 includes an internal cache memory for performing load and store operations. In at least one embodiment, graphics multiprocessor 2134 may omit an internal cache and use a cache memory (e.g., L1 cache 2148) within processing cluster 2194. In at least one embodiment, each graphics multiprocessor 2134 also has access to level 2 ("L2") caches within partition units (e.g., partition units 2120A- 2120N of FIG. 21A ) shared by all processing clusters 2194, which may be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2134 may also access global off-chip memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2102 may be used as global memory. In at least one embodiment, processing cluster 2194 includes multiple instances of graphics multiprocessor 2134 that can share common instructions and data that can be stored in L1 cache 2148.In at least one embodiment, each processing cluster 2194 may include an MMU 2145 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2145 may be located within memory interface 2118 of FIG. 21. In at least one embodiment, MMU 2145 includes a set of page table entries ("PTEs") used to map a virtual address to a physical address of a tile and optionally a cache line index. In at least one embodiment, MMU 2145 may include address translation buffers ("TLBs") or caches, which may be located within graphics multiprocessor 2134 or L1 cache 2148 or processing cluster 2194. In at least one embodiment, a physical address is processed to distribute surface data access locality to enable efficient request interleaving between partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or a miss.In at least one embodiment, processing cluster 2194 may be configured such that each graphics multiprocessor 2134 is coupled to a texture unit 2136 to perform texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 2134, and retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 2134 outputs a processed task to data crossbar 2140, to provide processed task to another processing cluster 2194 for further processing, or to store processed task in an L2 cache, local parallel processor memory, or system memory via memory crossbar 2116. In at least one embodiment, a pre-raster operations unit ("PreROP") 2142 is configured to receive data from graphics multiprocessor 2134, to pass data to ROP units that may be located with partition units as described herein (e.g., partition units 2120A- 2120N of FIG. 21 ). In at least one embodiment, PreROP 2142 may perform optimizations for color mixing, organize pixel color data, and perform address translations.FIG. 21C illustrates a graphics multiprocessor 2196 according to at least one embodiment. In at least one embodiment, graphics multiprocessor 2196 is graphics multiprocessor 2134 of FIG. 21B. In at least one embodiment, graphics multiprocessor 2196 is coupled to pipeline manager 2132 of processing cluster 2194. In at least one embodiment, graphics multiprocessor 2196 includes an execution pipeline that includes, among other things, an instruction cache 2152, an instruction unit 2154, an address mapping unit 2156, a register file 2158, one or more GPGPU cores 2162, and one or more LSUs 2166. GPGPU cores 2162 and LSUs 2166 are coupled to cache memory 2172 and shared memory 2170 via a memory and cache connection 2168.In at least one embodiment, instruction cache 2152 receives a stream of instructions for execution from pipeline manager 2132. In at least one embodiment, instructions are cached in instruction cache 2152 and dispatched for execution by instruction unit 2154. In at least one embodiment, instruction unit 2154 may dispatch instructions as thread groups (e.g., warps), each thread of a thread group being assigned to a different execution unit within GPGPU core 2162. In at least one embodiment, an instruction may access any of a local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2156 may be used to translate addresses in a unified address space into a unique memory address accessible by LSUs 2166.In at least one embodiment, register file 2158 provides a set of registers for functional units of graphics multiprocessor 2196. In at least one embodiment, register file 2158 provides temporary storage for operands connected to data paths of functional units (e.g., GPGPU cores 2162, LSUs 2166) of graphics multiprocessor 2196. In at least one embodiment, register file 2158 is partitioned between each of functional units such that each functional unit is assigned a dedicated portion of register file 2158. In at least one embodiment, register file 2158 is partitioned between different thread groups executed by graphics multiprocessor 2196.In at least one embodiment, GPGPU cores 2162 may each include FPUs and / or integer ALUs used to execute instructions of graphics multiprocessor 2196. The GPGPU cores 2162 may be similar in architecture or different in architecture. In at least one embodiment, a first portion of GPGPU cores 2162 includes a single precision FPU and an integer ALU, while a second portion of GPGPU cores 2162 includes a double precision FPU. In at least one embodiment, FPUs may implement IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics multiprocessor 2196 may additionally include one or more fixed function or special function units to perform specific functions such as copy rectangle or pixel blending operations. In at least one embodiment, one or more of GPGPU cores 2162 may also include fixed or special function logic.In at least one embodiment, GPGPU cores 2162 include SIMD logic capable of performing a single instruction on multiple data sets. In at least one embodiment, GPGPU cores 2162 may physically execute instructions of SIMD4, SIMD8, and SIMD16, and logically execute instructions of SIMD1, SIMD2, and SIMD32. In at least one embodiment, SIMD instructions for GPGPU cores 2162 may be generated by a shader compiler at compilation time or automatically generated when executing programs written and compiled for single program multiple data ("SPMD") or SIMT architectures. In at least one embodiment, multiple threads of a program configured for a SIMT execution model may be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing same or similar operations may be executed in parallel via a single SIMD8 logic unit.In at least one embodiment, memory and cache interconnect 2168 is an interconnect network that connects each functional unit of graphics multiprocessor 2196 to register file 2158 and shared memory 2170. In at least one embodiment, memory and cache interconnect 2168, is a crossbar interconnect that allows LSU 2166 to implement load and store operations between shared memory 2170 and register file 2158. In at least one embodiment, register file 2158 may operate at the same frequency as GPGPU cores 2162, such that data transfer between GPGPU cores 2162 and register file 2158 is very low latency. In at least one embodiment, shared memory 2170 may be used to enable communication between threads executing on functional units within graphics multiprocessor 2196. In at least one embodiment, cache 2172 may be used, for example, as a data cache to cache texture data communicated between functional units and texture unit 2136. In at least one embodiment, shared memory 2170 may also be used as a cached managed program. In at least one embodiment, threads executing on GPGPU cores 2162 may programmatically store data within shared memory in addition to automatically cached data stored within cache memory 2172.In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to host / processor cores to speed up graphics operations, machine learning operations, pattern analysis operations, and various functions of general purpose GPU (GPGPU). In at least one embodiment, a GPU may be communicatively coupled to host processors / cores via a bus or other connection (e.g., a high speed connection such as PCIe or NVLink). In at least one embodiment, a GPU may be integrated on same package or die as cores and communicatively coupled to cores via a processor bus / connection residing within a package or die. In at least one embodiment, regardless of how a GPU is connected, processor cores may assign work to GPU in sequences of instructions / instructions included in a WD. In at least one embodiment, GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.FIG. 22 illustrates a graphics processor 2200, according to at least one embodiment. In at least one embodiment, graphics processor 2200 includes a ring interconnect 2202, a pipeline front end 2204, a media engine 2237, and graphics cores 2280A- 2280N. In at least one embodiment, ring interconnect 2202 couples graphics processor 2200 to other processing units including other graphics processors or one or more general purpose processor cores. In at least one embodiment, graphics processor 2200 is one of many processors incorporated into a multi-core processing system.In at least one embodiment, graphics processor 2200 receives batches of commands via ring connection 2202. In at least one embodiment, incoming commands are interpreted by a command streamer 2203 in pipeline front end 2204. In at least one embodiment, graphics processor 2200 includes scalable execution logic to perform 3D geometry processing and media processing via graphics core(s) 2280A- 2280N. In at least one embodiment, 3D geometry processing instruction streamer 2203 provides instructions to geometry pipeline 2236. In at least one embodiment, command streamer 2203 provides commands for at least some media processing commands to a video front end 2234 that couples to a media engine 2237. In at least one embodiment, media engine 2237 includes a video quality engine ("VQE") 2230 for video and image post-processing and a multi-format coding / decoding engine ("MFX") 2233 to provide hardware accelerated media data coding and decoding. In at least one embodiment, geometry pipeline 2236 and media engine 2237 each generate execution threads for thread execution resources provided by at least one graphics core 2280A.In at least one embodiment, graphics processor 2200 includes scalable thread execution resources with modular graphics cores 2280A- 2280N (sometimes referred to as core slices) each having multiple sub-cores 2250A- 550N, 2260A- 2260N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2200 may include any number of graphics cores 2280A- 2280N. In at least one embodiment, graphics processor 2200 includes a graphics core 2280A having at least a first sub-core 2250A and a second sub-core 2260A. In at least one embodiment, graphics processor 2200 is a low power processor having a single sub-core (e.g., sub-core 2250A). In at least one embodiment, graphics processor 2200 includes a plurality of graphics cores 2280A- 2280N, each including a set of first sub-cores 2250A- 2250N and a set of second sub-cores 2260A- 2260N. In at least one embodiment, each sub-core in first sub-cores 2250A- 2250N includes at least a first set of execution units ("EUs") 2252A- 2252N and media / texture samplers 2254A- 2254N. In at least one embodiment, each sub-core in second sub-cores 2260A- 2260N includes at least a second set of execution units 2262A- 2262N and samplers 2264A- 2264N. In at least one embodiment, each sub-core 2250A- 2250N, 2260A- 2260N shares a set of shared resources 2270A- 2270N. In at least one embodiment, shared resources 2270 include shared cache memory and pixel operation logic.FIG. 23 illustrates a processor 2300, according to at least one embodiment. In at least one embodiment, processor 2300 may include, without limitation, logic circuitry to perform instructions. In at least one embodiment, processor 2300 may perform instructions including x86 instructions, ARM instructions, specialized instructions for ASICs, etc. In at least one embodiment, processor 2310 may include registers for storing packed data, such as 64-bit wide MMXTM registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers available in both integer and floating point form may operate with packed data elements accompanying SIMD and streaming SIMD extension ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers relating to SSE2, SSE3, SSE4, AVX, or beyond (commonly referred to as "SSEx") technology may hold such packed data operands. In at least one embodiment, processors 2310 may perform instructions to accelerate CUDA programs.In at least one embodiment, processor 2300 includes an in-order front end ("front end") 2301 to fetch instructions to be executed and prepare instructions to be used later in processor pipeline. In at least one embodiment, front end 2301 may include multiple units. In at least one embodiment, an instruction prefetcher 2326 fetches instructions from memory and supplies instructions to an instruction decoder 2328, which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder 2328 decodes a received instruction into one or more operations referred to as "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "uops") for execution. In at least one embodiment, instruction decoder 2328 parse instructions into an opcode and corresponding data and control fields that may be used by microarchitecture to perform operations. In at least one embodiment, a trace cache 2330 may assemble decoded uops into program ordered sequences or lanes in a uop queue 2334 for execution. In at least one embodiment, microcode ROM 2332, when trace cache 2330 encounters a complex instruction, provides uops needed to complete an operation.In at least one embodiment, some instructions may be converted to a single micro-operation, while others require multiple micro-ops to complete full operation. In at least one embodiment, if more than four micro-ops are needed to complete an instruction, instruction decoder 2328 may access microcode ROM 2332 to perform an instruction. In at least one embodiment, an instruction may be decoded into a small number of microops for processing at instruction decoder 2328. In at least one embodiment, an instruction may be stored within microcode ROM 2332 if a number of microops are needed to complete operation. In at least one embodiment, trace cache 2330 refers to a programmable entry point logic array ("PLA") to determine a correct microinstruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM 2332. In at least one embodiment, after microcode ROM 2332 completes sequencing micro-ops for an instruction, front end 2301 of machine may resume retrieving micro-ops from trace cache 2330.In at least one embodiment, out-of-order ("out-of-order") engine 2303 may prepare instructions for execution. In at least one embodiment, out-of-order execution logic includes a number of buffers to smooth and reorder flow of instructions to optimize performance as they descend a pipeline and are scheduled for execution. Out-of-order execution engine 2303 includes, without limitation, allocator / register renamer 2340, memory uop queue 2342, integer / floating point uop queue 2344, memory scheduler 2346, fast scheduler 2302, slow / general floating point scheduler ("slow / general FP scheduler") 2304, and a simple floating point scheduler ("simple FP scheduler") 2306. In at least one embodiment, fast scheduler 2302, slow / general floating point scheduler 2304, and simple floating point scheduler 2306 are also collectively referred to herein as "uop scheduler 2302, 2304, 2306.". In at least one embodiment, allocator / register renamer 2340 renames logic registers to entries in a register file. In at least one embodiment, allocator / register renamer 2340 also allocates an entry for each uop in one of two uop queues, memory uop queue 2342 for memory operations, and integer / floating point uop queue 2344 for non-memory operations, prior to memory scheduler 2346 and uop schedulers 2302, 2304, 2306. In at least one embodiment, uop schedulers 2302, 2304, 2306 determine when a uop is ready for execution based on readiness of their dependent input register operand sources and availability of execution resources that require uops to complete their operation. In at least one embodiment, fast scheduler 2302 of at least one embodiment may schedule on each half of main clock cycle, while slow / general floating point scheduler 2304 and simple floating point scheduler 2306 may schedule once per main processor clock cycle. In at least one embodiment, uop schedulers 2302, 2304, 2306 decide dispatch ports to schedule uops for execution.In at least one embodiment, execution block 2311 includes, without limitation, an integer register file / bypass network 2308, a floating point register file / bypass network ("FP register file / bypass network") 2310, address generation units ("AGUs") 2312 and 2314, fast ALUs 2316 and 2318, a slow ALU 2320, a floating point ALU ("FP") 2322, and a floating point move unit ("FP move") 2324. In at least one embodiment, AGUs 2312 and 2314, fast ALUs 2316 and 2318, slow ALU 2320, floating point ALU 2322, and floating point move unit 2324 are also referred to herein as "execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324.".In at least one embodiment, register files 2308, 2310 may be arranged between uop schedulers 2302, 2304, 2306 and execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324. In at least one embodiment, integer register file / bypass network 2308 performs integer operations. In at least one embodiment, floating point register file / bypass network 2310 performs floating point operations. In at least one embodiment, each of register files 2308, 2310 may include, without limitation, a bypass network that may bypass or forward just completed results that have not yet been written to register file to new dependent uops. In at least one embodiment, register files 2308, 2310 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2308 may include, without limitation, two separate register files, a low-order thirty-two data bit register file and a second high-order thirty-two data bit register file. In at least one embodiment, floating point register file / bypass network 2310 may include, without limitation, 128-bit wide entries, as floating point instructions typically have operands 64 to 128 bits wide. In at least one embodiment, floating point register file / bypass network 2310 may execute one or more instructions contained in one or more of register files 2308, 2310.In at least one embodiment, execution units 2312, 2314, 2316, 2318, 2320, 2322, 2324 may execute instructions. In at least one embodiment, register files 2308, 2310 store integer and floating point data operand values that are to execute microinstructions. In at least one embodiment, processor 2300 may include, without limitation, any number and combination of execution units 2312, 2314, 2316, 2318, 2320, 2322, 2324. In at least one embodiment, floating point ALU 2322 and floating point move unit 2324 may perform floating point, MMX, SIMD, AVX, and SSE or other operations. In at least one embodiment, floating point ALU 2322 may include, without limitation, a 64-bit by 64-bit floating point divider to perform divide, square root, and residual microops. In at least one embodiment, instructions including a floating point value may be handled with floating point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs 2316, 2318. In at least one embodiment, fast ALUs 2316, 2318 may perform fast operations with an effective latency of one-half clock cycle. In at least one embodiment, most complex integer operations pass to slow ALU 2320 because slow ALU 2320 may include, without limitation, integer execution hardware for some type of long latency operations, such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations may be performed by AGUs 2312, 2314. In at least one embodiment, fast ALU 2316, fast ALU 2318, and slow ALU 2320 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2316, fast ALU 2318, and slow ALU 2320 may be implemented to support a variety of data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, floating point ALU 2322 and floating point move unit 2324 may be implemented to support a range of operands having bits of different widths. In at least one embodiment, floating point ALU 2322 and floating point move unit 2324 may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.In at least one embodiment, uop schedulers 2302, 2304, 2306 send dependent operations before predecessor load completes execution. In at least one embodiment, since uops may be speculative scheduled and executed in processor 2300, processor 2300 may also include logic to handle memory errors. In at least one embodiment, if a data load fails in a data cache, there may be dependent on-the-fly operations in pipeline that have left a scheduler with temporarily incorrect data. In at least one embodiment, a playback mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations may need to be rendered and independent operations may be completed. In at least one embodiment, schedulers and playback mechanisms of at least one embodiment of a processor may also be configured to detect instruction sequences for text string comparison operations. In at least one embodiment, schedulers and playback mechanisms of at least one embodiment of a processor may also be configured to detect instruction sequences for text string comparison operations. In at least at least one InIn at least one embodiment, term "register" may refer to on-board processor memory locations that may be used as part of instructions to identify operands. In at least one embodiment, registers may be those that may be usable from outside a processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to any particular type of circuit. Instead, in at least one embodiment, a register may store data, provide data, and perform functions described herein. In at least one embodiment, registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. A register file of at least one embodiment also includes eight multimedia SIMD packed data registers.FIG. 24 illustrates a processor 2400, according to at least one embodiment. In at least one embodiment, processor 2400 includes, without limitation, one or more processor cores ("cores") 2402A- 2402N, an integrated memory controller 2414, and an integrated graphics processor 2408. In at least one embodiment, processor 2400 may include additional cores up to and including additional processor core 2402N, which are represented by dashed lined boxes. In at least one embodiment, each of processor cores 2402A- 2402N includes one or more internal cache units 2404A- 2404N. In at least one embodiment, each processor core also has access to one or more shared cache units 2406. In at least one embodiment, one or more processor cores 2402A- 2402N are referred to as one or more computing devices or computing devices.In at least one embodiment, internal cache units 2404A- 2404N and shared cache units 2406 represent a cache memory hierarchy within processor 2400. In at least one embodiment, cache memory units 2404A- 2404N may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as an L2, L3, level 4 ("L4"), or other levels of cache, where a highest level of cache before external memory is classified as an LLC. In at least one embodiment, cache coherency logic maintains coherency between different cache units 2406 and 2404A- 2404N.In at least one embodiment, processor 2400 may also include a set of one or more bus controllers 2416 and a system agent core 2410. In at least one embodiment, one or more bus controller units 2416 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, system agent core 2410 provides management functionality for various processor components. In at least one embodiment, system agent core 2410 includes one or more integrated memory controllers 2414 to manage access to various external storage devices (not shown).In at least one embodiment, one or more of processor cores 2402A- 2402N include support for simultaneous multi-threading. In at least one embodiment, system agent core 2410 includes components for coordinating and operating processor cores 2402A- 2402N during multi-threading processing. In at least one embodiment, system agent core 2410 may additionally include a power control unit ("PCU") including logic and components for regulating one or more power states of processor cores 2402A- 2402N and graphics processor 2408.In at least one embodiment, processor 2400 additionally includes graphics processor 2408 to perform graphics processing operations. In at least one embodiment, graphics processor 2408 couples to shared cache units 2406 and system agent core 2410, including one or more integrated memory controllers 2414. In at least one embodiment, system agent core 2410 also includes a display controller 2411 to drive graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2411 may also be a separate module coupled to graphics processor 2408 via at least one link, or may be integrated within graphics processor 2408.In at least one embodiment, a ring-based interconnect unit 2412 is used to couple internal components of processor 2400. In at least one embodiment, an alternative connection unit may be used, such as a point-to-point connection, a switched connection, or other techniques. In at least one embodiment, graphics processor 2408 couples to ring interconnect 2412 via an I / O link 2413.In at least one embodiment, I / O link 2413 represents at least one of several variations of I / O links, including an on-package I / O link that facilitates communication between various processor components and a high-performance embedded memory module 2418, such as an eDRAM module. In at least one embodiment, each of processor cores 2402A- 2402N and graphics processor 2408 use embedded memory modules 2418 as a shared LLC.In at least one embodiment, processor cores 2402A- 2402N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2402A- 2402N are heterogeneous with respect to ISA, where one or more of processor cores 2402A- 2402N execute a common instruction set, while one or more other cores of processor cores 2402A- 2402N execute a subset of a common instruction set or another instruction set. In at least one embodiment, processor cores 2402A- 2402N are heterogeneous in terms of microarchitecture, where one or more cores with a relatively higher power consumption couple to one or more cores with a lower power consumption. In at least one embodiment, processor 2400 may be implemented on one or more chips or as an SoC integrated circuit.FIG. 25 illustrates a graphics processor core 2500 according to at least one described embodiment. In at least one embodiment, graphics processor core 2500 is included in a graphics core array. In at least one embodiment, graphics processor core 2500, sometimes referred to as a core slice, may be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 2500 is exemplary of a graphics core slice and a graphics processor as described herein may include multiple graphics core slices based on target power and power envelopes. In at least one embodiment, each graphics core 2500 may include a fixed function block 2530 coupled to multiple sub-cores 2501A- 2501F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed function logic.In at least one embodiment, fixed function block 2530 includes a geometry / fixed function pipeline 2536 that may be shared by all sub-cores in graphics processor 2500, for example, in lower power and / or lower power graphics processor implementations. In at least one embodiment, geometry / fixed function pipeline 2536 includes a 3D fixed function pipeline, a video front end unit, a thread dispatcher, and a thread dispatcher, and a unified return buffer manager that manages unified return buffers.In at least one embodiment, fixed function block 2530 also includes a graphics SoC interface 2537, a graphics microcontroller 2538, and a media pipeline 2539. Graphics SoC interface 2537 provides an interface between graphics core 2500 and other processor cores within an SoC integrated circuit. In at least one embodiment, graphics microcontroller 2538 is a programmable sub-processor configurable to manage various functions of graphics processor 2500, including thread dispatch, scheduling, and preemption. In at least one embodiment, media pipeline 2539 includes logic to enable decoding, encoding, preprocessing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 2539 implements media operations via requests for compute or scan logic within sub-cores 2501-2501F.In at least one embodiment, SoC interface 2537 enables graphics core 2500 to communicate with general purpose application processor cores (e.g., CPUs) and / or other components within a SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or on-package DRAM. In at least one embodiment, SoC interface 2537 may also enable communication with fixed functional devices within a SoC, such as camera imaging pipelines, and enables use of and / or implements global memory atomics that may be shared between graphics core 2500 and CPUs within a SoC. In at least one embodiment, SoC interface 2537 may also implement power management controls for graphics core 2500 and enable an interface between a clock domain of graphics core 2500 and other clock domains within a SoC. In at least one embodiment, SoC interface 2537 enables receipt of command buffers from a command streamer and global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. In at least one embodiment, instructions and instructions may be dispatched to media pipeline 2539 when media operations are to be performed, or to a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline 2536, geometry and fixed function pipeline 2514) when graphics processing operations are to be performed.In at least one embodiment, graphics microcontroller 2538 may be configured to perform various scheduling and management tasks for graphics core 2500. In at least one embodiment, graphics microcontroller 2538 may perform graphics and / or compute workload scheduling on various graphics parallel engines within execution unit (EU) arrays 2502A- 2502F, 2504A- 2504F within sub-cores 2501A- 2501F. In at least one embodiment, host software executing on a CPU core of an SoC including graphics core 2500 may submit workloads one of multiple graphics processor doorbell blades that invoke a scheduling operation on a suitable graphics engine. In at least one embodiment, scheduling operations include determining which workload to execute next, delivering a workload to a command streamer, pre-empting existing workloads executing on a machine, monitoring progress of a workload, and notifying host software when a workload is completed. In at least one embodiment, graphics microcontroller 2538 may also enable low power or idle states for graphics core 2500, thereby providing graphics core 2500 with capability to store and restore registers within graphics core 2500 via low power state transitions independent of operating system and / or graphics driver software on a system.In at least one embodiment, graphics core 2500 may include more than or less than illustrated sub-cores 2501A- 2501F, up to N modular sub-cores. In at least one embodiment, graphics core 2500 may include more than or less than illustrated sub-cores 2501A- 2501F, up to N modular sub-cores. In at least one embodiment, for each set of N sub-cores, graphics core 2500 may also include shared function logic 2510, shared and / or cache memory 2512, geometry / fixed function pipeline 2514, and additional fixed function logic 2516 to speed up various graphics and compute processing operations. In at least one embodiment, shared function logic 2510 may include logic units (e.g., sampler, math, and / or inter-thread communication logic) that may be shared by each of N sub-cores within graphics core 2500. Shared and / or cache memory 2512 may be an LLC for N sub-cores 2501A- 2501F within graphics core 2500, and may also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2514 may be included within fixed function block 2530 instead of geometry / fixed function pipeline 2536, and may include same or similar logic units.In at least one embodiment, graphics core 2500 includes additional fixed function logic 2516 that may include various fixed function acceleration logic for use by graphics core 2500. In at least one embodiment, additional fixed function logic 2516 includes an additional geometry pipeline for use in position-only shading. In position-only shading, at least two geometry pipelines exist, whereas in a full geometry pipeline within the geometry / fixed function pipeline 2516, 2536 and a cull pipeline, which is an additional geometry pipeline that may be included within the additional fixed function logic 2516. In at least one embodiment, cull pipeline is a trimmed version of a full geometry pipeline. In at least one embodiment, a full pipeline and a cull pipeline may execute different instances of an application, each instance having a separate context. In at least one embodiment, position-only shading may hide long cull runs of discarded triangles, thereby allowing shading to be completed earlier in some instances. For example, in at least one embodiment, cull pipeline logic within additional fixed function logic 2516 may execute position shaders in parallel with a host application and generally generates critical results faster than a full pipeline because a cull pipeline fetches and shaders position attributes of vertices without performing rastering and rendering of pixels to a frame buffer. In at least one embodiment, a cull pipeline may use generated critical results to calculate visibility information for all triangles regardless of whether those triangles are sorted out. In at least one embodiment, a full pipeline (which may be referred to as a rendering pipeline in this instance) may consume visibility information to skip sorted triangles to shading only visible triangles, which are ultimately passed to a raster phase.In at least one embodiment, additional fixed function logic 2516 may also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, for accelerating CUDA programs.In at least one embodiment, each graphics sub-core 2501A- 2501F includes a set of execution resources that can be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader programs. In at least one embodiment, graphics sub-cores 2501A- 2501F include multiple EU arrays 2502A- 2502F, 2504A- 2504F, thread dispatch and inter-thread communication ("TD / IC") logic 2503A- 2503F, a 3D (e.g., texture) sampler 2505A- 2505F, a media sampler 2506A- 2506F, a shader processor 2507A- 2507F, and shared local memory ("SLM") 2508A- 2508F. EU arrays 2502A- 2502F, 2504A- 2504F each include multiple execution units that are GPGPUs capable of performing floating point and integer / fixed point logic operations in the service of a graphics, media, or compute operation, including graphics, media, or compute shader programs. In at least one embodiment, TD / IC logic 2503A- 2503F performs local thread dispatch and thread control operations for execution units within a sub-core and facilitates communication between threads executing on execution units of a sub-core. In at least one embodiment, 3D sampler 2505A- 2505F may read texture or other 3D graphics related data into memory. In at least one embodiment, 3D sampler may read texture data differently based on a configured sample state and texture format associated with a given texture. In at least one embodiment, media sampler 2506A- 2506F may perform similar read operations based on a type and format associated with media data. In at least one embodiment, each graphics sub-core 2501A- 2501F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each of sub-cores 2501A- 2501F may use shared local memory 2508A- 2508F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.FIG. 26 illustrates a parallel processing unit ("PPU") 2600, in accordance with at least one embodiment. In at least one embodiment, PPU 2600 is configured with machine readable code that, when executed by PPU 2600, causes PPU 2600 to perform some or all of processes and techniques described herein. In at least one embodiment, PPU 2600 is a multi-threading processor implemented on one or more integrated circuit devices that uses multi-threading as a latency concealing technique configured to process computer readable instructions (also referred to as machine readable instructions or simply instructions) on multiple threads in parallel. In at least one embodiment, a thread refers to an execution thread and is an instantiation of a set of instructions configured to be executed by PPU 2600. In at least one embodiment, PPU 2600 is a GPU configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device, such as an LCD device. In at least one embodiment, PPU 2600 is used to perform computations such as linear algebraic operations and machine learning operations. FIG. 26 illustrates an example parallel processor for illustrative purposes only and should be construed as a non-limiting example of a processor architecture that may be implemented in at least one embodiment.In at least one embodiment, one or more PPUs 2600 are configured to accelerate high performance computing ("HPC") applications, data center, and machine learning applications. In at least one embodiment, one or more PPUs 2600 are configured to accelerate CUDA programs. In at least one embodiment, PPU 2600 includes, without limitation, an I / O unit 2606, a front end unit 2610, a scheduler unit 2612, a work distribution unit 2614, a hub 2616, a crossbar ("Xbar") 2620, one or more general processing clusters ("GPCs") 2618, and one or more partition units ("Speicherpartitionseinheiten") 2622. In at least one embodiment, PPU 2600 is connected to a host processor or other PPUs 2600 via one or more high-speed GPU ("GPU") links 2608. In at least one embodiment, PPU 2600 is connected to a host processor or other peripheral devices via a system bus or link 2602. In at least one embodiment, PPU 2600 is coupled to local memory that includes one or more memory devices ("memories") 2604. In at least one embodiment, memory devices 2604 include, without limitation, one or more dynamic random access memory (DRAM) devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as high bandwidth memory ("HBM") subsystems, with multiple DRAM dies stacked in each device.In at least one embodiment, high speed GPU link 2608 may refer to a multi-lane wire-based communication link used by systems for scaling and including one or more PPUs 2600 in combination with one or more CPUs that support cache coherency between PPUs 2600 and CPUs and CPU mastering. In at least one embodiment, data and / or instructions are transmitted through high speed GPU link 2608 via hub 2616 to / from other units of PPU 2600, such as one or more copy engines, video encoders, video decoders, power management units, and other components that may not be explicitly illustrated in FIG. 26.In at least one embodiment, I / O unit 2606 is configured to transmit and receive communications (e.g., commands, data) from a host processor (not illustrated in FIG. 26) via system bus 2602. In at least one embodiment, I / O unit 2606 communicates with host processor directly over system bus 2602 or through one or more intermediary devices, such as a memory bridge. In at least one embodiment, I / O unit 2606 may communicate with one or more other processors, such as one or more of PPUs 2600, via system bus 2602. In at least one embodiment, I / O unit 2606 implements a PCIe interface for communication over a PCIe bus. In at least one embodiment, I / O unit 2606 implements interfaces for communication with external devices.In at least one embodiment, I / O unit 2606 decodes packets received over system bus 2602. In at least one embodiment, at least some packets represent commands configured to cause PPU 2600 to perform various operations. In at least one embodiment, I / O unit 2606 transmits decoded instructions to various other units of PPU 2600 as specified by instructions. In at least one embodiment, instructions are transmitted to front end unit 2610 and / or transmitted to hub 2616 or other units of PPU 2600, such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly illustrated in FIG. 26). In at least one embodiment, I / O unit 2606 is configured to route communications between and among different logical units of PPU 2600.In at least one embodiment, a program executed by host processor encodes a command stream in a buffer that provides workloads to PPU 2600 for processing. In at least one embodiment, a workload includes instructions and data to be processed by those instructions. In at least one embodiment, buffer is an area in memory that can be accessed (e.g., read / written) by both a host processor and PPU 2600 - a host interface unit may be configured to access buffer in system memory coupled to system bus 2602 via memory requests transmitted over system bus 2602 by I / O unit 2606. In at least one embodiment, a host processor writes a command stream to a buffer and then transfers a pointer to beginning of command stream to PPU 2600 such that front end unit 2610 receives pointers to one or more command streams and manages one or more command streams, reads commands from command streams, and forwards commands to various units of PPU 2600.In at least one embodiment, front end unit 2610 is coupled to scheduler unit 2612, which configures various GPCs 2618 to process tasks defined by one or more instruction streams. In at least one embodiment, scheduler unit 2612 is configured to track state information related to various tasks managed by scheduler unit 2612, where state information may indicate to which of GPCs 2618 a task is assigned, whether task is active or inactive, a priority level associated with task, and so forth. In at least one embodiment, scheduler unit 2612 manages execution of a plurality of tasks on one or more of GPCs 2618.In at least one embodiment, scheduler unit 2612 is coupled to work distribution unit 2614, which is configured to dispatch tasks for execution on GPCs 2618. In at least one embodiment, work distribution unit 2614 tracks a number of scheduled tasks received from scheduler unit 2612, and work distribution unit 2614 manages a pending task pool and an active task pool for each of GPCs 2618. In at least one embodiment, pending task pool includes a number of slots (e.g., 32 slots) that contain tasks allocated to be processed by a particular GPC 2618; active task pool may include a number of slots (e.g., 4 slots) for tasks that are actively processed by GPCs 2618 such that when one of GPCs 2618 completes execution of a task, that task is flushed from active task pool for GPC 2618 and one of other tasks from pending task pool is selected and scheduled for execution on GPC 2618. In at least one embodiment, when an active task on GPC 2618 is idle, such as while waiting for data dependency to be solved, active task is flushed from GPC 2618 and returned to a pending task pool, while another task in pending task pool is selected and scheduled for execution on GPC 2618.In at least one embodiment, work distribution unit 2614 communicates with one or more GPCs 2618 via XBar 2620. In at least one embodiment, XBar 2620 is an interconnect network that couples many units of PPU 2600 to other units of PPU 2600 and may be configured to couple work distribution unit 2614 to a particular GPC 2618. In at least one embodiment, one or more other units of PPU 2600 may also be connected to XBar 2620 via hub 2616.In at least one embodiment, tasks are managed by scheduler unit 2612 and dispatched to one of GPCs 2618 by work distribution unit 2614. GPC 2618 is configured to process tasks and generate results. In at least one embodiment, results may be consumed by other tasks within GPC 2618, routed to another GPC 2618 via XBar 2620, or stored in memory 2604. In at least one embodiment, results may be written to memory 2604 via partition units 2622 implementing a memory interface for reading and writing data to / from memory 2604. In at least one embodiment, results may be transmitted to another PPU 2604 or CPU via high-speed GPU link 2608. In at least one embodiment, PPU 2600 includes, without limitation, a number U of partition units 2622 equal to a number of separate and unique storage devices 2604 coupled to PPU 2600.In at least one embodiment, a host processor executes a driver kernel that implements an application programming interface ("API") that enables one or more applications executing on host processor to schedule operations for execution on PPU 2600. In at least one embodiment, multiple computing applications are executed simultaneously by PPU 2600 and PPU 2600 provides isolation, quality of service ("QoS"), and independent address spaces for multiple computing applications. In at least one embodiment, an application generates instructions (e.g., in form of API calls) that cause a driver kernel to generate one or more tasks for execution by PPU 2600, and driver kernel outputs tasks to one or more streams processed by PPU 2600. In at least one embodiment, each task includes one or more groups of related threads, which may be referred to as warp. In at least one embodiment, a warp includes a plurality of related threads (e.g., 32 threads) that may be executed in parallel. In at least one embodiment, cooperative threads may refer to a plurality of threads that include instructions to perform a task and that exchange data through shared memory.FIG. 27 illustrates a GPC 2700, according to at least one embodiment. In at least one embodiment, GPC 2700 is of GPC 2618 of FIG. 26. In at least one embodiment, each GPC 2700 includes, without limitation, a number of hardware units for processing tasks, and each GPC 2700 includes, without limitation, a pipeline manager 2702, a pre-raster operations unit ("PROP") 2704, a raster engine 2708, a work distribution crossbar ("WDX") 2716, a MMU 2718, one or more data processing clusters ("DPCs") 2706, and any suitable combination of portions.In at least one embodiment, operation of GPC 2700 is controlled by pipeline manager 2702. In at least one embodiment, pipeline manager 2702 manages configuration of one or more DPCs 2706 for processing tasks assigned to GPC 2700. In at least one embodiment, pipeline manager 2702 configures at least one of one or more DPCs 2706 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, DPC 2706 is configured to execute a vertex shader program on a programmable streaming multiprocessor ("SM") 2714. In at least one embodiment, pipeline manager 2702 is configured to route packets received from a work distribution unit to appropriate logical units within GPC 2700, and in at least one embodiment, some packets may be routed to fixed function hardware units in PROP 2704 and / or raster engine 2708, while other packets may be routed to DPCs 2706 for processing by a primitive engine 2712 or an SM 2714. In at least one embodiment, pipeline manager 2702 configures at least one of DPCs 2706 to implement a compute pipeline. In at least one embodiment, pipeline manager 2702 configures at least one of DPCs 2706 to execute at least a portion of a CUDA program.In at least one embodiment, PROP unit 2704 is configured to route data generated by raster engine 2708 and DPCs 2706 to a raster operations unit ("ROP*") in a partition unit, such as memory partition unit 2622 described in more detail above in connection with FIG. 26. In at least one embodiment, PROP unit 2704 is configured to perform optimizations for color mixing, organize pixel data, perform address translations, and more. In at least one embodiment, raster engine 2708 includes, without limitation, a number of fixed function hardware units configured to perform various raster operations, and in at least one embodiment, raster engine 2708 includes, without limitation, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile coalescing engine, and any suitable combination thereof. In at least one embodiment, a setup engine receives transformed vertices and generates level equations associated with a geometric primitive defined by vertices; level equations are transmitted to a coarse raster engine to generate coverage information (e.g., an x, y coverage mask for a tile) for a primitive; output of coarse raster engine is transmitted to a culling engine where fragments associated with a primitive that fails a z test are sorted out and transmitted to a clipping engine where fragments that are outside of a viewing frustum are clipped. In at least one embodiment, fragments that survive clipping and culling are passed to a fine raster engine to generate attributes for pixel fragments based on plane equations generated by a setup engine. In at least one embodiment, output of raster engine 2708 includes fragments to be processed by any suitable entity, such as a fragment shader implemented within DPC 2706.In at least one embodiment, each DPC 2706 included in GPC 2700 includes, without limitation, an M-pipe controller ("MPC") 2710; a primitive engine 2712; one or more SMs 2714; and any suitable combination thereof. In at least one embodiment, MPC 2710 controls operation of DPC 2706 and routes packets received from pipeline manager 2702 to appropriate entities in DPC 2706. In at least one embodiment, packets associated with a vertex are directed to primitive engine 2712, which is configured to retrieve vertex attributes associated with a vertex from memory; in contrast, packets associated with a shader program may be transmitted to SM 2714.In at least one embodiment, SM 2714 includes, without limitation, a programmable streaming processor configured to process tasks represented by a number of threads. In at least one embodiment, SM 2714 is multi-threading and is configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads simultaneously, and implements a SIMD architecture, where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on a same set of instructions. In at least one embodiment, all threads in a group of threads execute same instructions. In at least one embodiment, SM 2714 implements a SIMT architecture, where each thread in a group of threads is configured to process a different dataset based on same instruction set, but individual threads in a group of threads may diverge during execution. In at least one embodiment, a program counter, a fetch stack, and an execution state are maintained for each warp, thereby allowing simultaneity between warps and serial execution within warps when threads within a warp diverge. In another embodiment, a program counter, a fetch stack, and an execution state are maintained for each individual thread, thereby allowing equal simultaneity between all threads within and between warps. In at least one embodiment, an execution state is maintained for each individual thread and threads executing same instructions may be converged and executed in parallel for better efficiency. At least one embodiment of SM 2714 is described in more detail in connection with FIG. 28.In at least one embodiment, MMU 2718 provides an interface between GPC 2700 and a memory partition unit (e.g., partition unit 2622 of FIG. 26 ), and MMU 2718 provides virtual address to physical address translation, memory protection, and memory request arbitration. In at least one embodiment, MMU 2718 provides one or more translation buffers (TLBs) for performing translation from virtual addresses to physical addresses in memory.FIG. 28 illustrates a streaming multiprocessor ("SM") 2800 according to at least one embodiment. In at least one embodiment, SM 2800 is SM 2714 of FIG. 27. In at least one embodiment, SM 2800 includes, without limitation, an instruction cache 2802; one or more scheduler units 2804; a register file 2808; one or more processing cores ("cores") 2810; one or more special function units ("SFUs") 2812; one or more LSUs 2814; an interconnect network 2816; a shared memory / L1 cache 2818; and any suitable combination thereof. In at least one embodiment, a work distribution unit sends tasks for execution on GPCs from parallel processing units (PPUs), and each task is assigned to a particular data processing cluster (DPC) within a GPC, and if a task is associated with a shader program, task is assigned to one of SMs 2800. In at least one embodiment, scheduler unit 2804 receives tasks from a work distribution unit and manages instruction scheduling for one or more thread blocks allocated to SM 2800. In at least one embodiment, scheduler unit 2804 schedules thread blocks for execution as warps of parallel threads, with at least one warp assigned to each thread block. In at least one embodiment, each warp executes threads. In at least one embodiment, scheduler unit 2804 manages a plurality of different thread blocks, allocates warps to different thread blocks, and then sends instructions from a plurality of different cooperative groups to different functional units (e.g., processing cores 2810, SFUs 2812, and LSUs 2814) during each clock cycle. In at least one embodiment, SM 2800 includes one or more thread block clusters, wherein a thread block cluster may enable programmatic control of locality at a granularity greater than a single thread block of a single streaming multiprocessor (SM). In at least one embodiment, thread block clusters (also referred to as "clusters") allow multiple thread blocks that concurrently pass over streaming multiprocessors to synchronize and shared, exchange, or otherwise use data.In at least one embodiment, "cooperative groups" may refer to a programming model for organizing groups of communicating threads that enables developers to express granularity at which threads are communicating, enabling expression of richer, more efficient parallel decompositions. In at least one embodiment, cooperative boot APIs support synchronization between thread blocks for execution of parallel algorithms. In at least one embodiment, conventional programming model APIs provide a single, simple construct for synchronizing interacting threads: a barrier across all threads of a thread block (e.g., syncthreads( ) function). However, in at least one embodiment, programmers may define groups of threads with less than thread block granularities and synchronize within defined groups to enable greater performance, design flexibility, and software reuse in the form of collective group-wide function interfaces. In at least one embodiment, cooperative groups enable programmers to explicitly define groups of threads at sub-block and multi-block granularities and perform collective operations such as synchronization on threads in a cooperative group. In at least one embodiment, sub-block granularity is as small as a single thread. In at least one embodiment, a programming model supports clean composition across software boundaries so that libraries and utility functions can be safely synchronized within their local context without having to make assumptions about convergence. In at least one embodiment, a programmable process programming model may enable synchronization between threads in a cooperative group. In at least one embodiment, cooperative group primitives enable new patterns of cooperative parallelism, including, without limitation, producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.In at least one embodiment, dispatch unit 2806 is configured to transmit instructions to one or more of functional units, and scheduler unit 2804 includes, without limitation, two dispatch units 2806 that enable two different instructions to be dispatched from same warp during each clock cycle. In at least one embodiment, each scheduler unit 2804 includes a single dispatch unit 2806 or additional dispatch units 2806.In at least one embodiment, each SM 2800 includes, in at least one embodiment, without limitation, a register file 2808 that provides a set of registers for functional units of SM 2800. In at least one embodiment, register file 2808 is split between each of functional units, such that each functional unit is assigned a dedicated portion of register file 2808. In at least one embodiment, register file 2808 is partitioned between different warps being executed by SM 2800, and register file 2808 provides temporary storage for operands connected to functional unit data paths. In at least one embodiment, each SM 2800 includes, without limitation, a plurality of L processing cores 2810. In at least one embodiment, SM 2800 includes, without limitation, a large number (e.g., 128 or more) of unique processing cores 2810. In at least one embodiment, each processing core 2810 includes, without limitation, a full pipeline, single precision, double precision, and / or mixed precision processing unit including, without limitation, a floating point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, floating point arithmetic logic units implement IEEE 754-2008 standard for floating point arithmetic. In at least one embodiment, processing cores 2810 include, without limitation, 64 single precision (32-bit) floating point cores, 64 integer cores, 32 double precision (64-bit) floating point cores, and 8 tensor cores.In at least one embodiment, tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing cores 2810. In at least one embodiment, tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiplication and accumulation operation D=A×B+C, where A, B, C, and D are 4×4 matrices.In at least one embodiment, matrix multiplication inputs A and B are 16-bit floating point matrices and accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, tensor cores operate on 16-bit floating point input data with 32-bit floating point accumulation. In at least one embodiment, 16-bit floating point multiplication uses 64 operations and results in a full precision product which is then accumulated using 32-bit floating point addition with other intermediates for 4×4×4 matrix multiplication. Tensor cores are used to perform much larger two-dimensional or higher-dimensional matrix operations, which are made up of these smaller elements, in at least one embodiment. In at least one embodiment, an API, such as a CUDA C++ API, enables specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use tensor cores from a CUDA C++ program. In at least one embodiment, at CUDA level, a warp level interface accepts 16×16-sized matrices spanning all 32 threads of a warp.In at least one embodiment, each SM 2800 includes, without limitation, M SFUs 2812 that perform specific functions (e.g., attribute evaluation, reciprocal square root, and the like). In at least one embodiment, SFUs 2812 include, without limitation, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, SFUs 2812 include, without limitation, a texture unit configured to perform texture mapping filter operations. In at least one embodiment, texture units are configured to load texture maps (e.g., a 2D array of texels) from memory and sample texture maps to generate sampled texture values for use in shader programs executed by SM 2800. In at least one embodiment, texture maps are stored in shared memory / L1 cache 2818. In at least one embodiment, texture units implement texture operations such as filter operations using mip-maps (e.g., texture maps with varying levels of detail). In at least one embodiment, each SM 2800 includes two texture units without limitation.In at least one embodiment, each SM 2800 includes, without limitation, N LSUs 2814 that implement load and store operations between shared memory / L1 cache 2818 and register file 2808. In at least one embodiment, each SM 2800 includes, without limitation, an interconnect network 2816 that connects each of functional units to register file 2808 and LSU 2814 to register file 2808 and shared memory / L1 cache 2818. In at least one embodiment, interconnect network 2816 is a crossbar that may be configured to connect any of functional units to any of registers in register file 2808 and connect LSUs 2814 to register file 2808 and memory locations in shared memory / L1 cache 2818.In at least one embodiment, shared memory / L1 cache 2818 is an array of on-chip memory that enables data storage and communication between SM 2800 and a primitive engine and between threads in SM 2800. In at least one embodiment, shared memory / L1 cache 2818 includes, without limitation, 128 KB memory capacity and is in a path from SM 2800 to a partition unit. In at least one embodiment, shared memory / L1 cache 2818 is used to cache read and write operations. In at least one embodiment, one or more of shared memory / L1 cache 2818, L2 cache, and memory are backup memory.In at least one embodiment, combining data cache and shared memory functionality into a single memory block provides improved performance for both types of memory accesses. In at least one embodiment, capacity is used by programs that do not use shared memory or is usable as a cache, such as when shared memory is configured to use half capacity, texture and load / store operations may use remaining capacity. In at least one embodiment, integration within shared memory / L1 cache 2818 allows shared memory / L1 cache 2818 to function as a high-throughput line for streaming data while simultaneously providing high bandwidth, low latency access to frequently reused data. In at least one embodiment, when configured for general purpose parallel calculation, a simpler configuration may be used compared to graphics processing. In at least one embodiment, fixed function GPUs are bypassed, thereby creating a much simpler programming model. In at least one embodiment and in a general purpose parallel computation configuration, a work distribution unit directly allocates and distributes blocks of threads to DPCs. In at least one embodiment, threads in a block execute same program, wherein a unique thread ID is used in a computation to ensure that each thread generates unique results, SM 2800 is used to execute a program and perform computations, shared memory / L1 cache 2818 is used to communicate between threads, and LSU 2814 is used to read and write global memory through shared memory / L1 cache 2818 and a memory partition unit. In at least one embodiment, SM 2800, when configured for general purpose parallel calculation, writes instructions that scheduler unit 2804 may use to start new operations on DPCs. In at least one embodiment, SM 2800 includes one or more distributed shared memories (or distributed shared memories) that enable direct SM-to-SM operations, such as loading, storing, and performing atoms across multiple shared SM memory blocks.In at least one embodiment, SM 2800 includes one or more asynchronous execution functions including a tensor storage accelerator (TMA) unit that can transfer data blocks between global memory and shared memory. In at least one embodiment, one or more processors use or access one or more TMAs to perform bidirectional copy operations, e.g., global to shared memory, and vice versa. In at least one embodiment, SM 2800 includes one or more TMAs for asynchronous copying between thread blocks in a cluster. In at least one embodiment, SM 2800 includes one or more asynchronous transaction barriers to perform atomic data movement and synchronization. In at least one embodiment, SM 2800 includes a tensor core transformer engine that includes software and one or more cores to speed up transformer model training and inference. In at least one embodiment, one or more processor cores of a transformer that perform one or more tensor core transformer engines dynamically manage and choose between FP8 and 16-bit computations by redesigning and scaling between FP8 and 16-bit in each layer of one or more neural networks.In at least one embodiment, PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smartphone (e.g., a wireless handheld device), a PDA, a digital camera, a vehicle, a head-mounted display, a handheld electronic device, and more. In at least one embodiment, PPU is embodied on a single semiconductor substrate. In at least one embodiment, PPU is included in a SoC along with one or more other devices, such as additional PPUs, memories, a RISC CPU, an MMU, a digital-to-analog converter ("DAC"), and the like.In at least one embodiment, PPU may be included on a graphics card that includes one or more storage devices. In at least one embodiment, a graphics card may be configured to interface with a PCIe slot on a desktop computer motherboard. In at least one embodiment, PPU may be an integrated GPU ("iG") included in a chipset of motherboard.Software Designs for General Purpose ComputersThe following figures set forth, without limitation, example software designs for implementing at least one embodiment.FIG. 29 illustrates a software stack of a programming platform, according to at least one embodiment. In at least one embodiment, a programming platform is a platform for employing hardware on a computing system to accelerate computing tasks. A programming platform may be accessible to software developers through libraries, compiler policies, and / or extensions of programming languages, in at least one embodiment. In at least one embodiment, a programming platform may be, but is not limited to, CUDA, Radon open compute platform ("ROCm"), OpenCL (OpenCL™ is developed by Khronos Group), SYCL, or Intel One API.In at least one embodiment, a software stack 2900 provides a programming platform execution environment for an application 2901. In at least one embodiment, application 2901 may include any computer software capable of being launched on software stack 2900. In at least one embodiment, application 2901 may include, but is not limited to, an artificial intelligence ("AI") / machine learning ("ML") application, a high performance computing ("HPC") application, a virtual desktop infrastructure ("VDI"), or a data center workload.In at least one embodiment, application 2901 and software stack 2900 run on hardware 2907. Hardware 2907, in at least one embodiment, may include one or more GPUs, CPUs, FPGAs, Al engines, and / or other types of computing devices supporting a programming platform. In at least one embodiment, such as with CUDA, software stack 2900 may be manufacturer specific and compatible only with devices from a particular manufacturer(s). In at least one embodiment, such as with OpenCL, software stack 2900 may be used with devices from various manufacturers. In at least one embodiment, hardware 2907 includes a host connected to one or more devices that are accessible to perform computing tasks via application programming interface ("API") calls. A device within hardware 2907, in at least one embodiment, may include, but is not limited to, a GPU, an FPGA, an AI engine, or other computing device (may also include a CPU) and its memory, as opposed to a host within hardware 2907 that, in at least one embodiment, may include, but is not limited to, a CPU (may also include a computing device) and its memory.In at least one embodiment, programming platform software stack 2900 includes, without limitation, a number of libraries 2903, a runtime 2905 and a device core driver 2906. Each of the libraries 2903 may include data and programming code that may be used by computer programs and deployed during software development, in at least one embodiment. In at least one embodiment, libraries 2903 may include, but are not limited to, prescribed code and subroutines, classes, values, type specifications, configuration data, documentation, auxiliary data, and / or templates. In at least one embodiment, libraries 2903 include functions optimized for execution on one or more types of devices. In at least one embodiment, libraries 2903 may include, but are not limited to, functions for performing mathematical, deep learning, and / or other types of operations on devices. In at least one embodiment, libraries 2903 are associated with corresponding APIs 2902, which may include one or more APIs that expose functions implemented in libraries 2903. In at least one embodiment, a processor (e.g., CPU, GPU) performs, otherwise calls, or otherwise uses one or more APIs to prioritize kernels. For example, a first kernel (e.g., predecessor) may launch a second kernel (e.g., successor kernel), and the second kernel may be used by a processor to launch additional kernels (e.g., grandchild kernels) independent of the first kernel. In at least one embodiment, a processor executes or calls an API from memory to be performed to support dynamic stream priority (e.g., update priority while a stream is being used to perform operations). For example, when a processor is executing the API, it allows a programmer to copy the stream priority from one stream to one or more other streams.In at least one embodiment, software stack 2900 includes an API to support dynamic stream priority (e.g., update priority while a stream is being used to perform operations), which allows a programmer to set priority of a stream at any time after generation. In at least one embodiment, software stack 2900 includes an API to support dynamic stream priority (e.g., update priority while stream is being used to perform operations), which allows a programmer to obtain current priority of a stream, where priority is one of multiple attributes of a stream. In at least one embodiment, software stack 2900 includes an API to support dynamic stream priority (e.g., update priority while stream is being used to perform operations), which allows a programmer to obtain current priority of a stream as a single attribute. In at least one embodiment, software stack 2900 includes an API to support dynamic stream priority (e.g., update priority while stream is being used to perform operations), which allows a programmer to launch a kernel to perform operations on a stream with a set priority that may be different than stream priority. In at least one embodiment, software stack 2900 includes an API to indicate whether an object (e.g., a thread synchronization object such as a barrier) tracks whether all data movement operations for a set of threads operating on a GPU are completed has a specified state after a specified period of time, where a specified state may be a state indicating that data has been moved and ready for use and is specified using an expected parity value as an input to API.In at least one embodiment, software stack 2900 includes one or more updated kernel APIs. In at least one embodiment, a processor executes or invokes an API from memory to be executed to update an existing API to support context-free kernels, allowing a programmer to add a kernel node to a graph without a graphics context so that a graphics context can be dynamically associated with a kernel at runtime. In at least one embodiment, software stack 2900 includes one or more APIs to enable a programmer to obtain kernel identifier and graphics context as separate parameters from a kernel node such that parameters from kernels and context-free kernels can be obtained. In at least one embodiment, software stack 2900 includes one or more APIs to use parallel processor(s), such as one or more graphics processing units, to launch task graphs (e.g., task graphs) and execute one or more task graphs (e.g., including one or more programs).In at least one embodiment, software stack 2900 includes one or more APIs to associate one or more instructions with one or more memory ordering operations, such as a fence or membar operation. In at least one embodiment, instructions are associated with one or more domains such that a storage ordering operation is performed in conjunction with one or more particular domains without disturbing instructions of other domains, an API to indicate that a thread has arrived (e.g., at a thread synchronization barrier), or a stage of work related to asynchronous data movement operations has ended on a GPU. In at least one embodiment, software stack 2900 includes one or more to enable programmers to manually indicate an expected transaction count when a thread has completed a stage of operation used to update an object that tracks whether all data movement operations for a set of threads are completed.In at least one embodiment, application 2901 is written as source code compiled to executable code, as discussed in more detail below in connection with FIGS. 34-36. Executable code of application 2901, in at least one embodiment, may run at least partially on an execution environment provided by software stack 2900. In at least one embodiment, during execution of application 2901, code may be reached that is to run on a device, as opposed to a host. In such a case, runtime 2905 may be invoked to load and start required code on the device, in at least one embodiment. In at least one embodiment, runtime 2905 may include any technically possible runtime system capable of supporting execution of application S 01.In at least one embodiment, runtime 2905 is implemented as one or more runtime libraries associated with corresponding APIs shown as API(s) 2904. One or more such runtime libraries may include, among other things, memory management, execution control, device management, fault handling, and / or synchronization functions in at least one embodiment. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, freeing, and copying device memory, as well as transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions to launch a function (sometimes referred to as a "kernel" when a function is a global function that can be invoked by a host) on a device and set attribute values in a buffer maintained by a runtime library for a given function to be executed on a device.Runtime libraries and corresponding API(s) 2904 may be implemented in any technically possible manner in at least one embodiment. In at least one embodiment, one (or any number of) API may expose a set of low-level functions for fine-grained control of a device, while another (or any number of) API may expose a set of such high-level functions. In at least one embodiment, a high-level runtime API may be built on a low-level API. In at least one embodiment, one or more runtime APIs may be language-specific APIs layered on a language-independent runtime API.In at least one embodiment, one or more processors disclosed in "processing systems" may execute, access, or otherwise use software stack 2900. For example, the APU 1600, CPU 1700, example graphics processors 19A- 19B, general purpose graphics processing unit ("GPGPU") 2030, parallel processor 2100, processing cluster 2194, graphics multiprocessor 2134, graphics multiprocessor 2196, graphics processor 2200, processor 2300, processor 2400, parallel processing unit ("PPU") 2600, GPC 2700, and / or streaming multiprocessor ("SM") 2800 may perform, use, invoke, or otherwise implement (e.g., by accessing memory) one or more APIs included in the software stack 2900.In at least one embodiment, device core driver 2906 is configured to enable communication with an underlying device. In at least one embodiment, device core driver 2906 may provide low-level functionalities that rely on APIs, such as API(s) 2904, and / or other software. In at least one embodiment, device core driver 2906 may be configured to compile intermediate representation ("IR") code into binary code at runtime. For CUDA, the device core driver 2906 may compile parallel thread execution ("PTX") IR code, which is not hardware specific, into binary code for a specific target device (caching compiled binary code), which is sometimes also referred to as a "completion code" in at least one embodiment. This may allow, in at least one embodiment, completed code to execute on a target device that may not exist when source code was originally compiled to PTX code. Alternatively, in at least one embodiment, device source code may be compiled offline to binary code without device core driver 2906 having to compile IR code at runtime.FIG. 30 illustrates a CUDA implementation of the software stack 2900 of FIG. 29, in accordance with at least one embodiment. In at least one embodiment, a CUDA software stack 3000 on which an application 3001 may be launched includes CUDA libraries 3003, a CUDA runtime 3005, a CUDA driver 3007, and a device kernel driver 3008. In at least one embodiment, CUDA software stack 3000 executes on hardware 3009, which may include a GPU that supports CUDA and is developed by NVIDIA Corporation of Santa Clara, CA.In at least one embodiment, application 3001, CUDA runtime 3005, and device core driver 3008 may perform similar functionalities as application 2901, runtime 2905 and device core driver 2906 respectively described above in connection with FIG. 29. In at least one embodiment, CUDA driver 3007 includes a library (libcuda.so) that implements a CUDA driver API 3006. Similar to a CUDA runtime API 3004 implemented by a CUDA runtime library (cudart), in at least one embodiment, CUDA driver API 3006 may expose, among other things, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, CUDA driver API 3006 differs from CUDA runtime API 3004 in that CUDA runtime API 3004 simplifies device code management by providing implicit initialization, context management (analogous to a process), and module management (analogous to dynamically loaded libraries). In contrast to the high-level CUDA runtime API 3004, in at least one embodiment, the CUDA driver API 3006 is a low-level API that provides a finer-grain control of the device, particularly with respect to contexts and module load. In at least one embodiment, CUDA driver API 3006 may expose context management features not exposed by CUDA runtime API 3004. In at least one embodiment, CUDA driver API 3006 is also voice independent and supports, e.g., OpenCL in addition to CUDA runtime API 3004. Further, in at least one embodiment, development libraries, including CUDA runtime 3005, may be considered separate from driver components, including user mode CUDA driver 3007 and kernel mode device driver 3008 (sometimes also referred to as a "display" driver).In at least one embodiment, CUDA libraries 3003 may include, but are not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries that may utilize parallel computing applications such as application 3001. In at least one embodiment, CUDA libraries 3003 may include mathematical libraries such as a cuBLAST library that is an implementation of basic linear algebraic subprograms ("BLAST") for performing linear algebraic operations, a cuFFT library for computing fast Fourier transforms ("FFTs"), and a cuRAND library for generating random numbers, among others. In at least one embodiment, CUDA libraries 3003 may include deep learning libraries, such as a cuDN library of deep neural network primitives and a TensorRT platform for high performance deep learning inference, among others.FIG. 31 illustrates a ROCm implementation of the software stack 2900 of FIG. 29, in accordance with at least one embodiment. In at least one embodiment, a ROCm software stack 3100 on which an application 3101 may be launched includes a voice runtime 3103, a system runtime 3105, a then 3107, and a ROCm core driver 3108. In at least one embodiment, ROCm software stack 3100 is executed on hardware 3109, which may include a GPU supporting ROCm and developed by AMD Corporation of Santa Clara, CA.In at least one embodiment, application 3101 may perform similar functionalities as application 2901 discussed above in connection with FIG. 29. Additionally, in at least one embodiment, voice runtime 3103 and system runtime 3105 may perform similar functionalities as runtime 2905 discussed above in connection with FIG. 29. In at least one embodiment, Runtime 3103 and System Runtime 3105 differ in that System Runtime 3105 is a Runtime Independent of Speech that implements a ROCr System Runtime API 3104 and uses a Heterogeneous System Architecture ("HSA") Runtime API. The HSA runtime API is a thin user mode API that exposes interfaces for access and interaction with an AMD GPU, including functions for memory management, execution control over architectural distribution of cores, fault handling, system and agent information, and runtime initialization and shutdown, among other things, in at least one embodiment. In contrast to system runtime 3105, in at least one embodiment, voice runtime 3103 is an implementation of a voice-specific runtime API 3102 layered on ROCr system runtime API 3104. In at least one embodiment, voice runtime API may include, but is not limited to, a heterogeneous computing interface for portability ("HIP") voice runtime API, a heterogeneous computing compiler ("HCC") voice runtime API, or an OpenCL API. The HIP language is, in particular, an extension of the C++ programming language with functionally similar versions of CUDA mechanisms, and in at least one embodiment, a HIP runtime API includes functions similar to those of the CUDA runtime API 3004 discussed above in connection with FIG. 30, such as functions for memory management, execution control, device management, error handling, and synchronization, among others.In at least one embodiment, the then (ROCt) 3107 is an interface 3106 that can be used to interact with underlying ROCm driver 3108. In at least one embodiment, ROCm driver 3108 is an ROCk driver that is a combination of an AMDGPU driver and an HSA core driver (AMDKFD). In at least one embodiment, AMDGPU driver is a device core driver for GPUs developed by AMD that performs similar functionalities as device core driver 2906 discussed above in connection with FIG. 29. In at least one embodiment, HSA core driver is a driver that allows different types of processors to more effectively share system resources via hardware features.In at least one embodiment, various libraries (not shown) may be included in ROCm software stack 3100 over runtime 3103 and provide functionality similarity to CUDA libraries 3003 discussed above in connection with FIG. 30. In at least one embodiment, different libraries may include, but are not limited to, mathematical, deep learning, and / or other libraries, such as a cuBLAST library that implements functions similar to those of CUDA cuBLAST, a rocFFT library for computing FFTs similar to CUDA cuFFT, among others.FIG. 32 illustrates an OpenCL implementation of the software stack 2900 of FIG. 29, in accordance with at least one embodiment. In at least one embodiment, an OpenCL software stack 3200 on which an application 3201 may be launched includes an OpenCL framework 3210, an OpenCL runtime 3200, and a driver 3207. In at least one embodiment, OpenCL software stack 3200 is executed on hardware 3009, which is not manufacturer specific. Because OpenCL is supported by devices developed by various manufacturers, specific OpenCL drivers may be required to cooperate with hardware from such manufacturers, in at least one embodiment.In at least one embodiment, application 3201, OpenCL runtime 3206, device kernel driver 3207 and hardware 3208 may perform similar functionalities as application 2901, runtime 2905, device kernel driver 2906 and hardware 2907, respectively, discussed above in connection with FIG. 29. In at least one embodiment, application 3201 further includes an OpenCL kernel 3202 with code to be executed on a device.In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to host. In at least one embodiment, an OpenCL framework provides a platform layer API and a runtime API, shown as platform API 3203 and runtime API 3205. In at least one embodiment, runtime API 3205 uses contexts to manage execution of cores on devices. In at least one embodiment, each identified device may be associated with a respective context that runtime API 3205 may use to manage command queues, program objects, and kernel objects, among other things, sharing storage objects for that device. In at least one embodiment, platform API 3203 enables functions that enable device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices, among other things. Additionally, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, and image processing functions, among others, in at least one embodiment.In at least one embodiment, compiler 3204 is also included in OpenCL framework 3210. Source code may be compiled offline before an application is executed, or online during execution of an application, in at least one embodiment. In contrast to CUDA and ROCm, in at least one embodiment, OpenCL applications may be compiled online by compiler 3204, which is included to be representative of any number of compilers that may be used to compile source code and / or IR code, such as standard portable intermediate representation ("SPIR-V") code, into binary code. Alternatively, in at least one embodiment, OpenCL applications may be compiled offline before such applications are executed.FIG. 33 illustrates software supported by a programming platform, according to at least one embodiment. In at least one embodiment, a programming platform 3304 is configured to support various programming models 3303, middlewares and / or libraries 3302, and frameworks 3301 upon which an application 3300 may rely. In at least one embodiment, application 3300 may be an AI / ML application implemented using, for example, a deep learning framework such as MXNet, PyTor, or TensorFlow that may rely on libraries such as cuDN, NVIDIA Collective Communications Library ("NCCL") and / or NVIDA Developer Data Loading Library ("DALI") CUDA libraries to provide accelerated computing on underlying hardware.In at least one embodiment, programming platform 3304 may be one of a CUDA, ROCm, or OpenCL platform described above in connection with FIGS. 30, 31, and 32, respectively. In at least one embodiment, programming platform 3304 supports multiple programming models 3303, which are abstractions of an underlying computing system that enable expressions of algorithms and data structures. The programming models 3303 may expose features from underlying hardware in at least one embodiment to improve performance. In at least one embodiment, programming models 3303 may include, but are not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multi-Processing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute.In at least one embodiment, libraries and / or middlewares 3302 provide implementations of abstractions of programming models 3304. In at least one embodiment, such libraries include data and programming code that can be used by computer programs and deployed during software development. In at least one embodiment, such middlewares include software that provides services for applications beyond those available from programming platform 3304. In at least one embodiment, libraries and / or middlewares 3302 may include, but are not limited to, cuBLAST, cuBLAST, cuRAND, and other CUDA libraries, or rocBLAST, rocFFT, rocRAND, and other ROCm libraries. Additionally, in at least one embodiment, libraries and / or middlewares 3302 may include NCCL and ROCm Communication Collective Library ("RCCL") libraries that provide communication routines for GPUs, a MIOpen library for deep learning acceleration, and / or a self-library for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.In at least one embodiment, application frameworks 3301 depend on libraries and / or middlewares 3302. In at least one embodiment, each of application frameworks 3301 is a software framework used to implement a standard structure of application software. Referring again to the AI / ML example discussed above, in at least one embodiment, an AI / ML application may be implemented using a framework such as coffee, coffee2, tensor discovery, keras, pyTor, or MxNet deep learning framework.FIG. 34 illustrates compilation code for execution on one of the programming platforms of FIGS. 29-32, in accordance with at least one embodiment. In at least one embodiment, compiler 3401 receives source code 3400 that includes both host code and device code. In at least one embodiment, compiler 3401 is configured to convert source code 3400 into host executable code 3402 for execution on a host and device executable code 3403 for execution on a device. In at least one embodiment, source code 3400 may be compiled either offline before an application is executed or online during execution of an application. In at least one embodiment, compiler 3401 includes or has access to one or more libraries to recognize a sequence of API calls to perform a single merged API, where a single merged API is a combined API for two or more APIs.In at least one embodiment, source code 3400 may include code in any programming language supported by compiler 3401, such as C++, C, Fortran, etc. In at least one embodiment, source code 3400 may be included in a single source file having a mixture of host code and device code, with locations of device code indicated therein. In at least one embodiment, a single source file may be a.cu file including CUDA code or a.hip.cpp file including HIP code. Alternatively, in at least one embodiment, source code 3400 may include multiple source code files instead of a single source file into which host code and device code are separated.In at least one embodiment, compiler 3401 is configured to compile source code 3400 into host executable code 3402 for execution on a host and device executable code 3403 for execution on a device. In at least one embodiment, compiler 3401 performs operations including parsing source code 3400 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment, where source code 3400 includes a single source file, compiler 3401 may separate device code from host code in such a single source file, compile device code and host code into device executable code 3403 and host executable code 3402, respectively, and associate device executable code 3403 and host executable code 3402 in a single file, as discussed in more detail below with respect to FIG. 35.In at least one embodiment, host executable code 3402 and device executable code 3403 may be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, host executable code 3402 may include native object code and device executable code 3403 may include code in a PTX intermediate representation. In the case of ROCm, both host executable code 3402 and device executable code 3403 may include target binary code in at least one embodiment.FIG. 35 is a more detailed illustration of compilation code for execution on one of the programming platforms of FIGS. 29-32, in accordance with at least one embodiment. In at least one embodiment, compiler 3501 is configured to receive source code 3500, compile source code 3500, and output executable file 3510. In at least one embodiment, source code 3500 is a single source file, such as a.cu file, a.hip.cpp file, or a file in another format that includes both host and device code. In at least one embodiment, compiler 3501 may be, but is not limited to, an NVIDIA CUDA compiler ("NVCC") for compiling CUDA code into.cu files or an HCC compiler for compiling HIP code into.hip.cpp files.In at least one embodiment, compiler 3501 includes compiler front end 3502, host compiler 3505, device compiler 3506, and linker 3509. In at least one embodiment, compiler front end 3502 is configured to separate device code 3504 from host code 3503 into source code 3500. Device code 3504 is compiled by device compiler 3506 in at least one embodiment into device executable code 3508 that may include binary code or IR code as described. Separately, host code 3503 is compiled by host compiler 3505, in at least one embodiment, into host executable code 3507. For NVCC, host compiler 3505 may be a general-purpose C / C++ compiler that outputs, but is not limited to, native object code, while device compiler 3506 may be a low-level virtual machine ("LLVM")-based compiler that forks an LLVM compiler infrastructure and outputs, in at least one embodiment, PTX code or binary code. For HCC, both host compiler 3505 and device compiler 3506 may be LLVM-based compilers that, in at least one embodiment, output target binary code, but are not limited thereto.After compiling source code 3500 into host executable code 3507 and device executable code 3508, in at least one embodiment, linker 3509 associates host and device executable code 3507 and 3508 with each other in executable file 3510. In at least one embodiment, native object code for a host and PTX or binary code for a device may be linked together in an executable and linkable format ("ELF") file, which is a container format used to store object code.FIG. 36 illustrates translating source code prior to compiling source code, in accordance with at least one embodiment. In at least one embodiment, source code 3600 is passed through a translation tool 3601 that translates source code 3600 to translated source code 3602. In at least one embodiment, compiler 3603 is used to compile translated source code 3602 into host executable code 3604 and device executable code 3605 in a process similar to compiling source code 3400 by compiler 3401 into host executable code 3402 and device executable code 3403, as discussed above in connection with FIG. 34.In at least one embodiment, translation performed by translation tool 3601 is used to connect source 3600 for execution in an environment other than where it should be originally executed. In at least one embodiment, translation tool 3601 may include a HIP translator used to "translate" CUDA code intended for a CUDA platform into HIP code that may be compiled and executed on a ROCm platform, but is not limited thereto. In at least one embodiment, translation of source code 3600 may include parsing source code 3600 and converting calls to API(s) provided by one programming model (e.g., CUDA) into corresponding calls to API(s) provided by another programming model (e.g., HIP), as discussed in more detail below in connection with FIGS. 37A-38. Returning to, for example, translating CUDA code, calls to CUDA runtime API, CUDA driver API, and / or CUDA libraries may be converted to corresponding HIP API calls, in at least one embodiment. In at least one embodiment, automated translations performed by translation tool 3601 may sometimes be incomplete, requiring additional manual effort to fully connect source code 3600.CONFIGURATION OF GUS FOR GENERAL PURPOSE COMPUTINGThe following figures set forth, without limitation, example architectures for compiling and executing compute source code, in accordance with at least one embodiment.FIG. 37A illustrates a system 3700 configured to compile and execute CUDA source code 3710 using various types of processing units, in accordance with at least one embodiment. In at least one embodiment, system 3700 includes, without limitation, CUDA source code 3710, CUDA compiler 3750, executable host code 3770( 1), executable host code 3770( 2), CUDA device executable code 3784, CPU 3790, CUDA-enabled GPU 3794, GPU 3792, CUDA-to-HIP translation tool 3720, HIP source code 3730, HIP compiler driver 3740, HCC 3760, and HCC device executable code 3782.In at least one embodiment, CUDA source code 3710 is a collection of human readable code in a CUDA programming language. In at least one embodiment, CUDA code is human readable code in a CUDA programming language. In at least one embodiment, a CUDA programming language is an extension of C++ programming language that includes, without limitation, mechanisms for defining device code and for distinguishing between device code and host code. In at least one embodiment, device code is source code that is executable in parallel on a device after compilation. In at least one embodiment, an apparatus may be a processor optimized for parallel instruction processing, such as CUDA-enabled GPU 3790, GPU 37192, or other GPGPU, etc. In at least one embodiment, host code is source code executable on a host after compilation. In at least one embodiment, a host is a processor optimized for sequential instruction processing, such as CPU 3790.In at least one embodiment, CUDA source code 3710 includes, without limitation, any number (including zero) of global functions 3712, any number (including zero) of device functions 3714, any number (including zero) of host functions 3716, and any number (including zero) of host / device functions 3718. In at least one embodiment, global functions 3712, device functions 3714, host functions 3716, and host / device functions 3718 may be mixed into CUDA source code 3710. In at least one embodiment, each of global functions 3712 is executable on a device and callable by a host. In at least one embodiment, one or more of global functions 3712 may therefore function as input points for a device. In at least one embodiment, each of global functions 3712 is a kernel. In at least one embodiment and in a technique known as dynamic parallelism, one or more of global functions 3712 define a kernel executable on a device and callable by such a device. In at least one embodiment, a kernel is executed N times (where N is any positive integer) in parallel by N different threads on a device during execution.In at least one embodiment, each of device functions 3714 is executed on a device and only callable by such a device. In at least one embodiment, each of host functions 3716 executes on a host and is callable only by such a host. In at least one embodiment, each of host / device functions 3716 defines both a host version of a function executable on a host and callable only by such a host and a device version of function executable on a device and callable only by such a device.In at least one embodiment, CUDA source code 3710 may also include, without limitation, any number of calls to any number of functions defined via a CUDA runtime API 3702. In at least one embodiment, CUDA runtime API 3702 may include, without limitation, any number of functions executing on a host to allocate and free device memory, transfer data between host memory and device memory, manage multi-device systems, etc. In at least one embodiment, CUDA source code 3710 may also include any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API configured for use by CUDA code. In at least one embodiment, CUDA APIs include, without limitation, a CUDA runtime API 3702, a CUDA driver API, APIs for any number of CUDA libraries, etc. In at least one embodiment, and with respect to CUDA runtime API 3702, CUDA driver API is a lower-level API, but provides finer-grain control of a device. In at least one embodiment, examples of CUDA libraries include, without limitation, cuBLAST, cu, cuRAND, cuDNN, etc.In at least one embodiment, CUDA compiler 3750 compiles input CUDA code (e.g., CUDA source code 3710) to generate host executable code 3770( 1) and CUDA executable device code 3784. In at least one embodiment, CUDA compiler 3750 is NVCC. In at least one embodiment, host executable code 3770( 1) is a compiled version of host code included in input source code executable on CPU 3790. In at least one embodiment, CPU 3790 may be any processor optimized for sequential instruction processing.In at least one embodiment, CUDA executable device code 3784 is a compiled version of device code included in input source code executable on a CUDA-enabled GPU 3794. In at least one embodiment, CUDA executable device code 3784 includes, without limitation, binary code. In at least one embodiment, CUDA executable device code 3784 includes, without limitation, IR code, such as PTX code, which is further compiled at runtime by a device driver into binary code for a specific target device (e.g., CUDA capable GPU 3794). In at least one embodiment, CUDA-enabled GPU 3794 may be any processor optimized for parallel instruction processing and supporting CUDA. In at least one embodiment, CUDA-capable GPU 3794 is developed by NVIDIA Corporation of Santa Clara, CA.In at least one embodiment, CUDA to HIP translation tool 3720 is configured to translate CUDA source code 3710 into functionally similar HIP source code 3730. In at least one embodiment, HIP source code 3730 is a collection of human readable code in a HIP programming language. In at least one embodiment, HIP code is human readable code in a HIP programming language. In at least one embodiment, a HIP programming language is an extension of C++ programming language that includes, without limitation, functionally similar versions of CUDA mechanisms for defining device code and for distinguishing between device code and host code. In at least one embodiment, a HIP programming language may include a subset of functionalities of a CUDA programming language. In at least one embodiment, for example, without limitation, a HIP programming language includes (a) mechanism(s) for defining global functions 3712 but such a HIP programming language may lack support for dynamic parallelism, and therefore global functions 3712 defined in HIP code may be callable only from a host.In at least one embodiment, HIP source code 3730 includes, without limitation, any number (including zero) of global functions 3712, any number (including zero) of device functions 3714, any number (including zero) of host functions 3716, and any number (including zero) of host / device functions 3718. In at least one embodiment, HIP source code 3730 may also include any number of calls to any number of functions specified in a HIP runtime API 3732. In at least one embodiment, HIP runtime API 3732 includes, without limitation, functionally similar versions of a subset of functions included in CUDA runtime API 3702. In at least one embodiment, HIP source code 3730 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, a HIP API may be any API configured for use by HIP code and / or ROCm. In at least one embodiment, HIP APIs include, without limitation, a HIP runtime API 3732, a HIP driver API, APIs for any number of HIP bibliotheken, APIs for any number of ROCm bibliotheken, etc.In at least one embodiment, CUDA-to-HIP translation tool 3720 converts each kernel call to CUDA code from a CUDA syntax to a HIP syntax, and converts any number of other CUDA calls to CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in a CUDA API, and a HIP call is a call to a function specified in a HIP API. In at least one embodiment, CUDA-to-HIP translation tool 3720 converts any number of calls to functions specified in CUDA runtime API 3702 to any number of calls to functions specified in HIP runtime API 3732.In at least one embodiment, CUDA-to-HIP translation tool 3720 is a tool known as a Hipify-perl that performs a text-based translation process. In at least one embodiment, CUDA-to-HIP translation tool 3720 is a tool known as Hipify-clang that performs a more complex and robust translation process compared to Hipify-perl that includes parsing CUDA code using clang (a compiler front end) and then translating resulting symbols. In at least one embodiment, properly converting CUDA code to HIP code may require modifications (e.g., manual manipulations) in addition to those performed by CUDA to HIP translation tool 3720.In at least one embodiment, HIP compiler driver 3740 is a front end that determines a target device 3746, and then configures a compiler compatible with target device 3746 to compile HIP source code 3730. In at least one embodiment, target device 3746 is a processor optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver 3740 may determine target device 3746 in any technically possible manner.In at least one embodiment, if target device 3746 is compatible with CUDA (e.g., CUDA-enabled GPU 3794), then HIP compiler driver 3740 generates a HIP / NVCC compilation instruction 3742. In at least one embodiment, and as described in more detail in connection with FIG. 37B, HIP / NVCC compilation instruction 3742 configures CUDA compiler 3750 to compile HIP source code 3730 using, without limitation, a HIP-to-CUDA translation header and a CUDA runtime library. In at least one embodiment, and in response to HIP / NVCC compilation instruction 3742, CUDA compiler 3750 generates host executable code 3770( 1) and CUDA executable device code 3784.In at least one embodiment, if target device 3746 is not compatible with CUDA, then HIP compiler driver 3740 generates a HIP / HCC compilation instruction 3744. In at least one embodiment, and as described in more detail in connection with FIG. 37C, HIP / HCC compilation instruction 3744 configures HCC 3760 to compile HIP source code 3730 using, without limitation, an HCC header and a HIP / HCC runtime library. In at least one embodiment, and in response to HIP / HCC compilation instruction 3744, HCC 3760 generates host executable code 3770( 2) and HCC executable device code 3782. In at least one embodiment, HCC executable device code 3782 is a compiled version of device code included in HIP source code 3730 executable on GPU 3792. In at least one embodiment, GPU 3792 may be any processor that is optimized for parallel instruction processing, is not compatible with CUDA, and is compatible with HCC. In at least one embodiment, GPU 3792 is a non-CUDA-capable GPU 3792.For purposes of illustration only, three different flows are shown in FIG. 37A, which may be implemented in at least one embodiment to compile CUDA source code 3710 for execution on CPU 3790 and various devices. In at least one embodiment, a direct CUDA flow compiles CUDA source code 3710 for execution on CPU 3790 and CUDA-capable GPU 3794 without translating CUDA source code 3710 into HIP source code 3730. In at least one embodiment, indirect CUDA flow translates CUDA source code 3710 into HIP source code 3730 and then compiles HIP source code 3730 for execution on CPU 3790 and CUDA-enabled GPU 3794. In at least one embodiment, a CUDA / HCC flow translates CUDA source code 3710 into HIP source code 3730 and then compiles HIP source code 3730 for execution on CPU 3790 and GPU 3792.A direct CUDA flow, which may be implemented in at least one embodiment, is represented by dashed lines and a series of bubbles labeled A1-A3. In at least one embodiment, and as shown with bubble A1, CUDA compiler 3750 receives CUDA source code 3710 and a CUDA compilation instruction 3748 configuring CUDA compiler 3750 to compile CUDA source code 3710. In at least one embodiment, CUDA source code 3710 used in a direct CUDA flow is written in a CUDA programming language based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to CUDA compilation instruction 3748, CUDA compiler 3750 generates host executable code 3770( 1) and CUDA executable device code 3784 (shown as bubble labeled A2). In at least one embodiment, and as shown with bubble A3, host executable code 3770( 1) and CUDA executable device code 3784 may be executed on CPU 3790 and CUDA capable GPU 3794, respectively. In at least one embodiment, CUDA executable device code 3784 includes, without limitation, binary code. In at least one embodiment, CUDA executable device code 3784 includes, without limitation, PTX code and is further compiled to binary code for a specific target device at runtime.An indirect CUDA flow, which may be implemented in at least one embodiment, is illustrated by dashed lines and a series of bubbles, designated B1-B6. In at least one embodiment, and as shown with bubble B1, CUDA to HIP translation tool 3720 receives CUDA source code 3710. In at least one embodiment, and as depicted with bubble B2, CUDA-to-HIP translation tool 3720 translates CUDA source code 3710 into HIP source code 3730. In at least one embodiment, and as shown with bubble B3, HIP compiler driver 3740 receives HIP source code 3730 and determines that target device 3746 is CUDA capable.In at least one embodiment, and as shown with bubble B4, HIP compiler driver 3740 generates a HIP / NVCC compilation instruction 3742, and transmits both HIP / NVCC compilation instruction 3742 and HIP source code 3730 to CUDA compiler 3750. In at least one embodiment, and as described in more detail in connection with FIG. 37B, HIP / NVCC compilation instruction 3742 configures CUDA compiler 3750 to compile HIP source code 3730 using, without limitation, a HIP-to-CUDA translation header and a CUDA runtime library. In at least one embodiment, and in response to HIP / NVCC compilation instruction 3742, CUDA compiler 3750 generates host executable code 3770( 1) and CUDA executable device code 3784 (shown as bubble labeled B 5). In at least one embodiment, and as shown with bubble B6, host executable code 3770( 1) and CUDA executable device code 3784 may be executed on CPU 3790 and CUDA capable GPU 3794, respectively. In at least one embodiment, CUDA executable device code 3784 includes, without limitation, binary code. In at least one embodiment, CUDA executable device code 3784 includes, without limitation, PTX code and is further compiled to binary code for a specific target device at runtime.A CUDA / HCC flow, which may be implemented in at least one embodiment, is represented by solid lines and a series of bubbles, designated C1-C6. In at least one embodiment, and as shown with bubble C1, CUDA to HIP translation tool 3720 receives CUDA source code 3710. In at least one embodiment, and as depicted with bubble C2, CUDA-to-HIP translation tool 3720 translates CUDA source code 3710 into HIP source code 3730. In at least one embodiment, and as shown with bubble C3, HIP compiler driver 3740 receives HIP source code 3730 and determines that target device 3746 is not CUDA capable.In at least one embodiment, HIP compiler driver 3740 generates a HIP / HCC compilation instruction 3744, and transmits both HIP / HCC compilation instruction 3744 and HIP source code 3730 to HCC 3760 (shown as bubble labeled C4). In at least one embodiment, and as described in more detail in connection with FIG. 37C, HIP / HCC compilation instruction 3744 configures HCC 3760 to compile HIP source code 3730 using, without limitation, an HCC header and a HIP / HCC runtime library. In at least one embodiment, and in response to HIP / HCC compilation instruction 3744, HCC 3760 generates host executable code 3770( 2) and HCC executable device code 3782 (shown as bubble C 5). In at least one embodiment, and as shown by bubble C6, host executable code 3770( 2) and HCC executable device code 3782 may be executed on CPU 3790 and GPU 3792, respectively.In at least one embodiment, after CUDA source code 3710 is translated to HIP source code 3730, HIP compiler driver 3740 may then be used to generate executable code for either CUDA-enabled GPU 3794 or GPU 3792 without re-executing CUDA-to-HIP translation tool 3720. In at least one embodiment, CUDA-to-HIP translation tool 3720 translates CUDA source code 3710 into HIP source code 3730, which is then stored in memory. In at least one embodiment, HIP compiler driver 3740 then configures HCC 3760 to generate host executable code 3770( 2) and HCC executable device code 3782 based on HIP source code 3730. In at least one embodiment, HIP compiler driver 3740 subsequently configures CUDA compiler 3750 to generate host executable code 3770( 1) and CUDA executable device code 3784, based on stored HIP source code 3730.FIG. 37B illustrates a system 3704 configured to compile and execute CUDA source code 3710 of FIG. 37A using the CPU 3790 and the CUDA-enabled GPU 3794, according to at least one embodiment. In at least one embodiment, system 3704 includes, without limitation, CUDA source code 3710, CUDA-to-HIP translation tool 3720, HIP source code 3730, HIP compiler driver 3740, CUDA compiler 3750), host executable code 3770(1), CUDA executable device code 3784, CPU 3790, and CUDA capable GPU 3794.In at least one embodiment, and as described hereinabove in connection with FIG. 37A, CUDA source code 3710 includes, without limitation, any number (including zero) of global functions 3712, any number (including zero) of device functions 3714, any number (including zero) of host functions 3716, and any number (including zero) of host / device functions 3718. In at least one embodiment, CUDA source code 3710 also includes, without limitation, any number of calls to any number of functions specified in any number of CUDA APIs.In at least one embodiment, CUDA-to-HIP translation tool 3720 translates CUDA source code 3710 into HIP source code 3730. In at least one embodiment, CUDA-to-HIP translation tool 3720 converts each kernel call to CUDA source code 3710 from a CUDA syntax to a HIP syntax, and converts any number of other CUDA calls to CUDA source code 3710 to any number of other functionally similar HIP calls.In at least one embodiment, HIP compiler driver 3740 determines that target device 3746 is CUDA capable and generates HIP / NVCC compilation instruction 3742. In at least one embodiment, HIP compiler driver 3740 then configures CUDA compiler 3750, via HIP / NVCC compilation instruction 3742, to compile HIP source code 3730. In at least one embodiment, HIP compiler driver 3740 provides access to a HIP-to-CUDA translation header 3752 as part of configuring CUDA compiler 3750. In at least one embodiment, HIP-to-CUDA translation header 3752 translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs into any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, CUDA compiler 3750 uses HIP-to-CUDA translation header 3752 in conjunction with a CUDA runtime library 3754 corresponding to CUDA runtime API 3702 to generate host executable code 3770( 1) and CUDA executable device code 3784. In at least one embodiment, host executable code 3770( 1) and CUDA executable device code 3784 may then be executed on CPU 3790 and CUDA capable GPU 3794, respectively. In at least one embodiment, CUDA executable device code 3784 includes, without limitation, binary code. In at least one embodiment, CUDA executable device code 3784 includes, without limitation, PTX code and is further compiled to binary code for a specific target device at runtime.FIG. 37C illustrates a system 3706 configured to compile and execute CUDA source code 3710 of FIG. 37A using the CPU 3790 and the non-CUDA-capable GPU 3792, according to at least one embodiment. In at least one embodiment, system 3706 includes, without limitation, CUDA source code 3710, CUDA to HIP translation tool 3720, HIP source code 3730, HIP compiler driver 3740, HCC 3760, host executable code 3770( 2), HCC executable device code 3782, CPU 3790, and GPU 3792.In at least one embodiment, and as described hereinabove in connection with FIG. 37A, CUDA source code 3710 includes, without limitation, any number (including zero) of global functions 3712, any number (including zero) of device functions 3714, any number (including zero) of host functions 3716, and any number (including zero) of host / device functions 3718. In at least one embodiment, CUDA source code 3710 also includes, without limitation, any number of calls to any number of functions specified in any number of CUDA APIs.In at least one embodiment, CUDA-to-HIP translation tool 3720 translates CUDA source code 3710 into HIP source code 3730. In at least one embodiment, CUDA-to-HIP translation tool 3720 converts each kernel call to CUDA source code 3710 from a CUDA syntax to a HIP syntax, and converts any number of other CUDA calls to source code 3710 to any number of other functionally similar HIP calls.In at least one embodiment, HIP compiler driver 3740 subsequently determines that target device 3746 is not CUDA capable and generates HIP / HCC compilation instruction 3744. In at least one embodiment, HIP compiler driver 3740 then configures HCC 3760 to execute HIP / HCC compilation instruction 3744 to compile HIP source code 3730. In at least one embodiment, HIP / HCC compilation instruction 3744 configures HCC 3760 to use, without limitation, a HIP / HCC runtime library 3758 and an HCC header 3756 to generate host executable code 3770( 2) and HCC executable device code 3782. In at least one embodiment, HIP / HCC runtime library 3758 corresponds to HIP runtime API 3732. In at least one embodiment, HCC header 3756 includes, without limitation, any number and type of interoperability mechanisms for HIP and HCC. In at least one embodiment, host executable code 3770( 2) and HCC executable device code 3782 may be executed on CPU 3790 and GPU 3792, respectively.FIG. 38 illustrates an example kernel translated by the CUDA to HIP translation tool 3720 of FIG. 37C, according to at least one embodiment. In at least one embodiment, CUDA source code 3710 partitions an overall problem a given kernel is to solve into relatively coarse sub-problems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads. In at least one embodiment, each sub-problem is partitioned into relatively fine parts that can be cooperatively solved in parallel by threads within a thread block. In at least one embodiment, threads within a thread block may cooperate by sharing data through shared memory and by synchronizing execution to coordinate memory accesses.In at least one embodiment, CUDA source code 3710 organizes thread blocks associated with a given kernel into a one-dimensional, a two-dimensional, or a three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads, and a raster includes, without limitation, any number of thread blocks.In at least one embodiment, a kernel is a function in device code defined using a declaration specifier "_gal__". In at least one embodiment, dimension of a grid executing a kernel for a given kernel call and associated streams is specified using a CUDA kernel launch syntax 3810. In at least one embodiment, CUDA kernel launch syntax 3810 is specified as "KernelName, BlockSize, SharedMemorySize, Stream"(KernelArguments);". In at least one embodiment, an execution configuration syntax is a construct "<... "" inserted between a kernel name ("KernelName") and a bracketed list of kernel arguments ("KernelArgument"). In at least one embodiment, CUDA kernel launch syntax 3810 includes, without limitation, a CUDA launch function syntax instead of an execution configuration syntax.In at least one embodiment, "GridSize" is type dim3 and specifies dimension and size of a grid. In at least one embodiment, type dim3is a CUDA-defined structure that includes unsigned integers x, y, and z without limitation. In at least one embodiment, z is default one if z is not specified. In at least one embodiment, y is default one if y is not specified. In at least one embodiment, number of thread blocks in a raster is equal to product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is dim3type and specifies dimension and size of each thread block. In at least one embodiment, number of threads per thread block is equal to product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing a kernel is given a unique thread ID that can be accessed within kernel by a built-in variable (e.g., "threadIdx").In at least one embodiment, and with respect to CUDA kernel launch syntax 3810, "SharedMemorySize" is an optional argument that specifies a number of bytes in shared memory dynamically allocated per thread block for a given kernel call in addition to statically allocated memory. In at least one embodiment, and with respect to CUDA kernel launch syntax 3810, SharedMemorySize is default to zero. In at least one embodiment, and with respect to CUDA kernel launch syntax 3810, "stream" is an optional argument that specifies an associated stream and is default to zero to specify a default stream. In at least one embodiment, a stream is a sequence of instructions (possibly issued by different host threads) that are executed in order. In at least one embodiment, different streams may execute out-of-order commands with respect to each other or simultaneously.In at least one embodiment, CUDA source code 3710 includes, without limitation, a kernel definition for an example kernel "MatAdd" and a main function. In at least one embodiment, main function is host code executing on a host and includes, without limitation, a kernel call that causes kernel MatAdd to execute on a device. In at least one embodiment and as shown, kernel MatAddadds two matrices A and B of size N×N, where N is a positive integer, and stores result in a matrix C. In at least one embodiment, main function defines a ThreadPerBlock variable as 16 times 16 and a numBlock variable as N / 16 times N / 16. In at least one embodiment, main function then specifies kernel call "MatAdd<<numBlocks threadPerBlock" (A, B, C);". In at least one embodiment, and in accordance with CUDA kernel launch syntax 3810, kernel MatAdd is executed using a grid of thread blocks having a dimension N / 16 times N / 16, each thread block having a dimension of 16 times 16. In at least one embodiment, each thread block includes 256 threads, a grid is created with enough blocks to have one thread per matrix element, and each thread in such a grid executes kernel MatAdd to perform pairwise addition.In at least one embodiment, CUDA-to-HIP translation tool 3720 while translating CUDA source code 3710 into HIP source code 3730 translates each kernel call to CUDA source code 3710 from CUDA kernel launch syntax 3810 into a HIP kernel launch syntax 3820 and converts any number of other CUDA calls to source code 3710 into any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax 3820 is specified as "hipLaKernel" (KernelName, GridSize, BlockSize, SharedMemorySize, Stream, KernelArgument); ". In at least one embodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArgument has same meaning in HIP kernel launch syntax 3820 as in CUDA kernel launch syntax 3810 (described hereinabove). In at least one embodiment, arguments SharedMemorySize and Stream are required in HIP kernel launch syntax 3820 and are optional in CUDA kernel launch syntax 3810.In at least one embodiment, a portion of HIP source code 3730 shown in FIG. 38 is identical to a portion of CUDA source code 3710 shown in FIG. 38, except for a kernel call that causes kernel MatAdd to execute on a device. In at least one embodiment, kernel MatAdd is defined in HIP source code 3730 with same declaration specifier "__global__" as kernel MatAdd is defined in CUDA source code 3710. In at least one embodiment, a kernel call in HIP source code 3730 is "hipLaunchKernelGGL(MatAdd numBlocks, threadPerBlock, 0, 0, A, B, C);" while a corresponding kernel call in CUDA source code 3710 is "MatAdd<<numBlocks threadPerBlock>>(A, B, C);".FIG. 39 illustrates a non-CUDA-capable GPU 3792 of FIG. 37C in more detail according to at least one embodiment. In at least one embodiment, GPU 3792 is developed by AMD Corporation of Santa Clara, CA. In at least one embodiment, GPU 3792 may be configured to perform computational operations in a highly parallel manner. In at least one embodiment, GPU 3792 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometric computations, and other operations associated with rendering an image on a display. In at least one embodiment, GPU 3792 is configured to perform operations that do not relate to graphics. In at least one embodiment, GPU 3792 is configured to perform both graphics-related operations and non-graphics-related operations. In at least one embodiment, GPU 3792 may be configured to execute device code included in HIP source code 3730.In at least one embodiment, GPU 3792 includes, without limitation, any number of programmable processing units 3920, instruction processor 3910, L2 cache 3922, memory controllers 3970, DMA engines 3980( 1), system memory controllers 3982, DMA engines 3980( 2), and GPU controllers 3984. In at least one embodiment, each programmable processing unit 3920 includes, without limitation, a workload manager 3930 and any number of compute units 3900. In at least one embodiment, command processor 3910 reads commands from one or more command queues (not shown) and distributes commands to workload manager 3930. In at least one embodiment, for each programmable processing unit 3920, associated workload manager 3930 distributes work to compute units 3940 included in programmable processing unit 3920. In at least one embodiment, each compute unit 3940 may execute any number of thread blocks, but each thread block is executed on a single compute unit 3940. In at least one embodiment, a working group is a thread block.In at least one embodiment, each computing unit 3940 includes, without limitation, any number of SIMD units 3950 and shared memory 3960. In at least one embodiment, each SIMD unit 3950 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each SIMD unit 3950 includes, without limitation, a vector ALU 3952 and a vector register file 3904. In at least one embodiment, each SIMD unit 3950 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in warp belongs to a single thread block and is configured to process a different dataset based on a single instruction set. In at least one embodiment, prediction may be used to disable one or more threads in a warp. In at least one embodiment, a trace is a thread. In at least one embodiment, a work element is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize with each other and communicate via shared memory 3960. In at least one embodiment, compute unit 3940 includes one or more distributed shared memories (or distributed shared memories) that enable a direct streaming multiprocessor (SM) to stream multiple processors (SM) for operations related to loading, storing, and performing atomics across multiple shared SM memory blocks.In at least one embodiment, programmable processing unit 3920 includes, without limitation, any amount of dedicated graphics hardware in addition to computing units 3900. In at least one embodiment, programmable processing unit 3920 includes, without limitation, any number (including zero) of geometry processors, any number (including zero) of rasters, any number (including zero) of render back ends, workload manager 3930, and any number of compute units 3900.In at least one embodiment, compute units 3940 share L2 cache 3922. In at least one embodiment, L2 cache 3922 is partitioned. In at least one embodiment, a GPU memory 3990 is accessible by all compute units 3940 in GPU 3792. In at least one embodiment, memory controllers 3970 and system memory controllers 3982 enable data transfers between GPU 3792 and a host, and DMA engines 3980( 1) enable asynchronous memory transfers between GPU 3792 and such a host. In at least one embodiment, memory controllers 3970 and GPU controllers 3984 enable data transfers between GPU 3792 and other GPUs 3792, and DMA engines 3980( 2) enable asynchronous memory transfers between GPU 3792 and other GPUs 3792.In at least one embodiment, GPU 3792 includes, without limitation, any amount and type of system connection that enables data and control transfers across any number and type of directly or indirectly connected components that may be internal or external to GPU 3792. In at least one embodiment, GPU 3792 includes, without limitation, any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices. In at least one embodiment, GPU 3792 may include, without limitation, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU 3792 implements a memory subsystem that includes, without limitation, any amount ...

Claims

A processor comprising: one or more circuits for executing an application programming interface (API) to indicate whether one or more memories indicated by one or more users of the API correspond to one or more non-uniform memory access (NUMA) memories or one or more graphics processing unit (GPU) memories.The processor of claim 1, wherein the API is to indicate a NUMA node to which data was last pre-called from another API.The processor of claim 1, wherein the API is to indicate a NUMA node specified by an API other than a preferred location of one or more memory addresses.The processor of claim 1, wherein the API is to indicate a location type and a location identity of a virtual memory accessible by one or more central processing units (CPUs) and one or more GPUs.The processor of claim 1, wherein the API is to receive one or more inputs indicating a storage area.The processor of claim 1, wherein the one or more memories indicated by one or more users are a region of virtual memory accessible by one or more central processing units (CPUs) and one or more GPUs.The processor of claim 1, wherein the API is to return an identifier of a location type and an identifier of a location identity based at least in part on one or more inputs indicating a storage area.A system, comprising: one or more processors to execute an application programming interface (API) to indicate whether one or more memories indicated by one or more users of the API correspond to one or more non-uniform memory access (NUMA) memories or one or more graphics processing unit (GPU) memories.The system of claim 8, wherein the API is to indicate a NUMA node to which data stored using one or more virtual memory addresses was previously explicitly pre-fetched.The system of claim 8, wherein the API is to indicate a NUMA node that is set as a preferred storage location of a range of virtual storage addresses.The system of claim 8, wherein the API is to indicate a NUMA node to which a region of virtual memory indicated by the one or more users was last pre-called.The system of claim 8, wherein the one or more memories indicated by one or more users of the API are indicated using information as input to the API indicating one or more virtual storage locations accessible by one or more NUMA nodes and one or more GPUs.The system of claim 8, wherein the API is to indicate a NUMA node to which a region of virtual memory accessible by one or more NUMA nodes and one or more GPUs was last pre-called using an API.A method comprising: executing an application programming interface (API) to indicate whether one or more memories indicated by one or more users of the API correspond to one or more non-uniform memory access (NUMA) memories or one or more graphics processing unit (GPU) memories.The method of claim 14, wherein the one or more memories indicated by one or more users of the API are one or more managed storage locations indicated by information received as one or more inputs to the API indicating a range of managed storage.The method of claim 14, wherein the API is to indicate a preferred NUMA or GPU memory of the one or more memories indicated by the one or more users.The method of claim 14, wherein the API is to indicate a NUMA memory or GPU memory to which the one or more memories were last pre-called.The method of claim 14, wherein the one or more NUMA memories are physical memories comprised in one or more NUMA nodes each including one or more central processing units (CPUs).The method of claim 14, wherein the one or more memories indicated by one or more users are one or more virtual memory addresses accessible by one or more central processing units (CPUs) and one or more GPUs.A non-transitory computer readable medium having stored thereon a set of instructions which, when executed by one or more processors, cause the one or more processors to perform at least the method of claim 14.

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