Structuring the gate contacts for a static random access memory

Abstract

Integrated circuit structures (ICs) with static random-access memory (SRAM) fabricated by structuring the gate contacts after source / drain (S / D) metallization are disclosed. An exemplary IC structure includes a transistor comprising an S / D region and a gate electrode material, an S / D contact in electrical contact with the S / D region, and a gate contact in electrical contact with the gate electrode material. The S / D contact comprises a first electrically conductive material, the gate contact comprises a second electrically conductive material, and a portion of the second electrically conductive material is in electrical contact with a portion of the first electrically conductive material, wherein the average grain size or orientation in the portion of the first electrically conductive material differs from the average grain size or orientation in the portion of the second electrically conductive material.

Description

background

[0001] Embedded memory is critical to the performance of modern system-on-a-chip (SoC) technology. Static random-access memory (SRAM) is one example that can be implemented as embedded memory, which is particularly suitable for modern SoCs due to its compatibility with manufacturing processes used to fabricate compute logic, such as front-end of line (FEOL) processes. In some deployment scenarios, SRAM may have advantages over other memory types, such as dynamic random-access memory (DRAM). Short description of the drawings

[0002] Embodiments will be readily understood from the following detailed description when taken in conjunction with the accompanying drawings. To facilitate this description, like reference numerals indicate like structural elements. Embodiments are illustrated in the figures of the accompanying drawings by way of example and not by way of limitation. Fig. 1 provides a perspective view of an example nanoribbon field effect transistor (FET) according to some embodiments of the present disclosure. Fig. 2 provides an electrical diagram of an exemplary SRAM cell according to some embodiments of the present disclosure. Fig. 3 is a flowchart of an exemplary SRAM manufacturing method according to some embodiments. Fig. 4A to 4F provide side cross-sectional views at various stages in the fabrication of an exemplary integrated circuit (IC) structure according to the method in Fig. 3 according to some embodiments. Fig. 5 is a top view of a wafer and die that may include any of the IC structures disclosed herein, according to any of the embodiments disclosed herein. Fig. 6 is a side cross-sectional view of an IC device that may include any of the IC structures disclosed herein, according to any of the embodiments disclosed herein. Fig. 7 is a side cross-sectional view of an IC package that may include any of the IC structures disclosed herein, according to various embodiments. Fig. 8 is a side cross-sectional view of an IC device assembly that may include any of the IC structures disclosed herein, in accordance with any of the embodiments disclosed herein. Fig. 9 is a block diagram of an exemplary electrical device that may include any of the IC structures disclosed herein, in accordance with any of the embodiments disclosed herein. Detailed description

[0003] Described herein is an SRAM manufacturing method and associated transistor arrangements, IC structures, and devices. The systems, methods, and devices of this disclosure each have several innovative aspects, none of which alone accounts for all of the desirable attributes noted herein. Details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0004] To illustrate an SRAM manufacturing process proposed herein, it may be useful to first understand the phenomena that may occur during SRAM manufacturing. The following basic information can be considered a basis from which the present disclosure can be adequately explained. This information is for illustrative purposes only and, accordingly, should in no way be construed to limit the broad scope of the present disclosure and its potential applications.

[0005] In recent decades, the scaling of functions in IC structures has been a driving force behind an ever-growing semiconductor industry. Scaling to ever smaller functions enables higher densities of functional units on the limited footprint of semiconductor chips. For example, reducing transistor size enables the integration of a larger number of memory or logic devices on a chip, enabling products with increased capacity. However, the drive for ever-increasing capacity also presents problems. The need to optimize every part of IC structures is becoming increasingly important. Careful design of SRAM can assist in such optimization.

[0006] An SRAM cell contains multiple transistors for storing a bit value or a memory state (e.g., logical "1" or "0") of the cell, and one or more access transistors for controlling access to the cell (e.g., access for writing information to the cell or access for reading information from the cell). For example, an SRAM cell may consist of six transistors (6T) and is therefore referred to as a "6T SRAM cell," where four transistors are used to store a bit value and two transistors are access transistors coupled to a bit line (BL) and a word line (WL). In such an SRAM cell, four of the transistors are transistors of a first type and two transistors of a second type, where the type of a transistor is defined by the majority of carriers in a transistor: N-type transistors (e.g.,N-type metal-oxide-semiconductor transistors (NMOS) have electrons as the majority carriers, and P-type transistors (e.g., P-type metal-oxide-semiconductor transistors (PMOS)) have holes as the majority carriers. Therefore, in some embodiments of a 6T SRAM cell, four of the transistors may be N-type transistors while two of the transistors are P-type transistors, and in other embodiments of a 6T SRAM cell, four of the transistors may be P-type transistors while two of the transistors are N-type transistors. Other examples of SRAM cells may include additional transistors; for example, an SRAM cell may include eight transistors, but such SRAM cells would also include the six transistors of a 6T SRAM cell.

[0007] In an SRAM cell with six or more transistors, the gate contacts of some transistors are intentionally shorted (i.e., directly electrically connected) to the source or drain contacts of other transistors. The performance of an SRAM device depends heavily on the quality of such an intentional short circuit. In particular, controlling the etch depth, critical dimension, and uniformity of the gate contacts shorted to S / D contacts is important for transistor performance. For example, it is critical that the gate contacts shorted to S / D contacts are deep enough and fully landed to provide sufficient non-resistive gate contact.At the same time, however, it is important that the gate contacts are not too deep to avoid damaging the titanium silicide formed at the interfaces between S / D regions and S / D contacts, which places strict requirements on process tolerances in SRAM manufacturing.

[0008] An SRAM manufacturing process proposed herein may help address one or more of the challenges described above. For example, it may help increase process tolerances for shorting gate contacts to adjacent structures while simultaneously fabricating reliable gate and S / D contacts. The process described herein implements gate contact patterning after S / D contact metallization, which is in sharp contrast to conventional SRAM manufacturing processes where gate contact patterning is performed before S / D contact metallization.Embodiments of the present disclosure are based on a finding that patterning the gate contacts after S / D contact metallization may help protect the titanium silicide formed at the interfaces between the S / D regions and the S / D contacts, thereby reducing or eliminating damage to the titanium silicide at these interfaces. When patterning the gate contacts is performed after S / D contact metallization, the titanium silicide may be covered by the S / D contact materials, providing better process tolerances of the gate contact depth and thereby improving SRAM yield.

[0009] Implementing an SRAM manufacturing process in which gate contact patterning is performed after S / D contact metallization may result in several features specific to the use of the process in the final IC structures. For example, in one aspect, an exemplary IC structure fabricated using gate contact patterning after S / D contact metallization includes a transistor including an S / D region and a gate electrode material, an S / D contact in electrical contact with the S / D region, and a gate contact in electrical contact with the gate electrode material.The S / D contact comprises a first electrically conductive material, the gate contact comprises a second electrically conductive material, and a portion of the second electrically conductive material is in electrical contact with a portion of the first electrically conductive material, wherein an average grain size or orientation in the portion of the first electrically conductive material differs from an average grain size or orientation in the portion of the second electrically conductive material.

[0010] IC structures as described herein, particularly IC structures with SRAM fabricated by performing gate contact patterning after S / D contact metallization, may be implemented in one or more components associated with an IC or various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those mounted on the IC or those connected to an IC. The IC may be either analog or digital and, depending on the components associated with the IC, is usable in a variety of applications such as microprocessors, optoelectronics, logic blocks, audio amplifiers, and others.In some embodiments, the IC devices described herein may be included in a radio frequency integrated circuit (RFIC), which may, for example, be included in any component associated with an IC of an RF receiver, an RF transmitter, or an RF transceiver, such as those used in telecommunications in base stations (BS) or user equipment (UE). These components may include, but are not limited to, power amplifiers, low-noise amplifiers, RF filters (including arrays of RF filters or RF filter banks), switches, upconverters, downconverters, and duplexers. In some embodiments, the IC structures described herein may be included in memory devices or circuits.In some embodiments, the IC structures described herein are usable as part of a chipset for performing one or more related functions in a computer.

[0011] For purposes of explanation, specific numbers, materials, and configurations are provided to provide a thorough understanding of the illustrative implementations. However, one skilled in the art will appreciate that the present disclosure may be practiced without the specific details and / or with only some of the described aspects. In other instances, well-known functions are omitted or simplified so as not to obscure the illustrative implementations. The terms "substantially," "near," "approximately," "near," and "approximately" generally refer to values ​​within + / - 10% of a target value, e.g., within + / - 5% of a target value, based on the context of a particular value, as described herein or known in the art. Similarly, terms indicating an orientation of various elements, e.g.,"coplanar," "perpendicular," "orthogonal," "parallel," or other angle between the elements, generally to be within + / - 10% of a target value, e.g., within + / - 5% of a target value based on the context of a particular value, as described herein or known in the art.

[0012] In the following description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown for purposes of illustration, practical embodiments. It is understood that other embodiments may be utilized and that structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, in a collection of drawings designated by different letters, e.g. Fig. 4A-4F, such a collection may be referred to here without the letters, e.g. as “ Fig. 4".

[0013] While some schematic representations of example structures of various devices and assemblies described herein may be depicted in the drawings with precise right angles and straight lines, this is for illustrative purposes only, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped, as dictated and sometimes unavoidable by the manufacturing processes used to fabricate semiconductor device assemblies. Therefore, it should be understood that these schematic representations do not necessarily reflect real-world processing limitations, which may result in features appearing less than "ideal" when the structures described herein are examined, for example, using scanning electron microscopy (SEM) or transmission electron microscopy (TEM) images.Such images of real structures may also reveal possible processing defects, e.g., imperfectly straight edges of materials, tapered vias or other openings, unintentional rounding of corners or variations in the thickness of different material layers, isolated screw, step, or combined dislocations within the crystalline region, and / or occasional dislocation defects of individual atoms or clusters of atoms. Other defects not listed here but common in the field of device manufacturing may also be present. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit, e.g., using optical microscopy, TEM, or SEM, and / or inspection of a cross-section of a device to identify the shape and position of various device elements described herein, e.g.,using physical failure analysis (PFA), would make it possible to determine the presence of an SRAM fabricated by patterning the gate contacts after S / D contact metallization as described herein.

[0014] Various aspects of the example implementations are described using terms commonly used by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the terms "oxide," "carbide," "nitride," "silicide," etc., refer to compounds containing oxygen, carbon, nitrogen, silicon, etc.; the term "high-k dielectric" refers to a material with a higher dielectric constant than silicon oxide; the term "low-k dielectric" refers to a material with a lower dielectric constant than silicon oxide. Materials referred to herein by formulas or compounds include any materials containing elements of the formula or a compound. For example, TiSi or titanium silicide may refer to materials containing titanium and silicon; WN or tungsten nitride may refer to materials containing tungsten and nitrogen; etc.The term "insulating" means "electrically insulating," and the term "conductive" means "electrically conductive," unless otherwise specified. Furthermore, the term "connected" can be used to describe a direct electrical or magnetic connection between the connected things without any intermediary devices, while the term "coupled" can be used to describe either a direct electrical or magnetic connection between the connected things or an indirect connection via one or more passive or active intervening devices. A first component described as being electrically coupled to a second component means that the first component is in conductive contact with the second component (i.e., that a conductive path is provided to conduct electrical signals / power between the first and second components).

[0015] Various operations may be described sequentially as multiple discrete actions or operations in a manner most useful for understanding the claimed subject matter. However, the order of description should not be construed to imply that these operations are necessarily order dependent. The operations need not be performed in the order presented. Described operations may be performed in a different order than the described embodiment. In additional embodiments, various additional operations may also be performed and / or described operations may be omitted.

[0016] For the purposes of this disclosure, the term "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the term "A, B, and / or C" means (A), (B), (C), (A and B), (A and C); (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is understood to include the endpoints of the measurement ranges.

[0017] The description uses the phrases "in one embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. The terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may employ perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate discussion and are not intended to limit the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise indicated, the use of the ordinal adjectives "first," "second," "third," etc., refers to the following:To describe a common object, this merely means that reference is made to various instances of similar objects, and is not intended to imply that the objects so described must be arranged in a particular sequence, whether temporally, spatially, in order, or otherwise. Although some materials can be described singularly, such materials may contain multiple materials; for example, a semiconductor material may contain two or more different semiconductor materials.

[0018] An SRAM fabrication process that includes patterning the gate contacts after S / D contact metallization can be performed with transistors of any architecture, such as a non-planar or planar architecture. Non-planar transistors, such as dual-gate transistors, tri-gate transistors, FinFETs, and nanowire / nanoribbon / nanosheet transistors, refer to transistors with a non-planar architecture. Compared to a planar architecture, where the transistor channel has only one boundary surface, a non-planar architecture is any type of architecture where the transistor channel has more than one boundary surface. A boundary surface refers to a specific orientation of the channel surface, which is limited by the gate field. Non-planar transistors can improve performance over transistors with a planar architecture, such as single-gate transistors.

[0019] Nanoribbon transistors can be particularly advantageous for the continuous scaling of complementary metal-oxide-semiconductor (CMOS) technology nodes because they can form gates on all four sides of a channel material (hence such transistors are sometimes referred to as "gate all around" transistors). Therefore, some IC structures presented herein show nanoribbon transistors as an example (e.g., in Fig. 1 and Fig. 4A to 4F), although the SRAM fabrication method described herein is not limited to such transistors.

[0020] As used herein, the term "nanoribbon" refers to an elongated structure of a semiconductor material having a longitudinal axis parallel to a support structure (e.g., a substrate, a die, a chip, or a wafer) over which such a structure is constructed. Typically, a length of such a structure (i.e., a dimension measured along the longitudinal axis, which in the present drawings is shown along the Y-axis of an exemplary XYZ coordinate system 105, illustrated in Fig. 1) is greater than any width (i.e., a dimension measured along the X-axis of the coordinate system 105) and any thickness / height (i.e., a dimension measured along the Z-axis of the coordinate system 105). In some cases, the terms "nanoribbon" or "nanosheet" have been used to describe elongated semiconductor structures having a rectangular cross-section (i.e., a cross-section in a plane perpendicular to the long axis of the structure), while the term "nanowire" has been used to describe similar elongated structures but having a circular cross-section. In the present disclosure, the term "nanoribbon" is used to refer to all such nanowires, nanoribbons, and nanosheets, as well as elongated semiconductor structures with a long axis parallel to the support structures and with cross-sections of any geometry (e.g.,Cross-sections in the shape of an oval or a polygon with rounded corners). A transistor can be called a "nanoribbon transistor" if the transistor's channel is part of a nanoribbon, i.e., a part around which a transistor's gate stack can wrap. The semiconductor material in the part of the nanoribbon that forms a transistor channel can be referred to as "channel material," with the source and drain regions of a transistor being provided on either side of the channel material.

[0021] Fig. 1 provides a perspective view of an exemplary IC structure 100 including a nanoribbon transistor 110 according to some embodiments of the present disclosure. As shown in Fig. 1, the IC structure 100 includes a semiconductor material formed as a nanoribbon 104 extending substantially parallel to a carrier 102. The transistor 110 may be formed on the basis of the nanoribbon 104 by wrapping a gate stack 106 around at least a portion of the nanoribbon, referred to as the “channel portion,” and by having source and drain regions formed in Fig. 1 as first S / D region 114-1 and second S / D region 114-2, on both sides of the gate stack 106. One of the S / D regions 114 is a source region, and the other is a drain region. However, since, as is common in the field of FETs, the terms source and drain are often interchangeable, they are referred to herein simply as first S / D region 114-1 and second S / D region 114-2.

[0022] Implementations of the present disclosure may be formed or performed on any suitable carrier 102, such as a substrate, a die, a wafer, or a chip. The carrier 102 may, for example, be the wafer 1500 discussed below from Fig. 5 and can be a Die such as the single Die 1502 discussed below from Fig. 5 or be included therein. The carrier 102 may be a semiconductor substrate consisting of semiconductor material systems, including, for example, n-type or p-type material systems. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In other implementations, the semiconductor substrate may be formed using alternative materials that may or may not be combined with silicon, including, but not limited to, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride, or gallium antimonide, or other combinations of Group III-V materials (i.e.Materials from Groups III and V of the Periodic Table of Elements), materials from Groups II-VI (i.e., materials from Groups II and IV of the Periodic Table of Elements), or materials from Group IV (i.e., materials from Group IV of the Periodic Table of Elements). In some embodiments, the substrate may be non-crystalline. In some embodiments, the carrier 102 may be a printed circuit board (PCB) substrate, a package substrate, an interposer, a wafer, or a die. Although some examples of materials from which the carrier 102 may be formed are described herein, any material that can serve as a foundation upon which an IC structure with SRAM can be built, fabricated by patterning the gate contacts after S / D contact metallization as described herein, falls within the spirit and scope of the present disclosure. Although only one nanoribbon 104 is shown in . Fig. 1, the IC structure 100 may include a stack of such nanoribbons, wherein multiple nanoribbons 104 are stacked on top of each other, e.g., as shown in the Fig. 4A through 4F, which illustrate IC structures that may be examples of IC structure 100. In some embodiments, a portion of carrier 102 directly below the bottommost nanoribbon 104 of the stack may be formed as a subfin extending from a base, as is known in the field of nanoribbon transistors.

[0023] The nanoribbon 104 may, for example, take the form of a nanowire or nanoribbon. In some embodiments, an area of ​​a cross-section of the nanoribbon 104 (i.e., an area in the XZ plane of the coordinate system 105, perpendicular to a longitudinal axis 120 of the nanoribbon 104) may be between about 25 and 10,000 square nanometers, including all values ​​and ranges therein (e.g., between 25 and 1,000 square nanometers or between 25 and 500 square nanometers). In some embodiments, a width of the nanoribbon 104 (i.e., a dimension measured in a plane parallel to the support 102 and in a direction perpendicular to the longitudinal axis 120 of the nanoribbon 104, e.g., along the Y-axis of the coordinate system 105) may be at least about 3 times greater than a height of the nanoribbon 104 (i.e., a dimension measured in a plane perpendicular to the support 102, e.g.,along the Z-axis of coordinate system 105), including all values ​​and ranges contained therein, e.g., at least four times larger, or at least five times larger. Although the value in . Fig. 1 is shown as having a rectangular cross-section, the nanoribbon 104 may instead have a cross-section that is rounded at corners or otherwise irregularly shaped, and the gate stack 106 may conform to the shape of the nanoribbon 104. The term "area" of a nanoribbon may refer to the side of the nanoribbon 104 that is larger than the side perpendicular thereto (measured in a plane substantially perpendicular to the longitudinal axis 120 of the nanoribbon 104), the latter side being referred to as the "sidewall" of a nanoribbon.

[0024] In various embodiments, the semiconductor material of the nanoribbon 104 may consist of semiconductor material systems, for example, including n-type or p-type material systems. In some embodiments, the nanoribbon 104 may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the nanoribbon 104 may include a combination of semiconductor materials. In some embodiments, the nanoribbon 104 may include a monocrystalline semiconductor such as silicon (Si) or germanium (Ge). In some embodiments, the nanoribbon 104 may include a compound semiconductor having a first sublattice of at least one element from group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from group V of the periodic table (e.g.,B. P, Aa, Sb).

[0025] In some exemplary n-type transistor embodiments (i.e., in embodiments where transistor 110 is an NMOS transistor), the channel material of nanoribbon 104 may include a III-V material with a relatively high electron mobility, such as InGaAs, InP, InSb, and InAs, among others. In some of these embodiments, the channel material of nanoribbon 104 may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. In some In x Ga 1-x As-fin embodiments, an In content (x) can be between 0.6 and 0.9 and advantageously at least 0.7 (e.g. In 0,7 Ga 0,3As). In some example embodiments with a p-type transistor (i.e., in embodiments where transistor 110 is a PMOS transistor), the channel material of nanoribbon 104 may advantageously be a Group IV material with high hole mobility, such as Ge or a Ge-rich SiGe alloy, among others. In some example embodiments, the channel material of nanoribbon 104 may have a Ge content between 0.6 and 0.9, and advantageously at least 0.7.

[0026] In some embodiments, the channel material of the nanoribbon 104 may be a thin film material, such as a high mobility oxide semiconductor material such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide.If the transistor formed in the nanoribbon is a thin-film transistor (TFT), the channel material of the nanoribbon 104 may include tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, amorphous or polycrystalline n- or p-type silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and / or black phosphorus, each of which may be doped with gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and / or magnesium, etc. can.In some embodiments, the channel material of nanoribbon 104 may have a thickness between about 5 and 75 nanometers, including all values ​​and ranges in between. In some embodiments, a thin-film channel material may be deposited at relatively low temperatures, allowing the channel material to be deposited within the thermal budgets imposed on back-end manufacturing to avoid damaging other components, e.g., front-end components such as logic devices.

[0027] A gate stack 106, which includes a gate electrode material 108 and optionally a gate insulator material 112, may completely or almost completely enclose a portion of the nanoribbon 104, as shown in Fig. 1, where the active region (channel region) of the channel material of the transistor 110 corresponds to the part of the nanoribbon 104 encased by the gate stack 106. As shown in Fig. 1, the gate insulator material 112 may wrap around a transverse portion of the nanoribbon 104, and the gate electrode material 108 may wrap around the gate insulator material 112.

[0028] The gate electrode material 108 may include one or more gate electrode materials, where the choice of gate electrode materials may depend on whether the transistor 110 is a PMOS transistor or an NMOS transistor. For a PMOS transistor, gate electrode materials that may be used in various portions of the gate electrode material 108 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, gate electrode materials that may be used in various portions of the gate electrode material 108 may include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).In some embodiments, the gate electrode material 108 may comprise a stack of multiple gate electrode materials, where zero or more materials of the stack are work function (WF) materials and at least one material of the stack is a fill metal layer. Additional materials / layers may be included in addition to the gate electrode material 108 for other purposes, such as a diffusion barrier layer and / or an adhesion layer.

[0029] In some embodiments, the gate insulator material 112 may include one or more high-k dielectrics, including the materials discussed herein with reference to the insulator material, which may surround portions of the transistor 110. In some embodiments, an annealing process may be performed on the gate insulator material 112 during fabrication of the transistor 110 to improve the quality of the gate insulator material 112. The gate insulator material 112 may have a thickness that, in some embodiments, may be between about 0.5 nanometers and 3 nanometers, including all values ​​and ranges in between (e.g., between about 1 and 3 nanometers or between about 1 and 2 nanometers). In some embodiments, the gate stack 106 may be surrounded by a gate spacer that may be Fig. 1 is not shown. Such a spacer would be configured to provide separation between the gate stack 106 and the S / D contacts of the transistor 110 and could be made of a low-k dielectric material, some examples of which were mentioned above.

[0030] Turning to the S / D regions 114 of the transistor 110, in some embodiments, the S / D regions may be highly doped, e.g., with dopant concentrations of about 10 21 cm -3 to advantageously establish ohmic contacts with the respective S / D contacts (in Fig. 1 not shown), although these regions may also have lower dopant concentrations and may form Schottky contacts in some implementations. Regardless of the exact doping levels, the S / D regions of a transistor are the regions with a dopant concentration that is higher than in other regions, e.g., higher than a dopant concentration in the transistor channel (i.e., in a channel material extending between the first S / D region 114-1 and the second S / D region 114-2), and may therefore be referred to as “highly doped” (HD) regions. Even if doped to realize the threshold voltage adjustment described herein, the channel portions of transistors typically contain semiconductor materials with a doping concentration that is significantly lower than that of the S / D regions 114.

[0031] The S / D regions 114 of the transistor 110 can generally be formed either by an implantation / diffusion process or by an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic can be introduced into the nanoribbon 104 by ion implantation to form the source and drain regions. The ion implantation can be followed by an annealing process that activates the dopants and causes them to diffuse further into the nanoribbon 104. In the latter process, portions of the nanoribbon 104 can first be etched to form recesses at the locations of the future S / D regions 114. An epitaxial deposition process can then be performed to fill the recesses with material used to fabricate the S / D regions 114.In some implementations, the S / D regions 114 may be fabricated using a silicon alloy, such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants, such as boron, arsenic, or phosphorus. In further embodiments, the S / D regions 114 may be formed using one or more alternative semiconductor materials, such as germanium or a Group III-V material or alloy. In still further embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D regions 114. In some embodiments, a distance between the first and second S / D regions 114 (i.e., a dimension measured along the long axis 120 of the nanoribbon 104) may be between about 5 and 40 nanometers, including all values ​​and ranges therebetween (e.g.,B. between about 22 and 35 nanometers or between about 20 and 30 nanometers).

[0032] The Fig. The IC structure 100 shown in Figure 1, as well as the IC structures shown in other drawings of the present disclosure, are intended to show the relative arrangement of some of the components included therein, and the IC structure 100 or portions thereof may include other components not shown (e.g., electrical contacts to the S / D regions 114 of the transistor 110, additional layers such as a spacer layer around the gate electrode of the transistor 110, etc.). For example, although Fig. 1, a dielectric spacer may be provided between a first S / D contact (which may also be referred to as a “first S / D electrode”) coupled to a first S / D region 114-1 of the transistor 110 and the gate stack 106, and between a second S / D contact (which may also be referred to as a “second S / D electrode”) coupled to a second S / D region 114-2 of the transistor 110 and the gate stack 106 to ensure electrical isolation between the source, gate, and drain electrodes. In another example, although not specifically illustrated in Fig. 1, at least portions of transistor 110 may be surrounded by an insulator material, such as any suitable interlayer dielectric (ILD) material. In some embodiments, such an insulator material may be a high-k dielectric, including elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used for this purpose may include, but are not limited to, hafnium oxide, hafnium silica, lanthanum oxide, lanthanum alumina, zirconium oxide, zirconium silica, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silica, lead scandium tantalum oxide, and lead zinc niobate.In other embodiments, the insulating material surrounding portions of transistor 110 may be a low-k dielectric material. Some examples of low-k dielectric materials include, but are not limited to, silicon dioxide, carbon-doped oxide, silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fused silica glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.

[0033] Fig. 2 provides an electrical diagram of an exemplary SRAM cell 200 according to some embodiments of the present disclosure. The SRAM cell 200 includes transistors M1 through M4 for storing a bit value or a memory state (e.g., logic "1" or "0") of the cell and two access transistors, M5 and M6, for controlling access to the cell (e.g., access for writing information to the cell or access for reading information from the cell 200). Each of the transistors M1 through M6 may be a nanoribbon transistor (e.g., a transistor 110 as shown in Fig. 1) and, to illustrate this, in Fig. 2, the first and second S / D regions 114-1 and 114-2, as well as the gate stack 106, are labeled for each of the transistors M1 to M6. However, in other embodiments of the SRAM cell 200, one or more of the transistors M1 to M6 may be implemented in a geometry / architecture that differs from that shown in Fig. 1 shown. In the description of Fig. 2 and the descriptions of the following drawings, which refer to the Fig. 2, where element A is described as being coupled to element B, the term "coupled" encompasses an embodiment where element A is directly connected to element B. For example, a description that the gate stack 106 of transistor M1 can be coupled to the gate stack 106 of transistor M2 covers an embodiment where the gate stack 106 of transistor M1 is directly connected to the gate stack 106 of transistor M2.

[0034] Fig. 2 illustrates some transistors as N-type transistors (i.e., transistors M1, M3, M5, and M6) and other transistors as P-type transistors (i.e., transistors M2 and M4), using a conventional schematic notation for such transistors. However, in other embodiments of the SRAM cell 200, this notation may be reversed (i.e., transistors M1, M3, M5, and M6 could be P-type transistors and transistors M2 and M4 could be N-type transistors), also using the notation of the transistors shown in Fig. 2, all embodiments being within the scope of the present disclosure.

[0035] In the SRAM cell 200, each bit can be stored on four transistors (M1, M2, M3, M4) forming two cross-coupled inverters 220, each having an input 222 and an output 224. The first inverter 220-1 can be formed by transistor M1 and transistor M2, while the second inverter 220-2 can be formed by transistor M3 and transistor M4. As shown in Fig. 2, the gate stack 106 of transistor M1 may be coupled to the gate stack 106 of transistor M2, and both of these gate stacks may be coupled to the input 222-1 of the first inverter 220-1. On the other hand, the first S / D region 114-1 of transistor M1 may be coupled to the first S / D region 114-1 of transistor M2, and both of these first S / D regions 114-1 may be coupled to the output 224-1 of the first inverter 220-1. Likewise, for the second inverter 220-2, the gate stack 106 of transistor M3 may be coupled to the gate stack 106 of transistor M4. and both of these gate stacks may be coupled to the input 222-2 of the second inverter 220-2, while the first S / D region 114-1 of the transistor M3 may be coupled to the first S / D region 114-1 of the transistor M4, and both of these first S / D regions 114-1 may be coupled to the output 224-2 of the second inverter 220-2. As also in Fig. 2, if the transistors M1 and M3 are N-transistors and the transistors M2 and M4 are P-transistors, as in Fig. 2, the second S / D regions 114-2 of the transistors M1 and M3 may be coupled to a ground voltage 232, while the second S / D regions 114-2 of the transistors M2 and M4 may be coupled to a supply voltage 234, e.g., VDD. In the embodiments of the SRAM cell 200 in which the N-type transistors in Fig. 2 are replaced by P-transistors and vice versa, the designation of the ground voltage 232 and the supply voltage 234 would also be swapped.

[0036] In this configuration, the four transistors M1 to M4 form a stable memory cell for storing a bit value of 0 or 1. As further in Fig. 2, two additional access transistors, M5 and M6, can be used to control access to the memory cell of transistors M1-M4 during read and write operations. As shown in Fig. 2, the first S / D region 114-1 of the access transistor M5 may be coupled to the output 224-1 of the first inverter 220-1. In other words, the first S / D region 114-1 of the access transistor M5 may be coupled to each of the first S / D region 114-1 of the transistor M1 and the first S / D region 114-1 of the transistor M2. The second S / D region 114-2 of the access transistor M5 may be coupled to a first BL 240-1. Thus, each of the first S / D region 114-1 of the transistor M1 and the first S / D region 114-1 of the transistor M2 may be coupled to the first BL 240-1 (e.g., via the access transistor M5). The gate stack 106 of the access transistor M5 can be coupled to a WL 250. As further in Fig. 2, the first S / D region 114-1 of access transistor M6 may be coupled to the output 224-2 of the second inverter 220-2. In other words, the first S / D region 114-1 of access transistor M6 may be coupled to each of the first S / D region 114-1 of transistor M3 and the first S / D region 114-1 of transistor M4. The second S / D region 114-2 of access transistor M6 may be coupled to a second BL 240-2. Thus, each of the first S / D region 114-1 of transistor M3 and the first S / D region 114-1 of transistor M4 may be coupled to the second BL 240-1 (e.g., via the access transistor M6). The gate stack 106 of the access transistor M6 can be coupled to the WL 250. Thus, the gate stacks 106 of the two access transistors M5 and M6 can be coupled to a single, shared WL, the WL 250. As in Fig. 2, the input 222-1 of the first inverter 220-1 may be coupled to the first S / D region 114-1 of the access transistor M6, while the input 222-2 of the second inverter 220-2 may be coupled to the first S / D region 114-1 of the access transistor M5. In other words, each of the gate stack 106 of the transistor M1 and the gate stack 106 of the transistor M2 may be coupled to the first S / D region 114-1 of the access transistor M6, while each of the gate stack 106 of the transistor M3 and the gate stack 106 of the transistor M4 may be coupled to the first S / D region 114-1 of the access transistor M5. In other words, each of the gate stack 106 of transistor M1 and the gate stack 106 of transistor M2 can be coupled to the second BL 240-2 (e.g., via the access transistor M6), while each of the gate stack 106 of transistor M3 and the gate stack 106 of transistor M4 can be coupled to the first BL 240-1 (e.g.,via the access transistor M5).

[0037] The WL 250 and the first and second BL 240 can be used together to read and program (i.e., write) the SRAM cell 200. In particular, access to the cell can be enabled by the WL 250, which controls the two access transistors M5 and M6, which in turn control whether the cell 200 should be connected to the BLs 240-1 and 240-2. During operation of the SRAM cell 200, a signal on the first BL 240-1 can complement a signal on the second BL 240-2. The two BLs 240 can be used to transfer data for read and write operations. In other embodiments of the SRAM cell 200, only a single BL 240 may be used instead of two BLs 240-1 and 240-2 (i.e., the signal on the BL 240-1 and the BL 240-2 may be the same), although a signal BL and an inverse signal, such as the two BLs 240, may contribute to improving the signal-to-noise ratios.

[0038] During read accesses, the BLs 240 are actively driven high and low by the inverters 220 in the SRAM cell 200. This can improve SRAM bandwidth compared to DRAM. The symmetrical structure of the SRAM cell 200 also enables differential signaling, which can improve the detection of small voltage fluctuations. Another difference from DRAM that can help make SRAM faster than DRAM is that commercial chips accept all address bits simultaneously. In comparison, in standard DRAMs, the address can be multiplexed in half—higher bits followed by lower bits—over the same package pins to keep their size and cost down.

[0039] Each of the WLs 250 and the BLs 240, as well as intermediate elements connecting these lines to various terminals described herein, may be made of any suitable electrically conductive material, which may include an alloy or a stack of multiple electrically conductive materials. In some embodiments, such electrically conductive materials may include one or more metals or metal alloys, including metals such as ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum. In some embodiments, such electrically conductive materials may include one or more electrically conductive alloys, oxides, or carbides of one or more metals.

[0040] Fig. 3 is a flowchart of an exemplary SRAM manufacturing method 300, according to some embodiments. Fig. 4A to 4F provide side cross-sectional views at various stages in the fabrication of an exemplary IC structure according to the method in Fig. 3 according to some embodiments. Each of the Fig. 4A to 4F shows a side cross-sectional view of a particular IC structure in the YZ plane of the coordinate system 105 along the axis 120 of Fig. 1. A set of elements referred to in the description of the Fig. 4A to 4F are shown in these drawings with different structures, with a legend showing the correspondence between the reference numbers and structures being located at the bottom of each drawing page with the Fig. 4A to 4F. The legend illustrates, for example, that Fig. 4A to 4F use different structures to show a carrier 402, nanoribbons 404, a gate electrode material 408, a gate insulator material 412, and so on.

[0041] Although the operations of method 300 are each illustrated once and in a particular order, they may be performed in any suitable order and repeated as needed. For example, one or more operations may be performed in parallel to fabricate multiple IC structures with SRAM cells substantially simultaneously. In another example, the operations may be performed in a different order to reflect the structure of an IC device implementing SRAM fabricated by patterning the gate contacts after S / D contact metallization.

[0042] In addition, the exemplary manufacturing process may include 300 additional operations that are Fig. 3, such as various cleaning or planarization processes known in the art. For example, in some embodiments, a carrier 402, as well as layers of various other materials subsequently deposited thereon, may be cleaned before, after, or during any of the processes of method 300 described herein, to remove, for example, oxides, surface-bound organic or metallic contaminants, and subsurface contaminants. In some embodiments, the cleaning may be performed, for example, using chemical solutions (such as peroxide) and / or ultraviolet (UV) radiation in combination with ozone and / or oxidizing the surface (e.g., using thermal oxidation), then removing the oxide (e.g., using hydrofluoric acid (HF)).In another example, the intermediate IC structures described herein may be planarized before, after, or during any of the processes of method 300 described herein to remove any remaining or excess materials. In some embodiments, planarization may be performed using wet or dry planarization processes, for example, where the planarization may be chemical mechanical planarization (CMP), which is understood to be a process that uses a polishing surface, an abrasive, and a polishing slurry to remove the excess and planarize the surface.

[0043] The method 300 may begin with a process 302 that includes providing a stack of released nanoribbons over a carrier and forming a gate stack, S / D regions, and openings for S / D contacts. An IC structure 452 of Fig. 4A illustrates an exemplary result of the process 302. The IC structure 452 shows a carrier 402, a stack of released nanoribbons 404 over the carrier 402, gate stacks 406 with a gate electrode material 408 and a gate insulator material 412 (the gate stacks 406 individually labeled as gate stacks 406-1, 406-2, 406-3, and 406-4), and S / D regions 414. The carrier 402, the nanoribbons 404, the gate stacks 406, the gate electrode material 408, the gate insulator material 412, and the S / D regions 414 may be examples of the carrier 102, the nanoribbons 104, the gate stacks 106, the gate electrode material 108, the Gate insulator material 112 and the S / D regions 114 from the above-described Fig. 1.

[0044] Fig. Figure 4A shows that a plurality of nanoribbons 404 can be stacked on top of each other. Fig. 4A and subsequent drawings show four nanoribbons 404 in a stack, but in other embodiments, a stack of nanoribbons 404 may include any number of two or more nanoribbons 404. The material composition of the various stacks of nanoribbons 404 may vary depending on whether the stacks are intended to implement NMOS or PMOS transistors, as described above. The nanoribbons 404 are "unlocked" by previously forming openings around channel portions of the nanoribbons 404, and then providing the gate insulator materials 412 and the gate electrode materials 408 in the openings, as described above. Fig. 4A also illustrates the gate spacers 422 surrounding each of the gate stacks 406. The gate spacers 422 may be configured to provide separation between the gate stack 406 and future S / D contacts of the transistors 110 along the stack of nanoribbons 404 and may be made of a low-k dielectric material, some examples of which were mentioned above. In some embodiments, the gate spacers 422 may include pores or air gaps to further reduce their dielectric constants. In some embodiments, the gate spacers 422 may include silicon and oxygen, carbon, and / or nitrogen. Fig. 4A further illustrates an insulator material 424 that may be provided over the gate electrode material 408. The insulator material 424 may include any suitable insulator material, e.g., one or more materials described with respect to the ILD materials.

[0045] Fig. 4A shows S / D regions 414 extending through the stack of nanoribbons 404, as well as an insulator material 416 to electrically isolate / separate the S / D regions 414 from the gate electrode material 408 of the gate stacks 406 and from the carrier 402. Portions of the insulator material 416 extending from the respective side of the S / D regions 414 into the openings between the nanoribbons 404, in which the gate stacks 406 are provided, may be referred to as “recesses” 417. In other embodiments, the shape of the recesses 417 may differ from that shown in Fig. 4A, as long as the recesses 417 of the insulator material 416 provide electrical isolation between the S / D regions 414 and the gate electrode material 408. The insulator material 416 may include any suitable insulator material, e.g., one or more materials described with respect to the ILD materials.

[0046] The stack of released nanoribbons 404 provided over the carrier 402, the gate stacks 406, and the S / D regions 414 may be formed according to any of the techniques known in the art. FIG. 4A further illustrates the openings 426, individually labeled as openings 426-1, 426-2, and 426-3, provided over the stack of nanoribbons 404 to expose the S / D regions 414. The gate stacks 406 and the openings 426 are individually labeled to explain which gates are intentionally shorted to which S / D contacts to form an SRAM cell such as the SRAM cell 200 of Fig. 2 to form. In particular, if the nanoribbons 404 have channel materials for the formation of PMOS transistors on them, then the gate stack 406-1, which is later short-circuited with an S / D contact provided in the opening 426-1, may cause a coupling of the gate stack 106 of the transistor M2 to the first S / D region 114-1 of the transistor M4 of the SRAM cell 200 (by coupling the nodes of the input 222-1 and the output 224-2), and the gate stack 406-3, which is later short-circuited with an S / D contact provided in the opening 426-2, may cause a coupling of the gate stack 106 of the transistor M4 to the first S / D region 114-1 of the transistor M2 of the SRAM cell 200 (by coupling the nodes of the input 222-2 and output 224-1) or vice versa.If, on the other hand, the nanoribbons 404 have channel materials to form NMOS transistors along them, then the gate stack 406-1, which is later shorted to an S / D contact provided in the opening 426-1, may couple the gate stack 106 of the transistor M1 to the first S / D region 114-1 of the transistor M3 of the SRAM cell 200 (again by coupling the nodes of the input 222-1 and the output 224-2), and the gate stack 406-3, which is later shorted to an S / D contact provided in the opening 426-2, may couple the gate stack 106 of the transistor M3 to the first S / D region 114-1 of the transistor M1 of the SRAM cell 200 (again by coupling the nodes of the input 222-2 and output 224-1) or vice versa.

[0047] The method 300 may then continue with a method 304 in which a lining material is applied to the sidewalls and bottom of the openings for the S / D contacts of the IC structure 452 and then sunk beneath the insulator material 424. An IC structure 454 made of Fig. 4B illustrates an example result of process 304. As in Fig. 4B, the liner material 428 may line the sidewalls and bottom of the openings 426. The liner material 428 may include any suitable material for forming ohmic contacts between the S / D regions 414 and the electrically conductive material of future S / D contacts. For example, in some embodiments, the liner material 428 may include titanium. The liner material 428 may be deposited using any suitable deposition technique, such as a suitable conformal deposition technique such as atomic layer deposition (ALD). A thickness of the liner material 428 may, in some embodiments, be between about 1 nanometer and about 8 nanometers, including all values ​​and ranges therein, e.g., between about 1 nanometer and 5 nanometers or between about 1 nanometer and 3 nanometers.

[0048] The method 300 also includes a method 306 in which portions of the liner material 428 that come into contact with the S / D regions 414 (i.e., portions at the bottom of the openings 426) interact with the materials of the S / D regions 414 to form an interface material. An IC structure 456 of Fig. Figure 4C illustrates an example result of process 306. As in Fig. 4C, the lower portions of the liner material 428 interact with the materials of the S / D regions 414 to form an interface material 430 at the bottom of the openings 426. For example, if the liner material 428 is titanium and the S / D regions 414 contain silicon, the interface material 430 may be titanium silicide or, more generally, a material containing titanium and silicon. Since the material at the sidewalls of the openings 426 is not a semiconductor material but an insulator material, the liner material 428 remains substantially as originally deposited on the sidewalls of the openings 426. In some embodiments, a thickness of the liner material 428 at the sidewalls may be between about 1 nanometer and about 3 nanometers, e.g., about 2 nanometers. In some embodiments, a thickness of the interface material 430 may be between about 2 and 8 nanometers, including all values ​​and ranges therein, e.g.between about 1 nanometer and 5 nanometers, or below about 6 nanometers.

[0049] The method 300 may then continue with a method 308 in which an electrically conductive fill material is deposited in the remaining portions of the openings for S / D contacts of the IC structure 456. An IC structure 458 of Fig. Figure 4D illustrates an example result of process 308. As in Fig. 4D, an electrically conductive filler material 432 may fill the openings 426, which are lined on their sidewalls with the lining material 428 and lined on their bottoms with the interface material 430, thereby forming electrically conductive S / D contacts in the openings 426. The electrically conductive filler material 432 may include any electrically conductive materials that can serve as S / D contact material and may be deposited in process 308 using methods such as ALD, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), and / or physical vapor deposition (PVD) methods such as sputtering. Examples of the electrically conductive filler 432 include one or more metals or metal alloys, with metals such as molybdenum, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum. Together, processes 304, 306 and 308 can be referred to as “S / D contact metallization.”For a given opening 426, an S / D contact structure comprising the liner material 428 and the electrically conductive material 432 deposited thereon may be referred to as an “S / D contact.”

[0050] After metallization of the S / D contact, the method 300 may continue with a process 310 in which openings are formed to electrically connect some of the gate contacts to some of the S / D contacts. An IC structure 460 of Fig. 4E illustrates an example result of process 310. Fig. 4E illustrates that a sacrificial material 434 may be provided over the top of the IC structure 458, and openings 436 may be formed in the sacrificial material 434, individually labeled as openings 436-1 and 436-2. Opening 436-1 may be an opening exposing the gate electrode material 408 of the gate stack 406-1 and the electrically conductive fill material 432 deposited in the opening 426-1. Opening 436-2 may be an opening exposing the gate electrode material 408 of the gate stack 406-3 and the electrically conductive fill material 432 deposited in the opening 426-2. The sacrificial material 434 may include any suitable material that can be patterned to form the openings 436, e.g., a suitable insulating material. For example, in some embodiments, the sacrificial material 434 may comprise a carbon-based material, e.g.a carbon hard mask (CHM) or a high-temperature CHM (HTCHM). Any suitable patterning technique may be used in process 310 to define the positions and dimensions of the openings 436 in the sacrificial material 434, such as, but not limited to, patterning by photolithography or electron beam (E-beam). Once the positions and dimensions of the openings 436 have been patterned / defined, any suitable etching technique, e.g., a dry etch such as a radio frequency (RF) reactive ion etch (RIE) or an inductively coupled plasma (ICP) RIE, could be used to remove insulator materials in the openings 436. In some embodiments, the etching performed in process 310 may include an anisotropic etch using etchants, e.g., in the form of chemically active ionized gas (i.e., plasma), e.g., using bromine (Br) and chloride (Cl)-based chemistries.In some embodiments, the IC structure may be heated to elevated temperatures during the etching of process 310, e.g., to temperatures between about room temperature and 200 degrees Celsius, including all values ​​and ranges therein, to promote etch byproducts being sufficiently volatilized to be removed from the surface.

[0051] Since electrically conductive materials are typically etch-selective with respect to insulator materials, the etch used in process 310 to form openings 436 would remove the insulator materials within openings 436 (e.g., sacrificial material 434, insulator material 424, and gate spacers 422) without substantially etching the electrically conductive materials within openings 436 (e.g., gate electrode material 408 and electrically conductive fill material 432). As is known in the art, two materials are considered "etch-selective" (or having "sufficient etch selectivity") to each other if etchants used to etch one material do not substantially etch the other, thereby enabling selective etching of one material but not the other.

[0052] The method 300 may further include a method 312 in which the sacrificial material 434 is removed and the remaining openings 436 of the IC structure 460 are filled with an electrically conductive filler material. An IC structure 462 made of Fig. Figure 4F illustrates an example result of process 312. As in Fig. 4F, an electrically conductive fill material 438 may fill the openings 436. The electrically conductive fill material 438 may include any suitable electrically conductive material, such as any of the materials described with respect to the electrically conductive fill material 432, and may be deposited in process 312 using techniques such as ALD, CVD, PECVD, or PVD. Together, the processes 310 and 312 may be referred to as "patterning the gate contacts." For a given gate stack 406, a gate structure comprising the gate electrode material 408 and the electrically conductive material 438 deposited thereon may be referred to as a "gate contact." Patterning the gate contacts after the S / D contact metallization enables the use of the electrically conductive fill material 438 deposited in process 312 to provide electrical continuity between (e.g.,in contact with) portions of the gate electrode material 408 exposed through the openings 436 in process 310 and the electrically conductive fill material 432 of the S / D contacts formed in the openings 426 during the S / D contact metallization. Fig. 4F shows that a portion 440-1 of the electrically conductive fill material 438 may be in electrically conductive contact with the gate electrode material 408 of the gate stack 406-1 and the electrically conductive fill material 432 of the S / D contact formed in the opening 426-1, which were exposed through the opening 436-1 in process 310. Fig. 4F further shows that a portion 440-2 of the electrically conductive fill material 438 may be in electrically conductive contact with the gate electrode material 408 of the gate stack 406-3 and the electrically conductive fill material 432 of the S / D contact formed in the opening 426-2, which were exposed through the opening 436-2 in process 310.

[0053] The execution of the method 300 results in several characteristic features in the IC structure 462 that would not be seen in IC structures with SRAM that were not manufactured by patterning the gate contacts after S / D contact metallization as described herein. For example, one such feature is that the interface material 430 (e.g., titanium silicide) is retained in its entirety and has a thickness (a dimension measured perpendicular to the S / D region 414, e.g., along the Z-axis of the coordinate system 105) between about 2 nanometers and 10 nanometers, e.g., of about 5 nanometers. If manufacturing processes are used that do not pattern the gate contacts after S / D contact metallization, the interface material 430 may be partially or completely damaged. Another feature of the application of the method 300 is that interfaces 442 (in Fig. 4F individually labeled as interface 442-1 and 442-2) between the electrically conductive fill materials 438 over the gate electrode materials 408 and the electrically conductive fill material 432 of the S / D contacts. In Fig. 4F, interface 442-1 is an interface between the electrically conductive fill material 438 above the gate electrode material 408 of the gate stack 406-1 and the electrically conductive fill material 432 of the S / D contact in the opening 426-1, while interface 442-2 is an interface between the electrically conductive fill material 438 above the gate electrode material 408 of the gate stack 406-3 and the electrically conductive fill material 432 of the S / D contact in the opening 426-2. In some embodiments, interface 442 may include a seam and / or a grain boundary. In some embodiments, interface 442 may be associated with differences in contrast, average grain size, or average grain orientation on different sides of interface 442.Another feature of the application of method 300 is that the gate spacers 422 and the lining material 428 on the sidewalls of the S / D contacts closest to the corresponding interfaces 442 are substantially preserved. In manufacturing processes that do not perform patterning of the gate contacts after metallization of the S / D contact, the gate spacers 422 and / or the lining material 428 on the sidewalls of the S / D contacts may be partially or completely damaged. Another feature of the application of method 300 is that, due to the double metal filling and polishing of method 300, the height of the insulator material 424 and, accordingly, the height of the electrically conductive fill material 438 (dimensions measured along the Z-axis of coordinate system 105) may be smaller than the dimensions achievable with other manufacturing processes.

[0054] IC structures with SRAM, fabricated by patterning the gate contacts after S / D contact metallization as described herein (e.g., as described with respect to Fig. 1 to 4) may be used to implement suitable components. For example, in various embodiments, the IC structures described herein may be part of one or more of the following: a central processing unit, a memory device (e.g., a high-bandwidth memory device), a memory cell, logic circuitry, input / output circuitry, a field-programmable gate array (FPGA) component such as an FPGA transceiver or FPGA logic, power delivery circuitry, an amplifier (e.g., a III-V amplifier), Peripheral Component Interconnect Express (PCIE) circuitry, Double Data Rate (DDR) transmission circuitry, a computing device (e.g., a portable or handheld computing device), etc.

[0055] The IC structures disclosed herein, e.g., IC structure 462, may be incorporated into any suitable electronic component. Fig. 5 through 9 illustrate various examples of devices that may include one or more IC structures 462 disclosed herein.

[0056] Fig. 5 is a top view of a wafer 1500 and dies 1502 that may include one or more of the IC structures 462 according to any of the embodiments disclosed herein. The wafer 1500 may be formed from a semiconductor material and include one or more dies 1502 with IC structures formed on a surface of the wafer 1500. Each of the dies 1502 may be a repeating unit of a semiconductor product including any suitable IC. After fabrication of the semiconductor product is complete, the wafer 1500 may undergo a singulation process in which the dies 1502 are separated from one another to provide discrete "chips" of the semiconductor product. The die 1502 may include one or more IC structures 462 and / or supporting circuitry to carry electrical signals to the transistors of the one or more IC structures 462, as well as to any other IC components.In some embodiments, wafer 1500 or die 1502 may include a memory device (e.g., a random access memory (RAM) device such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive bridging RAM (CBRAM), etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple such devices may be combined on a single die 1502. For example, a memory array formed from multiple memory devices may be implemented on the same die 1502, as may a processing device (e.g., processing device 1802 of FIG. Fig. 9) or other logic configured to store information in the memory devices or to execute instructions stored in the memory array.

[0057] Fig. 6 is a side cross-sectional view of an IC device 1600 that may include one or more IC structures 100 according to any of the embodiments disclosed herein. One or more of the IC devices 1600 may be incorporated into one or more dies 1502 ( Fig. 5). The IC device 1600 may include a device region 1604 including one or more IC structures 462 disclosed herein. The device region 1604 may further include electrical contacts to the gate and S / D contacts of the transistors included in the device region 1604.

[0058] Electrical signals, such as power and / or input / output (I / O) signals, may be routed to and / or from the devices (e.g., the transistors) of the device region 1604 through one or more interconnect layers disposed on the device region 1604 (in Fig. 6 as interconnect layers 1606, 1608, and 1610). For example, electrically conductive features of device region 1604 (e.g., gate electrode materials 108, electrically conductive materials 432, and electrically conductive materials 438 of IC structures 462) may be electrically coupled to interconnect structures 1628 of interconnect layers 1606, 1608, and 1610. The one or more interconnect layers 1606, 1608, and 1610 may form a metallization stack (also referred to as an "ILD stack") 1619 of IC device 1600.

[0059] The interconnect structures 1628 may be arranged within the interconnect layers 1606, 1608, and 1610 to conduct electrical signals according to a variety of designs (in particular, the arrangement is not limited to the particular configuration of the interconnect structures 1628 shown in Fig. 6). Although a certain number of connection layers 1606, 1608 and 1610 in Fig. 6, embodiments of the present disclosure include IC structures with more or fewer interconnect layers than illustrated.

[0060] In some embodiments, the connection structures 1628 may comprise lines 1628a and / or vias 1628b filled with an electrically conductive material, such as a metal. The lines 1628a may be arranged to conduct electrical signals in a direction of a plane that is substantially parallel to a surface of the carrier 102 on which the device region 1604 is formed. For example, the lines 1628a may be viewed from the perspective of Fig. 6 conduct electrical signals in a direction into and out of the page. Vias 1628b may be arranged to conduct electrical signals in a direction of a plane substantially perpendicular to the surface of carrier 102 on which device region 1604 is formed. In some embodiments, vias 1628b may electrically couple lines 1628a of different interconnect layers 1606, 1608, and 1610.

[0061] The interconnect layers 1606, 1608 and 1610 may include a dielectric material 1626 disposed between the interconnect structures 1628, as shown in Fig. 6. In some embodiments, the dielectric material 1626 disposed between the interconnect structures 1628 in different ones of the interconnect layers 1606, 1608, and 1610 may have different compositions; in other embodiments, the composition of the dielectric material 1626 may be the same between different interconnect layers 1606, 1608, and 1610.

[0062] A first interconnect layer 1606 may be formed above the device region 1604. In some embodiments, the first interconnect layer 1606 may include lines 1628a and / or vias 1628b, as shown. The lines 1628a of the first interconnect layer 1606 may be coupled to contacts (e.g., contacts to the S / D regions 114 of the IC structures 100) of the device region 1604.

[0063] A second interconnect layer 1608 may be formed above the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the lines 1628a of the second interconnect layer 1608 to the lines 1628a of the first interconnect layer 1606. Although the lines 1628a and the vias 1628b are structurally delineated with a line in each interconnect layer (e.g., in the second interconnect layer 1608) for clarity, in some embodiments the lines 1628a and the vias 1628b may be structurally and / or materially contiguous (e.g., filled simultaneously during a dual damascene process).

[0064] A third interconnect layer 1610 (and additional interconnect layers, if desired) may subsequently be formed on the second interconnect layer 1608 according to similar techniques and configurations as described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers located "higher up" in the metallization stack 1619 in the IC device 1600 (i.e., farther away from the device region 1604) may be thicker.

[0065] The IC device 1600 may include a solder stop material 1634 (e.g., polyimide or a similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606, 1608, and 1610. In Fig. 6, the conductive contacts 1636 are illustrated as taking the form of bond pads. The conductive contacts 1636 may be electrically coupled to the interconnect structures 1628 and configured to conduct the electrical signals of the transistor(s) of the device region 1604 to other external devices. For example, solder connections may be formed on one or more conductive contacts 1636 to mechanically and / or electrically couple a chip, including the IC device 1600, to another component (e.g., a circuit board). The IC device 1600 may include additional or alternative structures to conduct the electrical signals from the interconnect layers 1606, 1608, and 1610; for example, the conductive contacts 1636 may include other analog features (e.g., posts) that conduct the electrical signals to external components.

[0066] Fig. Figure 7 is a side cross-sectional view of an exemplary IC package 1650 that may include one or more IC structures 462 according to any of the embodiments described herein. In some embodiments, the IC package 1650 may be a system-in-package (SIP).

[0067] The package substrate 1652 may be formed from a dielectric material (e.g., a ceramic, a build-up film, an epoxy film with filler particles therein, glass, an organic material, an inorganic material, combinations of organic and inorganic materials, embedded parts formed from different materials, etc.) and may have conductive paths extending through the dielectric material between the surface 1672 and the surface 1674 or between different locations on the surface 1672 and / or between different locations on the surface 1674. These conductive paths may take the form of any of the conductive paths described above with reference to Fig. 6 discussed compounds 1628.

[0068] The package substrate 1652 may include conductive contacts 1663 coupled through the package substrate 1652 to conductive paths (not shown), thereby enabling circuitry within the die 1656 and / or the interposer 1657 to be electrically coupled to various conductive contacts 1664 (or to other devices included in the package substrate 1652 that are not shown).

[0069] The IC package 1650 may include an interposer 1657 coupled to the package substrate 1652 via conductive contacts 1661 of the interposer 1657, first-level connections 1665, and the conductive contacts 1663 of the package substrate 1652. In the embodiments shown in Fig. The first-level connections 1665 illustrated in Figure 7 are solder bumps; however, any other suitable first-level connections 1665 may be used. In some embodiments, an interposer 1657 may not be included in the IC package 1650; instead, the dies 1656 may be directly coupled to the conductive contacts 1663 at the surface 1672 by first-level connections 1665. More generally, one or more dies 1656 may be coupled to the package substrate 1652 via any suitable structure (e.g., a silicon bridge, an organic bridge, one or more waveguides, one or more interposers, wire bonds, etc.).

[0070] The IC package 1650 may include one or more dies 1656 coupled to the interposer 1657 via conductive contacts 1654 of the dies 1656, first-level interconnects 1658, and conductive contacts 1660 of the interposer 1657. The conductive contacts 1660 may be coupled through the interposer 1657 to conductive paths (not shown), thereby enabling circuitry within the dies 1656 to be electrically coupled to various of the conductive contacts 1661 (or to other devices included in the interposer 1657 not shown). Fig. The first-level connections 1658 illustrated in Figure 7 are solder bumps; however, any other suitable first-level connections 1658 may be used. As used herein, a "conductive contact" may refer to a portion of a conductive material (e.g., metal) that serves as an interface between different components; conductive contacts may be recessed into, flush with, or extend from a surface of a component and may take any suitable form (e.g., a conductive pad or a socket).

[0071] In some embodiments, an underfill material 1666 may be disposed between the package substrate 1652 and the interposer 1657 around the first-level interconnects 1665, and a potting compound 1668 may be disposed around the dies 1656 and the interposer 1657 and in contact with the package substrate 1652. In some embodiments, the underfill material 1666 may be the same as the potting compound 1668. Example materials that may be used as the underfill material 1666 and the potting compound 1668 are suitable epoxy potting materials. Second-level interconnects 1670 may be coupled to the conductive contacts 1664. In the embodiments shown in Fig. The second-level connections 1670 illustrated in Figure 7 are solder balls (e.g., for a ball grid array arrangement); however, any suitable second-level connections 1670 may be used (e.g., pins in a pin grid array arrangement or contact pads in a contact pad grid array arrangement). The second-level connections 1670 may be used to couple the IC package 1650 to another component, such as a printed circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and described below with reference to Fig. 8 is discussed.

[0072] The dies 1656 may take the form of any of the embodiments of the die 1502 discussed herein (e.g., include any of the embodiments of the IC device 1600). In embodiments where the IC package 1650 includes multiple dies 1656, the IC package 1650 may be referred to as a multi-chip package (MCP). The dies 1656 may include circuitry to perform any desired functionality. For example, one or more of the dies 1656 may be logic dies (e.g., silicon-based dies) and one or more of the dies 1656 may be memory dies (e.g., high-bandwidth memory).

[0073] Although the Fig. 7 is a flip-chip package, other package architectures are also usable. For example, the IC package 1650 may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 1650 may be a wafer-level chip scale (WLCSP) package or a panel fanout (FO) package. Although the IC package 1650 is made of Fig. 7 illustrates two dies 1656, an IC package 1650 may include any desired number of dies 1656. An IC package 1650 may include additional passive components, such as surface-mount resistors, capacitors, and inductors, disposed on the first surface 1672 or the second surface 1674 of the package substrate 1652 or on a surface of the interposer 1657. More generally, an IC package 1650 may include any other active or passive components known in the art.

[0074] Fig. 8 is a side cross-sectional view of an IC device assembly 1700, which may include one or more IC packages or other electronic components (e.g., a die) having one or more IC structures 100 according to any of the embodiments disclosed herein. The IC device assembly 1700 includes a number of components disposed on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes components disposed on a first surface 1740 of the circuit board 1702 and an opposite second surface 1742 of the circuit board 1702; generally, components may be disposed on one or both surfaces 1740 and 1742. Each of the IC packages discussed below with reference to the IC device assembly 1700 may take the form of one of the IC packages discussed above with reference to Fig. 7 (e.g., may include one or more IC structures 100).

[0075] In some embodiments, circuit board 1702 may be a PCB that includes multiple metal layers separated by layers of dielectric material and connected by electrically conductive vias. One or more of the metal layers may be formed into a desired circuit pattern to conduct electrical signals (optionally in conjunction with other metal layers) between components coupled to circuit board 1702. In other embodiments, circuit board 1702 may be a non-PCB substrate.

[0076] The Fig. The IC device assembly 1700 illustrated in Figure 8 includes a package-on-interposer structure 1736 coupled to the first surface 1740 of the circuit board 1702 by coupling components 1716. The coupling components 1716 may electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702 and may include solder balls (as shown in Fig. 8), plugs and sockets of a socket, an adhesive, an underfill material and / or other suitable electrical and / or mechanical coupling structure.

[0077] The package-on-interposer structure 1736 may include an IC package 1720 coupled to a package interposer 1704 by coupling components 1718. The coupling components 1718 may take any form suitable for the application, such as the forms discussed above with reference to the coupling components 1716. Although in Fig. 8, a single IC package 1720 is shown, multiple IC packages may be coupled to the package interposer 1704; indeed, additional interposers may be coupled to the package interposer 1704. The package interposer 1704 may provide an intermediate substrate that serves to form a bridge between the circuit board 1702 and the IC package 1720. The IC package 1720 may, for example, contain a die (the die 1502 of Fig. 5), an IC device (e.g., the IC device 1600 of Fig. 6) or other suitable component. In general, the package interposer 1704 may spread an interconnect to a wider pitch or reroute an interconnect to a different interconnect. For example, the package interposer 1704 may couple the IC package 1720 (e.g., a die) to a set of conductive BGA contacts of the coupling components 1716 for coupling to the circuit board 1702. In the Fig. In the embodiment illustrated in Figure 8, the IC package 1720 and the circuit board 1702 are mounted on opposite sides of the package interposer 1704; in other embodiments, the IC package 1720 and the circuit board 1702 may be attached to a same side of the package interposer 1704. In some embodiments, three or more components may be interconnected via the package interposer 1704.

[0078] In some embodiments, the package interposer 1704 may be formed as a circuit board, including multiple metal layers separated by layers of dielectric material and connected by electrically conductive vias. In some embodiments, the package interposer 1704 may be formed from an epoxy resin, a glass-fiber reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymeric material such as polyimide. In some embodiments, the package interposer 1704 may be formed from alternative rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials.The package interposer 1704 may include metal lines 1710 and vias 1708, including, but not limited to, through-silicon vias (TSVs) 1706. The package interposer 1704 may also include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package interposer 1704.The package-on-interposer structure 1736 may take the form of any package-on-interposer structures known in the art.

[0079] The IC device assembly 1700 may include an IC package 1724 coupled to the first surface 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.

[0080] The Fig. The IC device assembly 1700 illustrated in Figure 8 includes a package-on-package structure 1734 coupled to the second surface 1742 of the circuit board 1702 by coupling components 1728. The package-on-package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together by coupling components 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any of the above-described embodiments of the coupling components 1716, and the IC packages 1726 and 1732 may take the form of any of the above-described embodiments of the IC device 1720. The package-on-package structure 1734 may be configured according to any of the package-on-package structures known in the art.

[0081] Fig. 9 is a block diagram of an exemplary electrical device 1800 that may include one or more IC structures 462, according to any of the embodiments disclosed herein. For example, any suitable components of the electrical device 1800 may include one or more of the IC device assemblies 1700, IC packages 1650, IC structures 1600, or dies 1502 disclosed herein. A number of components are shown in Fig. 9 as included in electrical device 1800; however, one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in electrical device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single SoC die.

[0082] Furthermore, in various embodiments, the electrical device 1800 may include one or more of the Fig.9, but rather, the electrical device 1800 may include interface circuitry for coupling to the one or more components. For example, the electrical device 1800 may not include a display device 1806, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 1806 may be coupled. In another set of examples, the electrical device 1800 may not include an audio input device 1824 or audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which an audio input device 1824 or an audio output device 1808 may be coupled.

[0083] The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. The processing unit 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptography algorithms within hardware), server processors, or any other suitable processing devices.The electrical device 1800 may include a memory 1804, which may itself include one or more storage devices such as volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard disk. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include, for example, embedded DRAM (eDRAM) or spin-transfer magnetic torque RAM (STT-MRAM).

[0084] In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured to manage wireless communication for transmitting data to and from the electrical device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data through modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated devices do not include wires, although they may not be present in some embodiments.

[0085] The 1812 communications chip can implement a range of wireless standards or protocols, including but not limited to IEEE (Institute for Electrical and Electronic Engineers) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with all amendments, updates, and / or revisions (e.g., Advanced LTE project, Ultra-Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, a certification mark for products that pass conformance and interoperability tests to IEEE 802.16 standards.The communication chip 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols referred to as 3G, 4G, 5G, and beyond. The communication chip 1812 may operate in accordance with other wireless protocols in other embodiments.The electrical device 1800 may include an antenna 1822 to enable wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0086] In some embodiments, the communication chip 1812 may manage wired communication such as electrical, optical, or other suitable communication protocols (e.g., Ethernet). As mentioned above, the communication chip 1812 may include multiple communication chips. For example, a first communication chip 1812 may be dedicated to shorter-range wireless communication such as Wi-Fi or Bluetooth, and a second communication chip 1812 may be dedicated to longer-range wireless communication such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1812 may be dedicated to wireless communication, and a second communication chip 1812 may be dedicated to wired communication.

[0087] The electrical device 1800 may include a battery / power circuitry 1814. The battery / power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the electrical device 1800 to a power source (e.g., AC power supply) separate from the electrical device 1800.

[0088] The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry as discussed above). The display device 1806 may include any visual display, such as a head-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0089] The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry as discussed above). The audio output device 1808 may include any device that generates an acoustic signal, such as a speaker, headphones, or earphones.

[0090] The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry as discussed above). The audio input device 1824 may include any device that generates a signal representative of sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a musical instrument digital interface (MIDI)).

[0091] The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry as discussed above). The GPS device 1818 may communicate with a satellite-based system and receive a position of the electrical device 1800, as known in the art.

[0092] The electrical device 1800 may include another output device 1810 (or corresponding interface circuitry as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0093] The electrical device 1800 may include another input device 1820 (or corresponding interface circuitry as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0094] Electrical device 1800 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cellular phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, electrical device 1800 may be another electronic device that processes data.

[0095] The following paragraphs provide various examples of the embodiments disclosed herein.

[0096] Example 1 provides an IC structure comprising: a transistor having a channel region and a region of doped semiconductor material, wherein the region is either a source region or a drain region of the transistor; a contact structure coupled to the region, wherein the contact structure includes a first electrically conductive material (e.g., the electrically conductive material 432; such a contact structure may be referred to as an “S / D contact” of the transistor); and a gate structure coupled to the channel region, wherein the gate structure includes a gate electrode material (e.g., the gate electrode material 408) and a second electrically conductive material (e.g.,the electrically conductive material 438); such a gate structure may be referred to as a "gate contact" of the transistor), wherein a portion of the second electrically conductive material is in electrically conductive contact with a portion of the first electrically conductive material, and wherein the IC structure includes a seam or grain boundary at an interface between the portion of the second electrically conductive material and the portion of the first electrically conductive material.

[0097] Example 2 provides the IC structure according to Example 1, wherein the first electrically conductive material and the second electrically conductive material have different material compositions.

[0098] Example 3 illustrates the IC structure according to any one of Examples 1 to 2, wherein an average grain size in the part of the first electrically conductive material differs from an average grain size in the part of the second electrically conductive material.

[0099] Example 4 illustrates the IC structure according to any one of Examples 1 to 3, wherein an average grain orientation in the part of the first electrically conductive material differs from an average grain orientation in the part of the second electrically conductive material.

[0100] Example 5 illustrates the IC structure according to any one of Examples 1 to 4 and further comprises a liner material including titanium below the interface, wherein a sidewall of the liner material is substantially aligned with the interface.

[0101] Example 6 provides the IC structure of Example 5 further including a gate spacer below the interface, wherein a sidewall of the gate spacer is substantially aligned with the interface.

[0102] Example 7 provides the IC structure according to Example 6, wherein the sidewall of the gate spacer is in contact with the sidewall of the liner material.

[0103] Example 8 provides the IC structure according to any one of Examples 1 to 4 and further comprises a gate spacer below the interface, wherein a sidewall of the gate spacer is substantially aligned with the interface.

[0104] Example 9 provides the IC structure according to any one of Examples 1 to 8 and further comprises an interface material between the first electrically conductive material and the region in which the interface material comprises titanium and silicon.

[0105] Example 10 illustrates the IC structure of Example 9, wherein a thickness of the interface material is at least about 5 nanometers.

[0106] Example 11 includes an IC structure comprising: a transistor having a source or drain (S / D) region and a gate electrode material; an S / D contact in electrical contact with the S / D region, in which the S / D contact comprises a first electrically conductive material (e.g., electrically conductive material 432); and a gate contact in electrical contact with the gate electrode material, in which the gate contact comprises a second electrically conductive material (e.g., electrically conductive material 438); wherein a portion of the second electrically conductive material is in electrical contact with a portion of the first electrically conductive material, and wherein an average grain size in the portion of the first electrically conductive material differs from an average grain size in the portion of the second electrically conductive material.As used herein, A in electrical contact with B refers to 1) A in physical contact with B, 2) A in direct contact with B, 3) A forming an electrically conductive interface with B, or 4) A being electrically continuous with B.

[0107] Example 12 provides the IC structure of Example 11, wherein the first electrically conductive material is different from the second electrically conductive material.

[0108] Example 13 illustrates the IC structure according to any one of Examples 11 to 12, wherein an average grain orientation in the portion of the first electrically conductive material differs from an average grain orientation in the portion of the second electrically conductive material.

[0109] Example 14 illustrates the IC structure of any one of Examples 11 to 13, further including a gate spacer between the gate electrode material and the first electrically conductive material.

[0110] Example 15 provides the IC structure of Example 14, wherein a first portion of the second electrically conductive material overlies and is in electrical contact with the gate electrode material and a second portion of the second electrically conductive material overlies the gate spacer.

[0111] Example 16 provides the IC structure according to any one of Examples 11 to 15, further including a grain boundary between the portion of the first electrically conductive material and the portion of the second electrically conductive material.

[0112] Example 17 provides the IC structure of any one of Examples 11 to 16 and further comprises an interface material between the first electrically conductive material and the S / D region, the interface material comprising titanium and silicon.

[0113] Example 18 illustrates the IC structure of Example 17, wherein a thickness of the interface material is at least about 5 nanometers.

[0114] Example 19 provides a method of manufacturing an IC structure, the method comprising: providing a transistor having a gate electrode material and a region comprising a doped semiconductor material, wherein the region is either a source or a drain region of the transistor; providing a contact structure coupled to the region, the contact structure including a first electrically conductive material; providing a contact structure coupled to the region, the contact structure including a second electrically conductive material (e.g., the electrically conductive material 342); such a contact structure may be referred to as an “S / D contact” of the transistor); and providing a gate structure coupled to the gate electrode material, the gate structure including a second electrically conductive material, the gate structure being provided after providing the contact structure.

[0115] Example 20 provides the method of Example 19, wherein a portion of the second electrically conductive material is in electrically conductive contact with a portion of the first electrically conductive material, and wherein the IC structure includes a seam or grain boundary at an interface between the portion of the second electrically conductive material and the portion of the first electrically conductive material.

[0116] Example 21 provides the method of any one of Examples 19 to 20, wherein the IC structure is an IC structure according to any one of the preceding Examples.

[0117] Example 22 provides an IC package including an IC die having an IC structure according to any one of Examples 1 to 18 and another IC component coupled to the IC die.

[0118] Example 23 provides the IC package of Example 22, wherein the further IC component includes a package substrate.

[0119] Example 24 provides the IC package of Example 22, wherein the further IC component includes an interposer.

[0120] Example 25 provides the IC package of Example 22, wherein the further IC component includes another IC die.

[0121] Example 26 provides a computing device including a carrier substrate and an IC structure coupled to the carrier substrate, wherein the IC structure is an IC structure according to any one of Examples 1 to 18 or the IC structure according to any one of Examples 22 to 25 is included in the IC package.

[0122] Example 27 provides the computing device of Example 26, wherein the computing device is a portable or handheld computing device.

[0123] Example 28 provides the computing device of Examples 26 or 27, wherein the computing device further includes one or more communication chips.

[0124] Example 29 provides the computing device of any one of Examples 26 to 28, wherein the computing device further includes an antenna.

[0125] Example 30 provides the computing device of any one of Examples 26 to 29, wherein the support substrate is a motherboard.

[0126] Example 31 provides the IC structure of any one of Examples 1 to 18, wherein the IC structure includes or is a part of a central processing unit.

[0127] Example 32 provides the IC structure of any one of Examples 1 to 31, wherein the IC structure includes or is a part of a memory device, e.g., a high bandwidth memory device.

[0128] Example 33 provides the IC structure of any one of Examples 1 to 32, wherein the IC structure includes or is a part of a logic circuit.

[0129] Example 34 provides the IC structure of any one of Examples 1 to 33, wherein the IC structure includes or is a part of input / output circuitry.

[0130] Example 35 provides the IC structure of any one of Examples 1 to 34, wherein the IC structure includes or is a part of an FPGA transceiver.

[0131] Example 36 provides the IC structure of any one of Examples 1 to 35, wherein the IC structure includes or is a part of FPGA logic.

[0132] Example 37 provides the IC structure of any one of Examples 1 to 36, wherein the IC structure includes or is a part of power delivery circuitry.

[0133] Example 38 provides the IC structure of any one of Examples 1 to 37, wherein the IC structure includes or is a part of a III-V amplifier.

[0134] Example 39 provides the IC structure of any one of Examples 1 to 38, wherein the IC structure includes or is a part of PCIE circuitry or DDR transfer circuitry.

[0135] The foregoing description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of the disclosure and examples thereof have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as one skilled in the art will recognize. These modifications may be made to the disclosure in light of the foregoing detailed description.

Claims

[1] Integrated circuit (IC) structure comprising: a transistor comprising a channel region and a region comprising a doped semiconductor material, wherein the region is either a source region or a drain region of the transistor; a contact structure coupled to the region, the contact structure comprising a first electrically conductive material; and a gate structure coupled to the channel region, the gate structure including a gate electrode material and a second electrically conductive material; wherein a portion of the second electrically conductive material is in electrically conductive contact with a portion of the first electrically conductive material, and wherein the IC structure has a seam or grain boundary at an interface between the portion of the second electrically conductive material and the portion of the first electrically conductive material. [2] The IC structure of claim 1, wherein the first electrically conductive material and the second electrically conductive material have different material compositions. [3] The IC structure according to any one of claims 1 to 2, wherein an average grain size in the part of the first electrically conductive material differs from an average grain size in the part of the second electrically conductive material. [4] The IC structure according to any one of claims 1 to 3, wherein an average grain orientation in the part of the first electrically conductive material differs from an average grain orientation in the part of the second electrically conductive material. [5] The IC structure of any one of claims 1 to 4, further comprising a liner material comprising titanium below the interface, wherein a sidewall of the liner material is substantially aligned with the interface. [6] The IC structure of claim 5, further comprising a gate spacer below the interface, wherein a sidewall of the gate spacer is substantially aligned with the interface. [7] The IC structure of claim 6, wherein the sidewall of the gate spacer is in contact with the sidewall of the liner material. [8] The IC structure of any one of claims 1 to 4, further comprising a gate spacer below the interface, wherein a sidewall of the gate spacer is substantially aligned with the interface. [9] The IC structure of any one of claims 1 to 8, further comprising an interface material between the first electrically conductive material and the region, the interface material comprising titanium and silicon. [10] The IC structure of claim 9, wherein a thickness of the interface material is at least about 5 nanometers. [11] Integrated circuit (IC) structure comprising: a transistor comprising a source or drain region (S / D) and a gate electrode material; an S / D contact in electrical contact with the S / D region, the S / D contact including a first electrically conductive material; and a gate contact in electrical contact with the gate electrode material, the gate contact including a second electrically conductive material; wherein a portion of the second electrically conductive material is in electrical contact with a portion of the first electrically conductive material, and wherein an average grain size in the portion of the first electrically conductive material differs from an average grain size in the portion of the second electrically conductive material. [12] The IC structure of claim 11, wherein the first electrically conductive material is different from the second electrically conductive material. [13] The IC structure according to any one of claims 11 to 12, wherein an average grain orientation in the part of the first electrically conductive material differs from an average grain orientation in the part of the second electrically conductive material. [14] The IC structure of any one of claims 11 to 13, further comprising a gate spacer between the gate electrode material and the first electrically conductive material. [15] The IC structure of claim 14, wherein a first portion of the second electrically conductive material is located over and in electrical contact with the gate electrode material and a second portion of the second electrically conductive material is located over the gate spacer. [16] The IC structure of any one of claims 11 to 15, further comprising a grain boundary between the portion of the first electrically conductive material and the portion of the second electrically conductive material. [17] The IC structure of any one of claims 11 to 16, further comprising an interface material between the first electrically conductive material and the S / D region, the interface material including titanium and silicon. [18] The IC structure of claim 17, wherein a thickness of the interface material is at least about 5 nanometers. [19] A method of manufacturing a structure of an integrated circuit (IC) structure, comprising: Providing a transistor comprising a gate electrode material and a region comprising a doped semiconductor material, wherein the region is either a source region or a drain region of the transistor; Providing a contact structure coupled to the region, the contact structure comprising a first electrically conductive material; Providing a contact structure coupled to the region, the contact structure comprising a second electrically conductive material; and Providing a gate structure coupled to the gate electrode material, wherein the gate structure includes a second electrically conductive material, wherein the gate structure is provided after providing the contact structure. [20] The method of claim 19, wherein a portion of the second electrically conductive material is in electrically conductive contact with a portion of the first electrically conductive material, and wherein the IC structure includes a seam or grain boundary at an interface between the portion of the second electrically conductive material and the portion of the first electrically conductive material.

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