Semiconductor device with isolated component regions and manufacturing method

Abstract

A semiconductor device is disclosed. The semiconductor device comprises a semiconductor layer (100) having a first surface (101); a buried region (2) of a first doping type formed in the semiconductor layer (100) at a distance from the first surface (101); an insulating grid (3) extending from the first surface (101) to the buried region (2) and having a first region of the first doping type; and device regions (4) of the second doping type adjacent to the buried region (2) and insulated from one another by the insulating grid (3).

Description

[0001] This disclosure generally relates to a semiconductor arrangement with isolated component regions.

[0002] Electronic circuits can contain multiple semiconductor devices. In many applications, it is desirable to implement several semiconductor devices of an electronic circuit in a single semiconductor body (die) to save space and costs. The individual semiconductor devices integrated into a semiconductor body can have different voltage ratings. Furthermore, the individual semiconductor devices can belong to different voltage domains of the electronic circuit. Each "voltage domain" is defined by the electrical potential to which the voltages occurring in the respective domain are referenced. The individual semiconductor devices can be interconnected by electrically conductive traces formed across the semiconductor body.

[0003] To prevent unintended current flow between individual components within the semiconductor body, each component is typically located in a component region that is isolated from other component regions by junction insulation. Each component region usually contains its own junction insulation.

[0004] US Patent 2008 / 0048287A1 describes a semiconductor array with a p-doped semiconductor substrate in which multiple semiconductor structures are arranged, each featuring an n-doped buried region and multiple trenches. The trenches extend from a surface into the semiconductor substrate, are filled with a dielectric, and are spaced apart from the buried region. Along the trenches and between the trenches and the buried region, n-doped regions extend from the surface of the semiconductor substrate to the buried region.

[0005] US Patent 6,410,965 B1 discloses a semiconductor device comprising a semiconductor substrate of a first doping type and at least one annular unit formed in the semiconductor substrate. The annular unit includes a well of a second doping type, a doped region of the first doping type, a contact ring of the second doping type, and a doped ring of the second doping type. The well is formed in the semiconductor substrate, and the doped region is formed within the well. The contact ring is formed within the well and surrounds the doped region. The doped ring is formed in the semiconductor substrate and surrounds the well.

[0006] US patent 2001 / 0019138A1 discloses a lateral thyristor structure for protection against electrostatic discharges in monolithic integrated circuits using CMOS technology, which exhibits a significantly lower trigger voltage compared to conventional thyristor structures.

[0007] Each junction insulation layer consumes space within the semiconductor body. There is a need for a space-saving semiconductor array with isolated component regions and a method for fabricating such an array.

[0008] One embodiment of the invention relates to a semiconductor arrangement according to claim 1. Another embodiment relates to a manufacturing method according to claim 9.

[0009] Examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so only aspects necessary for understanding these principles are shown. The drawings are not to scale. In the drawings, the same reference symbols denote the same features. Fig. Figure 1 illustrates a vertical cross-sectional view of a semiconductor arrangement, which includes a buried region formed in a semiconductor layer and an insulating grid adjacent to the buried region and defining component regions in the semiconductor layer; Fig. 2-5 show top views of semiconductor arrangements of the in Fig. 1 of the type shown according to various examples; Fig. Figures 6A-6B illustrate an example of a procedure for creating the buried area; Fig. Figures 7A-7C illustrate another example of a procedure for producing the buried area; Fig. Figures 8A-8C illustrate an example of a method for manufacturing the insulating grid; Fig. Figures 9A-9B illustrate optional process steps in the procedure according to the Fig. 8A-8C; Fig. Figures 10A-10B illustrate a T-shaped section of the insulating grid according to an example; Fig. Figures 11A-11C illustrate vertical cross-sectional views of the T-shaped section according to Fig. 10A at various positions; Fig. Figures 12-13 illustrate a transistor component according to an example integrated in a component domain; Fig. 14 illustrates a modification of the in Fig. 13 transistor component shown; Fig. Figure 15 shows a top view of a component area in which several transistor components are integrated; Fig. 16 illustrates a modification of the one in the Fig. 12-13 of the transistor component shown; Fig. Figures 17-18 illustrate a transistor device integrated in a component area, according to another example; and Fig. 19 illustrates a modification of the one in the Fig. 17-18 transistor component shown.

[0010] The following detailed description refers to the accompanying drawings. The drawings form part of the description and show examples of how the invention can be used and implemented. It is understood that the features of the various embodiments described herein can be combined unless expressly stated otherwise.

[0011] Fig. Figure 1 schematically illustrates a vertical cross-sectional view of a semiconductor arrangement according to an example. Fig. Figures 2-5 illustrate top views of semiconductor arrangements of the in Fig. 1 of the type shown according to various examples.

[0012] Referring to the Fig. The semiconductor arrangement comprises a semiconductor layer 100 with a first surface 101, a buried region 2 of a first doping type formed in the semiconductor layer 100 spaced apart from the first surface 101, an insulating grid extending from the first surface 101 to the buried region 2, and component regions 4. The component regions 4 are of a second doping type complementary to the first doping type, border the buried region 2, and are isolated from each other by the insulating grid 3.

[0013] Semiconductor layer 100, for example, is a monocrystalline semiconductor layer. According to one example, the semiconductor material of semiconductor layer 100 is silicon (Si) or silicon carbide (SiC).

[0014] The insulating lattice 3 provides barrier insulation between the device regions 4 of the second doping type. For this purpose, the insulating lattice 3 includes a doped region of a first doping type complementary to the second doping type. Thus, a PN junction is formed between the insulating lattice 3 and each of the device regions 4, such that two device regions 4 are barrier-insulated from each other by two PN junctions formed by a section of the insulating lattice 3 located between the two device regions and by a respective section of each of the two device regions 4. The PN junctions formed between the insulating lattice 3 and each of the device regions 4 are shown in the Fig. Examples 1-3 are represented by diodes. To simplify the representation, the diodes are shown in the Fig. 4 and Fig. 5 not shown. The diodes shown represent a scenario in which the doped region of the insulating grid 3 is an N-type region and the device regions 4 are P-type regions. Thus, in this example, the first doping type is an N-type and the second doping type is a P-type.

[0015] However, this is just one example. It is also possible to implement the component regions as N-type regions and the doped region of the insulating lattice 3 as a P-type region.

[0016] According to one example, the semiconductor layer 100 has a base doping of the second doping type, wherein the base doping of the semiconductor layer 100 defines a base doping of the second doping type of the device regions 4. According to one example, a doping concentration of the base doping of the semiconductor layer 100 is selected from a range between 1E13 cm⁻¹. -3 and 1E17 cm -3According to one example, the base doping of semiconductor layer 100 is at least approximately homogeneous. According to another example, the base doping of semiconductor layer 100 varies in a vertical direction, which is a direction perpendicular to the first surface 101.

[0017] A maximum of the doping concentration of the doped region of the first doping type of the insulating lattice 3 is higher than 1E18 cm⁻¹ -3 , higher than 1E19 cm -3 or even higher than 1E20 cm -3 As explained below, the doped regions of the insulating lattice 3 can be produced by a diffusion process. In this case, the doping concentration of the doped region of the insulating lattice 3 can vary and can decrease, in particular, towards the regions with the base doping of the semiconductor layer 100.

[0018] According to one example, the insulating grid 3 comprises an insulating ring 31 and at least one insulating bridge 32 formed within the insulating ring 31. Referring to the Fig. In the lateral directions of semiconductor layer 100, the insulating ring forms a closed loop. "Lateral directions" of semiconductor layer 100 are directions that are essentially parallel to the first surface 101. The at least one insulating bridge 32 adjoins the insulating ring and, together with the insulating ring 31, defines the device regions 4. The number and lengths of the individual insulating bridges 32 are arbitrary. Some examples of insulating bridges 32 and the resulting device regions 4 are shown in the Fig. 2-5 are shown and explained further below.

[0019] The buried region 2, together with the insulating ring 31 extending from the first surface 101 to the buried region 2, encloses the component regions 4 within the semiconductor layer 100. A section of the semiconductor layer 100 bordering the insulating ring 31 and the buried region 2 from outside the arrangement containing the component regions 4 is referred to as the outer region 140 of the semiconductor layer 100. At least the sections of the outer region 140 bordering the insulating ring 31 and the buried region 2 may have the base doping of the second doping type of the semiconductor layer 100. The region of the semiconductor layer 100 enclosed by the insulating rings 31 and the buried region 2 is referred to below as the "inner region" 130.

[0020] The insulating ring 31 and the buried region 2 provide barrier insulation between the component regions 4 and the outer region. That is, a PN junction is formed between the outer region 140 and the insulating ring 31, and between the outer region 140 and the buried region 2. Furthermore, a PN junction is formed between each component region 4 and the buried region 2, and a PN junction is formed between the insulating grid 31 and each of the component regions 4 adjacent to the insulating ring 31.

[0021] Each of the component areas (4) can integrate an electronic component, such as a transistor, resistor, or capacitor. Such electronic components are found in the Fig. 1-5 not shown. Examples of electronic components that can be integrated in the individual component areas 4 are explained below.

[0022] According to one example, semiconductor layer 100 is a semiconductor substrate of the second doping type. According to another example, which is in Fig. As shown in dashed lines in Figure 1, the semiconductor layer 100 is an epitaxial layer grown on a substrate 200. The substrate 200 can have either the first or the second doping type. According to one example, the epitaxial layer forming the semiconductor layer 100 contains several sublayers stacked on top of each other. According to another example, fabricating the semiconductor layer 100 and the buried region 2 involves fabricating a first sublayer of the epitaxial layer 100, implanting dopant atoms into the first sublayer to fabricate the buried region 2, and fabricating at least one further sublayer on top of the first sublayer after implanting the dopant atoms.

[0023] As explained above, the insulating lattice 3 includes at least one insulating bridge 32. Thus, the insulating lattice 3 can include exactly one insulating bridge 32 or it can include several insulating bridges 32. Some examples of implementing the insulating lattice 3 are given in the Fig. 2-5 are shown and are explained below.

[0024] In the Fig. In the example shown, the insulating grid 3 comprises exactly one insulating bridge 32. The insulating bridge 32 divides the area of ​​the semiconductor layer 100 within the insulating ring 31 into two component regions 4, a first component region 421 and a second component region 422. For example only, the first and second component regions 421 and 422 have, according to Fig. Two different sizes. It is also possible to implement component areas 421 and 422 in such a way that they have essentially identical sizes.

[0025] In the Fig. In the example shown, the insulating grid 3 comprises three insulating bridges. A first insulating bridge divides the inner region 130 into two sections. A second insulating bridge divides one of the two sections defined by the first insulating bridge into first and second component regions 431, 432, and a third insulating bridge divides the other of the two sections defined by the first insulating bridge into third and fourth component regions 433, 434.

[0026] In the Fig. In the example shown in Figure 4, the insulating grid 3 comprises a first insulating bridge that divides the inner region into two sections, one of which forms a first component region 441. The other of these sections is divided into two subsections. One of these subsections forms a second component region 442. The other of these subsections is divided by a third insulating bridge into a third component region 443 and a fourth component region 444.

[0027] In the in the Fig. In the examples shown in Figures 2-4, each of the component areas 4 is partially defined by the insulating ring 31. That is, each of the component areas 4 borders the insulating ring 31. As can be seen from Fig. As can be seen in section 5, this is just one example.

[0028] The semiconductor arrangement according to Fig. 5 contains a component area 454, which is defined only by insulating bridges and is surrounded by further component areas 451, 452, 453, 455, 456 and 457.

[0029] In the in the Fig. In examples 2-4, the component areas are essentially rectangular and each contains four outer corners, each bordering two sides of the respective component area. However, this is just one example. It is also possible to implement one or more component areas as, for example, L-shaped or T-shaped areas.

[0030] An example of an L-shaped component area 455 is in Fig. 5 shown. The L-shaped component area 455 contains five outer corners and one inner corner. A T-shaped component area, not shown, can contain two inner corners of the L-shaped component area. Fig. The 5 types shown are included. In principle, 32 component areas with any shape, that is, with any number of inner and outer corners, can be produced using bridge areas.

[0031] As shown by the Fig. As can be seen in Figures 2-5, the inner region 130 can be arbitrarily segmented using the insulating bridges 32 to define any number of component regions of any size. The size of the individual component regions 4 can be adjusted depending on the size or number of semiconductor devices to be integrated in each component region 4.

[0032] During operation of the semiconductor assembly, the insulating grid 3 can be connected to a circuit node that has a predefined electrical potential. The buried region 2, adjacent to the insulating grid 3, is connected to the same electrical potential as the insulating grid 3. If the first doping type is N-type and the second doping type is P-type, the predefined electrical potential across the insulating grid 3 and the buried region 2 can be, for example, the highest electrical potential present in the electronic circuit. In this case, the electrical potentials of the component regions 4 are lower than or equal to this highest electrical potential. Thus, the PN junctions formed between the component regions 4 on one side and the insulating grid 3 and the buried region 2 on the other side are reverse-biased.In this example, the outer region 140 can be connected to an electrical potential lower than that of the insulating grid 3 to reverse-bias the PN junction between the insulating ring 31 and the buried region 2 on one side and the outer region 140 on the other. The electrical potential of the outer region 140 can be higher or lower than the electrical potentials of the component regions 4. In one example, the electrical potential of the outer region 140 is the lowest electrical potential present in the electronic circuit. In this example, the electrical potential of the outer region 140 is equal to or lower than the electrical potential of each of the component regions 4.

[0033] If the first doping type is a P-type and the second doping type is an N-type, the predefined electrical potential applied to the insulating grid 3 and the buried region 2 can be the lowest electrical potential occurring in the electronic circuit. In this example, the outer region 140 or any section (potential) of the inner region 4 can be connected to the highest electrical potential occurring in the electronic circuit.

[0034] To connect the outer region 140 to a predefined electrical potential, which can be the lowest or highest electrical potential occurring in the electronic circuit, a first contact ring 7 can be arranged in the outer region 140. Referring to the Fig. 2-5 The first contact ring 7 can be arranged at a distance from the insulating ring 31 and surround the insulating ring 31 in lateral directions. According to one example, the first contact ring 7 is a doped region of the second doping type and has a higher doping concentration than the base doping of the semiconductor layer 100. According to another example, the doping concentration of the first contact ring is higher than 1E18 cm⁻¹. -3 or even higher than 1E19 cm -3 .

[0035] In the semiconductor arrangement described above, the insulating grid 3, which defines at least two component regions 4, ensures a space-saving and flexible segmentation of the semiconductor layer 100 into the individual component regions 4. Each insulating bridge 32, for example, is shared by at least two component regions 4. Thus, junction insulation is provided for each of the component regions in a space-saving manner.

[0036] Some examples of how to create the buried area 2 and the insulating grid 3 are explained below.

[0037] The Fig. 6A and Fig. 6B illustrates an example of a procedure for creating the buried area 2. Referring to Fig. 6A comprises the process of implanting first-type dopant atoms through the first surface 101 into the semiconductor layer 100 to create an implanted region 2' containing first-type dopant atoms. The implanted region 2' is spaced apart from the first surface 101. The distance between the first surface 101 and the implanted region 2' can be adjusted by appropriately selecting the implantation energy during the implantation process, taking into account the desired implantation dose. Generally, the higher the implantation energy, the greater the distance between the first surface 101 and the implanted region 2'. Furthermore, the higher the implantation dose, the shallower the implantation depth.

[0038] According to one example, the process of fabricating the implanted regions 2' involves fabricating an implantation mask 301 over the first surface 101. The implantation mask 301 includes an opening that defines the size and position of the implanted region 2'. Through the opening in the implantation mask 301, the dopant atoms are implanted into the semiconductor body 100. The remainder of the semiconductor layer 100 is protected from dopant atoms being implanted by the implantation mask 301.

[0039] Referring to Fig. 6B further includes an annealing process in which the semiconductor layer 100 is annealed to activate the implanted dopant atoms and to create the buried region 2 based on the implanted region 2'. The implanted dopant atoms can diffuse during the annealing process, so that the buried region 2 can have larger dimensions than the implanted region 2'. Furthermore, the annealing process can lead to the growth of an oxide layer on the first surface 101, which can help prevent outgassing of the implanted dopant atoms.

[0040] In the Fig. 6A and Fig. In the example shown in Figure 6B, the dopant atoms are implanted into the semiconductor layer 100 via the first surface 101. In the finished semiconductor assembly, the first surface 101 is the surface from which the insulating lattice 3 extends downwards to the buried region 2. However, implanting the dopant atoms into the first surface 101 to create the buried region 2 is only one example. According to another example (not shown), the dopant atoms are implanted into the semiconductor layer 100 via a second surface of the semiconductor layer 100 opposite the first surface 101.

[0041] The Fig. Figures 7A-7C illustrate a modification of the procedure according to the Fig. 6A-6B. The procedure according to the Fig. 7A-7C differs from the procedure according to the Fig. 6A-6B by the fact that, as in Fig. Figure 7A shows the implanted area 2' being produced in a first section 110 of the semiconductor layer 100 before, as in Fig. Figure 7B shows that a second section 120 of the semiconductor layer 100 is fabricated on the first section 110. The fabrication of the second section 120 includes, for example, an epitaxial growth process. Referring to Fig. 7C The annealing process for fabricating the buried region 2 based on the implanted region 2' can take place before or after the fabrication of the second section 120 on the first section 110. The first section 110 is, for example, a semiconductor substrate or an epitaxial layer formed on a substrate. Further annealing processes can occur during the fabrication of semiconductor devices in the device regions 4. These further annealing processes can cause further diffusion of the dopant atoms in the buried region 2 and can therefore further "widen" the buried region 2.

[0042] The Fig. Figures 8A-8C illustrate an example of a method for producing insulating grid 3. It should be noted that the Fig. Figures 8A-8C each illustrate a vertical cross-sectional view of only one section of the insulating grid 3 during the manufacturing process.

[0043] Referring to Fig. 8A comprises the fabrication of the insulating grid 3 comprising the fabrication of at least one trench 33 extending from the first surface 101 into the semiconductor layer 100. By way of example, the at least one trench 33 extends substantially in a vertical direction along the semiconductor layer 100. "The vertical direction" is a direction that is substantially perpendicular to the first surface 101. Sidewalls of the at least one trench 33 may be substantially vertical or may be inclined.

[0044] The production of the trench can include an etching process in which an etching mask (shown in dashed lines) is produced on the first surface 101. In the conventional manner, the etching mask 201 includes an opening in which sections of the surface 101 are not covered and which defines the position of the at least one trench 33.

[0045] According to one example, a trench width, which is a minimum dimension of the at least one trench 33 in a lateral direction, lies in a range between 0.4 micrometers (µm) and 5 micrometers, in particular between 1 micrometer and 3 micrometers. A trench depth, which is the dimension of the trench 33 in the vertical direction, lies in a range between 5 micrometers and 30 micrometers, in particular between 10 micrometers and 15 micrometers. According to one example, the aspect ratio, which is the ratio between the trench depth and the trench width, lies in a range between 5 and 40. If the trench 33 has sloping side walls, the trench width used to calculate the aspect ratio is an average of the trench width over the depth of the trench 33.

[0046] Referring to Fig. 8B The method comprises the fabrication of a dopant source 34 in the at least one trench 33. According to an example, the dopant source 34 is a layer comprising dopant atoms of the first doping type, which can diffuse from the dopant source 34 into the semiconductor region surrounding the at least one trench 33. The dopant source 34 covers at least side walls and a bottom of the at least one trench 33. In the Fig. In the example shown in Figure 8B, the dopant source 34 completely fills the at least one trench 33. According to another example (not shown), the dopant source only covers the side walls and the bottom of the at least one trench 33.

[0047] According to one example, the surface 101 of the semiconductor layer 100 is covered by a protective layer during the process of fabricating the dopant source 34. The protective layer protects the surface 101 outside the trench 33 from the fabrication of the dopant source 34 on it. According to one in Fig. In the example shown in Figure 8B, the protective layer is the etching mask 201, which is used in the process of producing at least one trench.

[0048] In one example, the dopant source 34 comprises a silicate glass. In this example, the first dopant type is N-type. In this example, the silicate glass is, for instance, a phosphosilicate glass (PSG). PSG comprises phosphorus (P) atoms as N-type dopants. In another example, the first dopant type is P-type. In this example, the silicate glass is, for instance, borosilicate glass (BSG). BSG comprises boron (B) atoms as P-type dopants.

[0049] According to a Fig. In the example shown in Figure 8B, the layer forming the dopant source 34 is produced such that it covers the side walls and one bottom of the at least one trench 33, leaving a residual trench. This facilitates the subsequent removal of the dopant source 34, if desired. According to another example (not shown), the layer forming the dopant source 34 completely fills the at least one trench 33.

[0050] Referring to Fig. 8C further includes a tempering process in which the dopant atoms of the second type are diffused from the dopant source 34 into semiconductor regions of the semiconductor layer 100 surrounding the trench 33 to produce the doped region 35 of the first doping type of the insulating lattice 3.

[0051] It should be noted that the insulating grid 3 can be manufactured before or after the construction of the buried area 2. For this reason, the buried area 2 is in the Fig. 8A-8C are shown in dashed lines. Furthermore, the same annealing process can be used to activate and diffuse the implanted dopant atoms forming the buried region 2 and to diffuse the dopant atoms from the dopant source 34 into the semiconductor layer 100. Alternatively, two different annealing processes are used to activate the implanted dopant atoms and to diffuse the dopant atoms from the dopant source 34. In each case, the trench depth of the at least one trench 33 is adapted to the vertical position of the implanted regions 2', such that after the at least one annealing process, the doped region 35 of the insulating lattice 3 borders the buried region 2 or extends into the buried region 2.“The vertical position of the implanted areas 2’” is the position that is spaced from the first surface 101 in a direction that is substantially perpendicular to the first surface 101.

[0052] Referring to a statement in the Fig. In the example shown in 9A-9B, the method can further include removing the doping source 34 from the at least one trench 33 and filling the trench 33 with a filling layer 36. Fig. Figure 9A illustrates the arrangement after the removal of the dopant source 34 from the trench 33 and Fig. Figure 9B illustrates the arrangement after filling the trench 33 with the fill layer 36.

[0053] The filler layer 36 comprises an electrically conductive or non-conductive material. In one example, the filler layer 36 is a homogeneous layer made of only one material. In another example, the filler layer 36 comprises a stack of layers with two or more sublayers made of different materials. In another example, at least one of the sublayers is electrically conductive and at least one other of the sublayers is non-conductive.

[0054] According to one example, the filler layer 36 is non-conductive and comprises a dielectric layer covering the side walls and bottom of the at least one trench 33 after removal of the dopant source 34, and an undoped polysilicon layer on the dielectric layer. The dielectric layer is, for example, an oxide layer. If the filler layer 36 is non-conductive, the electrically conductive doped region 35 can be connected to a circuit node having the desired predefined electrical potential, in order to connect the insulating grid 3 to the circuit node having the predefined electrical potential.

[0055] According to another example, the filler layer 36 is electrically conductive and comprises, for example, doped polysilicon or a metal. If the filler layer 36 is conductive, the filler layer 36 and / or the doped region 35 can be connected to the circuit node that has the desired predefined electrical potential in order to connect the insulating grid 3 to the circuit node that has the predefined electrical potential.

[0056] According to another example, the filler material 36 is electrically insulating. In this example, the filler material 36 can comprise an oxide. Furthermore, in this example, the doped region 35 is connected to a circuit node that has the desired predefined electrical potential.

[0057] As stated above, the fabrication of the insulating lattice 3 comprises the fabrication of at least one trench in the semiconductor layer 100. According to one example, the fabrication of the insulating lattice 3 comprises the fabrication of several trenches spaced apart from one another. According to one example, the distance between adjacent trenches 33 is such that the doped regions 35 fabricated along the sidewalls of the trenches overlap and form a continuous doped region of the first doping type.

[0058] Referring to the Fig. 2-5 The insulating grid can comprise 3 T-sections. At a T-section, an insulating bridge 32 adjoins another insulating bridge 32 or the insulating ring 31 and is substantially perpendicular to the other insulating bridge 32 or the insulating ring 31. In the Fig. In the example shown, T-sections occur in those areas where the insulating bridge 32 adjoins the insulating ring 31. In the Fig. In the examples shown in Figures 3-5, T-type areas occur in those areas where isolating bridges 32 adjoin the isolating ring 31, and also occur in those areas where two isolating bridges 32 adjoin each other.

[0059] An example of a T-section is in Fig. 10A is shown in more detail. In particular, it shows Fig. 10A a top view of a T-section of the insulating grid 3. The in Fig. The insulating grid 3 shown in Figure 10A is based on one of the ones in the Fig. Examples shown in 8A-8C or 9A-9B and includes several trenches 33. The trenches 33 are in Fig. Figure 10 is represented by bold lines. After the insulating grid 3 has been constructed, the trenches can still be filled with the dopant source 34, as shown in Figure 10. Fig. 8C shown, or they can be filled with an electrically conductive or an electrically insulating filler material 36, as in Fig. 9B is shown.

[0060] The in Fig. The trenches 33 shown in Figure 10A comprise a first trench 331 and a second trench 332. The second trench 332 is essentially perpendicular to the first trench 331. Furthermore, one longitudinal end of the second trench 332 is spaced apart from the first trench 331. For example, the distance between the longitudinal end of the second trench 332 and the first trench 331 is between 0.5 micrometers and 2 micrometers. The first trench 331 is, for example, a section of the insulating rings 31 or a section of an insulating bridge 32. The second trench 332 is a section of an insulating bridge 32.

[0061] As in Fig. As shown in Figure 10, the T-section further comprises a third trench 333 and a fourth trench 334. The third trench 333 is located at a first corner defined by the first trench 331 and the second trench 332, and the fourth trench 334 is located at a second corner defined by the first trench 331 and the second trench 332. The second corner differs from the first corner. Each of the third and fourth trenches 333, 334 is spaced apart from each of the first and second trenches 331, 332. Furthermore, each of the third and fourth trenches 333, 334 is curved. The third and fourth trenches 333, 334 can have the same curvature. However, this is only an example. It is also possible to implement the third and fourth trenches 333, 334 in such a way that they have different curvatures.

[0062] As explained above, dopant atoms for the production of the doped region 35 are supplied from a dopant source 34 (in Fig. 10 (not shown), which is arranged in the trenches 33, diffuses into the surrounding semiconductor material of the semiconductor layer 100. As from Fig. As can be seen in Figure 10, a curvature of the second and fourth trenches 333, 334 essentially defines a curvature of the doped area 35 of the insulating grid 3 in a corner region of the insulating grid 3. A “corner region” of the insulating grid 3 is a region in which a first section of the insulating grid adjoins a second section of the insulating grid, which is essentially perpendicular to the first section.

[0063] As described above, a PN junction is formed between the insulating grid 3 and the device region 4. It is generally known that an electric field occurs at a reverse-biased PN junction. Curved PN junctions can be critical because the electric field resulting from a given reverse-biasing voltage applied to the PN junction can be higher at a curved PN junction than at a linear PN junction. In general, the greater the curvature, the higher the electric field for a given reverse-biasing voltage applied to the PN junction. Furthermore, an avalanche breakdown can occur when the electric field reaches a predefined critical field strength.

[0064] The fabrication of the T-type section of the in Fig. The insulating grid 3 shown in Figure 10A, based solely on the first and second trenches 331, 332, can lead to a strong curvature of the PN junction between the doped region 35 of the insulating grid 3 and the device region 4. In contrast, by additionally providing the third and fourth trenches 333, 334, the curvature of the doped region 35, and therefore the curvature of the PN junction formed between the doped region 35 and the device region 4, can be reduced, resulting in a decrease in the electric field strength in the corner region. This makes it possible to use a single insulating bridge 32 for barrier insulation between two adjacent device regions 4. Essentially, the lower the curvature of the third and fourth trenches 333, 334, the higher the voltage that can be absorbed by the PN junction.In the same semiconductor body 100, T-type sections of the insulating grid 3 with different curvatures of the third and fourth trenches 333, 334 can be implemented, making it possible to implement component regions 4 that have different dielectric strengths relative to the insulating grid 3.

[0065] Implementing the first, second, third, and fourth trenches 331, 332, 333, 334, which are spaced apart from each other, makes it possible to use each of the trenches 331-334 in the process according to the Fig. 8A-8C or 9A-9B at each location are to be partially filled or filled in essentially the same way. This would be different if, for example, the first trench 331 were to merge into the second trench 332. At the point where the two trenches 331, 332 merge, a cross-sectional area would be locally increased, leading to a higher risk of void formation during the filling process. The same would apply if the third and fourth trenches 333, 334 were to merge into one or both of the first and second trenches 331, 332.

[0066] The distance between the third trench 333 and the first and second trenches 331, 332 is such that the doped area 35, which surrounds the third trench 333 based on the doping source 34 (in Fig. 10 not shown) is produced in the third trench 333, to the doped areas 35, which are along the first and second trenches 331, 332 based on the doping source 34 (in Fig. 10 (not shown) in the first and second trenches 331, 332, borders and connects these endowed areas produced along the first and second trenches 331, 332. Equivalently, a distance from the fourth trench 334 to the first and second trenches 331, 332 is such that the endowed area produced around the fourth trench 334 borders the endowed areas 35 produced along the first and second trenches 331, 332 and connects the endowed areas produced along the first and second trenches 331, 332. This is in the Fig. 11A-11C shown.

[0067] Fig. Figure 11A shows a vertical cross-sectional view of the insulating grid 3 in a vertical section plane AA, which is in Fig. 10A is shown, which is essentially perpendicular to the second trench 332 and intersects the second, third and fourth trenches 332, 333, 334. Fig. Figure 11B shows a vertical cross-sectional view of the insulating grid 3 in a vertical section plane B1-B1, which is in Fig. 10A is shown, which is essentially perpendicular to the first trench 331 and cuts through the first trench 331 and the fourth trench 334. Fig. Figure 11C shows a vertical cross-sectional view of the insulating grid 3 in a vertical section plane B2-B2, which is in Fig. 10A is shown, which is essentially perpendicular to the first cutting plane AA and intersects through the first trench 331 and the third trench 333.

[0068] As from Fig. As can be seen in Figure 11A, the endowed areas 35, which are constructed around the third and fourth ditches 333, 334, border the endowed area 35, which is constructed around the second ditch 332. As can be seen from Fig. As can be seen in Figure 11B, the endowed area 35, which is created around the fourth trench 334, borders the endowed area 35, which is created along the first trench 331. Equivalently, as shown in Figure 11B, the endowed area 35, which is created around the fourth trench 334, borders the endowed area 35, which is created along the first trench 331. Fig. As can be seen in Figure 11C, the endowed area created around the third trench 333 borders the endowed area created along the first trench 331.

[0069] As from Fig. As can be seen in Figure 10A, the distances between the third and fourth trenches 333, 334 on the one hand and the second trench 332 on the other hand increase in the direction of the first trench 331. Equivalently, the distances between the third and fourth trenches 333, 334 on the one hand and the first trench 331 on the other increase in the direction of the second trench 332. This may result in the endowed area 35 not covering the entire area located between the third trench 333, the first trench 331 and the second trench 332, nor the entire area located between the fourth trench 334, the first trench 331 and the second trench 332. However, this is not critical. In any case, the endowed area 35 is a contiguous endowed area along each of the first, second, third and fourth ditches 31, 32, 33, 34.

[0070] Fig. 10B shows a modification of the one in Fig. T-type section shown in 10A. The in Fig. The arrangement shown in 10B results from mirroring the in Fig. The arrangement shown in Figure 10A is along a line defined by the first trench 331, such that the arrangement contains two T-type sections that share the first trench 331. This combination of two T-type sections can be called an X-type section.

[0071] The Fig. 12 and Fig. Figure 13 illustrates an example of a semiconductor device that can be integrated in device area 4. The [device] in the Fig. 12 and Fig. Figure 13 shows a semiconductor device that is a lateral transistor device. Fig. Figure 12 shows a top view of the transistor component and Fig. Figure 13 shows a vertical cross-section of the transistor device in a section plane CC, which is in Fig. 12 is shown.

[0072] This is only for illustrative purposes in the Fig. 12 and Fig. Figure 13 shows a transistor device 5, a MOSFET. In particular, the MOSFET is a MOSFET with one channel of the first doping type, such that the MOSFET is an N-type MOSFET (N-channel MOSFET) if the first doping type is an N-type, and a P-type MOSFET (P-channel MOSFET) if the second doping type is a P-type.

[0073] In this example, the transistor device 5 comprises a first-type drift region 51, a first-type drain region 54 adjacent to the drift region 51, a second-type body region 53 adjacent to the drift region 51 and spaced apart from the drain region 54, and a first-type source region 52 separated from the drift region 51 by the body region 53. Each of the drift region 51, the drain region 54, the body region 53, and the source region 52 is a doped region formed within the device region 4 of the semiconductor body 100.

[0074] The drift region 51, the source region 52, the body region 53, and the drain region 54 are active component regions of the transistor device 5. The fabrication of the active component regions of the transistor device 5 can involve the implantation of dopant atoms into component region 4 and can include a thermal process to activate the implanted dopant atoms. As described above, component region 4 has a base doping of the second doping type.

[0075] According to an example, sections of the component region 4, which have the basic doping concentration, remain after the production of the active component regions, so that at least in some sections doped regions with the basic doping concentration of the second doping type of the component region 4 are arranged between the active component regions and the insulating grid 3.

[0076] The doping concentrations in the source and drain areas 52, 54 are, for example, higher than 1E19 cm -3 and can be as high as 1E21 cm, for example -3 The doping concentration of drift area 51, for example, is selected from 1E14 cm. -3 and 1E18 cm -3 and the doping concentration of body region 53 is, for example, selected from 1E14 cm -3 and 1E18 cm -3 .

[0077] As in the Fig. 12 and Fig. As shown in Figure 13, the transistor device 5 further comprises a gate electrode 55. The gate electrode 55 is located adjacent to the body region 53 and is dielectrically isolated from the body region 53 by a gate dielectric 56. In the conventional manner, the gate electrode 55 serves to control a conducting channel in the body region 53 between the source region 52 and the drift region 51. The channel is a first-type doping channel. That is, the channel is an N-channel if the first doping type is N-type, and a P-channel if the first doping type is P-type.

[0078] In the Fig. 12 and Fig. In the example shown in Figure 13, the gate electrode 55 is a planar electrode formed on a first surface 101 of the semiconductor body 100 and separated from the semiconductor body 100 by the gate dielectric 56. However, this is only one example. According to another example (not shown), the gate electrode 55 is a trench electrode formed in a trench extending vertically from the first surface 101 into the semiconductor body 100 and laterally from the source region 52 through the body region 53 to the drift region 51. The “vertical direction” is a direction that is essentially perpendicular to the first surface 101. “Lateral directions” are directions that are essentially parallel to the first surface 101.

[0079] Referring to Fig. In section 13, the drain region 54 is connected to a drain node D, the gate electrode 55 is connected to a gate node G, and the source region 52 is connected to a source node S. These circuit nodes of the transistor components 5 can be formed by electrically conductive layers (not shown), which can serve to connect the transistor component 5 to electronic components located in component regions 4 other than the one shown in the Fig. 12 and Fig. The 13 components shown are integrated. Connections between the active component areas 51, 52, 53, 54 and the individual circuit nodes S, G, D are shown in Fig. Figure 14 is shown only schematically. The connection of active component regions of semiconductor devices with respective circuit nodes and the connection of electronic components that are arranged in different component regions of a semiconductor body is generally known, so that no further explanation is required in this regard.

[0080] In the Fig. 12 and Fig. In the example shown in Figure 13, the body region 53 comprises two body region sections, a first body region section 531 and a second body region section 532. Each of the first and second body region sections 531, 532 is spaced from the drain region 54 in a respective lateral direction. Furthermore, the first and second body region sections 531, 532 are spaced apart from each other such that the drain region 54 is located between the first and second body region sections 531, 532. According to one example, the distances between the drain region 54 and the first body region section 531 on one side and between the drain region 54 and the second body region section 532 on the other side are substantially equal, so that the first and second body region sections 531, 532 are symmetrical to each other with respect to the drain region 54. Each of the first and second body region sections 531, 532 is connected to the source node S of the transistor element 5.

[0081] Furthermore, the in the Fig. 12 and Fig. In the transistor element shown in Figure 13, the source region 52 comprises a first source region section 521, which is separated from the drift region 51 by the first body region section 531, and a second source region section 522, which is separated from the drift region 51 by the second body region section 532. Each of the first and second source region sections 521, 522 is connected to the source node S.

[0082] Furthermore, the transistor component comprises according to the Fig. 12 and Fig. 13 The gate electrode 55 has two gate electrode sections, a first gate electrode section 551 and a second gate electrode section 552. The first gate electrode section 551 is adjacent to the first body region section 531 and serves to control a first conducting channel in the first body region section 531 between the first source region section 521 and the drift region 51. The second gate electrode section 552 is adjacent to the second body region section 532 and serves to control a second conducting channel in the second body region section 532 between the second source region section 522 and the drift region 51. Each of the first and second gate electrode sections 551, 552 is connected to the gate node G, so that the first and second conducting channels are controlled simultaneously.

[0083] According to a Fig. In the example shown in Figure 12, the doped region forming the first and second body region sections 531 and 532 forms a closed loop or ring that laterally surrounds the drift region 51 and the drain region 54. According to another example, the body region 53 is configured such that at every position of the body region 53, the (shortest) distance between the body region 53 and the drain region 54 is substantially the same. In this example, the body region 53 includes a third body region section 533, which is located between the first and second body region sections 531 and 532 in a first boundary region ER1 of the device region 4, and a fourth body region section 534, which is located between the first and second body region sections 531 and 532 in a second boundary region ER2 of the device region 4. The third and fourth body region sections 533, 534 are free of embedded source region sections.Furthermore, the first, second, third and fourth body area sections 531, 532, 533, 534 form a closed loop of body area 53 around the drift and drain areas 51, 54.

[0084] Referring to Fig. 13 The gate electrode 55 can be annular in a similar way to the body region 53 and can form a closed loop around projections of the drift and drain regions 51, 54 above the first surface 101. The gate electrode 55 is dielectrically isolated from the first and second body region sections 531, 532 and the corresponding source region sections 521, 522 by the gate dielectric 56 (outside the view in Fig. 12).

[0085] According to an example, in the boundary regions ER1, ER2 the gate electrode 55 is separated from the semiconductor body 100 by a dielectric layer (outside the view in Fig. 12) separated, which is thicker than the gate dielectric 56 and forms a field dielectric. According to another example (not shown), the source region 52, like the body region 53, forms a closed loop around the drift and drain regions 51, 54. In this example, the source and body regions 52, 53 in the boundary regions ER1, ER2 can be separated from the annular gate electrode 55 by a dielectric layer that is thicker than the gate dielectric 56, such that the portions of the source region 52 located in the boundary regions ER1, ER2 are essentially electrically inactive. That is, essentially no conducting channel is generated in the body region 53 between the source region 52 and the drift region 51 in the boundary regions ER1, ER2.

[0086] It should be noted that implementing a lateral MOSFET such that it has two source and body regions that are essentially symmetrical is just one example. It is also possible to implement a lateral MOSFET of the type described in the Fig. 12 and Fig. 13 of the type shown, to be implemented in such a way that it has only a source and body region, which are separated from the drain region.

[0087] As explained above, to electrically isolate the electronic components integrated in the individual component regions 4 from one another, the insulating grid 3 can be connected to the highest electrical potential, and each component region 4 can be connected to an electrical potential equal to or lower than the highest electrical potential, or the insulating grid 3 can be connected to the lowest electrical potential, and each component region 4 can be connected to an electrical potential equal to or higher than the lowest electrical potential. Whether the insulating grid 3 is connected to the highest or lowest electrical potential depends on how the PN junction between the insulating grid 3 and the component region 4 is implemented.In a semiconductor arrangement, in which, for example, the first doping type, which is the doping type of the insulating grid 3, is an N-type and in which the second doping type, which is the doping type of the device regions 4, is a P-type, the insulating grid 3 can be connected to the highest electrical potential and each of the device regions 4 can be connected to an electrical potential that is equal to or lower than the highest electrical potential applied to the insulating grid 3.

[0088] As explained above, the semiconductor arrangement for connecting the outer region 140 of the semiconductor layer 100 to a predefined electrical potential can include the first contact ring 7, which laterally surrounds the insulating grid 3. Similar inner rings 6 can be arranged in the individual device regions 4. The inner ring 6 has a higher doping concentration than the base doping of the device region 4. According to one example, the doping concentration of the contact ring 6 is at least 10 times that of the base doping. According to another example, the doping concentration of the inner ring 6 is so high that the inner ring 6 cannot be completely depleted of charge carriers. The inner ring 6 is optional and is therefore not included in the Fig. 12 and Fig. 13 shown in dashed lines.

[0089] According to one example, if the component region 43 has the same doping type as the component region 4, the component region 4 can be connected to the desired electrical potential, such as a potential source, via the body region 53. According to another example, the component region 43 is connected to the desired electrical potential via the inner region 6. For this purpose, the inner region 6 can be connected to a contact electrode (in Fig. 13 (not shown) connected to the desired electrical potential, such as a source potential.

[0090] According to an example, the inner ring 6 is implemented such that the distance between the contact ring 6 and the insulating grid 3 is essentially the same at every position. The insulating grid 3, in particular the doped regions 35 (in the Fig. 12 and Fig. The insulating grid (13 not shown), the inner ring 6, and sections of the component area 4, which have the basic doping of the second doping type, form a PN diode. The dielectric strength of this PN diode, and therefore the maximum voltage that can be applied between the insulating grid 3 and the component area 4, depends on the distance between the contact ring 6 and the insulating grid 3. Generally, the greater the distance, the higher the dielectric strength.

[0091] It should be noted that in different component regions 4, the distance between the inner ring 6 and the insulating grid 3 can vary to achieve different voltage ratings. Thus, in component regions 4 where a relatively low voltage is expected between the insulating grid 3 and the electronic component implemented in that region 4, the distance between the contact ring 6 and the insulating grid 3 can be small, which helps to implement this component region 4 in a space-saving manner. Therefore, in the same semiconductor arrangement, the size of the individual component regions 4 can be optimized with regard to the electronic components to be integrated into each region 4. In the same semiconductor arrangement, voltage ratings between several volts and several tens of volts, up to 200 V and more, can be achieved.

[0092] As explained above, during operation of the semiconductor assembly, the component region 4 can have an electrical potential that differs from the electrical potential of the insulating grid 3. The resulting voltage difference is absorbed by the PN junction formed between the insulating grid 3 and the component region 4. As also explained above, the maximum voltage that can be applied between the component region 4 and the insulating grid 3 can be defined by the inner ring 6 and the distance between the inner ring 6 and the insulating grid 3. The desired electrical potential can be applied to the component region 4 in various ways.

[0093] According to a Fig. In the example shown in Figure 13, the source node S is connected to the body region 53. In this example, the source node S can be used to apply a predefined electrical potential to the component region 4. The body region 53 has the same doping type as the component region 4 and borders it, so that by applying a predefined electrical potential to the body region 53 via the source node S, the predefined electrical potential can be applied to the component region 4.

[0094] Another example of connecting component area 4 to a predefined electrical potential is in Fig. 14 shown. Fig. Figure 14 illustrates an enlarged view of a section of a component of the in Fig. 13 of the type shown. In the one in Fig. In the example shown in Figure 14, the transistor device comprises, in addition to the source node S, the gate node G, and the drain node D, a further device node B, which can be referred to as a bulk node. The bulk node B is connected to the body region 53. According to one example, an isolation region 57, such as a shallow trench isolation (STI), is arranged between a section of the body region 53, to which the bulk node B is connected, and the source region 52.

[0095] In the Fig. 12 and Fig. In the example shown in 13, a transistor component is integrated into a component area 4. However, this is only one example. According to another example, which is shown in Fig. As shown schematically in Figure 15, several transistor components are integrated into a component area 4. Fig. Figure 14 shows the transistor components only schematically. A second contact ring 6 (shown in dashed lines) can laterally surround the area in which the individual transistor components are integrated.

[0096] In the Fig. 12 and Fig. In the example shown in Figure 13, the transistor device is a first-type transistor device, which is a transistor device that, in the conducting state, has a channel of the first doping type. In this transistor device, the drift region 51, the source region 52, and the drain region 54 have the first doping type, which is the same doping type as the doped region 35 (in the Fig. 12 and Fig. (13 not shown) of the insulating grid 3, and the body region 53 has the second doping type, which is the same doping type as the base doping of the device region 4. For example, if the transistor device is an N-type transistor device, the source and drain regions 54 are N-type regions, and the body region 53 and the device region 4 are P-type regions. As explained above, in this case, the insulating grid 3 can be connected to the highest electrical potential occurring in the semiconductor assembly, and the device region 4 can be connected to an electrical potential equal to or lower than the electrical potential of the insulating grid 3.The drain region 54 can be connected to an electrical potential that is even higher than the electrical potential of the insulating grid 3, whereby a voltage difference between the drain region 54 and the component region 4 is absorbed by a PN junction between the drift region 51 and the component region 4.

[0097] Fig. Figure 16 illustrates a vertical cross-sectional view of a transistor device of a first type according to another example. In this example, the body region 53 and the source region 52 are arranged within an annular drain region 54. The ring defined by the drain region 54 is shown in the vertical cross-sectional view according to Fig. 15 not shown. The ring defined by the drain area 54 is similar to that defined by the source area 52 according to the Fig. 12 and Fig. 13 defined ring.

[0098] The source region 52 is embedded in the body region 53 and can have an elongated shape similar to the shape of the drain region in the Fig. 12 and Fig. The example shown in Figure 13 illustrates this. Above the first surface 101 of the semiconductor body 100, the gate electrode 55 forms a ring around the source region 52. The gate electrode 55 is dielectrically insulated from the semiconductor body 100 by the gate dielectric 56.

[0099] Referring to Fig. In Figure 16, the drift region 51 is arranged between the body region 53 and the drain region 54, with the drain region 54 being embedded within the drift region 51. According to one example, the drift region 51 extends to the insulating grid 3. The drain region 54 can be spaced apart from the insulating grid 3 (as shown) or can be adjacent to the insulating grid 3 (not shown). In this example, the insulating grid 3 and the drain region 54 have substantially the same electrical potential. Furthermore, the transistor device can be operated such that the electrical potential of the body region 53, and therefore the electrical potential of the device region 4, is such that the PN junction between the device region 4 and the insulating grid 3 is reverse biased. The body region 53 is connected either to the source node S or to a bulk node B. However, such a connection is not necessary in Fig. 15 not shown.

[0100] The semiconductor arrangement is not limited to having four integrated transistor devices of the first type in the component areas.

[0101] A second-type transistor device, which is a transistor device with one channel of the second doping type, is in the Fig. 17 and Fig. 18 shown. Fig. 17 shows a top view and Fig. Figure 16 shows a vertical cross-sectional view of the transistor component. The one in the Fig. 17 and Fig. The transistor component shown in section 18 is based on the one described in the Fig. 12 and Fig. The transistor component shown in Figure 13 differs in that the drift region 51 and the source and drain regions 52, 54 are of the second doping type, while the body region 53 is of the first doping type. Furthermore, the transistor component differs according to the Fig. 17 and Fig. 18 of the transistor component according to the Fig. 12 and Fig. 13 by the fact that the body region extends in lateral directions to the insulating grid 3. In the Fig. In the example shown in 17, the body region 53 is connected to the source node S. However, this is only one example. It is also possible to connect the body region 53 to the one shown in Fig. 14. To connect to a bulk node B as shown.

[0102] In the Fig. 17 and Fig. In the example shown in Figure 18, the drain region 54 is arranged within a ring defined by the source and body regions 52 and 53. Another example of a second-type transistor device, arranged in the device region 4, is shown in Figure 18. Fig. 19 shown.

[0103] The in Fig. The transistor component shown in 19 is based on the one described in Fig. The example shown in Figure 16 comprises a source region 52 of the second doping type, surrounded by an annular drain region 54 of the second doping type. The drift region 51 and the drain region 54 are spaced apart from the insulating grid 3. In this type of transistor device, the electrical potential of the device region 4 is defined by the electrical potential of the drain region 54. The body region 53 can be connected either to the source node S or to a bulk node B. A connection between the body region 53 and either the source node S or the bulk node B is shown in Figure 16. Fig. However, 19 is not shown.

[0104] Some of the aspects explained above are briefly summarized below with reference to numbered examples. Example 1. Semiconductor arrangement comprising: a semiconductor layer with a first surface; a buried region of a first doping type formed in the semiconductor layer spaced apart from the first surface; an insulating lattice extending from the first surface to the buried region and containing a first region of the first doping type; and device regions of the second doping type adjacent to the buried region and isolated from each other by the insulating lattice. Example 2. Semiconductor arrangement according to Example 1, further comprising: a first contact ring of the second doping type, which laterally surrounds the insulating grid. Example 3. Semiconductor arrangement according to Example 1 or 2, wherein at least one of the component regions contains a second ring of the second doping type. Example 4. Semiconductor arrangement according to one of the preceding examples, wherein the insulating grid comprises: an insulating ring; and at least one insulating bridge formed within the insulating ring. Example 5. Semiconductor arrangement according to one of the preceding examples, wherein the insulating grid further comprises at least one insulating trench extending from the first surface to the buried region and surrounded by the first region. Example 6. Semiconductor arrangement according to Example 5, wherein the at least one insulating trench contains several trenches spaced laterally apart from each other. Example 7. Semiconductor arrangement according to Example 6, wherein the insulating grid contains T-shaped sections, each T-shaped section containing: an elongated first trench; an elongated second trench that is at least approximately perpendicular to the first trench; a curved third trench that is arranged in a first corner defined by the first trench and the second trench; and a curved fourth trench that is arranged in a second corner defined by the first trench and the second trench. Example 8. Semiconductor arrangement according to Example 7, wherein two T-shaped sections share an elongated first trench (331) and form an X-shaped section. Example 9. Semiconductor arrangement according to one of Examples 6 to 8, wherein the trenches are filled with a dopant source. Example 10. Semiconductor arrangement according to one of Examples 6 to 8, wherein the trenches are filled with an electrically conductive or electrically insulating filler material. Example 11. Semiconductor arrangement according to one of the preceding examples, further comprising: at least one semiconductor device integrated in each of the component regions. Example 12. Semiconductor arrangement according to Example 11, wherein at least two semiconductor devices are integrated in at least one of the component areas. Example 13. Semiconductor arrangement according to Example 11 or 12, wherein the at least one semiconductor device is selected from the group consisting of a transistor; a resistor; a diode; a capacitor. Example 14. Semiconductor arrangement according to Example 13, wherein the transistor is selected from the group consisting of: a MOSFET; a JFET; a BJT; an IGBT.

Claims

[1] Semiconductor arrangement comprising: a semiconductor layer (100) with a first surface (101); a buried area (2) of a first doping type formed in the semiconductor layer (100) spaced apart from the first surface (101); an insulating grid (3) extending from the first surface (101) to the buried area (2) and comprising a first area (35) of the first doping type; and Component areas (4) of the second doping type, which are adjacent to the buried area (2) and are isolated from each other by the insulating grid (3), wherein the insulating grid (3) has several trenches (331-334) extending from the first surface (101) to the buried area (2), surrounded by the first area (35), spaced laterally apart from each other and filled with an electrically conductive or electrically insulating material (36) or a dopant source (34), wherein the insulating grid (3) has T-shaped sections (T), and each of the T-shaped sections (T) has: a long first trench (331) of the several trenches (331-334); a long, narrow second trench (332) of the several trenches (331-334), which is at least approximately perpendicular to the first trench (331); a curved third trench (333) of the several trenches (331-334), arranged in a first corner defined by the first trench (331) and the second trench (332); and a curved fourth trench (334) of the several trenches, which is arranged in a second corner defined by the first trench (331) and the second trench (332). [2] Semiconductor arrangement according to claim 1, further comprising: a first contact ring (7) of the second doping type, which laterally surrounds the insulating grid (3). [3] Semiconductor arrangement according to claim 1 or 2, wherein at least one of the component regions (4) has a second ring (6) of the second doping type. [4] Semiconductor arrangement according to any one of claims 1 to 4, wherein the semiconductor arrangement has two T-shaped sections which have a common elongated first trench (331) and form an X-shaped section. [5] Semiconductor arrangement according to any one of the preceding claims, further comprising: at least one semiconductor device integrated in each of the component areas (4). [6] Semiconductor arrangement according to claim 5, wherein at least two semiconductor devices (5) are integrated in at least one of the component areas (4). [7] Semiconductor arrangement according to claim 5 or 6, wherein at least one semiconductor device is selected from the group consisting of a transistor (5); a resistance; a diode; a capacitor. [8] Semiconductor arrangement according to claim 7, wherein the transistor is selected from the group consisting of: a MOSFET; a JFET; a BJT; an IGBT. [9] Method for producing an insulating lattice (3) comprising a first region (35) of a first doping type, extending from a first surface (101) of a semiconductor layer (100) to a buried region (2) of the first doping type arranged spaced apart from the first surface (101) in the semiconductor layer (100) and isolating component regions (4) of the second doping type adjacent to the buried region (2) from each other, wherein the method comprises: Constructing several trenches (331-334) extending from the first surface (101) to the buried area (2), spaced laterally apart and filled with a dopant source (34); and Diffusion of dopant atoms of the first doping type from the dopant source (34) into a material of the semiconductor body surrounding the multiple trenches (331-334) to produce the first region (35), wherein the insulating grid (3) is manufactured such that it has T-shaped sections (T) which each have: a long first trench (331) of the several trenches (331-334); a long, narrow second trench (332) of the several trenches (331-334), which is at least approximately perpendicular to the first trench (331); a curved third trench (333) of the several trenches (331-334), arranged in a first corner defined by the first trench (331) and the second trench (332); and a curved fourth trench (334) of the several trenches, which is arranged in a second corner defined by the first trench (331) and the second trench (332). [10] The method of claim 9, further comprising: Removal of the doping source (34) from the multiple trenches (331-334); and Filling the several trenches (331-334) with an electrically insulating or electrically conductive material (36).

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