semiconductor device

Abstract

Semiconductor device, comprising: a semiconductor substrate (10); a low-side switching area (RL) that is located in the semiconductor substrate and receives a first reference potential (GND); a high-side switching area (RH) located in the semiconductor substrate that receives a second reference potential (VS) different from the first reference potential; and a first isolation area (30) that electrically isolates the low-side circuit area from the high-side circuit area, where the semiconductor substrate has a circuit base region in which the low-side circuit region and the high-side circuit region are not located, and the high-side circuit area comprises first and second high-side circuit areas, a first high-side circuit (CH1) is arranged in the first high-side circuit area, a second high-side circuit (CH2) is arranged in the second high-side circuit area, the first high-side circuit operates with a first supply voltage (VB1) based on the second reference potential, the second high-side circuit operates with a second supply voltage (VB2) based on the second reference potential, and the first and second supply voltages have different voltage values. the semiconductor device further comprises: a second insulation area (7) that electrically isolates the first high-side circuit area and the second high-side circuit area.

Description

BACKGROUND OF THE INVENTION Area of ​​the invention

[0001] The present invention relates to a semiconductor device comprising a high-side switching area and a low-side switching area. Description of the background technology

[0002] A high-voltage integrated circuit (HVIC) for power control, primarily used to drive a gate of a power semiconductor device, generally comprises a low-side circuit operating with a ground (GND) potential as a reference potential, a high-side circuit operating with a potential different from or deviating from GND, such as a floating potential, as a reference potential, and a level-shifting circuit that performs signal transfer between the low-side circuit and the high-side circuit.

[0003] A conventional HVIC, for example, is a semiconductor device disclosed in Japanese patent JP 7 001 050 B2. In the semiconductor device with an HVIC configuration disclosed in Japanese patent JP 7 001 050 B2, a high breakdown voltage termination structure in a high-side circuit area, which is equipped with a high-side circuit, and a high breakdown voltage level-shifting element are electrically isolated by trench insulation.

[0004] In a conventional semiconductor device with an HVIC configuration, the high-breakdown voltage termination structure of the high-side circuit area and the high-breakdown voltage level-shifting element can be isolated from each other. However, the internal configuration of the high-side circuit area is generally one in which N-type elements are provided in the same diffusion area, thus reducing the high-side circuit area's supply voltage to a single supply voltage. Furthermore, in cases where multiple high-side circuits operating at different supply voltages are arranged within the high-side circuit area, it is necessary to design one element's breakdown voltage to represent the maximum voltage across the circuits. This leads to the problem of increased device size.

[0005] As described above, the conventional semiconductor device with the HVIC configuration has the problem that the multitude of high-side circuits operating with different supply voltages cannot be arranged in the high-side circuit area without increasing the size of the device.

[0006] Publication US 2016 / 0043067A1 discloses a semiconductor device in which a first n-diffusion region, in which a PMOS transistor is configured as a gate driver, and a second n-diffusion region, in which a p-diffusion region is configured, are arranged on the surface layer of a p-substrate in a high-side region. An NMOS transistor is configured as a gate driver in the p-diffusion region. A p-isolation diffusion region at ground potential is located between the first and second n-diffusion regions. The first n-diffusion region and the second n-diffusion region are electrically isolated from each other. The first n-diffusion region is connected to a VB terminal at supply potential. The second n-diffusion region is connected to a reference or floating potential terminal. The p-diffusion region is connected to a VS terminal at reference potential.This allows parasitic processes caused by overvoltages to be suppressed without the use of external components and without component breakdown. SUMMARY

[0007] The present invention was created to solve the problem described above, and its objective is to obtain a semiconductor device having a high-side circuit area equipped with a plurality of high-side circuits operating at different supply voltages, without increasing the size of the device.

[0008] The problem underlying the invention is solved according to the invention in a semiconductor device by the features of claim 1. Advantageous further developments are the subject of the respective dependent claims.

[0009] A semiconductor device according to the present invention comprises a semiconductor substrate, a low-side switching area, a high-side switching area and a first isolation area.

[0010] The low-side circuit area is located in the semiconductor substrate and receives a first reference potential.

[0011] The high-side circuit area is located in the semiconductor substrate and receives a second reference potential that differs from the first reference potential.

[0012] The first isolation area electrically isolates the low-side circuit area from the high-side circuit area.

[0013] The semiconductor substrate has a circuit base region in which the low-side circuit region and the high-side circuit region are not located.

[0014] The high-side circuitry comprises first and second high-side circuitry sections. A first high-side circuitry section is located in the first high-side circuitry section, and a second high-side circuitry section is located in the second high-side circuitry section.

[0015] The first high-side circuit operates with a first supply voltage based on the second reference potential, and the second high-side circuit operates with a second supply voltage based on the second reference potential. The first and second supply voltages have different voltage values.

[0016] The semiconductor device further comprises a second isolation area that electrically isolates the first high-side circuit area and the second high-side circuit area.

[0017] Since the semiconductor device of the present invention has the second isolation area which electrically isolates the first and the second high-side circuit area from each other, there are no problems even if the first high-side circuit arranged in the first high-side circuit area is operated with the first supply voltage and the second high-side circuit arranged in the second high-side circuit area is operated with the second supply voltage which is different from the first supply voltage.

[0018] Therefore, in the semiconductor device of the present invention, the first and second high-side circuit areas can be arranged with the first and second high-side circuits in the high-side circuit area with a structure that retains miniaturization.

[0019] These and other objectives, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when it is taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is an explanatory illustration that schematically depicts a planar configuration of a semiconductor device of a first preferred embodiment; Fig. 2 is an explanatory diagram showing a circuit configuration of the in Fig. 1 illustrated semiconductor device schematically illustrated; Fig. Figure 3 is a cross-sectional view illustrating a cross-section of a semiconductor device as a first aspect of the first preferred embodiment; Fig. Figure 4 is a cross-sectional view illustrating a cross-section of a semiconductor device as a second aspect of the first preferred embodiment; Fig. Figure 5 is a cross-sectional view illustrating a cross-section of a semiconductor device as a third aspect of the first preferred embodiment; Fig. Figure 6 is a cross-sectional view illustrating a cross-section of a semiconductor device as a first aspect of a second preferred embodiment; Fig. Figure 7 is a cross-sectional view illustrating a cross-section of a semiconductor device as a second aspect of the second preferred embodiment; Fig. Figure 8 is a cross-sectional view illustrating a cross-section of a semiconductor device as a third aspect of the second preferred embodiment; Fig. Figure 9 is a cross-sectional view illustrating a cross-section of a semiconductor device as a first aspect of a third preferred embodiment; Fig. Figure 10 is a cross-sectional view illustrating a cross-section of a semiconductor device as a second aspect of the third preferred embodiment; Fig. Figure 11 is a cross-sectional view illustrating a cross-section of a semiconductor device as a first aspect of a fourth preferred embodiment; and Fig. Figure 12 is a cross-sectional view illustrating a cross-section of a semiconductor device as a second aspect of the fourth preferred embodiment. DESCRIPTION OF PREFERRED EXECUTION FORMS<Erste bevorzugte Ausführungsform> (Planar configuration and circuit configuration)

[0020] Fig. Figure 1 is an explanatory illustration schematically depicting a planar configuration of a semiconductor device 100 of a first preferred embodiment of the present invention. The semiconductor device 100 is used as a general term encompassing semiconductor devices 101 to 108 and semiconductor devices 201 and 202. Note that semiconductor devices 102 to 108, 201, and 202 are described in detail later. That is to say, a Fig. The structure illustrated in 1 is a planar structure common to semiconductor devices 101 to 108 and semiconductor devices 201 and 202, which are illustrated in the first to fourth preferred embodiments.

[0021] As in Fig. As illustrated in Figure 1, an N-type diffusion layer 30a is arranged at the outer periphery of a high-side switching region RH, and a P-type diffusion layer 40 is arranged surrounding the periphery of the N-type diffusion layer 30a in plan view. A combination of the N-type diffusion layer 30a and the P-type diffusion layer 40 serves as the first insulation region. A low-side switching region RL and the high-side switching region RH are electrically isolated by the N-type diffusion layer 30a and the P-type diffusion layer 40, which serve as the first insulation region. Therefore, both the N-type diffusion layer 30a and the P-type diffusion layer 40 serve as a first insulation diffusion region contained within the first insulation region. In the present description, a P-type is specified as the first conductivity type and an N-type is specified as the second conductivity type.

[0022] The high-side circuitry area RH comprises a first high-side circuitry area RH1 and a second high-side circuitry area RH2. A first high-side circuit CH1 is located in the first high-side circuitry area RH1, and a second high-side circuit CH2 is located in the second high-side circuitry area RH2.

[0023] Fig. Figure 2 is an explanatory diagram that schematically illustrates a circuit configuration of the semiconductor device 100. As illustrated in the drawing, the circuit configuration of the semiconductor device 100 comprises as its main components a low-side circuit CL, the first high-side circuit CH1, the second high-side circuit CH2, and a level-shifting circuit 6.

[0024] As described above, the low-side circuit CL is a circuit located in the low-side circuit area RL, the first high-side circuit CH1 is a circuit located in the first high-side circuit area RH1, and the second high-side circuit CH2 is a circuit located in the second high-side circuit area RH2.

[0025] The low-side circuit CL receives a ground potential (GND) as a reference potential and a low-side power supply voltage (VCC) as its operating voltage, again with ground potential (GND) as the reference potential. Ground potential (GND) serves as the first reference potential for the low-side circuit CL. Therefore, the low-side circuit CL operates at the low-side power supply voltage (VCC) based on ground potential (GND). The level-shifting circuit 6 performs signal transmission between the low-side circuit CL and the first high-side circuit area (RH1).

[0026] The first high-side circuit CH1 receives a high-side reference potential VS as its reference potential and a high-side power supply voltage VB1 as its operating voltage. Therefore, the first high-side circuit CH1 operates at the high-side power supply voltage VB1 based on the high-side reference potential VS.

[0027] The second high-side circuit, CH2, receives the high-side reference potential VS as its reference potential and a high-side power supply voltage VB2 as its operating voltage. Therefore, the second high-side circuit, CH2, operates at the high-side power supply voltage VB2, based on the high-side reference potential VS. The high-side power supply voltage VB2 is set to a voltage value that differs from that of the high-side power supply voltage VB1.

[0028] The high-side reference potential VS becomes a second common reference potential between the first and second high-side circuits CH1 and CH2. The high-side reference potential VS is a potential different from the ground potential GND and is electrically isolated from it, thus normally floating.

[0029] As described above, the first high-side circuit CH1 performs circuit operation with the high-side power supply voltage VB1 as the operating voltage, and the second high-side circuit CH2 performs circuit operation with the high-side power supply voltage VB2 as the operating voltage.

[0030] The high-side power supply voltage VB1 received by the first high-side circuit CH1 is a first power supply voltage, and the high-side power supply voltage VB2 received by the second high-side circuit CH2 is a second power supply voltage. As described above, the high-side power supply voltage VB1 (the first power supply voltage) and the high-side power supply voltage VB2 (the second power supply voltage) are set to different voltage levels.

[0031] Fig. Figure 1 mainly illustrates a top view of the periphery of the high-side circuit area RH in the semiconductor device 100. Fig. 1. A description relating to diffusion layers, which form a cross-sectional structure of Fig. 3 and the like, which will be described below, correspond, partially omitted. Furthermore, one is as described in Fig. 2. Level shifting circuit illustrated; 6. High breakdown voltage MOS used not illustrated.

[0032] As in Fig. As illustrated in Figure 1, an isolation area 7 is arranged in the high-side switching area RH1 at the outer circumference or outer periphery of the second high-side switching area RH2. The first high-side switching area RH1 and the second high-side switching area RH2 are electrically isolated by the isolation area 7.

[0033] The in Fig. 2 Illustrated semiconductor device 100 controls an IGBT 2 and an IGBT 3 connected in series. A collector of the IGBT 2 receives a high voltage HV, an emitter of the IGBT 2 and a collector of the IGBT 3 are connected at a node N1, and an emitter of the IGBT 3 is connected to ground potential GND.

[0034] The low-side circuit CL receives an external input signal IN and outputs a low-side control signal SL to a gate of IGBT 3. Simultaneously, the first high-side circuit CH1 outputs a high-side control signal SH to a gate of IGBT 2. A signal received at node N1 is fed to each of the first and second high-side circuits CH1 and CH2. Additionally, a signal is transmitted between the first and second high-side circuits CH1 and CH2.

[0035] The low-side switching area RL and the high-side switching area RH are isolated with a high breakdown voltage of 100 V or more by the N-type diffusion layer 30a and the P-type diffusion layer 40, respectively, which each serve as the first insulating diffusion layer. The low-side switching area RL and the high-side switching area RH are further isolated by a RESURF insulation structure that utilizes the N-type diffusion layer 30a as the second conductivity-type diffusion layer.

[0036] As described above, the low-side switching area RL and the high-side switching area RH are isolated from each other by the N-type diffusion layer 30a and the P-type diffusion layer 40, each serving as the first isolation diffusion area, so that there is no problem even if a voltage difference between the low-side switching area RL and the high-side switching area RH is 100 V or more.

[0037] The isolation area 7, which serves as a second isolation area, isolates the first high-side switching area RH1 and the second high-side switching area RH2 from each other with a breakdown voltage at a level of several tens of volts. The in Fig. One non-illustrated MOS with high breakdown voltage is arranged in the N-type diffusion layer 30a or the low-side switching area RL.

[0038] As described above, the first and second high-side switching areas RH1 and RH2 are isolated from each other by the isolation area 7, which serves as the second isolation area, so there is no problem if a voltage difference between the first high-side switching area RH1 and the second high-side switching area RH2 is approximately 10 V. (First aspect)

[0039] Fig. Figure 3 is a cross-sectional view that schematically illustrates a cross-sectional structure of the semiconductor device 101 as a first aspect of the first preferred embodiment. Fig. Figure 3 illustrates an AA cross-section of Fig. 1. Corresponding cross-sectional structure. The cross-sectional structure in Fig. 3 and the cross-sectional structures in Fig. Figures 4 to 12, which are to be described below, are schematically illustrated, and the shape, scale, dimension, and the like do not necessarily correspond to those of the cross-sectional structures that are actually produced.

[0040] As in Fig. As illustrated in Figure 3, the first and second high-side circuit regions RH1 and RH2 are arranged in an upper layer subregion of a P-type substrate 10, which is a first-conductivity semiconductor substrate. As shown in Fig. As illustrated in Figure 3, the first isolation layer for isolating the high-side switching area RH and the low-side switching area RL consists of the N-type diffusion layer 30a and the P-type diffusion layer 40, located in the upper layer region of the P-type substrate 10. The P-type diffusion layer 40 is positioned so that, in plan view, it surrounds the high-side switching area RH. The N-type diffusion layer 30a fulfills a RESURF condition.

[0041] A P + Diffusion layer 60 is located in part of the surface of diffusion layer 40 of the P type. The P + -Diffusion layer 60 is a layer to create contact between the P-type diffusion layer 40 and a (in Fig. 3 (not illustrated) metal wiring layer to produce. A N + Diffusion layer 50 is located in part of the surface of diffusion layer 30a of type N. The N +-Diffusion layer 50 is a layer to create contact between the N-type diffusion layer 30a and the (in Fig. 3 (not illustrated) metal wiring layer to produce. The N + -Diffusion layer 50 is located at a position on the surface of diffusion layer 30a of N type separated from the P-type diffusion layer 40 by a certain distance of several tens of µm or more.

[0042] A thermal oxide film 81 is on the surface of the N-type diffusion layer 30a between the P-type diffusion layer 40 and the N-type diffusion layer 50. + -type arranged. A polysilicon-containing field plate or a metal wiring layer is arranged on the thermal oxide film 81. Note that, for the sake of simplicity, the field plate is shown in Fig. Figure 3 is not illustrated. The field plate can be arranged over end regions of the thermal oxide film 81.

[0043] A diffusion layer 31a of N-type is arranged in the upper layer part region of the substrate 10 of P-type, which is the semiconductor substrate of the first conductivity type, in the first high-side switching region RH1, and a diffusion layer 32a of N-type is arranged in the upper layer part region of the substrate 10 of P-type in the second high-side switching region RH2.

[0044] The N-type diffusion layer 31a and the N-type diffusion layer 32a are formed simultaneously, and the N-type diffusion layer 30a is formed after the formation of the N-type diffusion layers 31a and 32a. The formation depth of each of the N-type diffusion layers 31a and 32a is greater than the diffusion depth of the N-type diffusion layer 30a, which is the first isolation diffusion region. The N-type diffusion layer 31a serves as the first circuit diffusion region, and the N-type diffusion layer 32a serves as the second circuit diffusion region. Therefore, the N-type diffusion layers 31a and 32a, which serve as the first and second circuit diffusion regions respectively, fulfill a requirement for the diffusion region depth that "a formation depth of each of the first and second circuit diffusion regions is deeper than a formation depth of the first isolation diffusion region".

[0045] A component element of the first high-side circuit CH1 is located in an upper layer sub-region of the N-type diffusion layer 31a, and a component element of the second high-side circuit CH2 is located in an upper layer sub-region of the N-type diffusion layer 32a. Fig. Figure 3 illustrates a case in which, for example, CMOS configurations are arranged as the component elements.

[0046] In the first high-side circuit region RH1, a P-type diffusion layer 41a is selectively arranged in the upper layer subregion of the N-type diffusion layer 31a. + -Diffusion layers 51 and 52 are selectively arranged in a surface of the diffusion layer 41a of the P-type and are N + Diffusion layers 51 and 52 are arranged at a specific interval of 0.1 µm or more. A polysilicon gate 90 is located above the P-type diffusion layer 41a between the N +Diffusion layers 51 and 52 are arranged with an intervening (not illustrated) gate oxide film. Furthermore, a diffusion layer 61 is separated from the P + -type arranged in a part of the surface of the diffusion layer 41a of the P-type and is the P + -Diffusion layer 61 a layer to establish contact between the P-type diffusion layer 41a and the (in Fig. 3 (not illustrated) metal wiring layer to be produced, and arranged so that it forms the N + -Diffusion layer 51 is adjacent.

[0047] Therefore, the diffusion layer 41a is of the P type and the N + -Diffusion layers 51 and 52, which are arranged in the upper layer part of the N-type diffusion layer 31a, the gate oxide film and the polysilicon gate 90, an NMOS transistor as a component element for the first high-side circuit CH1.

[0048] In the first high-side switching area RH1 are P +-Diffusion layers 62 and 63 are selectively arranged in the surface of the N-type diffusion layer 31a and are the P + Diffusion layers 62 and 63 are arranged at a specific interval of 0.1 µm or more. A polysilicon gate 91 is located above the N-type diffusion layer 31a between the P + -Diffusion layers 62 and 63 with an intermediate (not illustrated) gate insulating film. Furthermore, an N + -Diffusion layer 53 is arranged in a part of the surface of the N-type diffusion layer 31a. The N + -Diffusion layer 53 is a layer to establish contact between the N-type diffusion layer 31a and the (in Fig. 3 (not illustrated) metal wiring layer to produce, and arranged so that it forms the P + -Diffusion layer 63 is adjacent.

[0049] Therefore, the P +-Diffusion layers 62 and 63, which are arranged in the upper layer part of the N-type diffusion layer 31a, the gate oxide film and the polysilicon gate 91, a PMOS transistor as the main component for the first high-side circuit CH1.

[0050] A combined structure of the NMOS transistor and the PMOS transistor described above is a CMOS configuration located in the first high-side circuit area RH1. The first high-side circuit CH1 features this CMOS configuration.

[0051] On the other hand, in the second high-side circuit region RH2, a P-type diffusion layer 42a is selectively arranged in the upper layer part of the N-type diffusion layer 32a. + -Diffusion layers 55 and 56 are selectively arranged in the surface of the P-type diffusion layer 42a and are the N +Diffusion layers 55 and 56 are arranged at a specific interval of 0.1 µm or more. A polysilicon gate 93 is located above the P-type diffusion layer 42a between the N + Diffusion layers 55 and 56 are arranged with an intervening (not illustrated) gate oxide film. Furthermore, a P + -Diffusion layer 66 is arranged in a part of the surface of the P-type diffusion layer 42a. The P + -Diffusion layer 66 is a layer to establish contact between the P-type diffusion layer 42a and the (in Fig. 3 (not illustrated) metal wiring layer to be produced, and arranged so that it forms the N + -Diffusion layer 56 is adjacent.

[0052] Therefore, the diffusion layer 42a is of the P-type and the N +-Diffusion layers 55 and 56, which are arranged in the upper layer part of the N-type diffusion layer 32a, the gate oxide film and the polysilicon gate 93, an NMOS transistor as a component element for the second high-side circuit CH2.

[0053] In the second high-side switching area RH2 are P + -Diffusion layers 64 and 65 are selectively arranged in the surface of the N-type diffusion layer 32a and are the P + Diffusion layers 64 and 65 are arranged at a specific interval of 0.1 µm or more. A polysilicon gate 92 is located above the N-type diffusion layer 32a between the P + Diffusion layers 64 and 65 are arranged with an intervening (not illustrated) gate oxide film. Furthermore, an N + -Diffusion layer 54 is arranged in a part of the surface of the N-type diffusion layer 32a. An N +-Diffusion layer 54 is a layer to establish contact between the N-type diffusion layer 32a and the (in Fig. 3 (not illustrated) metal wiring layer to be produced and arranged so that it is the P + -Diffusion layer 64 is adjacent.

[0054] Therefore, the P + -Diffusion layers 64 and 65, which are arranged in the upper layer part of the N-type diffusion layer 32a, the gate oxide film and the polysilicon gate 92, a PMOS transistor as a component element for the second high-side circuit CH2.

[0055] A combination structure of the NMOS transistor and the PMOS transistor described above is a CMOS configuration located in the second high-side circuit area RH2. The second high-side circuit CH2 features this CMOS configuration.

[0056] In Fig. 3 is each of the N + -Diffusion layers 51, 52, 55 and 56 and the P +The diffusion layers 62 to 65, which serve as the drain or source of the MOS transistor with the CMOS configuration, are designed as a single drain structure. Considering a breakdown voltage between the drain and the source, a double-diffused drain structure (DDD) or a lightly doped drain structure (LDD) can be used instead of the single drain structure.

[0057] In substrate 10 of the P-type, there is a region in which the first and second high-side circuits CH1 and CH2 are not located; this is a circuit base region. The first high-side circuit CH1 is located in and on the N-type diffusion layer 31a, and the second high-side circuit CH2 is located in and on the N-type diffusion layer 32a.

[0058] In the first preferred embodiment, a P-type substrate region, which is the first conductivity type in the P-type substrate 10 and is located below the P-type diffusion layer 40, the N-type diffusion layer 30a, the N-type diffusion layer 31a, and the N-type diffusion layer 32a, is the circuit base region. Note that the P-type substrate region in the P-type substrate 10 is set to ground potential, which is the first reference potential.

[0059] In the semiconductor device 101, an isolation trench 70 is arranged in the isolation region 7. The isolation trench 70 is arranged between the N-type diffusion layer 31a, which serves as the first circuit diffusion region, and the N-type diffusion layer 32a, which serves as the second circuit diffusion region, and is arranged such that the deepest part reaches the P-type substrate region of the P-type substrate 10.

[0060] The N-type diffusion layer 31a and the N-type diffusion layer 32a are electrically insulated by the insulation trench 70. The insulation trench 70 is designed, for example, as follows.

[0061] A temporary N-type diffusion layer is formed in an upper layer sub-region encompassing the first and second high-side switching regions RH1 and RH2 and the isolation region 70 in the P-type substrate 10. Subsequently, the isolation trench 70 is formed such that it reaches the substrate sub-region from the surface of the P-type substrate 10, which contains the temporary N-type diffusion layer in isolation region 7. The temporary N-type diffusion layer is isolated between the first and second high-side switching regions RH1 and RH2 by the isolation trench 70 formed in this manner.

[0062] In the present description, "provisional" is used as a term that indicates a structure in an intermediate stage, which is not the completion stage.

[0063] Consequently, the temporary N-type diffusion layer remaining in the first high-side switching area RH1 serves as the N-type diffusion layer 31a, and the temporary N-type diffusion layer remaining in the second high-side switching area RH2 serves as the N-type diffusion layer 32a. Therefore, the N-type diffusion layer 31a and the N-type diffusion layer 32a are electrically isolated by the insulation trench 70.

[0064] The isolation trench 70 contains within it a buried insulating film 78, configured to insulate and isolate the first and second high-side switching areas RH1 and RH2 from each other. Two burial aspects are conceivable for the burying of the insulating film 78. The first burial aspect is one in which the isolation trench 70 is filled with the buried insulating film 78. The second burial aspect is one in which the buried insulating film 78 is selectively formed on a side wall within the isolation trench, and (not illustrated) polysilicon is filled into the isolation trench 70 containing the buried insulating film 78.

[0065] Note that the depth of the isolation trench 70 is specified, for example, as approximately a few micrometers to 20 micrometers, and its width as approximately 1 to 2 micrometers. The term "a few micrometers" means 2 to 3 micrometers.

[0066] If the buried insulating film 78 is arranged in the first burial aspect, a breakdown voltage between the first and second high-side switching regions RH1 and RH2 is ensured by an insulation breakdown voltage of the buried insulating film 78 with which the insulation trench 70 has been filled. In this case, the thickness of the buried insulating film 78 corresponds to the width of the insulation trench 70. If the buried insulating film 78 is arranged in the second burial aspect, the breakdown voltage between the first and second high-side switching regions RH1 and RH2 is ensured by the insulation breakdown voltage of the buried insulating film 78 arranged on the side wall of the insulation trench 70.

[0067] The high-side power supply voltage VB1 is supplied via the N +-Diffusion layer 53 is connected to the N-type diffusion layer 31a as the first circuit diffusion area, and the high-side power supply voltage VB2 is supplied via the N + Diffusion layer 54 is connected to the N-type diffusion layer 32a as the second circuit diffusion area. The high-side power supply voltages VB1 and VB2 are both high voltages of 100 V or more, and the potential difference between the high-side power supply voltage VB1 and the high-side power supply voltage VB2 is several volts to several tens of volts.

[0068] An insulating layer 88 is arranged to cover the entire surface of the semiconductor device 101. A metal wiring layer is arranged on the insulating layer 88, and the metal wiring layer is individually wired with both the N + -Diffusion layers 50 to 56, the P +The diffusion layers 60 to 66 and the polysilicon gates 90 to 93 are connected by a contact hole arranged to penetrate the insulating layer 88. Note that the metal wiring layer and the contact hole are shown in the drawing for simplicity. Fig. 3 are not illustrated. (Effects)

[0069] The N-type diffusion layer 31a arranged in the first high-side switching region RH1 and the N-type diffusion layer 32a arranged in the second high-side switching region RH2 are insulated in the horizontal direction by the RESURF insulation structure of the first insulation region including the N-type diffusion layer 30a and are insulated from the ground potential GND and a high voltage of 100 V or more in the vertical direction by a blocking bias of a PN junction between the P-type substrate region of the P-type substrate 10 and the N-type diffusion layers 31a and 32a.

[0070] The first and second high-side circuit regions RH1 and RH2 are both isolated to ground potential GND and a high voltage, and the n-type diffusion layer 31a of the first high-side circuit region RH1 and the n-type diffusion layer 32a of the second high-side circuit region RH2 are electrically isolated by the insulation trench 70 with the insulating film 78 buried inside, which serves as a dielectric.

[0071] The high-side power supply voltage VB1 applied to the N-type diffusion layer 31a corresponds to the first power supply voltage for the first high-side circuit CH1 arranged in the first high-side circuit area RH1, and the high-side power supply voltage VB2 applied to the N-type diffusion layer 32a corresponds to the second power supply voltage for the second high-side circuit CH2 arranged in the second high-side circuit area RH2.

[0072] As described above, in the semiconductor device 101, as the first aspect of the first preferred embodiment, the N-type diffusion layer 31a and the N-type diffusion layer 32a are electrically isolated by the insulation trench 70 and can thus operate the first and second high-side circuits CH1 and CH2 by means of the high-side power supply voltages in VB1 and VB2 respectively with the high-side reference potential VS as the common second reference potential.

[0073] The semiconductor device 101, as the first aspect of the first preferred embodiment, features the isolation trench 70 as the isolation area 7, which electrically isolates the first and second high-side circuit areas RH1 and RH2 from each other. Therefore, no problems arise in the semiconductor device 101 even when the first high-side circuit CH1, located in the first high-side circuit area RH1, is operated with the high-side power supply voltage VB1, which is the first power supply voltage, and the second high-side circuit CH2, located in the second high-side circuit area RH2, is operated with the high-side power supply voltage VB2, which is the second power supply voltage.

[0074] Therefore, in the semiconductor device 101, as the first aspect of the first preferred embodiment, the first and second high-side circuits CH1 and CH2, which operate with the different high-side power supply voltages VB1 and VB2 respectively, can be arranged in the high-side circuit area RH, which receives the high-side reference potential VS as the common second reference potential, while maintaining the miniaturization of the structure.

[0075] The two N-type diffusion layers 31a and 32a, which constitute the first and second circuit diffusion regions in the semiconductor device 101, respectively, meet the requirements for diffusion region depth. One requirement is that their formation depths are deeper than those of the N-type diffusion layer 30a, which forms the first isolation diffusion region. Therefore, in the semiconductor device 101, the breakdown voltage in the horizontal direction can be improved by the N-type diffusion layer 30a, which forms the first isolation region, and the breakdown voltage in the vertical direction can be improved by the N-type diffusion layers 31a and 32a.

[0076] The semiconductor device 101 can suppress parasitic operation between the first and the second high-side circuit CH1 and CH2 by means of the isolation trench 70 with the insulating film 78 buried therein. (Second aspect)

[0077] Fig. Figure 4 is a cross-sectional view that schematically illustrates a cross-sectional structure of the semiconductor device 102 as a second aspect of the first preferred embodiment. Fig. Figure 4 illustrates a cross-section of AA. Fig. 1 corresponding cross-sectional structure. Note that a planar configuration and a circuit configuration of the semiconductor device 102 correspond to the one in Fig. 1 and Fig. The two illustrated configurations are similar.

[0078] The following points, which differ from those in Fig. Since the semiconductor device 101 illustrated in the first aspect has in common the same reference symbols, its description may be omitted and predominantly characteristic points of the semiconductor device 102 of the second aspect are described.

[0079] The semiconductor device 102 contains buried N +-Diffusion layers 20 and 21 of the N-type are arranged in contact with a substrate region of the substrate 10 of the P-type as lower layer structures of the first and second high-side switching regions RH1 and RH2, respectively. That is, the buried N + -Diffusion layers 20 and 21, which are the first and second buried diffusion layers, are selectively arranged on the substrate area of ​​the P-type in the substrate 10 of the P-type.

[0080] In the following, a case in which a provisional epitaxial layer of N-type is formed as an intermediate stage is described as a first manufacturing procedure, and a case in which a provisional epitaxial layer of P-type is formed as an intermediate stage is described as a second manufacturing procedure.

[0081] If the first manufacturing process is adopted, in the Fig. 4 illustrated cross-sectional structure of the buried N +-Diffusion layers 20 and 21 are formed simultaneously in an upper layer sub-region of the P-type substrate 10, and subsequently the provisional N-type epitaxial layer is formed on the P-type substrate 10, which contains the buried N + The diffusion layer 40, containing diffusion layers 20 and 21, is formed. Subsequently, the P-type diffusion layer 40 is formed within the temporary N-type epitaxial layer outside the high-side switching area RH. The temporary N-type epitaxial layer remaining after the formation of the P-type diffusion layer 40 outside the high-side switching area RH serves as the N-type epitaxial layer 30b. The P-type diffusion layer 40 is positioned so that, in plan view, it surrounds the high-side switching area RH.

[0082] The N-type epitaxial layer 30b acts as one of the first isolation diffusion regions, and the P-type diffusion layer 40 and the N-type epitaxial layer 30b form a first isolation region. The low-side switching region RL and the high-side switching region RH are electrically isolated by the P-type diffusion layer 40 and the N-type epitaxial layer 30b. At this time, the N-type epitaxial layer 30b satisfies a RESURF condition.

[0083] Furthermore, a P-type diffusion layer 41b and an N-type diffusion layer 31b are selectively formed in the provisional N-type epitaxial layer in the first high-side circuit region RH1, and a P-type diffusion layer 42b and an N-type diffusion layer 32b are formed in the provisional N-type epitaxial layer in the second high-side circuit region RH2. At this time, the P-type diffusion layers 41b and 42b are formed such that they enclose the buried N + -Diffusion layers 20 and 21 are reached.

[0084] In the provisional N-type epitaxial layer, a remaining area after the formation of the P-type diffusion layer 40, the P-type diffusion layers 41b and 42b, and the N-type diffusion layers 31b and 32b serves as the N-type epitaxial layer 30b.

[0085] If, on the other hand, the second manufacturing process is adopted, the buried N + -Diffusion layers 20 and 21 in the upper layer region of the substrate 10 of P-type are formed at the same time, and a provisional epitaxial layer of P-type is then formed on the substrate 10 of P-type, which contains the buried N + -contains diffusion layers 20 and 21. Subsequently, an (not illustrated) N-type diffusion layer 30b2 is selectively formed in the provisional P-type epitaxial layer. The N-type diffusion layer 30b2 corresponds to the one in Fig. 4 illustrated epitaxial layer 30b of N-type and forms a RESURF area.

[0086] Furthermore, the P-type diffusion layer 40 is selectively formed within the P-type provisional epitaxial layer. The concentration of P-type defects in the P-type diffusion layer 40 is determined to be higher than the concentration of P-type defects in the P-type provisional epitaxial layer. Therefore, an area surrounded by the P-type diffusion layer 40 in plan view serves as the N-type diffusion layer 30b2.

[0087] Furthermore, the P-type diffusion layer 41b and the N-type diffusion layer 31b are selectively formed in the P-type provisional epitaxial layer in the first high-side circuit area RH1, and the P-type diffusion layer 42b and the N-type diffusion layer 32b are formed in the P-type provisional epitaxial layer in the second high-side circuit area RH2. At this time, the N-type diffusion layers 31b and 32b are formed in such a way that they enclose the buried N + -Diffusion layers 20 and 21 are reached.

[0088] If the first manufacturing process is adopted, the buried N + -Diffusion layers 20 and 21 in the intermediate stage are in contact with a lower surface of the provisional N-type epitaxial layer. Similarly, when the second manufacturing process is adopted, the buried N +-Diffusion layers 20 and 21 in the intermediate stage in contact with a lower surface of the provisional epitaxial layer of P-type.

[0089] As described above, the N-type diffusion layers 31b and 32b and the P-type diffusion layers 41b and 42b are arranged in the N-type or P-type provisional epitaxial layer.

[0090] In the case of the first manufacturing process, a portion of the provisional N-type epitaxial layer can be used as the N-type diffusion layers 31b and 32b. In this case, the provisional N-type epitaxial layer remaining after the formation of the P-type diffusion layer 41b in the first high-side switching area RH1 serves as N-type diffusion layer 31b, and the provisional N-type epitaxial layer remaining after the formation of the P-type diffusion layer 42b in the second high-side switching area RH2 serves as N-type diffusion layer 32b.

[0091] In the case of the second manufacturing process, a portion of the provisional P-type epitaxial layer can form the P-type diffusion layers 41b and 42b. In this case, the provisional P-type epitaxial layer remaining after the formation of the N-type diffusion layer 31b in the first high-side switching area RH1 serves as the P-type diffusion layer 41b, and the provisional P-type epitaxial layer remaining after the formation of the N-type diffusion layer 32b in the second high-side switching area RH2 serves as the P-type diffusion layer 42b.

[0092] In the semiconductor device 102, the isolation area 7 is provided with an isolation trench 71, which separates the N-type diffusion layers 31b and 32b and the buried N + -penetrates diffusion layers 20 and 21 and reaches the P-type substrate area in the P-type substrate 10.

[0093] The N-type diffusion layer 31b and the N-type diffusion layer 32b are electrically isolated by the insulation trench 71. The insulation trench 71 is formed, for example, as follows.

[0094] If the first manufacturing process is adopted, the isolation trench 71 in the isolation area 7 is formed such that it is separated from a surface of the substrate 10 of the P-type, which contains the provisional epitaxial layer of the N-type and the buried N + -Diffusion layers 20 and 21, reaching the substrate area. The buried N formed at the same time + -Diffusion layers 20 and 21 are electrically isolated by the insulation trench 71 formed in this way.

[0095] If the second manufacturing process is adopted, the isolation trench 71 in the isolation area 7 is formed such that it is separated from a surface of the substrate 10 of the P-type, which contains the provisional epitaxial layer of the P-type and the buried N + -Diffusion layers 20 and 21 contain the substrate area. The buried N + -Diffusion layers 20 and 21, which are formed at the same time, are electrically insulated by the insulation trench 71 formed in this way.

[0096] Furthermore, the N-type diffusion layers 31b and 32b can be isolated by the isolation trench 71, similar to the N-type diffusion layers 31a and 32a formed in the semiconductor device 101.

[0097] As described above, the semiconductor device 102 contains the buried N arranged on the substrate area of ​​the P-type substrate 10 + -Diffusion layer 20 and the one buried on the N+ -Diffusion layer 20 selectively arranged diffusion layer 31b of N-type as first circuit diffusion areas. The buried N + -Diffusion layer 20 serves as the first buried diffusion layer, and the N-type diffusion layer 31b serves as the first surface diffusion layer.

[0098] The semiconductor device 102 further includes as a second circuit diffusion area the buried N arranged on the substrate area of ​​the P-type substrate 10 + -Diffusion layer 21 and the one buried on the N + -Diffusion layer 21 selectively arranged diffusion layer 32b of N-type. The buried N + -Diffusion layer 21 serves as the second buried diffusion layer, and the N-type diffusion layer 32b serves as the second surface diffusion layer.

[0099] Note that the N + -Diffusion layer 53 and the P +Diffusion layers 62 and 63 are selectively arranged on a surface of diffusion layer 31b of the N type, similar to diffusion layer 31a. Furthermore, the N + -Diffusion layer 54 and the P + -Diffusion layers 64 and 65 similar to the N-type diffusion layer 32a are selectively arranged in a surface of the N-type diffusion layer 32b.

[0100] Note that the P + -Diffusion layer 61 and the N + Diffusion layers 51 and 52 are selectively arranged on a surface of diffusion layer 41b of type P, similar to diffusion layer 41a of type P. Furthermore, the P + -Diffusion layer 66 and the N + -Diffusion layers 55 and 56 similar to the P-type diffusion layer 42a are selectively arranged in a surface of the P-type diffusion layer 42b.

[0101] In the semiconductor device 102, the isolation trench 71 is arranged in the isolation area 7. The isolation trench 71 is located between the N-type diffusion layer 31b and the buried N + -Diffusion layer 20, which serve as the first circuit diffusion areas, and the N-type diffusion layer 32b and the buried N + -Diffusion layer 21, which serve as the second circuit diffusion areas, is arranged and is arranged such that the deepest sub-area reaches the P-type substrate area in the P-type substrate 10.

[0102] The N-type diffusion layer 31b and the buried N + -Diffusion layer 20 are separated by the isolation trench 71 from the diffusion layer 32b of N-type and the buried N + -Diffusion layer 21 electrically insulated.

[0103] Similar to the isolation trench 70, the isolation trench 71 contains inside the buried insulating film 78, which is configured to insulate and isolate the first and second high-side circuit areas RH1 and RH2 from each other.

[0104] The semiconductor device 102, as the second aspect of the first preferred embodiment, includes the isolation trench 71 as the isolation area 7, which isolates the first and second high-side circuit areas RH1 and RH2 from each other.

[0105] Therefore, in the semiconductor device 102, as the second aspect of the first preferred embodiment, the first and second high-side circuits CH1 and CH2, which operate with the high-side power supply voltages VB1 and VB2 respectively, can be arranged in the high-side circuit area RH1 with a miniaturization-preserving structure as in the semiconductor device 101.

[0106] In the semiconductor device 102, both the buried N + -Diffusion layer 20, which is the first buried diffusion layer, forming part of the first circuit diffusion area, as well as the buried N + -Diffusion layer 21, which is the second buried diffusion layer forming part of the second circuit diffusion area, has a formation depth that is deeper than that of diffusion layer 30 from N + -Type, which is the first isolation diffusion area.

[0107] The buried N + -Diffusion layer 20 and the N-type diffusion layer 31b form the first circuit diffusion area, and the buried N +The diffusion layer 21 and the N-type diffusion layer 32b form the second circuit diffusion region. Therefore, similar to the semiconductor device 101, the semiconductor device 102 also fulfills a requirement for the diffusion region depth that "the formation depth of each of the first and second circuit diffusion regions is deeper than the formation depth of the first isolation diffusion region".

[0108] Therefore, in the semiconductor device 102, a breakdown voltage in the horizontal direction can be improved by the N-type diffusion layer 30a forming the first insulation region, and a breakdown voltage in the vertical direction can be improved by a combination of the N-type diffusion layer 31b and the buried N + -Diffusion layer 20 and a combination of the N-type diffusion layer 32b and the buried N + -Diffusion layer 21 can be improved.

[0109] The semiconductor device 102, similar to the semiconductor device 101, can suppress parasitic operation between the first and second high-side circuits CH1 and CH2 by means of the isolation trench 71 with the insulating film 78 buried therein.

[0110] Furthermore, a first combination structure from the buried N can be formed in the semiconductor device 102. + The diffusion layer 20 and the diffusion layer 31b of the N type relatively easily fulfill the requirement for a diffusion area depth and can form a second combination structure from the buried N + The diffusion layer 21 and the diffusion layer 32b of the N type relatively easily meet the requirement for the diffusion area depth. (Third aspect)

[0111] Fig. Figure 5 is a cross-sectional view that schematically illustrates a cross-sectional structure of a semiconductor device 103 as a third aspect of the first preferred embodiment. Fig. Figure 5 illustrates a cross-section of AA. Fig. 1 corresponding cross-sectional structure. Note that a planar configuration and a circuit configuration of the semiconductor device 103 are shown in Fig. 1 and Fig. The two illustrated configurations are similar.

[0112] The following points are related to those in Fig. Since the semiconductor device 102 illustrated in the second aspect has the same reference symbols, its description may be omitted and predominantly characteristic points of the semiconductor device 103 of the third aspect are described.

[0113] The semiconductor device 103 of the third aspect has a structure in which the buried N+ -Diffusion layers 20 and 21 of the semiconductor device 102 by buried N + -Diffusion layers 22 and 23 are replaced and isolation trench 71 is replaced by isolation trench 72.

[0114] Therefore, the buried N + -Diffusion layer 22 as a first buried diffusion layer and serves the buried N + -Diffusion layer 23 as a second buried diffusion layer. That is, the buried N + -Diffusion layers 22 and 23 are selectively arranged on a substrate area of ​​the P-type substrate 10.

[0115] As in the second aspect, the N-type diffusion layer 31b serves as a first surface diffusion layer, and the N-type diffusion layer 32b serves as a second surface diffusion layer. That is, the N-type diffusion layer 31b is located on the buried N +-Diffusion layer 22 is selectively arranged, and the N-type diffusion layer 32b is on the buried N + -Diffusion layer 23 selectively arranged.

[0116] In the semiconductor device 102 of the second aspect, which is in Fig. As illustrated in section 4, the buried N + -Diffusion layers 20 and 21 are isolated by the isolation trench 71 and each of the buried N + -Diffusion layers 20 and 21 in contact with a side wall of the isolation trench 71.

[0117] On the other hand, in the semiconductor device 103 of the third aspect, the buried N + -Diffusion layers 22 and 23 are isolated by a pattern that was present at the time the buried N + -Diffusion layers 22 and 23 are formed, as in Fig. 5 illustrates that it is trained discreetly or independently.

[0118] Note that the buried N +-Diffusion layers 22 and 23 using a manufacturing process similar to that of the buried N + -Diffusion layers 20 and 21 are formed, except that the buried N + -Diffusion layers 22 and 23 are formed independently.

[0119] In the semiconductor device 103, the isolation area 7 is provided with the isolation trench 72, which penetrates the N-type diffusion layers 31b and 32b and the substrate area of ​​the P-type substrate 10 between the buried N + -Diffusion layers 22 and 23 are reached.

[0120] As in Fig. As illustrated in section 5, the buried N + -Diffusion layers 22 and 23 form a specific interval that is wider than the width of the isolation trench 72, and thus a side wall section of the isolation trench 72 is not connected to any of the buried N + -Diffusion layers 22 and 23 in contact.

[0121] The isolation trench 72 reaches the substrate area of ​​type P in the substrate 10 of type P; however, the deepest part of the isolation trench 72 is designed to be shallower than the deepest part of each of the buried N + -Diffusion layers 22 and 23.

[0122] That means that isolation trench 72 has no connection to any of the buried N + -Diffusion layers 22 and 23 have a contact relationship. The isolation trench 72 of the semiconductor device 103 then fulfills a requirement for the trench depth, which is a requirement that "a formation depth of the isolation trench 72 is shallower than a formation depth of each of the buried N + -Diffusion layers 22 and 23 are the first and second buried diffusion layers."

[0123] Similar to the isolation trenches 70 and 71, the isolation trench 72 contains inside the buried insulating film 78, which is configured to insulate and isolate the first and second high-side circuit areas RH1 and RH2 from each other.

[0124] The semiconductor device 103, as the third aspect of the first preferred embodiment, has the isolation trench 72 as the isolation area 7, which isolates the first and second high-side circuit areas RH1 and RH2 from each other.

[0125] Therefore, in the semiconductor device 103, as the third aspect of the first preferred embodiment, the first and second high-side circuits CH1 and CH2, which operate with the high-side power supply voltages VB1 and VB2 respectively, can be provided in the high-side circuit area RH as in the semiconductor devices 101 and 102 with a structure that retains miniaturization.

[0126] In the semiconductor device 103, both the buried N + -Diffusion layer 22, which is the first buried diffusion layer forming part of the first circuit diffusion area, as well as the buried N + -Diffusion layer 23, which is the second buried diffusion layer forming part of a second circuit diffusion area, has a depth of formation that is deeper than that of the N-type epitaxial layer 30b, which is a first isolation diffusion area.

[0127] The buried N + -Diffusion layer 22 and the N-type diffusion layer 31b form the first circuit diffusion area, and the buried N +The diffusion layer 23 and the N-type diffusion layer 32b form the second circuit diffusion region. Therefore, the semiconductor device 103, similar to the semiconductor devices 101 and 102, also fulfills a requirement for the diffusion region depth that "the formation depth of each of the first and second circuit diffusion regions is deeper than the formation depth of the first isolation diffusion region".

[0128] Therefore, in the semiconductor device 103, a breakdown voltage in the horizontal direction can be improved by the epitaxial layer 30b of N-type forming a first insulation region, and a breakdown voltage in the vertical direction can be improved by a first combination of the diffusion layer 31b of N-type and the buried N + -Diffusion layer 22 and a second combination of the N-type diffusion layer 32b and the buried N + -Diffusion layer 23 can be improved.

[0129] The semiconductor device 103, similar to the semiconductor devices 101 and 102, can suppress parasitic operation between the first and second high-side circuits CH1 and CH2 by means of the isolation trench 72 with the insulating film 78 buried therein.

[0130] Furthermore, a first combination structure from the buried N can be formed in the semiconductor device 103. + -Diffusion layer 22 and diffusion layer 31b from N + -Type relatively easily fulfills the requirement for the diffusion area depth and can form a second combination structure from the buried N + The diffusion layer 23 and the diffusion layer 32b of the N type relatively easily meet the requirement for the diffusion area depth.

[0131] Since the isolation trench 72 of the semiconductor device 103, as the third aspect of the first preferred embodiment, fulfills the requirement for the trench depth, a process load at the time of the formation of the isolation trench 72 can be reduced to such an extent that the formation depth of the isolation trench 72 can be kept relatively shallow.

[0132] Furthermore, in the semiconductor device 103, the side wall section of the isolation trench 72 is not connected to any of the buried N + -Diffusion layers 22 and 23 are in contact and a discrete distance is maintained between the buried N + The diffusion layers 22 and 23 are positioned such that it is relatively long. Therefore, the semiconductor device 103 can control the degree of electrical insulation between the buried N + -Further increase diffusion layers 22 and 23. <Zweite bevorzugte Ausführungsform> (First aspect)

[0133] Fig. Figure 6 is a cross-sectional view that schematically illustrates a cross-sectional structure of a semiconductor device 104 as a first aspect of the second preferred embodiment. Fig. Figure 6 illustrates a cross-section of AA. Fig. 1 corresponding cross-sectional structure. Note that a planar configuration and a circuit configuration of the semiconductor device 104 are shown in Fig. 1 and Fig. The two illustrated configurations are similar.

[0134] The following points, which differ from those of the in Fig. 3 illustrated semiconductor device 101 of the first aspect of the first preferred embodiment are designated with the same reference numerals, their description may be omitted, and predominantly characteristic points of the semiconductor device 104 of the first aspect of the second preferred embodiment are described.

[0135] In addition to the structure of the semiconductor device 101, the semiconductor device 104 further comprises a P-type diffusion layer 110 arranged in contact with the deepest part of the isolation trench 70 at the periphery of the deepest part of the isolation trench 70 in a substrate region of the substrate 10 of the P-type. The P-type diffusion layer 110 serves as a trench bottom diffusion region. In the Fig. In the illustrated structure 6, an upper surface of the P-type diffusion layer 110 is located at a position higher than the lower surfaces of the N-type diffusion layers 31a and 32a, and the P-type diffusion layer 110 also has a contact relationship with the N-type diffusion layers 31a and 32a.

[0136] The concentration of P-type defects in the P-type diffusion layer 110 is adjusted to be higher than the concentration of P-type defects in the substrate area of ​​the P-type substrate 10.

[0137] After an empty trench for the isolation trench 70 is formed in a step by trench etching, a step is carried out to produce the P-type diffusion layer 110 before the buried insulating film 78 is formed in the isolation trench 70. The P-type diffusion layer 110 is formed by ion implantation, diffusion treatment, or the like from P-type defects above the P-type substrate 10 through the empty isolation trench 70.

[0138] The semiconductor device 104, as the first aspect of the second preferred embodiment, exhibits effects similar to those of the semiconductor device 101, as the first aspect of the first preferred embodiment, and further exhibits the following unique effect.

[0139] Since the semiconductor device 104, as the first aspect of the second preferred embodiment, has the P-type diffusion layer 110, which is the trench bottom diffusion layer, it is possible to suppress a leakage current due to a parasitic bipolar transistor passing through a P-type substrate region in the P-type substrate 10.

[0140] The parasitic bipolar transistor in the semiconductor device 101, as the first aspect of the first preferred embodiment, is a parasitic NPN bipolar transistor formed by the N-type diffusion layer 31a, the P-type substrate region within the P-type substrate 10, and the N-type diffusion layer 32a. That is, the operation of the parasitic NPN bipolar transistor described above can be considered as parasitic operation in the semiconductor device 101. However, in the semiconductor device 104, as the first aspect of the second preferred embodiment, the P-type diffusion layer 110 is arranged in a base region of the parasitic NPN bipolar transistor.

[0141] As described above, since the P-type diffusion layer 110 is arranged with a relatively high concentration of P-type impurities at the bottom of the insulation trench 70 in the semiconductor device 104, the current gain hFE of the NPN bipolar transistor passing through the P-type substrate area in the P-type substrate 10 can be reduced, and the leakage current between the first and second high-side circuit areas RH1 and RH2, generated by the operation of the parasitic NPN bipolar transistor, can be suppressed. (Second aspect)

[0142] Fig. Figure 7 is a cross-sectional view that schematically illustrates a cross-sectional structure of a semiconductor device 105 as the second aspect of the second preferred embodiment. Fig. Figure 7 illustrates a cross-section of AA. Fig. 1 corresponding cross-sectional structure. Note that a planar configuration and a circuit configuration of the semiconductor device 105 are shown in Fig. 1 and Fig. The two illustrated configurations are similar.

[0143] The following points, which differ from those of the semiconductor device 102 of the second aspect of the first preferred embodiment, which is described in Fig. As illustrated in Figure 4, the components in common are designated with the same reference numerals; their description may be omitted and predominantly characteristic points of the semiconductor device 105 of the second aspect of the second preferred embodiment are described.

[0144] In addition to the structure of the semiconductor device 102, the semiconductor device 105 also features a P-type diffusion layer 111 arranged in contact with the deepest part of the isolation trench 71 at the periphery of the deepest part of the isolation trench 71 in a substrate region of the P-type substrate 10. The P-type diffusion layer 111 serves as a trench bottom diffusion region. In the Fig. In the illustrated structure 7, an upper surface of the P-type diffusion layer 111 is located at a position higher than the lower surfaces of the buried N + -Diffusion layers 20 and 21 are located, and the P-type diffusion layer 111 also exhibits a contact relationship with the buried N + -Diffusion layers 20 and 21.

[0145] A concentration of P-type defects in the P-type diffusion layer 111 is set such that it is higher than a concentration of P-type defects in the substrate area of ​​the P-type substrate 10.

[0146] After an empty trench for the isolation trench 71 is formed in a step by trench etching, a step is carried out to produce the P-type diffusion layer 111 before the buried insulating film 78 is formed in the isolation trench 71. The P-type diffusion layer 111 is formed by ion implantation, diffusion treatment, or the like from P-type defects above the P-type substrate 10 through the empty isolation trench 71.

[0147] As a further step towards producing the P-type diffusion layer 111, in a case where the first manufacturing process is adopted at the time of manufacturing the semiconductor device 102, it is conceivable to selectively form the P-type diffusion layer 111 as a buried diffusion layer in an upper layer region of the P-type substrate 10 before forming a provisional N-type epitaxial layer.

[0148] The semiconductor device 105, as the second aspect of the second preferred embodiment, has effects similar to those of the semiconductor device 102, as the second aspect of the first preferred embodiment, and further exhibits the following unique effect.

[0149] Since the semiconductor device 105, as the second aspect of the second preferred embodiment, has the P-type diffusion layer 111, which is the trench bottom diffusion region, it is possible, as in the first aspect of the second preferred embodiment, to suppress a leakage current due to a parasitic bipolar transistor passing through a P-type substrate region in the P-type substrate 10.

[0150] The parasitic bipolar transistor in the semiconductor device 102, as the second aspect of the first preferred embodiment, is a parasitic NPN bipolar transistor that is controlled by the buried N + -Diffusion layer 20, the substrate area of ​​the P-type substrate 10 of the P-type and the buried N +-Diffusion layer 21 is formed. That is, operation of the parasitic NPN bipolar transistor described above can be considered as parasitic operation assumed in the semiconductor device 102. However, in the semiconductor device 105, as the second aspect of the second preferred embodiment, the P-type diffusion layer 111 is arranged in a base region of the parasitic NPN bipolar transistor. (Third aspect)

[0151] Fig. Figure 8 is a cross-sectional view that schematically illustrates a cross-sectional structure of a semiconductor device 106 as a third aspect of the second preferred embodiment. Fig. Figure 8 illustrates a cross-section of AA. Fig. 1 corresponding cross-sectional structure. Note that a planar configuration and a circuit configuration of the semiconductor device 106 are shown in Fig. 1 and Fig. The two illustrated configurations are similar.

[0152] The following points, which correspond to those of the semiconductor device 103 of the third aspect of the first preferred embodiment, which is described in Fig. 5 is illustrated, which are common, designated with the same reference numerals, their description is omitted if necessary and characteristic points of the semiconductor device 106 of the third aspect of the second preferred embodiment are predominantly described.

[0153] In addition to the structure of the semiconductor device 103, the semiconductor device 106 further comprises a P-type diffusion layer 112 arranged in contact with the deepest part of the isolation trench 72 at the periphery of the deepest part of the isolation trench 72 in a substrate region of the substrate 10 of the P-type. The P-type diffusion layer 112 serves as a trench bottom diffusion region.

[0154] In the Fig. In the structure illustrated in Figure 8, the P-type diffusion layer 112 also exhibits a contact relationship with the N-type diffusion layers 31b and 32b. Furthermore, the P-type diffusion layer 112 is located in a substrate region of the P-type substrate 10 between the buried N + -Diffusion layers 22 and 23 arranged.

[0155] A concentration of P-type defects in the P-type diffusion layer 112 is set such that it is higher than a concentration of P-type defects in the substrate area of ​​the P-type substrate 10.

[0156] After an empty trench for the isolation trench 72 has been formed by trench etching in a step to create the isolation trench 72, a step to produce the P-type diffusion layer 112 is carried out before the buried insulating film 78 is formed in the isolation trench 72. The P-type diffusion layer 112 is formed by ion implantation, diffusion treatment, or the like from P-type defects above the P-type substrate 10 through the empty isolation trench 72.

[0157] As a further step towards producing the P-type diffusion layer 112, in a case where a first manufacturing process for forming a provisional N-type epitaxial layer is adopted in an intermediate stage during the production of the semiconductor device 103, it is conceivable to selectively form the P-type diffusion layer 112 as a buried diffusion layer in an upper layer region of the P-type substrate 10 before forming a provisional N-type epitaxial layer.

[0158] The semiconductor device 106, as the third aspect of the second preferred embodiment, exhibits effects similar to those of the semiconductor device 103, as the third aspect of the first preferred embodiment, and further exhibits the following unique effect.

[0159] Since the semiconductor device 106, as the third aspect of the second preferred embodiment, includes the P-type diffusion layer 112, which is the trench bottom diffusion region, it is possible to suppress a leakage current due to a parasitic bipolar transistor passing through a P-type substrate region in the P-type substrate 10, as in the first and second aspects of the second preferred embodiment.

[0160] The parasitic bipolar transistor in the semiconductor device 103, as the third aspect of the first preferred embodiment, is a parasitic NPN bipolar transistor that is controlled by the buried N + -Diffusion layer 22, the substrate area of ​​P-type in substrate 10 of P-type and the buried N +-Diffusion layer 23 is formed. That is, operation of the parasitic NPN bipolar transistor described above can be considered as parasitic operation assumed in the semiconductor device 103. However, in the semiconductor device 106, as the third aspect of the second preferred embodiment, the P-type diffusion layer 112 is arranged in a base region of the parasitic NPN bipolar transistor. <Dritte bevorzugte Ausführungsform> (First aspect)

[0161] Fig. Figure 9 is a cross-sectional view that schematically illustrates a cross-sectional structure of the semiconductor device 107 as the first aspect of the third preferred embodiment. Fig. Figure 9 illustrates a cross-section of AA. Fig. 1 corresponding cross-sectional structure. Note that a planar configuration and a circuit configuration of the semiconductor device 107 are shown in Fig. 1 and Fig. The two illustrated configurations are similar.

[0162] The following points are discussed that are distinct from those of the semiconductor device 101 of the first aspect of the first preferred embodiment, which is described in Fig. 3 is illustrated, which are common, designated with the same reference numerals, their description is omitted if necessary and predominantly characteristic points of the semiconductor device 107 of the first aspect of the third preferred embodiment are described.

[0163] In the semiconductor device 107, a P-type layer 11 is arranged in place of the isolation trench 70 of the semiconductor device 101, an N-type diffusion layer 33a is arranged in place of the N-type diffusion layer 31a, and an N-type diffusion layer 34a is arranged in place of the N-type diffusion layer 32a.

[0164] The semiconductor device 107, as the first aspect of the third preferred embodiment, includes the P-type layer 11, which serves as the second isolation diffusion region, as the isolation region 7. The P-type layer 11 is arranged between the N-type diffusion layer 33a, which serves as the first circuit diffusion region, and the N-type diffusion layer 34a, which serves as the second circuit diffusion region, such that it is in contact with each of the N-type diffusion layers 33a and 34a.

[0165] The following describes a first and a second fabrication process for layer 11 of the P-type. The first fabrication process is a method for the selective formation of the N-type diffusion layers 33a and 34a in an upper layer region of the substrate 10 of the P-type. A remaining area on the surface of the substrate 10 of the P-type, in which the N-type diffusion layers 33a and 34a are not formed, serves as layer 11 of the P-type.

[0166] The second manufacturing process is a method for forming layer 11 of the P-type with a higher concentration of defects of the P-type than a substrate region of the substrate 10 of the P-type in the upper layer region of the substrate 10 of the P-type by means of ion implantation, diffusion treatment or the like.

[0167] If the second manufacturing process is adopted, the N-type diffusion layers 33a and 34a can be produced using a manufacturing process similar to that of the N-type diffusion layers 31a and 32a.

[0168] Note that the N + -Diffusion layer 53 and the P + -Diffusion layers 62 and 63 are selectively arranged in a surface of the N-type diffusion layer 33a, similar to the N-type diffusion layers 31a and 31b. Furthermore, the N + -Diffusion layer 54 and the P + Diffusion layers 64 and 65 are selectively arranged in a surface of the N-type diffusion layer 34a, similar to the N-type diffusion layers 32a and 32b. Furthermore, after the formation of the N-type diffusion layer 30a, a thermal oxide film 84 arranged on the P-type layer 11 is formed simultaneously with the thermal oxide film 81.

[0169] The semiconductor device 107, as the first aspect of the third preferred embodiment, exhibits effects similar to those of the semiconductor device 101 of the first aspect of the first preferred embodiment and further exhibits the following unique effect.

[0170] The semiconductor device 107 contains the P-type layer 11, which is the second isolation diffusion area arranged in contact with each of the N-type diffusion layers 33a and 34a, between the N-type diffusion layer 33a serving as the first circuit diffusion area and the N-type diffusion layer 34a serving as the second circuit diffusion area.

[0171] Since the semiconductor device 107, as the first aspect of the third preferred embodiment, has the P-type layer 11 in the isolation region 7 as the second isolation diffusion region, the first and second high-side circuit regions RH1 and RH2 can be electrically isolated from each other with a relatively simple structure.

[0172] Since the P-type layer 11 has an electrical connection with the P-type substrate region of the P-type substrate 10, its potential is the ground potential GND, and the N-type diffusion layers 33a and 34a, which receive the high-side power supply voltages VB1 and VB2 respectively, have high voltages of 100 V or more, so that a PN junction between the N-type diffusion layers 33a and 34a and the P-type substrate 10 and the P-type layer 11 is put into a reverse bias state.

[0173] Therefore, the first and second high-side switching regions RH1 and RH2 are electrically isolated from each other by the blocking bias of the PN junction.

[0174] The P-type layer 11 can be formed in a single step of a wafer process (WP) without an additional step, or by adding a relatively small number of steps such as photogravure, ion implantation, and subsequent diffusion treatment. That is, in a single step for forming the P-type layer 11, a process load can be reduced compared to the step for forming the isolation trenches 70 to 72 described in the first or second preferred embodiment. (Second aspect)

[0175] Fig. Figure 10 is a cross-sectional view that schematically illustrates a cross-sectional structure of a semiconductor device 108 as the second aspect of the third preferred embodiment. Fig. Figure 10 illustrates a cross-section of AA. Fig. 1 corresponding cross-sectional structure. Note that a planar configuration and a circuit configuration of the semiconductor device 108 are shown in Fig. 1 and Fig. The two illustrated configurations are similar.

[0176] The following points, which are those of the semiconductor device 103 of the third aspect of the first preferred embodiment, which is described in Fig. 5 is illustrated, which are common, designated with the same reference numerals, their description is omitted if necessary and predominantly characteristic points of the semiconductor device 108 of the second aspect of the third preferred embodiment are described.

[0177] In the semiconductor device 108, a P-type layer 12 is arranged in place of the isolation trench 72 of the semiconductor device 103, an N-type diffusion layer 33b is arranged in place of the N-type diffusion layer 31b, and an N-type diffusion layer 34b is arranged in place of the N-type diffusion layer 32b. Therefore, the N-type diffusion layer 33b serves as the first surface diffusion layer, and the N-type diffusion layer 34b serves as the second surface diffusion layer.

[0178] The semiconductor device 108, as the second aspect of the third preferred embodiment, is provided with the P-type layer 12, which serves as the second isolation diffusion region, namely the isolation region 7. The P-type layer 12 is located between a first combination structure consisting of the N-type diffusion layer 33b and the buried N +-Diffusion layer 22, which serves as the first circuit diffusion area, and a second combination structure consisting of the N-type diffusion layer 34b and the buried N + Diffusion layer 23, which serves as the second circuit diffusion area, is arranged. The P-type layer 12 has a contact relationship with the N-type diffusion layers 33b and 34b and the buried N + -Diffusion layers 22 and 23 and serves as the second isolation diffusion area.

[0179] Note that the N + -Diffusion layer 53 and the P + -Diffusion layers 62 and 63 are selectively arranged in a surface of the N-type diffusion layer 33b, similar to the N-type diffusion layers 31a, 31b and 33a. Furthermore, the N + -Diffusion layer 54 and the P +-Diffusion layers 64 and 65 are selectively arranged in a surface of the N-type diffusion layer 34b similar to the N-type diffusion layers 32a, 32b and 34a.

[0180] The following describes a first and a second manufacturing process for layer 12 of the P-type. The first manufacturing process is a method for forming a temporary epitaxial layer of the N-type on the substrate 10 of the P-type and subsequently forming layer 12 of the P-type by means of ion implantation, a diffusion treatment or the like from the interior of the temporary epitaxial layer of the N-type to a substrate region of the substrate 10 of the P-type.

[0181] The second manufacturing process is a method for forming a provisional P-type epitaxial layer on the P-type substrate 10 and forming the P-type layer 12 as the remaining layer after forming the N-type diffusion layers 33b and 34b in the provisional P-type epitaxial layer. In this case, the concentration of P-type defects in the provisional P-type epitaxial layer must be adjusted to a concentration equal to or higher than the concentration of p-type defects in the substrate region of the P-type substrate 10.

[0182] Note that the N-type diffusion layers 33b and 34b can be fabricated similarly to the N-type diffusion layers 31b and 32b of the semiconductor device 103.

[0183] The semiconductor device 108, as the second aspect of the third preferred embodiment, exhibits effects similar to those of the semiconductor device 103, as the third aspect of the first preferred embodiment, and further exhibits the following unique effect.

[0184] The semiconductor device 108 contains the P-type layer 12 between the first combination structure of the N-type diffusion layer 33b and the buried N + -Diffusion layer 22, which serves as the first circuit diffusion area, and the second combination structure of the N-type diffusion layer 34b and the buried N + -Diffusion layer 23, which serves as the second circuit diffusion area. The P-type layer 12 has a contact relationship with each of the N-type diffusion layers 33b and 34b and the buried N + -Diffusion layers 22 and 23.

[0185] Since the semiconductor device 108, as the second aspect of the third preferred embodiment, contains the P-type layer 12 in the isolation region 7 as the second isolation diffusion region, the first and second high-side circuit regions RH1 and RH2 can be electrically isolated from each other with a relatively simple structure.

[0186] Since the P-type layer 12 has an electrical connection with the P-type substrate region in the P-type substrate 10, its potential is the ground potential GND, and the N-type diffusion layers 33b and 34b, which receive the high-side power supply voltages VB1 and VB2 respectively, have high voltages of 100 V or more, so that a PN junction between the N-type diffusion layers 33b and 34b and the P-type substrate 10 and the P-type layer 12 is put into a reverse bias state.

[0187] Therefore, the first and second high-side switching regions RH1 and RH2 are electrically isolated from each other by the blocking bias of the PN junction.

[0188] Similar to layer 11 of the P-type, layer 12 of the P-type can be formed without an additional step in a single WP step or by adding a relatively small number of steps such as photogravure, ion implantation, and subsequent diffusion treatment. This means that in a single step to form layer 12 of the P-type, the process load can be reduced compared to the step to form the isolation trenches 70 to 72 described in the first or second preferred embodiment. <Vierte bevorzugte Ausführungsform> (First aspect)

[0189] Fig. Figure 11 is a cross-sectional view that schematically illustrates a cross-sectional structure of a semiconductor device 201 as the first aspect of the fourth preferred embodiment. Fig. Figure 11 illustrates a cross-section of AA. Fig. 1 corresponding cross-sectional structure. Note that a planar configuration and a circuit configuration of the semiconductor device 201 correspond to the one in Fig. 1 and Fig. The two illustrated configurations are similar.

[0190] The following points are discussed that are distinct from those of the semiconductor device 101 of the first aspect of the first preferred embodiment, which is described in Fig. 3 is illustrated, which are common, designated with the same reference numerals, their description is omitted if necessary and predominantly characteristic points of the semiconductor device 201 of the first aspect of the fourth preferred embodiment are described.

[0191] In semiconductor device 201, instead of the P-type substrate 10 of semiconductor device 101, an SOI substrate 9, generally referred to as a SOl wafer, is used as the semiconductor substrate. The SOl substrate 9 has a laminate structure consisting of a support substrate 10a, a buried oxide film 120, and an SOI layer 130, with the SOI layer 130 being the top layer of the SOI substrate 9. Fig. 11 is a conductivity type of the support substrate 10a, a P-type, but it can be an N-type. The SOI substrate 130, which is an active silicon layer, is configured as, for example, the N-type.

[0192] As in Fig. As illustrated in Figure 11, the first and second high-side switching areas RH1 and RH2 are arranged in SOI layer 130. As shown in Fig. As illustrated in Figure 11, an N-type diffusion layer 30c and a P-type diffusion layer 40 are arranged in the SOL substrate as first insulation regions for isolating the high-side switching region RH and the low-side switching region RL. The P-type diffusion layer 40 is arranged so that it surrounds the high-side switching region RH in plan view. The N-type diffusion layer 30c fulfills a RESURF condition. Similar to the N-type diffusion layer 30a, the N + -Diffusion layer 50 arranged in a surface of the diffusion layer 30c of N-type.

[0193] A diffusion layer 31c of N-type is arranged in the SOI layer 130 in the first high-side switching area RH1, and a diffusion layer 32c of N-type is arranged in the SOI layer 130 in the second high-side switching area RH2.

[0194] The N-type diffusion layer 31c and the N-type diffusion layer 32c are formed simultaneously. The N-type diffusion layer 30c serves as the first isolation diffusion layer, the N-type diffusion layer 31c serves as the first circuit diffusion layer, and the N-type diffusion layer 32c serves as the second circuit diffusion layer.

[0195] Component elements of the first high-side circuit CH1 are located in the upper layer sub-regions of the N-type diffusion layer 31c and a P-type diffusion layer 41c, similar to the N-type diffusion layer 31b and the P-type diffusion layer 41b, respectively, of the in Fig. 4 illustrated semiconductor device 102, and component elements of the second high-side circuit CH2 are arranged in upper circuit sub-regions of the N-type diffusion layer 32c and the diffusion layer 42c similar to the N-type and P-type diffusion layers 32b and 42b respectively of the in Fig. 4 illustrated semiconductor device 102 arranged.

[0196] In the SOl substrate 9, which serves as the semiconductor substrate of the fourth preferred embodiment, a region in which the first and second high-side circuits CH1 and CH2 are not arranged serves as the circuit base region. The first high-side circuit CH1 is arranged in the N-type diffusion layer 31c, in the P-type diffusion layer 41c, on the N-type diffusion layer 31c, and on the P-type diffusion layer 41c. The second high-side circuit CH2 is arranged in the N-type diffusion layer 32c, in the P-type diffusion layer 42c, on the N-type diffusion layer 32c, and on the P-type diffusion layer 42c.

[0197] In the semiconductor device 201, the support substrate 10a and the buried oxide film 120 serve as circuit base regions. The P-type diffusion layer 40, the N-type diffusion layer 30c, the N-type diffusion layer 31c, the N-type diffusion layer 32c, the P-type diffusion layer 41c, and the P-type diffusion layer 42c are arranged in the SOI layer 130 and not in the support substrate 10a and the buried oxide film 120. Therefore, the support substrate 10a and the buried oxide film 120 serve as the circuit base regions.

[0198] Note that in a case where the conductivity type of SOI layer 130, which is the active silicon layer, is N-type, the remaining areas after the diffusion layer 40 of P-type, the diffusion layer 41c of P-type and the diffusion layer 42c of P-type in SOI layer 130 may be the diffusion layer 30c of N-type, the diffusion layer 31c of N-type and the diffusion layer 32c of N-type.

[0199] Note that the N + -Diffusion layer 53 and the P + -Diffusion layers 62 and 63 are selectively arranged in a surface of the N-type diffusion layer 31c, similar to the N-type diffusion layers 31a, 31b, 33a and 33b. Furthermore, the N + -Diffusion layer 54 and the P + -Diffusion layers 64 and 65 are selectively arranged in a surface of the N-type diffusion layer 32c similar to the N-type diffusion layers 32a, 32b, 34a and 34b.

[0200] Note that the P + -Diffusion layer 61 and the N + Diffusion layers 51 and 52 are selectively arranged on a surface of diffusion layer 41c of P-type, similar to diffusion layers 41a and 41b. Furthermore, the P + -Diffusion layer 66 and the N + -Diffusion layers 55 and 56 similar to diffusion layers 42a and 42b are selectively arranged in a surface of the P-type diffusion layer 42c.

[0201] In the semiconductor device 201, an isolation trench 73 is arranged in the isolation region 7. The isolation trench 73 is arranged between the N-type diffusion layer 31c, which serves as the first circuit diffusion region, and the N-type diffusion layer 32c, which serves as the second circuit diffusion region, and is arranged such that the deepest part reaches an upper surface of the buried oxide film 120.

[0202] The N-type diffusion layer 31c and the N-type diffusion layer 32c are electrically insulated by the insulation trench 73. The insulation trench 73 is formed, for example, as follows.

[0203] After a temporary N-type diffusion layer is formed in the SOI layer 130 in an area containing the first and second high-side circuit regions RH1 and RH2 and the isolation region 7, the isolation trench 73 is formed in the isolation region 7 such that it reaches the upper surface of the buried oxide film 120 from a surface of the SOI layer 130 containing the temporary N-type diffusion layer. The temporary N-type diffusion layer is isolated by the isolation trench 73 between the first and second high-side circuit regions RH1 and RH2.

[0204] Consequently, the temporary N-type diffusion layer remaining in the high-side switching area RH1 serves as the N-type diffusion layer 31c, and the temporary N-type diffusion layer remaining in the second high-side switching area RH2 serves as the N-type diffusion layer 32c. Therefore, the N-type diffusion layer 31c and the N-type diffusion layer 32c are electrically isolated by the insulation trench 73.

[0205] The isolation trench 73 contains, similar to the isolation trenches 70 to 72 of the first and second preferred embodiments, the buried insulating film 78 inside. (Effects)

[0206] The semiconductor device 201, as the first aspect of the fourth preferred embodiment, exhibits effects similar to those of the semiconductor device 101, as the first aspect of the first preferred embodiment, and further exhibits the following unique effect.

[0207] Since the semiconductor device 201, as the first aspect of the fourth preferred embodiment, is insulated in the depth direction into the SOI layer 130 and the support substrate 10a by the buried oxide film 120, which is a dielectric, a leakage current between the first and second high-side switching areas RH1 and RH2 can be further reduced.

[0208] Furthermore, the semiconductor device 201 can suppress parasitic operation between the first and the second high-side switching area RH1 and RH2 by means of the isolation trench 73, which is designed to penetrate the SOI layer 130 and has the buried insulating film 78 inside. (Second aspect)

[0209] Fig. Figure 12 is a cross-sectional view that schematically illustrates a cross-sectional structure of a semiconductor device 202 as the second aspect of the fourth preferred embodiment. Fig. Figure 12 illustrates a cross-section of AA. Fig. 1 corresponding cross-sectional structure. Note that a planar configuration and a circuit configuration of the semiconductor device 202 correspond to the one in Fig. 1 and Fig. The two illustrated configurations are similar.

[0210] The following points, which differ from those of the semiconductor device 201 of the first aspect of the fourth preferred embodiment, which is described in Fig. As illustrated in Figure 11, the common features are designated with the same reference numerals; their description may be omitted, and predominantly characteristic points of the semiconductor device 202 of the second aspect of the fourth preferred embodiment are described.

[0211] In the semiconductor device 202, a P-type layer 13 is arranged instead of the isolation trench 73 of the semiconductor device 201, a N-type diffusion layer 33c is arranged instead of the N-type diffusion layer 31c, and a N-type diffusion layer 34c is arranged instead of the N-type diffusion layer 32c.

[0212] Note that the diffusion layer 53 is from N + -Type and the P + Diffusion layers 62 and 63 are selectively arranged on a surface of diffusion layer 33c of the N type, similar to diffusion layers 31a to 31c, 33a and 33b of the N type. Furthermore, the N + -Diffusion layer 54 and the P + -Diffusion layers 64 and 65 similar to the N-type diffusion layers 32a to 32c, 34a and 34b are selectively arranged in a surface of the N-type diffusion layer 34c.

[0213] As described above, the semiconductor device 202, as the second aspect of the fourth preferred embodiment, is provided with the P-type layer 13, which serves as the second isolation diffusion region, the isolation region 7. The P-type layer 13 is arranged between the N-type diffusion layer 33c, which serves as the first circuit diffusion region, and the N-type diffusion layer 34c, which serves as the second circuit diffusion region, such that it is in contact with the N-type diffusion layers 33c and 34c. The P-type layer 13 functions as the second isolation diffusion region.

[0214] The following describes a manufacturing process for the P-type layer 13. For example, a method for forming the P-type layer 13 within the N-type SOI layer 130 is employed, using ion implantation, diffusion processing, and the like, with the aid of P-type defects. It is necessary to position the P-type layer 13 so that it penetrates the SOI layer 130 and reaches the upper surface of the buried oxide film 120.

[0215] The semiconductor device 202, as the second aspect of the fourth preferred embodiment, exhibits effects similar to those of the semiconductor device 101, as the first aspect of the first preferred embodiment, and further exhibits the following effect.

[0216] Since the semiconductor device 202, as the second aspect of the fourth preferred embodiment, is insulated in the depth direction into the SOI layer 130 and the support substrate 10a by the buried oxide film 120, which is a dielectric, a leakage current between the first and the second high-side switching area RH1 and RH2 can be further suppressed.

[0217] Furthermore, the semiconductor device 202 includes the P-type layer 13 as the second isolation diffusion region between the N-type diffusion layer 33c, which serves as the first circuit diffusion region, and the N-type diffusion layer 34c, which serves as the second circuit diffusion region. The P-type layer 13 is arranged in contact with each of the diffusion layers 33c and 34c.

[0218] Therefore, the semiconductor device 202, as the second aspect of the fourth preferred embodiment, includes the P-type layer 13 in the isolation region 7 as the second isolation diffusion region, and consequently the first and second high-side circuit regions RH1 and RH2 can be electrically isolated from each other with a relatively simple structure similar to the semiconductor devices 107 and 108 of the third preferred embodiment. <sonstiges>

[0219] In the present disclosure, the P-type is specified as the first conductivity type and the N-type as the second conductivity type, but a modification is also conceivable in which the first conductivity type is the N-type and the second conductivity type is the P-type.< / sonstiges>

Claims

[1] Semiconductor device comprising: a semiconductor substrate (10); a low-side switching area (RL) that is located in the semiconductor substrate and receives a first reference potential (GND); a high-side switching area (RH) located in the semiconductor substrate that receives a second reference potential (VS) different from the first reference potential; and a first isolation area (30) that electrically isolates the low-side circuit area from the high-side circuit area, where the semiconductor substrate has a circuit base region in which the low-side circuit region and the high-side circuit region are not located, and the high-side circuit area comprises first and second high-side circuit areas, a first high-side circuit (CH1) is arranged in the first high-side circuit area, a second high-side circuit (CH2) is arranged in the second high-side circuit area, the first high-side circuit operates with a first supply voltage (VB1) based on the second reference potential, the second high-side circuit operates with a second supply voltage (VB2) based on the second reference potential, and the first and second supply voltages have different voltage values. the semiconductor device further comprises: a second insulation area (7) that electrically isolates the first high-side circuit area and the second high-side circuit area. [2] Semiconductor device according to claim 1, wherein the circuit base area contains a substrate area of ​​a first conductivity type, the first insulation region contains a first insulation diffusion region (30a to 30c) of a second conductivity type and the first insulation diffusion region is located on the substrate region, the first high-side circuit region contains a first circuit diffusion region (20, 22, 31a to 31c, 33a to 33c) of the second conductivity type and the first circuit diffusion region is located on the substrate region, the second high-side circuit area contains a second circuit diffusion area (21, 23, 32a to 32c, 34a to 34c) of the second conductivity type and the second circuit diffusion area is located on the substrate area and the first and second circuit diffusion areas meet a diffusion area depth requirement and the diffusion area depth requirement is a requirement that a formation depth of each of the first and second circuit diffusion areas is deeper than a formation depth of the first isolation diffusion area. [3] Semiconductor device according to claim 2, wherein the second isolation area comprising an insulation trench (70 to 72) located between the first circuit diffusion area and the second circuit diffusion area, having a deepest sub-area reaching the substrate area, and the insulation trench having inside a buried insulating film (78) configured to insulate and isolate the first and second high-side circuit areas from each other. [4] Semiconductor device according to claim 3, wherein the first circuit diffusion region includes a first buried diffusion layer (20, 22) of the second conductivity type, selectively arranged on the substrate region, and a first surface diffusion layer (31b) of the second conductivity type, selectively arranged on the first buried diffusion layer, and the second circuit diffusion region includes a second buried diffusion layer (21, 23) of the second conductivity type, selectively arranged on the substrate region, and a second surface diffusion layer (32b) of the second conductivity type, selectively arranged on the second buried diffusion layer. [5] Semiconductor device according to claim 4, wherein the isolation trench has no contact relationship with the first and second buried diffusion layers and The isolation trench fulfills a requirement for trench depth, and the requirement for trench depth is a requirement that the construction depth of the isolation trench is shallower than the construction depth of each of the first and second buried diffusion layers. [6] Semiconductor device according to any one of claims 3 to 5, further comprising: a trench bottom diffusion area (110 to 112) of the first conductivity type arranged in contact with the deepest part of the isolation trench in a periphery of the deepest part of the isolation trench in the substrate area. [7] Semiconductor device according to claim 2, wherein the second insulation region includes a second insulation diffusion region (11, 12) of the first conductivity type, which is arranged between the first circuit diffusion region and the second circuit diffusion region in contact with the first and second circuit diffusion regions. [8] Semiconductor device according to claim 1, wherein the semiconductor substrate contains an SOL substrate (9) with a laminate structure consisting of a support substrate (10a), a buried oxide film (120) and an SOI layer (130), the circuit base area includes the carrier substrate and the buried oxide film and the low-side switching area, the high-side switching area and the second isolation area are arranged in the SOI layer. [9] Semiconductor device according to claim 8, wherein the second isolation area includes an isolation trench (73) located between the first high-side circuit area and the second high-side circuit area, and having a deepest sub-area reaching the buried oxide film, and the insulation trench has inside a buried insulating film (78) configured to insulate and isolate the first and second high-side circuit areas from each other. [10] Semiconductor device according to claim 8, wherein the first high-side circuit region contains a first circuit diffusion region (33c) of a second conductivity type and the first circuit diffusion region is located in the SOI layer, the second high-side circuit area contains a second circuit diffusion area (34c) of the second conductivity type and the second circuit diffusion area is located in the SOI layer and the second insulation area contains a second insulation diffusion area (13) of a first conductivity type, which is arranged between the first circuit diffusion area and the second circuit diffusion area in contact with the first and second circuit diffusion areas.

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