Semiconductor module arrangement and method for manufacturing semiconductor module arrangements

Abstract

A semiconductor module arrangement comprises a substrate (10), a base plate or heat sink (30) and a layer (40) arranged between the substrate (10) and the base plate or heat sink (30), wherein the layer (40) comprises a liquid or viscous heat transfer material, TIM, (42), a plurality of filler particles (44) distributed in the liquid or viscous heat transfer material, TIM, (42) and a plurality of capsules (46) distributed in the liquid or viscous heat transfer material, TIM, wherein each of the plurality of capsules (46) comprises a catalyst or radical initiator and the plurality of capsules (46) are configured to rupture upon activation and release the catalyst or radical initiator, causing the catalyst or radical initiator to spread throughout the heat transfer material, TIM, (42) and thus triggering the curing of the layer (40).

Description

TECHNICAL AREA

[0001] The present disclosure relates to a semiconductor module arrangement and a method for manufacturing semiconductor module arrangements. BACKGROUND

[0002] Document US 2017 / 0130993A1 discloses a self-heating thermal interface material (TIM) that can be manufactured using heating components distributed within the TIM. The heating components can generate heat when the TIM is compressed. The heating components can consist of microcapsules, and the microcapsules can contain exothermic reactants. The reactants can be isolated from the contact within the microcapsule until a compressive force is applied.

[0003] Power semiconductor module assemblies typically include at least one substrate. The substrate may be mounted on a base plate or a heat sink. A semiconductor assembly containing a variety of semiconductor devices (e.g., diodes, MOSFETs, JFETs, HEMTs, IGBTs, or any other suitable controllable or uncontrollable semiconductor devices in a parallel, half-bridge, or any other configuration) is typically mounted on at least one of the at least one substrate. Each substrate typically has a substrate layer (e.g., a ceramic layer), a first metallization layer applied to one side of the substrate layer, and a second metallization layer applied to the other side of the substrate layer. The semiconductor devices are, for example, mounted on the first metallization layer. The second metallization layer may be mounted on a base plate or a heat sink.

[0004] The heat generated by the semiconductor devices is transferred via the substrate to the base plate or heat sink. A thermally conductive layer is typically placed between the substrate and the base plate or heat sink to effectively conduct the heat away from the substrate. A liquid or viscous thermally conductive layer is able to conform perfectly to any surface and any irregularity, so that there are no significant air pockets between the substrate and the base plate or heat sink that could impair heat transfer. However, liquid thermally conductive layers can be unintentionally "pumped out" of the space between the substrate and the base plate or heat sink due to the thermal changes that occur during operation of the semiconductor module assembly.Furthermore, liquid thermally conductive layers can unintentionally dry out over the lifetime of the semiconductor module, preventing effective heat dissipation from the substrate. As an alternative to liquid thermally conductive layers, film materials are often used for thermally conductive layers. However, a film layer is typically relatively thick, difficult to apply, and expensive. Moreover, film materials generally cannot perfectly conform to arbitrary surfaces and irregularities.

[0005] There is a need for a semiconductor module assembly that is easy and inexpensive to manufacture, offers good thermal conductivity between the substrate and the base plate or heat sink, and has an increased lifetime. OVERVIEW

[0006] A power semiconductor module assembly comprises a substrate, a base plate or a heat sink and a layer arranged between the substrate and the base plate or heat sink, wherein the layer comprises a liquid or viscous thermal interface material (TIM), a plurality of filler particles dispersed in the liquid or viscous thermal interface material, TIM, and a plurality of capsules dispersed in the liquid or viscous thermal interface material, TIM, wherein each of the plurality of capsules contains a catalyst or radical initiator and the plurality of capsules is configured to rupture upon activation and release the catalyst or radical initiator, causing the catalyst or radical initiator to disperse in the thermal interface material, TIM, and thus trigger the curing of the layer.

[0007] A method according to embodiments of the disclosure includes arranging a layer between a substrate and a base plate or heat sink of a semiconductor module arrangement, wherein the layer comprises a liquid or viscous thermal interface material (TIM), a plurality of filler particles distributed in the liquid or viscous thermal interface material (TIM), and a plurality of capsules distributed in the liquid or viscous thermal interface material (TIM), wherein each of the plurality of capsules contains a catalyst or radical initiator, and the plurality of capsules is configured to be activated and, upon activation, to rupture and release the catalyst or radical initiator, causing the catalyst or radical initiator to disperse in the thermal interface material (TIM) and thus triggering the curing of the layer.

[0008] A method according to further embodiments of the disclosure includes forming a first sublayer on a surface of a substrate and a base plate or a heat sink, wherein the first sublayer contains a liquid or viscous heat transfer material, TIM, and a plurality of filler particles distributed in the liquid or viscous heat transfer material, TIM; forming a second sublayer on a surface of the corresponding other of the substrate and the base plate or the heat sink, wherein the second sublayer contains a catalyst or radical initiator; and arranging the substrate on the base plate or the heat sink, wherein the first sublayer and the second sublayer are arranged between the substrate and the base plate or the heat sink such that the first sublayer and the second sublayer are in direct contact with each other.

[0009] The invention can be better understood with reference to the following drawings and description. The components in the figures are not necessarily to scale; rather, the focus is on illustrating the principles of the invention. Furthermore, in the figures, the same reference numerals denote corresponding parts in the different views. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 schematically shows a cross-sectional view of a semiconductor module arrangement. Fig. Figure 2 schematically shows a cross-sectional view of a section of the semiconductor substrate arrangement of Fig. 1. Fig. Figure 3 schematically shows a method for manufacturing a semiconductor module arrangement according to embodiments of the disclosure. Fig. 4, the Fig. 4A and Fig. Figure 4B contains a schematic representation of further steps of a method for manufacturing a semiconductor module arrangement according to embodiments of the disclosure. Fig. Figure 5 schematically shows a method according to further embodiments of the disclosure. DETAILED DESCRIPTION

[0010] The following detailed description refers to the accompanying drawings. The drawings show specific examples in which the invention can be implemented. It is understood that the features and principles described in relation to the various examples can be combined with one another, unless expressly stated otherwise. In the description and in the claims, designations of certain elements as "first element," "second element," "third element," etc., are not to be understood as enumerative. Rather, such designations merely serve to name different "elements." That is to say, for example, that the presence of a "third element" does not require the presence of a "first element" and a "second element." A semiconductor body, as described herein, can be made of (doped) semiconductor material and can be a semiconductor chip or be contained within a semiconductor chip.A semiconductor body has electrically connecting pads and contains at least one semiconductor element with electrodes.

[0011] Fig. Figure 1 illustrates an example semiconductor module arrangement comprising a substrate 10. The substrate 10 contains a dielectric insulating layer 110, a (structured) first metallization layer 111 attached to the dielectric insulating layer 110, and a second metallization layer 112 attached to the dielectric insulating layer 110. The dielectric insulating layer 110 is located between the first and second metallization layers 111 and 112.

[0012] Each of the first and second metallization layers 111, 112 can consist of or contain one of the following materials: copper, a copper alloy, aluminum, an aluminum alloy, or any other metal or alloy that remains solid during operation of the power semiconductor module assembly. Optionally, the first and / or second metallization layer 111, 112 can be covered, for example, with a thin layer of nickel or silver. Such a layer can be formed, for example, using a nickel plating process or a silver plating process. The substrate 10 can be a ceramic substrate, that is, a substrate in which the dielectric insulating layer 110 is a ceramic, e.g., a thin ceramic layer.The ceramic can contain or consist of one of the following materials: aluminum oxide, aluminum nitride, zirconium oxide, silicon nitride, boron nitride; or any other dielectric ceramic. For example, the dielectric insulating layer 110 can consist of or contain one of the following materials: Al₂O₃, AlN, or Si₃N₄. The substrate 10 can be, for example, a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal brazing (AMB) substrate.

[0013] Typically, one or more semiconductor bodies 20 are arranged on a substrate 10. Each semiconductor body 20 arranged on a substrate 10 can contain a diode, an IGBT (insulated-gate bipolar transistor), a MOSFET (metal-oxide-semiconductor field-effect transistor), a JFET (junction field-effect transistor), a HEMT (high-electron-mobility transistor), or any other suitable controllable or non-controllable semiconductor element. One or more semiconductor bodies 20 can form a semiconductor array on the substrate 10. Fig. Figure 1 shows two semiconductor bodies 20 as an example. However, any other number of semiconductor bodies 20 is also possible.

[0014] At the in Fig. In the example shown in Figure 1, the substrate 10 is attached to a base plate or heat sink 30, with the second metallization layer 112 arranged between the dielectric insulating layer 110 and the base plate or heat sink 30. A layer 40 of thermally conductive material is arranged between the second metallization layer 112 and the base plate or heat sink 30. Heat generated by the semiconductor bodies 20 can be transferred to the base plate or heat sink 30 via the substrate 10 and the layer 40 of thermally conductive material. This is illustrated by the arrows in bold in Figure 1. Fig. Figure 1 shows the second metallization layer 112 of the substrate 10 in Fig. 1 is a continuous layer. The first metallization layer 111 is located in the Fig. The arrangement shown in Figure 1 is a structured layer. In this context, "structured layer" means that the first metallization layer 111 is not a continuous layer, but contains recesses between different sections of the layer. Such recesses are in Fig. Figure 1 is shown schematically. The first metallization layer 111 in this arrangement contains, by way of example, four different sections. Different semiconductor bodies 20 can be attached to the same or to different sections of the first metallization layer 111. Different sections of the first metallization layer 111 may have no electrical connection or may be electrically connected to one or more other sections using electrical connections such as bond wires. Electrical connections may also include, for example, bond tapes, connecting plates, or busbars, to name just a few examples. However, the fact that the first metallization layer 111 is a structured layer is only one example. It is also possible that the first metallization layer 111 is a continuous layer.According to another example, the substrate 10 can have only a dielectric insulating layer 110 and a first metallization layer 111. The second metallization layer 112 can be a continuous layer or a structured layer. However, the second metallization layer 112 can also be omitted.

[0015] The base plate or heat sink 30 can have a metal or be made of a metal. For example, the base plate or heat sink 30 has or is made of at least one of Al and Cu. According to another example, the base plate or heat sink 30 can be a metal matrix composite (MMC) base plate having an MMC material such as AlSiC. All other suitable materials are possible. The base plate or heat sink 30 can optionally also be coated with a thin layer of, for example, nickel or silver. Such a layer can be formed, for example, using a nickel plating process or a silver plating process.

[0016] Materials used for known thermally conductive layers 40 generally exhibit very low thermal conductivity, which may not be satisfactory for certain applications. Therefore, thermally conductive filler particles 44 can be added to the layer 40 to further increase its thermal conductivity. This is demonstrated in Fig. 2, which comprise a section A of the semiconductor module arrangement of Fig. Figure 1 shows a schematic representation.

[0017] The thermally conductive filler particles 44, which can be added to the layer 40 of thermally conductive material, can be (uniformly) distributed within the layer 40. The thermal conductivity of the filler particles 44 can be greater than the thermal conductivity of the surrounding material of the thermally conductive layer 40. For example, the filler particles 44 can have a thermal conductivity between 60 and 400 W / mK, so that the resulting layer 40 with filler particles 44 can have a thermal conductivity between 1 and 10 W / mK. The filler particles 44 can, for example, be a ceramic material, glass, or a metal powder. A maximum dimension d44 of each of the filler particles 44 can be equal to or less than the thickness d1 of the layer 40. For example, a maximum dimension d44 of each of the filler particles 44 can be between 100 nm and 150 µm. The filler particles 44 can all be of the same shape and size, as shown in Fig. 2 is shown schematically. However, this is only an example. In general, it is possible that the plurality of filler particles 44 has a first plurality of particles of a first type and a second plurality of particles of a second type. The particles of the first type may, for example, be smaller or larger than the particles of the second type. In the case of the Fig. In the example shown, the filler particles 44 have a round shape. In this case, a maximum dimension d44 of each particle corresponds to a diameter of the respective particle. However, this is only one example. In general, each particle of the plurality of filler particles 44 can have any regular or irregular shape.

[0018] Now, with reference to Fig. 3 A semiconductor module arrangement and a corresponding method for forming a semiconductor module arrangement according to embodiments of the disclosure are schematically illustrated. The semiconductor module arrangement comprises a substrate 10, a base plate or heat sink 30, and a layer 40 arranged between the substrate 10 and the base plate or heat sink 30. The layer 40 comprises a liquid or viscous heat transfer material, TIM, 42, and, similar to what is described above with respect to Fig. As described in Figure 2, a plurality of filler particles 44 are distributed within the liquid or viscous heat transfer material, TIM, 42. Each filler particle of the plurality of filler particles 44 can consist of a thermally conductive material, wherein the thermal conductivity of the thermally conductive material is greater than the thermal conductivity of the liquid or viscous heat transfer material TIM 42. For example, the thickness d1 of the layer 40 can be between 70 µm and 120 µm or between 40 µm and 70 µm.

[0019] A thermally conductive layer 40 formed essentially by a liquid or viscous heat transfer material TIM 42 is able to perfectly adapt to any surface (i.e., the surface 61 of the substrate 10 and the surface 31 of the base plate or heat sink 30) and to any irregularities that may be present on the respective surfaces 31, 61 (protrusions, conduits, ridges, gaps, cavities, etc.), so that there are no significant air inclusions between the substrate 10 and the base plate or heat sink 30 that could impair the heat transfer between the substrate 10 and the base plate or heat sink 30.However, a thermally conductive layer 40 made of liquid or viscous heat transfer material, TIM, 42, can be unintentionally "pumped out" of the space between the substrate 10 and the base plate or heat sink 30 during operation of the semiconductor module due to the heat changes occurring during the operation of the semiconductor module assembly. Furthermore, thermally conductive layers 40 made of liquid or viscous heat transfer material (TIM) 42 can unintentionally dry out during the lifetime of the semiconductor module, so that heat can no longer be effectively dissipated from the substrate 10.

[0020] For this reason, layer 40 further comprises a plurality of capsules 46 dispersed in the liquid or viscous heat transfer material TIM 42, each capsule containing a catalyst or radical initiator. The plurality of capsules 46 is configured to release the catalyst or radical initiator upon activation.

[0021] This means that layer 40 (i.e., the heat transfer material TIM 42) is initially liquid or viscous. In this way, the advantages of liquid or viscous layers are fully realized. When layer 40 is positioned between a substrate 10 and a base plate or heat sink 30, it can be, as shown in Fig. As shown in Figure 3, both the surface 61 of the substrate 10 and the surface 31 of the base plate or heat sink 30 make smooth contact. This ensures optimal contact between the substrate 10 and the layer 40, as well as between the layer 40 and the base plate or heat sink 30. Upon activation, however, a curing process is initiated. After curing, the layer 40 (i.e., the heat transfer material, TIM, 42) is no longer liquid or viscous. This effectively prevents undesirable pumping effects during operation of the semiconductor module assembly. The arrangement as shown in Fig. Figure 3 shows the layer 40 arranged between the substrate 10 and the base plate or heat sink 30 before the activation of the plurality of capsules 46.

[0022] Each capsule of the plurality of capsules 46 can, for example, be a microcapsule with a diameter d46 between 10 µm and 50 µm. However, other diameters, sizes, or shapes are also possible. Round microcapsules are generally easy to manufacture. In addition to the catalyst or radical initiator, each capsule of the plurality of capsules 46 can also contain a solvent, as well as other small filler particles and / or small amounts of the liquid or viscous heat transfer material. The liquid or viscous heat transfer material TIM 42 can have a variety of separate polymer chains. For example, the liquid or viscous heat transfer material TIM 42 can have one of a silicone-based polymer, an epoxy molding or potting compound, or an acrylate. The liquid or viscous heat transfer material, TIM 42, can also contain a crosslinking agent.When the plurality of capsules 46 are activated and release the catalyst or radical initiator, the catalyst or radical initiator disperses in the heat transfer material, TIM, 42, and binds the crosslinking agent contained in the heat transfer material, TIM, 42, to the polymer chains of the heat transfer material, TIM, 42, thereby hardening the liquid or viscous heat transfer material, TIM, 42. In general terms, each of the plurality of capsules 46 contains a material which, when released from the capsule and coming into direct contact with the heat transfer material, TIM, 42, triggers a reaction in which a crosslinking agent binds to the polymer chains, forming a crosslinked chain network.

[0023] The number of capsules 46 contained in layer 40 generally depends on several factors. For example, the number of capsules 46 may depend on the size of each individual capsule and thus on the amount of catalyst or radical initiator contained in each capsule. The number of capsules also generally depends on the volume of heat transfer material TIM 42 contained in layer 40. Furthermore, the number of capsules 46 may depend on the specific materials used, as this also defines the total amount of catalyst or radical initiator required to fully cure layer 40.

[0024] A method for forming a semiconductor module assembly comprises arranging a layer 40 between a substrate 10 and a base plate or heat sink 30 of a semiconductor module assembly. The layer 40 comprises a liquid or viscous heat transfer material, TIM, 42, a plurality of filler particles 44 dispersed in the liquid or viscous heat transfer material, TIM, and a plurality of capsules 46 dispersed in the liquid or viscous heat transfer material, TIM, each of the plurality of capsules 46 comprising a catalyst or radical initiator. The plurality of capsules 46 is configured to release the catalyst or radical initiator upon activation. The plurality of capsules 46 may be configured to be activated by elevated temperatures, elevated pressure, or other forms of activation.

[0025] Activating the plurality of capsules 46 may not require any specific additional steps. The plurality of capsules 46 can be configured to activate at elevated temperatures and / or under elevated pressure. For example, the plurality of capsules 46 is activated when the substrate 10 is pressed against the base plate or heat sink 30, thereby exerting pressure on the layer 40 and on the plurality of capsules 46 contained within the layer 40. The substrate 10 is typically pressed against the base plate or heat sink 30 with a certain force when it is positioned on the base plate or heat sink 30 during the assembly process. That is, the plurality of capsules 46 can be activated as the substrate 10 is positioned on the base plate or heat sink 30, with the layer 40 positioned between the substrate 10 and the base plate or heat sink 30.

[0026] According to another example, the multitude of capsules 46 is activated when heat is generated within the semiconductor module assembly during operation. As soon as the semiconductor module assembly is first operated, heat is generated, for example, by the components arranged on the substrate 10 (e.g., the semiconductor body 20). As described above, this heat is transferred through the substrate 10 and layer 40 towards the base plate or heat sink 30. That is, layer 40 is automatically heated during operation of the semiconductor module assembly. The activation of the multitude of capsules 46 therefore occurs when layer 40 is heated for the first time. Thus, once the semiconductor module assembly is operated in an application, layer 40 hardens, and undesirable pumping effects can no longer occur during subsequent operation of the semiconductor module assembly.The various capsules 46, for example, can be activated at temperatures above 100 °C or at or above 150 °C. Elevated temperatures can also accelerate the curing process. However, many materials are also known to cure at lower temperatures.

[0027] The step of activating the multitude of capsules 46 is in Fig. Figure 4A is shown schematically. When pressure and / or heat is applied, for example, the capsules 46 rupture and the catalyst or radical initiator is released, triggering the hardening of layer 40. As mentioned above, other forms of activation are generally possible as well. A resulting, hardened layer 50 is in Fig. Figure 4B shows a schematic representation. The capsules 46 are no longer present in the cured layer 50. If the multitude of capsules 46 contain a solvent prior to activation, this solvent generally evaporates during the curing (crosslinking) process and is no longer present in the resulting cured layer 50. The catalyst can be, for example, a so-called Pt catalyst. The resulting cured layer 50 can be a highly crosslinked and strong layer.

[0028] When providing a layer 40 with a plurality of capsules 46 distributed therein, as described above, the method and the resulting arrangement benefit from the advantages of both liquid or viscous layers (e.g., optimal contact between the layer 40 and the surfaces 31, 61) and cured layers (e.g., no pumping out during operation). The same advantages can be achieved and the same problems can be solved by employing a method according to further embodiments of the disclosure. This method is described below with reference to Fig. 5 described.

[0029] The in Fig. The alternative method shown in Figure 5 involves forming a first sublayer 402 on a surface 31, 61 of a substrate 10 and a base plate or heat sink 30, wherein the first sublayer 402 comprises a liquid or viscous heat transfer material, TIM, 42, and a plurality of filler particles 44 dispersed in the liquid or viscous heat transfer material, TIM, 42. The liquid or viscous heat transfer material, TIM, 42, and the plurality of filler particles 44 dispersed in the viscous heat transfer material, TIM, 42, can be similar to those described above. Instead of providing a plurality of capsules 46 in the first sublayer 402, a second sublayer 404 is formed on a surface 31, 61 of the respective other of the substrate 10 and the base plate or the heat sink 30, wherein the second sublayer 404 comprises a catalyst or radical initiator. In the Fig. In the example shown in Figure 5, the first sublayer 402 is formed on a surface 61 of the substrate 10, and the second sublayer 404 is formed on a surface 31 of the base plate or heat sink 30. However, this is only one example. It is also possible that the first sublayer 402 is formed on a surface 31 of the base plate or heat sink 30, and the second sublayer 404 is formed on a surface 61 of the substrate 10.

[0030] The method further comprises arranging the substrate 10 on the base plate or heat sink 30, wherein the first sublayer 402 and the second sublayer 404 are positioned between the substrate 10 and the base plate or heat sink 30 such that the first sublayer 402 and the second sublayer 404 are in direct contact with each other. The step of arranging the substrate 10 on the base plate or heat sink 30 is described in Fig.5 is schematically represented by an arrow. When the first sublayer 402 and the second sublayer 404 contact each other, their materials mix. This triggers the curing of the heat transfer material, TIM, 42, similar to what was described above regarding the activation of the plurality of capsules 46.

[0031] The first sublayer 402 and the second sublayer 404 are both applied to their respective surfaces 31, 61 while still liquid or viscous. This means that the first sublayer 402 and the second sublayer 404 are both able to perfectly conform to their respective surfaces (i.e., surface 61 of the substrate 10 and surface 31 of the base plate or heat sink 30) and to any irregularities that may be present on the respective surfaces 31, 61 (protrusions, channels, bumps, cracks, cavities, etc.), so that when the substrate 10 is placed on the base plate or heat sink 30, there are no significant air inclusions between the substrate 10 and the base plate or heat sink 30 that could impair heat transfer.When the substrate 10 is positioned in its desired mounting position on the base plate or heat sink 30, the materials of the sublayers 402 and 404 come into direct contact with each other. The substrate 10 is typically pressed onto the base plate or heat sink 30 with a certain degree of force. In this way, the materials of the sublayers 402 and 404 mix, and the curing process is automatically triggered during the mounting of the substrate 10 onto the base plate or heat sink 30. No additional curing steps are required. When the semiconductor substrate assembly is first operated, the resulting layer is already fully cured, and no pumping effects can occur.

[0032] The thickness d3 of the first sublayer 402 can, for example, be between 70 µm and 120 µm or between 40 µm and 70 µm. The thickness d1 of the first sublayer 402 can essentially define the thickness of the resulting cured layer 50. The thickness d2 of the second sublayer 404 can generally be less than the thickness of the first sublayer 402. For example, the thickness d2 of the second sublayer 404 can be less than half, less than a third, or even less than a quarter of the thickness d3 of the first sublayer 402. That is, for example, d2 < d3 / 2, d2 < d3 / 3, or d2 < d3 / 4. This is because a comparatively small amount of catalyst or radical initiator is usually required to fully cure the heat transfer material, TIM, 42.

Claims

[1] Semiconductor module arrangement comprising: a substrate (10); a base plate or heat sink (30); and a layer (40) arranged between the substrate (10) and the base plate or the heat sink (30), wherein the layer (40) comprises a liquid or viscous heat transfer material, TIM, (42), a plurality of filler particles (44) distributed in the liquid or viscous heat transfer material, TIM, (42) and a plurality of capsules (46) distributed in the liquid or viscous heat transfer material, TIM, (42), each of the plurality of capsules (46) comprising a catalyst or radical initiator and the plurality of capsules (46) is designed to break upon activation and release the catalyst or radical initiator, so that the catalyst or radical initiator is distributed in the heat transfer material, TIM, (42) and thus triggers the hardening of the layer (40). [2] Semiconductor module arrangement according to claim 1, wherein the plurality of capsules (46) are configured to be activated at elevated temperatures and / or under elevated pressure. [3] Semiconductor module arrangement according to claim 1, wherein each capsule of the plurality of capsules (46) is a microcapsule with a diameter (d46) between 10 µm and 50 µm. [4] Semiconductor module arrangement according to claim 1, wherein each capsule of the plurality of capsules (46) further comprises a solvent. [5] Semiconductor module arrangement according to any one of claims 1 to 3, wherein each filler particle of the plurality of filler particles (44) consists of a thermally conductive material, wherein a thermal conductivity of the thermally conductive material is greater than a thermal conductivity of the liquid or viscous heat transfer material, TIM, (42). [6] Semiconductor module arrangement according to one of the preceding claims, wherein a maximum dimension (d44) of each filler particle of the plurality of filler particles (44) is between 100 nm and 150 µm. [7] Semiconductor module arrangement according to one of the preceding claims, wherein the thickness (d1) of the layer (40) is between 70 µm and 120 µm or between 40 µm and 70 µm. [8] Semiconductor module arrangement according to one of the preceding claims, wherein the liquid or viscous heat transfer material, TIM, (42) comprises a plurality of separate polymer chains. [9] Semiconductor module arrangement according to any of the preceding claims, wherein the liquid or viscous heat transfer material, TIM, (42) comprises a silicone-based polymer, an epoxy molding or potting compound or an acrylate. [10] Semiconductor module arrangement according to claim 9, wherein the liquid or viscous heat transfer material, TIM, (42) further comprises a crosslinking agent. [11] method which features Arranging a layer (40) between a substrate (10) and a base plate or heat sink (30) of a semiconductor module arrangement, wherein the layer (40) comprises a liquid or viscous heat transfer material, TIM, (42), a plurality of filler particles (44) distributed in the liquid or viscous heat transfer material, TIM, (42), and a plurality of capsules (46) distributed in the liquid or viscous heat transfer material, TIM, (42), each of the plurality of capsules (46) comprising a catalyst or radical initiator, and the plurality of capsules (46) is designed to be activated and, upon activation, to break and release the catalyst or radical initiator, so that the catalyst or radical initiator is distributed in the heat transfer material, TIM, (42) and thus triggers the hardening of the layer (40). [12] The method of claim 11, further comprising activating the plurality of capsules (46) by applying increased temperatures and / or increased pressure. [13] Method according to claim 12, wherein either the plurality of capsules (46) is activated when the substrate (10) is pressed against the base plate or the heat sink (30), thereby exerting pressure on the layer (40) and on the plurality of capsules (46) contained in the layer (40), or the plurality of capsules (46) is activated when heat is generated in the semiconductor module assembly during operation. [14] Method according to any one of claims 11 to 13, wherein the liquid or viscous heat transfer material, TIM, (42) comprises a plurality of separate polymer chains and a crosslinking agent and wherein, when the plurality of capsules (46) release the catalyst or radical initiator, the catalyst or radical initiator links the crosslinking agent to the polymer chains and thereby cures the liquid or viscous heat transfer material, TIM, (42). [15] Method which features: Forming a first sublayer (402) on a surface (31, 61) of a substrate (10) or a base plate or a heat sink (30), wherein the first sublayer (402) comprises a liquid or viscous heat transfer material, TIM, (42) and a plurality of filler particles (44) distributed in the liquid or viscous heat transfer material, TIM, (42), Forming a second sublayer (404) on a surface (31, 61) of the corresponding other of the substrate (10) and the base plate or heat sink (30), wherein the second sublayer (404) comprises a catalyst or radical initiator; and Arranging the substrate (10) on the base plate or heat sink (30), wherein the first sublayer (402) and the second sublayer (404) are arranged between the substrate (10) and the base plate or heat sink (30) such that the first sublayer (402) and the second sublayer (404) are in direct contact with each other.

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