INTEGRATED CIRCUIT DEVICE WITH LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR AND ZENER DIODE

Abstract

A method for forming an integrated circuit comprising the following steps: Forming a first and a second region of a first semiconductor type in a semiconductor substrate in a first implantation, each of the first and second regions having a first dopant concentration; Forming a third and a fourth region of the first semiconductor type in the semiconductor substrate in a second implantation, wherein the third region overlaps at least partially with the first region and the fourth region overlaps at least partially with the second region, each of the third and fourth regions having a second dopant concentration that differs from the first dopant concentration; Forming a transistor source in the first and third regions; and forming one from a diode anode or a diode cathode in the second and fourth regions.

Description

TECHNICAL AREA

[0001] The examples described relate to integrated semiconductor circuits (ICs) and their manufacture, and in particular, but not exclusively, an IC that incorporates a laterally diffused metal oxide semiconductor (LDMOS) and an integrated Zener diode. BACKGROUND

[0002] When manufacturing integrated circuits (ICs), trade-offs are typically considered and balanced between a number of factors, including one or more of the IC size, cost, complexity, performance, and yield. These factors can become even more complex when an IC incorporates different types of devices, as sometimes adjusting one factor with respect to one of these devices can have adverse effects on another device or devices. These adverse effects might occur, for example, in an IC with both a transistor and a diode, such as an LDMOS device and a Zener diode, respectively. In some ICs, the LDMOS device might be a transistor whose drain is located away from the transistor gate to enable high-power applications and high-power operations.Such an IC may also contain a Zener diode, which is coupled to the transistor in such a way that, in the event of an increased voltage on the LDMOS transistor, a reverse breakdown of the Zener diode is possible in order to protect the transistor gate oxide from possible damage.

[0003] While this may occur in various basic devices as described above, this document presents certain examples that may improve upon the aforementioned concepts, as described in more detail below. SUMMARY

[0004] In an exemplary embodiment, a method for forming an integrated circuit is described. The method forms an integrated circuit through steps comprising: In a first implantation, forming a first and a second region of a first semiconductor type in a semiconductor substrate, each of the first and second regions having a first dopant concentration; in a second implantation, forming a third and a fourth region of the first semiconductor type in a semiconductor substrate, the third region at least partially overlapping with the first region and the fourth region at least partially overlapping with the second region, each of the third and fourth regions having a second dopant concentration that differs from the first dopant concentration; Forming a transistor source in the first and third regions; and forming a diode anode or diode cathode in the second and fourth regions.

[0005] Other aspects are also described and claimed. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figures 1 to 6 and 8 to 9 are partial cross-sectional views that depict successive manufacturing stages and the resulting structures of an IC semiconductor structure. Fig. Figure 9A shows a schematic equivalent circuit of an example. Fig. 7 is a dopant profile diagram of selected areas in the cross-sectional view in Fig. 6. Fig. Figure 10 is a flowchart of an exemplary process for manufacturing a semiconductor structure. DETAILED DESCRIPTION

[0006] Fig. Figures 1 to 6 and 8 to 9 are cross-sectional views showing successive manufacturing stages and the resulting structures of a semiconductor structure 100, e.g., a region of an IC. Ultimately, the semiconductor structure 100 includes a transistor and a diode (e.g., a Zener diode), such that Fig. Figure 1 and others show a transistor region 102 and a diode region 104 in which the transistor and diode, respectively, are formed. As an example, the IC may include an LDMOS transistor that operates at a higher voltage than conventional planar transistors, for example, 10 volts or more, and a diode may be placed near the LDMOS transistor for voltage protection, as will be explained in more detail later. Furthermore, in addition to the diode, the IC may include numerous other devices (not shown) that work in conjunction with the transistor. Such devices may be located at the substrate level by the components shown in Figure 1. Fig. The structures shown in Figure 1 (and other figures described later) can be separated, for example, by field oxides formed, for example, by a shallow trench isolation (STI) process or local silicon oxidation (LOCOS), and can be separated at a connection element level with those shown in Figure 1 (and other figures described later), ...). Fig. The structures shown in section 1 are connected.

[0007] First, with reference to Fig. Figure 1 shows the semiconductor structure 100 on a semiconductor substrate 101, for example as part of a silicon wafer. Such a wafer typically has several sites, each corresponding to the same or a different IC on the wafer, so that the representation according to Fig. 1 (and figures described later) can be repeated at each IC site of the wafer. The wafer typically has either a p-type or an n-type semiconductor, and the substrate 101 can be a region of the bulk wafer or a region (e.g., a well or a buried layer) formed in association with the wafer. In the example shown, the substrate 101 is a p-type epitaxy (epi) layer. A resist mask layer 105 is formed, for example, using a photolithographic process such as can be used for other masks described below, at selected locations on the wafer surface 101US. The resist mask layer 105 has an opening 106 in a region where implantation is to take place.In the example shown, such implantation is carried out in a region of the transistor area 102, for example using an n-type dopant and to form a drift region 108 in the substrate 101. The drift region 108 can have a dopant concentration in the range of 3E15 / cm. 3 up to 1E17 / cm 3 and have a maximum depth D1 (shown in the vertical dimension) extending in a range of 0.2 µm to 2 µm from the upper surface 101US into the substrate 101.

[0008] According to Fig. 2 is the resist mask layer 105 according to Fig. 1 was removed. A hard mask 110 is then formed over one or more selected areas of the upper surface 101US. The hard mask 110 can be formed from a silicon nitride layer textured with another resist layer (not shown). The hard mask 110 has an opening 112 over a region of the drift area 108.

[0009] According to Fig. 3. A thick LOCOS structure 114 is formed through the opening 112 in the etching mask 110. In general, the LOCOS structure 114 can be formed by oxidizing the area of ​​the upper surface 101US exposed through the opening 112. As shown, the LOCOS structure 114 can have a central part that has a greater depth in the vertical dimension towards its central region, in contrast to the area around its lateral or peripheral edges, which form what is sometimes referred to as the "bird's beak".

[0010] According to Fig. 4 is the hard mask 110 according to Fig. 3 was removed. A resist implantation mask 116 is then formed over one or more selected sites on the upper surface 101US. The resist implantation mask 116 has a first opening 118 over a region of the transistor area 102, but laterally spaced from the drift area 108. The resist implantation mask 116 also has a second opening 120 over a region of the diode area 104. Implantation is carried out through both the first and second openings 118 and 120, using a dopant type opposite to that used for the drift area 108. Accordingly, in the present example, where the drift area 108 is of the n type, the implantation is carried out in Fig. 4 of the p-type, for example using boron. Furthermore, the result of the implantation is determined according to Fig. 4 is referred to as a shallow implantation area because the implantation requires a lower implantation energy than is used for deeper implantations (such as implantation according to Fig. 1) as might be expected in some examples where a doubly diffused transistor well (DWELL) is generated. The implantation dose in Fig. 4 can, for example, be found in a range of 1.0E14 atoms / cm² 2 up to 2.0E14 atoms / cm² 2 (e.g. 1.4E14 atoms / cm²) 2) and at an energy in the range of 5 keV to 10 keV (e.g., 8 keV). The shallow implantation forms a shallow DWELL region 122 in the substrate 101, which is generally aligned with the first opening 118, and also forms a shallow DWELL region 124 in the substrate 101, which is generally aligned with the second opening 120. In one example, each of the shallow DWELL region 122 and the shallow DWELL region 124 is thereby formed simultaneously with the same implantation and with a depth D2 extending into the substrate 101. The depth D2 is based on a depth D4 of a subsequently formed source / drain (see D4, Fig. 6) selected, where D2 is fifty percent (50%) or less of D4. For example, if D4 is in the range of 0.10 µm to 0.25 µm, then D2 can be in the range of 50 nm to 125 nm.

[0011] According to Fig. 5. The resist implantation mask 116 remains according to Fig. 4, and a second implantation is performed, again through the first opening 118 and the second opening 120. The second implantation uses the same dopant conductivity type as the implantation in Fig. 4, which in this example is of the p-type, is used to create additional Dwell areas. In practical implementation, implantation according to Fig. 5 the same type of dopant as the implantation according to Fig. 4, although in some cases a different dopant type (still of the same conductivity type, p or n) may be used. The second implantation forms a deeper secondary DWELL area 126 below the shallow DWELL area 122 and likewise a deeper secondary DWELL area 128 below the shallow DWELL area 124. Furthermore, the second implantation consumes more energy than the first implantation. Again with reference to Fig. 4 The implantation aims at a resulting device with a depth D2 that is less (shallower) than a subsequently formed depth D4 of subsequently formed transistor source / drain regions, e.g. source 144 and drain 146 according to Fig. 6. In contrast, the second implantation aims according to Fig. 5 to a depth D3 that is greater (deeper) than a subsequently formed depth D4 of the transistor source / drain regions. In one example, D3 is at least twice as large as D4; that is, if D4 can be in a range of 0.10 µm to 0.25 µm, D3 can correspondingly be in a range of at least 0.2 µm to 0.5 µm or greater. The second implantation uses doses and energies that correspond to these targets. For example, if the first implantation dose in Fig. 4 1.0E14 atoms / cm² 2 up to 2.0E14 atoms / cm³ 2 (e.g. 1.4E14 atoms / cm²) 2 ) and has an energy in the range of 5 keV to 10 keV (e.g., 8 keV), then the second implantation can be performed according to Fig. 5 have a lower dose and a higher energy, e.g., correspondingly in a range of 1E13 atoms / cm². 2 up to 6E13 atoms / cm³ 2 and at an energy in the range of 20 keV to 50 keV (e.g. 3E13 atoms / cm²). 2(at an energy of 32 keV). Accordingly, the shallow DWELL region 122 and the deeper secondary DWELL region 126 combine to form a DWELL 127 for the transistor region 102, and the shallow DWELL region 124 and the deeper secondary DWELL region 128 form a DWELL 129 for the diode region 104. In one example, the DWELL 127 for the transistor region 102 and the DWELL 129 for the diode region 104 are formed simultaneously with the same implantation and with a depth of D3, as shown below in conjunction with Fig. 7 described.

[0012] According to Fig. 6 is the Resist implantation mask 116 according to Fig. 5 was removed, and a transistor-gate poly 130 and associated structures were formed. The transistor-gate poly 130 is so named because it can be formed from polysilicon to provide a conductor. In this context, a thin gate insulator 132 was formed, which abuts a region of the LOCOS structure 114 and extends laterally along a region of the surface 101US, for example, beyond the vertical edge of the drift region 108. The thin gate insulator 132 can be formed by growing or depositing an insulator, such as an oxide, over exposed regions of the upper surface 101US and forming a layer of polysilicon over it. The polysilicon layer and the insulator can then be structured to form a gate structure that features the transistor gate poly 130 overlapping with the thin gate insulator 132 and an area of ​​the gate oxide structure 114.Accordingly, one vertical end of the transistor-gate poly 130 forms a first sidewall above the LOCOS structure 114, and the other vertical end forms a second sidewall extending laterally beyond the vertical edge of the drift region 108. The transistor-gate poly 130 can be formed by depositing polysilicon, followed by structuring / etching into the desired structure / position. The deposited polysilicon can also be doped in situ or subsequently. Gate-sidewall spacers 134 are then formed along the first and second sidewalls of the transistor-gate poly 130, for example, by forming an oxide layer over the transistor-gate conductor, followed by suitable etching, so that the remaining parts of the oxide later form the gate-sidewall spacers 134. Finally, it should be noted that the implantations according to... Fig. 5 and Fig. 6 are shown in the sequence of a first, shallow implantation followed by a second, deeper implantation; however, in another example, this sequence may be reversed.

[0013] After the transistor-gate poly 130 and its associated structures have been formed, a resist implantation mask 136 is formed by structuring a resist layer over one or more selected locations of the upper surface 101US. The resist implantation mask 136 has a first and a second opening 138 and 140 over corresponding regions of the transistor region 102, with the first opening 138 being located over the drift region 108 and the second opening 140 being located over both the flat Dwell region 122 and the secondary Dwell region 126. The resist implantation mask 136 also has a third opening 142 over a region of the diode region 104 and, in particular, has a lateral width W1 that is greater than a width W2 of the flat Dwell region 124.A source / drain implantation is performed through each of the first, second, and third openings 138, 140, and 142, using a dopant type that is the same as that used for the drift region 108. The source / drain implantation can be referred to as an NSD implantation, i.e., the implantation of an n-type dopant to provide source / drain functionality to the LDMOS transistor region 102. Accordingly, in the present example, where the drift region 108 is of the n type, the implantation is also performed according to [reference missing]. Fig. 6 of the n-type, for example using arsenic (or phosphorus or antimony). The implantation in Fig. 6 can, for example, be 1.0E15 to 1.6E15 atoms / cm³ 2 and exhibit an energy of 20 to 30 keV. Furthermore, the implantation is carried out according to Fig. 6 is referred to as source / drain implantation, since the implantation for transistor region 102 creates a drain region 144 in the drift region 108 and a source region 146 in a region of the flat DWELL region 122 and the secondary DWELL region 126, both of which are p-type regions created by the n-type implantation according to Fig. 6. Furthermore, the n-type source / drain implantation through the third opening 142 forms a region extending into the substrate 101 and referred to as the cathode region 148, which is sometimes also referred to as the first diode terminal, insofar as the n-type dopant counter-dopes the entire flat DWELL p-type region 124 and an upper region of the secondary p-type DWELL region 128. Since width W1 is greater than W2 (the upper width of the DWELL, which includes the flat DWELL region 124 and the secondary DWELL region 128), cathode region 148 also has a larger surface width than the remaining p-type regions of DWELL regions 124 and 128. In one example, width W1 is in the range of 0.2 µm to 0.5 µm, while width W2 is in the range of 1.0 µm to 5.0 µm. Furthermore, it should be noted that cathode region 148 is identified as such because the Fig. The 6 depicted counter-doping implantation (of the n-type) creates a region in which electrons are the majority charge carriers (of the n-type), thereby forming a cathode relative to the p-type atoms in the remaining (and deeper) part of the secondary DWELL region 128, which is formed by the n-type implantation according to Fig. 6 is not reached. Accordingly, this remaining and deeper area forms a diode-shaped vertical anode area 150 relative to the cathode area 148. Finally, in one example, each of the drain area 144, the source area 146, and the cathode area 148 is formed simultaneously with the same implantation and with a depth D4 that is greater than D2, i.e., the depth of the shallow implantation in Fig. 4; accordingly, the cathode region 148, for example, completely covers the flat Dwell region 124 with respect to the diode region 104 and extends beyond and below it. Additional details regarding the effects of implantation according to Fig. 6 are below in conjunction with Fig. 7 described.

[0014] Fig. Figure 7 is a dopant profile diagram 700 of the DWELL ranges according to Fig. 6, which is a non-restrictive example of the dopant concentration of such areas as a function of the depth extending into substrate 101 (in Fig. 6 vertically) and originates from the upper surface 101US. Diagram 700 shows the depth along the horizontal axis and the dopant concentration (in atoms / cm²). 3, logarithmically scaled) along the vertical axis. Diagram 700 features a p-type dopant curve 702 and an n-type dopant curve 704, each showing the corresponding dopant concentration in the shallow Dwell regions 122 and 124 and the secondary Dwell regions 126 and 128 in Fig. 6.

[0015] The p-type dopant curve 702 shows a remarkable change in dopant concentration at a depth of approximately 0.12 µm. At relatively shallow depths, e.g., from the upper surface 101US (0 µm) to a depth of approximately 0.12 µm, the p-type dopant curve 702 shows the highest p-type dopant concentrations in the Dwell regions. At these shallower depths, the p-type dopants reach a maximum of approximately 2E19 atoms / cm³. 3 , which has a starting point at the upper surface 101US with an initial concentration in the range of approximately 3E18 atoms / cm² 3 up to about 2E19 atoms / cm³ 3between the surface and about 0.10 µm, followed by a decreasing concentration to about 2.3E18 atoms / cm² 3 at a depth of 0.12 µm and 2E18 atoms / cm 3 at a depth of 0.14 µm. Accordingly, these relatively higher concentrations of the p-type dopant primarily represent the doping of the in Fig. Figure 4 shows the formation of the flat DWELL regions 122 and 124 with higher dose / lower energy dopants, which are further enhanced by the formation of the secondary DWELL regions 126 and 128 according to Fig. 5 is further enhanced with lower dose / higher energy dopants. At depths greater than approximately 0.12 µm, the p-type dopant curve 702 shows that the concentration of the p-type dopants progressively decreases with increasing depth, albeit at lower concentrations—for example, with a maximum concentration at least 10 times lower, or 50 times lower, than the peak value between the surface and 0.12 µm depth—down to a depth of at least 0.5 µm, with the depth eventually continuing to the depth D3 described above.

[0016] The n-type doping curve 704 shows the dopant concentration resulting from the single source / drain implantation that forms the drain and source regions 144 and 146, respectively, and simultaneously forms the cathode region 148. Since a relatively low implantation energy is used in the implantation step employed for this n-type doping, curve 704 shows the highest dose at the upper surface 101US, which decreases from this point to a depth of 0.25 µm, approximately corresponding to D4, as explained above.

[0017] In light of this, it should be noted that the two-implantation steps ( Fig. 4 and Fig. 5) of the p-type dopant yield a curve 702 with attributes related to each implantation, and it should further be noted that the p-type dopant curve 702 and the n-type dopant curve 704 intersect at an observable depth, this depth being approximately 0.12 µm in the example shown. The intersection of these curves represents where p-type and n-type materials are equal, i.e., the quantity of donors and acceptors is equal, representing a metallurgical transition between the diode cathode region 148 and the vertical diode anode region 150. Accordingly, these attributes further represent that, on the one hand, the shallow p-type implantation according to Fig. 4 the n-type carrier (electron) concentrations in the transistor region 102 can be adjusted for the purpose of adjusting the transistor threshold voltage with respect to the source region 146 within its DWELL, while the additional p-type implantation according to Fig. 5. DWELL can further increase the amount of p-type dopants at greater depths by increasing the amount of p-type dopants to adjust the point where the p-type dopant curve 702 and the n-type dopant curve 704 intersect. In particular, the additional higher-energy p-type implantation dopant concentration in Fig. 5 considerably lower than the doping concentration of the shallow implantation in Fig. 4 - for example, by a factor of 10 to 100 to adapt the metallurgical junction. In other words, this additional adaptation allows for a corresponding adjustment of the reverse breakdown voltage between the cathode region 148 and the vertical anode region 150 of the diode. Accordingly, shallow implantation can achieve a relatively high dopant concentration in the transistor channel of the transistor DWELL, thereby achieving a beneficial (e.g., higher) transistor threshold voltage, while additional implantation with a lower concentration and greater depths in the DWELLs can advantageously increase the breakdown voltage in the diode DWELL compared to what might result from using a higher concentration in a single DWELL implantation for the entire DWELL. Furthermore, the desired diode breakdown voltage can be achieved without excessively lowering the transistor threshold voltage.

[0018] In Fig. 8 is the implantation mask 136 according to Fig. 6 was removed. Subsequently, a resist implantation mask 152 is formed over one or more selected locations of the upper surface 101US by structuring a further resist layer. The resist implantation mask 152 has a first opening 154 over the flat DWELL area 122, which is laterally spaced and has a vertical edge that is potentially aligned with a vertical edge of the source area 146. The resist implantation mask 152 also has a second and a third opening 156 and 158, respectively, each located over a region of the diode area 104 and offset laterally outward from the vertical anode area 150 of the diode (in a top view, not shown), the second and third openings 156, 158 being able to surround the vertical anode area 150 of the diode in combination.An implantation is performed through each of the first, second, and third openings 154, 156, and 158, using a semiconductor type opposite to that used for the drain and source regions 144 and 146. Accordingly, in the present example, where the drain and source regions 144 and 146 are of the n type, the implantation is performed in . Fig. 8 of the p-type, again using, for example, boron. The implantation in Fig. 8 can be found in a range of 1E15 atoms / cm² 2 up to 10E15 atoms / cm² 2and have an energy in the range of 5 keV to 10 keV. Consequently, the p-type implantation forms a body contact 160 in the flat DWELL area 122 and the secondary DWELL area 126, which can be biased to apply a bias voltage to the transistor DWELL, which has the flat DWELL area 122 and the secondary DWELL area 126. Due to the formation of the p-type body contact 160, the implantation can be carried out according to Fig. 8 can be referred to as PSD implantation, i.e., the implantation of a p-type dopant and in conjunction with the completion of the source / drain functionality of the LDMOS transistor of transistor area 102. (The same p-type implantation as in Fig. 8 also forms lateral anode contacts 162 and 164, which are sometimes referred to as second diode terminals and are offset laterally outwards from the cathode region 148. It should be noted that the lateral anode contacts 162 and 164 are identified as part of the anode structure for the diode 104, since they can be electrically connected to the vertical anode region 150 of the diode via the same conductivity type (e.g., p-type) through the p-type epi-layer of the substrate 101.

[0019] In Fig. 9 is the etching mask 152 according to Fig. 8 has been removed. Connections can then be made to the transistor in transistor section 102 and the diode in diode section 104, either between the devices or with other devices. In Fig. Figure 9 shows, for example, a schematic representation of electrical connections between the transistor area 102 and the diode area 104, although in other cases the diode can be biased independently of the transistor. In the example shown, after completion of the semiconductor structure 100 according to Fig. Eight additional steps are performed to establish such electrical connections. For example, conductive silicide regions 166, 168, 170, 172, 174, and 176 are formed along selected semiconductor surfaces, e.g., laterally along the surfaces of the drain region 144, the source region 146, and the body contact 160 (which are interconnected), each of the lateral anode contacts 162 and 164, the cathode region 148, and the transistor gate poly 130. Additional electrical connections can be established, for example, by metal layers and metallic vias (not shown), which are generally located across the surface of the semiconductor. Fig. The structures shown in 9 are formed by contacting suitable conductive silicide areas. An example of such electrical connections is shown schematically in Fig. Figure 9 shows a first connection 178 between the transistor gate poly 130 and the cathode contact 148, and a second connection 180 between the side anode contacts 162 and 164 and the source area 146 and the body contact 160. With such connections, as shown in Fig. As schematically represented in Figure 9A, the entire diode structure in diode section 104 implements a Zener diode connected in parallel across the gate-source path of the transistor in transistor section 102, with the diode cathode connected to the gate and the diode anode to the source. Accordingly, the reverse breakdown voltage of the (e.g., Zener) diode acts as a clamping limit to the maximum gate-source voltage to which the transistor is subjected, thereby limiting, in particular, the voltage drop across the thin gate insulator 132. In other words, as the gate-source voltage of the transistor increases, the diode conducts once it reaches its reverse breakdown voltage, thus preventing (or clamping) any further increase in the gate voltage.Furthermore, due to the advantageous transistor structure and manufacturing process described above, the reverse breakdown voltage can be set to a desirable level without excessively lowering the threshold voltage of the transistor in the transistor region 102.

[0020] Fig. Figure 10 is a flowchart of an exemplary process 1000, which summarizes several of the steps described above for fabricating the semiconductor structure 100, e.g., the final provision of the structure 100, as in Fig. 9 shown. The process 1000 begins with a step 1002 in which the semiconductor substrate 101 is prepared according to Fig.1 is obtained. The semiconductor substrate 101 can be a bare wafer at this stage or have one or more semiconductor features already formed on it. The semiconductor substrate 101 also has one or more regions where it is desirable to form a transistor with a relatively higher voltage and a diode. In a next step 1004, pre-DWELL structures are formed. Such structures can, for example, include the transistor drift region 108 and the LOCOS structure 114. Next, in a step 1006, a pair of flat implantation regions are formed, a first for a region of the transistor DWELL (e.g., flat DWELL region 122) and a second for a region of a diode DWELL (e.g., flat DWELL region 124). In one example, the two flat implantation regions are formed with the same conductivity type and in the same implantation step.Next, in step 1008, a pair of deeper secondary implantation regions are formed, a first for a region of the transistor DWELL (e.g., deeper secondary DWELL region 126) and a second for a region of a diode DWELL (e.g., deeper secondary DWELL region 128). In one example, the pair of deeper implantation regions is formed with the same conductivity type and in the same implantation step as the shallow regions from step 1006; however, the regions from step 1008 have a lower dopant concentration. Next, in step 1010, source / drain regions for the transistor are formed with a first source / drain implantation, and simultaneously, a first cathode or anode for the diode is formed, e.g., a cathode for an NSD implantation or an anode for a PSD implantation.In one example, the first source / drain implantation uses processes (dose and energy) such that the source / drain regions and the anode or cathode are deeper than the shallow regions from step 1006, but shallower than the deeper regions from step 1008. In a subsequent step 1012, a second source / drain implantation (PSD for an n-channel transistor, NSD for a p-channel transistor) forms a body contact for the transistor and simultaneously for the other cathode contact or the anode contact for the diode. After step 1012, as generally shown in step 1014, additional structures can be formed in association with the transistor, the diode, and connections to these, as well as other devices associated with the semiconductor substrate from step 1002.

[0021] It is evident to those skilled in the art that examples are provided for the fabrication of semiconductor ICs, e.g., for an IC comprising a transistor with a relatively higher voltage rating and a diode, which are at least partially fabricated through simultaneous processing steps. Such examples offer several advantages, some of which have already been described above, but also others. For instance, a transistor and a diode can be realized, both exhibiting DWELL structures, with these structures being formed during the same implantation step and using a single mask common to both structures, through which multiple implantations are performed.Accordingly, both the transistor threshold voltage and the diode breakdown voltage can be advantageously adjusted without, for example, the need for an additional mask focused solely on one or the other of these attributes. These advantages can also be realized in more complex structures or with multiple devices on the same substrate (and the same IC), resulting in a scaled-up improvement for the entire device. Further modifications of the described embodiments are possible, and other embodiments are possible within the scope of the following claims.

Claims

[1] A method of forming an integrated circuit, comprising: Forming a first and a second region of a first semiconductor type in a semiconductor substrate in a first implantation, each of the first and second regions having a first dopant concentration; Forming a third and a fourth region of the first semiconductor type in the semiconductor substrate in a second implantation, the third region at least partially overlapping the first region and the fourth region at least partially overlapping the second region, each of the third and fourth regions having a second dopant concentration different from the first dopant concentration; Forming a transistor source in the first and third regions; and Forming one of a diode anode or a diode cathode in the second and fourth regions. [2] The method of claim 1, wherein a third implantation step comprises forming a transistor source and forming one of a diode anode or a diode cathode. [3] Method according to claim 1, wherein the transistor source extends a first depth from a surface of the semiconductor substrate into the semiconductor substrate; and wherein the first region extends a second depth from the surface of the semiconductor substrate into the semiconductor substrate, the second depth being no greater than fifty percent of the first depth. [4] The method of claim 3, wherein the first depth is in a range of 0.10 µm to 0.25 µm. [5] Method according to claim 1, wherein the transistor source extends a first depth from a surface of the semiconductor substrate into the semiconductor substrate; wherein the first region extends a second depth from the surface of the semiconductor substrate into the semiconductor substrate, the second depth being no greater than fifty percent of the first depth; and wherein the third region extends a third depth from the surface of the semiconductor substrate into the semiconductor substrate, the third depth being at least twice the first depth. [6] The method of claim 5, wherein the first depth is in a range of 0.10 µm to 0.25 µm. [7] The method of claim 1, wherein in addition to forming one of a diode anode or a diode cathode, the other of the diode anode or the diode cathode is formed in the semiconductor substrate, and wherein a reverse breakdown bias between the diode anode and the diode cathode depends on a cut depth between the first dopant concentration and the second dopant concentration. [8] Method according to claim 1, wherein the second region has a first width in a lateral dimension relative to the semiconductor substrate; and wherein the other of the diode anode or the diode cathode has a second width in the lateral dimension relative to the semiconductor substrate, the second width being greater than the first width. [9] The method of claim 1, further comprising: Forming a transistor drain and a transistor channel in the semiconductor substrate and a transistor gate in a fixed position relative to the semiconductor substrate; and in addition to forming one of a diode anode or a diode cathode, forming the other of the diode anode or diode cathode in the semiconductor substrate. [10] Method according to claim 9, wherein a transistor threshold voltage relative to the transistor source and the transistor gate depends on the second dopant concentration; and wherein a reverse breakdown bias voltage between the diode anode and the diode cathode depends on an intersection point between the first dopant concentration and the second dopant concentration. [11] The method of claim 1, wherein the first semiconductor type comprises boron. [12] The method of claim 11, wherein the transistor source is formed from an n-type semiconductor. [13] The method of claim 12, wherein the transistor source is formed from arsenic. [14] The method of claim 1, wherein forming one of a diode anode or a diode cathode forms at least a portion of the diode anode. [15] The method of claim 11, further comprising forming a coupling between the transistor source and the diode anode. [16] The method of claim 1, wherein the second dopant concentration has a peak value of less than 10% of the peak value of the first dopant concentration. [17] A method of forming an integrated circuit, comprising: simultaneously implanting a first dopant of a first conductivity type into first and second regions extending into a semiconductor substrate having the first semiconductor type, the first and second regions having a first dopant concentration; simultaneously implanting a second dopant of the first conductivity type in a third region overlapping the first region and in a fourth region overlapping the second region, the third and fourth regions being deeper than the first and second regions and having a lower dopant concentration than the first and second regions; simultaneously implanting a third dopant of an opposite second conductivity type in a fifth region overlapping the first and third regions and in a sixth region overlapping the second and fourth regions, the fifth region forming a transistor source and the sixth region forming a first terminal of a diode; implanting a third dopant of the first conductivity type into a seventh region spaced from the sixth region and extending into the semiconductor substrate and forming a second terminal of the diode; Forming a transistor gate over the semiconductor substrate adjacent to the transistor source; and electrically connecting the transistor source to the second diode terminal and the transistor gate to the first diode terminal. [18] The method of claim 17, wherein the first conductivity type is p-type and the second conductivity type is n-type. [19] The method of claim 17, wherein the sixth region has a peak concentration of the first conductivity type dopants of no more than 10% of a peak concentration of the second conductivity type dopants. [20] Integrated circuit, comprising: a substrate; a transistor at least partially disposed in the substrate and having a transistor well structure extending from a surface of the substrate into the substrate, the transistor well structure having a first region from the surface of the substrate to a first depth and having a first peak dopant concentration and a second region from the surface of the substrate to a second depth greater than the first depth and having a second peak dopant concentration less than the first peak dopant concentration; and a diode at least partially disposed in the substrate and having a diode well structure extending from the surface of the substrate into the substrate, the diode well structure having a third region from the surface of the substrate to the first depth and having the first peak dopant concentration and a fourth region from the surface of the substrate to the second depth and having the second peak dopant concentration.

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