Semiconductor device and method for manufacturing a semiconductor device

Abstract

A semiconductor device is provided in which degradation of a gate insulating layer is suppressed. A semiconductor device (100a) comprises a semiconductor substrate (1), a gate insulating film (2a), a gate electrode (2b), a first electrical conductor (5a), and a semiconducting insulating layer (3). The gate insulating film (2a) is formed on the semiconductor substrate (1). The gate electrode (2b) is formed on the semiconductor substrate (1), with the gate insulating film (2a) positioned between them. The first electrical conductor (5a) is connected to the gate electrode (2b). The semiconducting insulating layer (3) is connected to at least one of the gate electrodes (2b) and the first electrical conductor (5a).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This non-provisional application is based on Japanese Patent Application No. 2023-183706 filed with the Japan Patent Office on October 26, 2023, the entire contents of which are hereby incorporated by reference. BACKGROUND OF THE INVENTIONField of the invention

[0002] The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. Description of the background technology

[0003] In a process for manufacturing a semiconductor device, an amorphous carbon film that delivers charge to a semiconductor substrate is formed to suppress charging of a gate insulating layer (see, for example, Japanese Patent Laid-Open No. 7-245390). By forming such an amorphous carbon film, charging during ion implantation is suppressed in the process for manufacturing the semiconductor device. SUMMARY OF THE INVENTION

[0004] However, the amorphous carbon film described above is removed after ion implantation. Accordingly, the gate insulating layer may become charged in a step after ion implantation, and the gate insulating layer may deteriorate.

[0005] The present disclosure has been made to solve the above-mentioned problem, and an object of the present disclosure is to provide a semiconductor device in which deterioration of a gate insulating film is suppressed.

[0006] A semiconductor device according to the present disclosure includes a semiconductor substrate, a gate insulating film, a gate electrode, a first electrically conductive pattern, and a semiconductive insulating layer. The gate insulating film is formed on the semiconductor substrate. The gate electrode is formed on the semiconductor substrate with the gate insulating film interposed therebetween. The first electrically conductive pattern is connected to the gate electrode. The semiconductive insulating layer is connected to at least one of the gate electrode and the first electrically conductive pattern.

[0007] A method of manufacturing a semiconductor device according to the present disclosure includes preparing a semiconductor substrate, forming a first semiconductive insulating layer on the semiconductor substrate, and rotating the semiconductor substrate after forming the first semiconductive insulating layer.

[0008] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. Fig. 2 is a schematic plan view of the semiconductor device according to the first embodiment. Fig. 3 is a flowchart of a method for manufacturing the semiconductor device according to the first embodiment. Fig. 4 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor device according to the first embodiment. Fig. 5 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor device according to the first embodiment. Fig. 6 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor device according to the first embodiment. Fig. 7 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor device according to the first embodiment. Fig. 8 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor device according to the first embodiment. Fig. 9 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor device according to the first embodiment. Fig. 10 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor device according to the first embodiment. Fig. 11 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor device according to the first embodiment. Fig. 12 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor device according to the first embodiment. Fig. 13 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor device according to the first embodiment. Fig. 14 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor device according to the first embodiment. Fig. 15 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor device according to the first embodiment. Fig. 16 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor device according to the first embodiment. Fig. 17 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. Fig. 18 is a flowchart of a method for manufacturing the semiconductor device according to the second embodiment. Fig. 19 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor device according to the second embodiment. Fig. 20 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. Fig. 21 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Embodiments of the present disclosure will be described below. It should be noted that, unless otherwise indicated, identical or corresponding parts in the drawings are designated by the same reference numerals below, and their descriptions will not be repeated. First embodiment<Konfiguration einer Halbleitervorrichtung>

[0010] Fig. 1 is a schematic cross-sectional view of a semiconductor device 100a according to a first embodiment. Fig. 2 is a schematic plan view of the semiconductor device 100a according to the first embodiment.

[0011] The Fig. The semiconductor device 100a shown in Figure 1 is, for example, a semiconductor device 100a for an integrated circuit (IC) and mainly comprises a semiconductor substrate 1, a gate insulating film 2a, a gate electrode 2b, a semiconductive insulating layer 3, an interlayer insulating layer 4, and an electrical wiring 5. It should be noted that in Fig. 2 the electrical conductor track 5 is not shown. In Fig. 2, the outer shape of the semiconducting insulating layer 3 is indicated by dashed lines.

[0012] As in Fig. 1, the semiconductor substrate 1 has a first main surface 11 and a second main surface 12. The second main surface 12 is a surface opposite the first main surface 11. Each of the first main surface 11 and the second main surface 12 extends in an x-direction and a y-direction perpendicular to the x-direction. A z-direction is a thickness direction of the semiconductor substrate 1. A normal direction of the first main surface 11 is the z-direction perpendicular to the x-direction and the y-direction. The first main surface 11 faces in a (+z) direction. The second main surface 12 faces in a (-z) direction. A material constituting the semiconductor substrate 1 is, for example, silicon. The material forming the semiconductor substrate 1 may be a substrate made of a wide band gap semiconductor, for example silicon carbide (SiC), gallium nitride (GaN) or gallium oxide (Ga2O3).

[0013] The concentration of an impurity contained in the semiconductor substrate 1 can be adjusted according to the withstand voltage characteristic of the semiconductor device 100a.

[0014] The conductivity type of the semiconductor substrate 1 may be n-type or p-type. A plurality of diffusion layers 13 are formed on the first main surface 11. If the conductivity type of the semiconductor substrate 1 is n-type, the conductivity type of the diffusion layers 13 may be p-type. If the conductivity type of the semiconductor substrate 1 is p-type, the conductivity type of the diffusion layers 13 may be n-type. As shown in Fig. 1, the plurality of diffusion layers 13 are formed spaced apart from one another on the first main surface 11.

[0015] As in Fig. As shown in FIG. 1, the gate insulating film 2a is formed on the first main surface 11 of the semiconductor substrate 1. In a plan view of the first main surface 11, the gate insulating film 2a is sandwiched between a pair of diffusion layers 13. In the plan view of the first main surface 11, the gate insulating film 2a partially overlaps the diffusion layers 13. A material constituting the gate insulating film 2a is, for example, silicon dioxide (SiO2).

[0016] As in Fig. As shown in Figure 1, the gate electrode 2b is formed on the gate insulating film 2a. Viewed from another angle, the gate electrode 2b is formed on the semiconductor substrate 1 with the gate insulating film 2a interposed therebetween. A material forming the gate electrode 2b may be, for example, polysilicon.

[0017] As in Fig. 1, the semiconductive insulating layer 3 is formed on the semiconductor substrate 1 so as to cover the first main surface 11 and the gate electrode 2b in the plan view of the first main surface 11. The semiconductive insulating layer 3 does not need to be directly connected to the gate electrode 2b. As described later, the semiconductive insulating layer 3 may be formed on a front surface 41 of the interlayer insulating layer 4 and may be disposed between the front surface 41 and a first electrical wiring pattern 5a in the z direction. The semiconductive insulating layer 3 may be formed so as to cover the front surface 41 and the first electrical wiring pattern 5a in a plan view of the front surface 41 of the interlayer insulating layer 4.

[0018] A material forming the semiconducting insulating layer 3 is, for example, a material containing semiconducting silicon nitride (SiNSiN) and / or silicon dioxide (SiO2). As described later, the semiconducting insulating layer 3 is formed by plasma CVD (chemical vapor deposition).

[0019] The semiconductive insulating layer 3 formed by the above-described material exhibits high insulation at low temperatures and high conductivity at high temperatures. From another perspective, the electrical resistivity of the semiconductive insulating layer 3 when the semiconductive insulating layer 3 is at 27°C (room temperature) is higher than the electrical resistivity of the semiconductive insulating layer 3 when the semiconductive insulating layer 3 is at 150°C. Specifically, the electrical resistivity of the semiconductive insulating layer 3 at room temperature (27°C) can be approximately 1×1012 Ωcm. The electrical resistivity of the semiconducting insulating layer 3 at 150°C can change to 1 / 1000 or less compared to the electrical resistivity at room temperature (27°C).

[0020] The electrical resistivity of the semiconducting insulating layer 3 can, when the semiconducting insulating layer 3 has a temperature of 27°C, be greater than or equal to 1×10 11 Ωcm and less than or equal to 1×10 13 Ωcm. The electrical resistivity of the semiconducting insulating layer 3 can be less than or equal to 1×10 10Ωcm. Thus, the electrical resistivity of the semiconducting insulating layer 3 exhibits a temperature dependence and changes inversely according to the temperature of the semiconducting insulating layer 3. That is, the electrical resistivity of the semiconducting insulating layer 3 can be adjusted by adjusting the temperature of the semiconducting insulating layer 3.

[0021] As in Fig. As shown in Figure 1, the interlayer insulating layer 4 is disposed on the semiconductor substrate 1. The interlayer insulating layer 4 has a front surface 41 and a rear surface 42. The rear surface 42 faces the semiconductor substrate 1 and the gate electrode 2b. In the first embodiment, the rear surface 42 of the interlayer insulating layer 4 is connected to the semiconductive insulating layer 3. The front surface 41 is a surface opposite the rear surface 42. A material forming the interlayer insulating layer 4 can be, for example, silicon dioxide (SiO2) or tetraethyl orthosilicate (TEOS).

[0022] As in Fig. 1 and Fig. 2, a plurality of contact holes H are formed in the interlayer insulating layer 4. As shown in Fig. 2, the contact holes H comprise a plurality of first contact holes h1 and a plurality of second contact holes h2. The first contact hole h1 reaches the gate electrode 2b from the front surface 41. The second contact hole h2 reaches the first main surface 11 of the semiconductor substrate 1 from the front surface 41. As shown in Fig. As shown in Figure 2, the first contact hole h1 and the second contact hole h2 are arranged so as to be spaced apart from each other. Viewed from another angle, in the front surface 41 of the interlayer insulating film 4, the first contact hole h1 is arranged at a position where it overlaps the gate electrode 2b. The second contact hole h2 is arranged at a position where it does not overlap the gate electrode 2b.

[0023] As in Fig. 1, the electrical conductor 5 is formed so as to fill the contact holes H. The electrical conductor 5 includes a first electrical conductor 5a and a second electrical conductor 5b (not shown). The first electrical conductor 5a provides conduction to the gate electrode 2b. The second electrical conductor 5b provides conduction to the semiconductor substrate 1. The first electrical conductor 5a is connected to the gate electrode 2b, an inner peripheral surface hs1 of the first contact hole h1, and the front surface 41 of the interlayer insulating film 4, with a barrier metal 6 interposed therebetween. The second electrical conductor 5b is connected to the first main surface 11 of the semiconductor substrate 1, an inner peripheral surface hs2 of the second contact hole h2 (see Fig. 20) and the front surface 41 of the interlayer insulating layer 4, with the barrier metal 6 disposed therebetween.

[0024] By forming the second contact hole h2 reaching the first main surface 11 of the semiconductor substrate 1 from the front surface 41, the second electrically conductive path 5b can be formed, which provides conduction to the semiconductor substrate 1. This allows more charges to be transferred to the semiconductor substrate 1. As a result, deterioration of the gate insulating film 2a can be further suppressed, as described later.

[0025] A material forming the electrical wiring 5 may be, for example, any metal. The electrical wiring 5 may be a single layer or may have a structure including a plurality of layers stacked in the z-direction. Specifically, the electrical wiring 5 is formed by depositing an aluminum alloy (for example, an Al-Si-based alloy) on the front surface 41 of the interlayer insulating film 4 and the inner peripheral surfaces of the contact holes H using PVD (Physical Vapor Deposition) such as sputtering or vapor deposition. A nickel alloy (a Ni alloy) may be formed on the aluminum alloy using electroless plating or electrolytic plating. The electrical wiring 5 can be formed by stacking the aluminum alloy and the nickel alloy in this way.

[0026] The above-described electrical conductor 5 is formed on the barrier metal 6. That is, the barrier metal 6 is formed on a contact interface between the electrical conductor 5 and the interlayer insulating layer 4, on a contact interface between the electrical conductor 5 and the gate electrode 2b, and on a contact interface between the electrical conductor 5 and the semiconductor substrate 1. A material constituting the barrier metal 6 is, for example, titanium (Ti) or titanium nitride (TiN).

[0027] The semiconductor device 100a according to the first embodiment is characterized here in that the semiconductor device 100a has the semiconductive insulating layer 3 as shown in Fig. 1. Since the semiconductive insulating layer 3 is formed, a charge generated during a process of manufacturing the semiconductor device 100a can be transferred to an outer peripheral portion (not shown) of the semiconductor substrate 1 via the semiconductive insulating layer 3. As a result, no charge is accumulated in the gate insulating film 2a, and deterioration of the gate insulating film 2a can be suppressed.

[0028] Furthermore, the electrical resistivity of the semiconductive insulating layer 3 exhibits temperature dependence. Accordingly, in a high-temperature condition such as during etching treatment and ion implantation treatment, the semiconductive insulating layer 3 exhibits high conductivity. Thus, the charge generated during the process of manufacturing the semiconductor device 100a can be transferred to the semiconductor substrate 1. On the other hand, at room temperature or at a temperature at which the semiconductor device 100a is operated, the semiconductive insulating layer 3 exhibits high insulation. Thus, there is no need to remove the semiconductive insulating layer 3 during the process of manufacturing the semiconductor device 100a, and the semiconductive insulating layer 3 can remain after the manufacturing of the semiconductor device 100a is completed.That is, since the semiconductive insulating layer 3 remains without being removed until the fabrication of the semiconductor device 100a is completed, a charge can be transferred to the semiconductor substrate 1, for example, when a process involving high temperature is performed, even after the ion implantation treatment is completed. As a result, no charge accumulates in the gate insulating film 2a, and deterioration of the gate insulating film 2a can be suppressed.

[0029] The film formation area of ​​the semiconductive insulating layer 3 is not particularly limited, and the semiconductive insulating layer 3 can be formed over the entire first main surface 11 of the semiconductor substrate 1. However, the semiconductive insulating layer 3 has a high dielectric constant. Accordingly, if the semiconductive insulating layer 3 is formed over the entire first main surface 11 of the semiconductor substrate 1, the semiconductor device 100a can have an increased load capacity.

[0030] The semiconducting insulating layer 3 can be as in Fig. 2. The semiconductive insulating layer 3 may be formed in a strip shape. The semiconductive insulating layer 3 includes a plurality of layers. In the plan view of the first main surface 11, the plurality of layers are arranged to be spaced apart from each other in the y-direction. Specifically, the semiconductive insulating layer 3 may include a first layer 31 and a second layer 32. In the plan view of the first main surface 11, the first layer 31 and the second layer 32 may be arranged to be spaced apart from each other in the y-direction. This allows the charge to be transferred to the semiconductor substrate 1 while suppressing an increase in the charging capacity of the semiconductor device 100a.Furthermore, a stress applied to the semiconductor substrate 1 when the semiconductive insulating layer 3 is formed in a stripe shape is lower than a stress applied to the semiconductor substrate 1 when the semiconductive insulating layer 3 is formed over the entire first main surface 11. As a result, warpage of the semiconductor substrate 1 can be suppressed.

[0031] In the plan view of the first main surface 11, the semiconductive insulating layer 3 may be formed to extend to an end surface (not shown) connecting the first main surface 11 and the second main surface 12 of the semiconductor substrate 1. This allows the charge to be conducted away from the end surface of the semiconductor substrate 1. As a result, no charge accumulates in the gate insulating film 2a, and deterioration of the gate insulating film 2a can be further suppressed.

[0032] As described above, the semiconductive insulating layer 3 can be formed on the semiconductor substrate 1 so as to cover the first main surface 11 and the gate electrode 2b in the plan view of the first main surface 11. This increases the contact area between the semiconductive insulating layer 3 and the semiconductor substrate 1, and more charges can be transferred to the semiconductor substrate 1. As a result, no charge accumulates in the gate insulating film 2a, and deterioration of the gate insulating film 2a can be suppressed.

[0033] A thickness t of the semiconductive insulating layer 3 in the z-direction may be greater than or equal to 50 nm. This stabilizes control of the film thickness in the semiconductive insulating layer 3 during the process of manufacturing the semiconductor device 100a.

[0034] The thickness t of the semiconductive insulating layer 3 in the z-direction can be less than or equal to 100 nm. This can suppress an increase in the charging capacity of the semiconductor device 100a. Furthermore, a stress applied to an underlying layer of the semiconductive insulating layer 3 decreases, and the occurrence of a crack in the underlying layer can be suppressed. Furthermore, a stress applied to the semiconductor substrate 1 decreases, and deformation of the semiconductor substrate 1 can be suppressed. As a result, the semiconductor device 100a can be stably manufactured. <Verfahren zum Herstellen der Halbleitervorrichtung>

[0035] Hereinafter, a method for manufacturing the semiconductor device 100a in the present embodiment will be described. Fig. 3 is a flowchart of the method for manufacturing the semiconductor device 100a according to the first embodiment. Fig. 4 to 16 are each a cross-sectional view illustrating a step of the method for manufacturing the semiconductor device 100a according to the first embodiment.

[0036] First, the step of preparing the semiconductor substrate 1 (S1a) is carried out. In this step (S1a), as in Fig. As shown in Figure 4, a semiconductor substrate 1 is prepared as a silicon wafer, which is a semiconductor material. The conductivity type of the semiconductor substrate 1 may be n-type or p-type. It should be noted that in the method for manufacturing the semiconductor device 100a according to the first embodiment, the conductivity type of the semiconductor substrate 1 is assumed to be n-type.

[0037] Thereafter, the step of forming a first semiconducting insulating layer 3a (S2a) is carried out. In this step (S2a), as shown in Fig. As shown in Figure 5, a first semiconductive insulating layer 3a is formed on the semiconductor substrate 1. The first semiconductive insulating layer 3a is formed by plasma CVD. A material forming the first semiconductive insulating layer 3a may be any material, including, for example, semiconductive silicon nitride (SiNSiN) or silicon dioxide (SiO2).

[0038] Then, the step of rotating the semiconductor substrate 1 (S3a) is carried out. In this step (S3a), as shown in Fig. 6, the semiconductor substrate 1 is cleaned by rotating the semiconductor substrate 1 while passing gas or water. The first semiconductive insulating layer 3a is charged by friction between a surface of the semiconductor substrate 1 having the first semiconductive insulating layer 3a formed thereon and the gas, water, or a deposited film. Conventionally, carbon dioxide (CO2) is added to increase the conductivity of the gas and suppress charging by charge. In contrast, in the method for manufacturing the semiconductor device 100a according to the first embodiment, the addition of carbon dioxide (CO2) is not required in this step (S3a). That is, charging in the first semiconductive insulating layer 3a can be suppressed without passing carbon dioxide (CO2).

[0039] Thereafter, the step of implanting an impurity into the semiconductor substrate 1 (S4a) is carried out. In this step (S4a), as in Fig. 7, a resist 71 is formed on the first semiconducting insulating layer 3a. Thereafter, an impurity is implanted into the semiconductor substrate 1. As a result, as shown in Fig. 8, diffusion layers 13 are formed in the first main surface 11 of the semiconductor substrate 1. As shown in Fig. As shown in Fig. 8, in the plan view of the first main surface 11, diffusion layers 13 are formed in regions where the resist 71 is not formed. When the conductivity type of the semiconductor substrate 1 is n-type, the conductivity type of the diffusion layers 13 may be p-type. When the conductivity type of the semiconductor substrate 1 is p-type, the conductivity type of the diffusion layers 13 may be n-type. Also in this step, a charge caused by the impurity implantation step can be removed via the first semiconductive insulating layer 3a.

[0040] Thereafter, the step of removing the first semiconducting insulating layer 3a (S5a) is carried out. In this step (S5a), as shown in Fig. 9, the resist 71 and the first semiconductive insulating layer 3a are removed by etching. It should be noted that in this step (S5a), only the resist 71 can be removed, and the first semiconductive insulating layer 3a does not need to be removed (not shown), as described later. If the first semiconductive insulating layer 3a is not removed in this step (S5a), the first semiconductive insulating layer 3a forms the semiconductive insulating layer 3.

[0041] Then, the step of forming the gate insulating film 2a (S6a) is performed. In this step (S6a), as shown in Fig. As shown in FIG. 10, the gate insulating film 2a is formed on the first main surface 11 by heating the semiconductor substrate 1 under an oxygen-containing atmosphere. The material forming the gate insulating film 2a is, for example, silicon dioxide (SiO2). It should be noted that, in order to ensure insulation of the gate insulating film 2a, the first semiconductive insulating layer 3a located between the gate insulating film 2a and the first main surface 11 of the semiconductor substrate 1 may be removed in the step of removing the first semiconductive insulating layer 3a (S5a).

[0042] Thereafter, the step of forming the gate electrode 2b (S7a) is carried out. In this step (S7a), as shown in Fig. As shown in Figure 11, the gate electrode 2b is formed by stacking polysilicon on the gate insulating film 2a using CVD. The polysilicon is doped with an n-type or p-type impurity.

[0043] Thereafter, the step of forming a second semiconducting insulating layer 3b (S8a) is carried out. In this step (S8a), as shown in Fig. As shown in Figure 12, the second semiconductive insulating layer 3b is formed on the semiconductor substrate 1. The second semiconductive insulating layer 3b is formed by plasma CVD. The material forming the second semiconductive insulating layer 3b may, for example, be the same as the material forming the first semiconductive insulating layer 3a, or it may be different from the material forming the first semiconductive insulating layer 3a.

[0044] The second semiconductive insulating layer 3b forms the semiconductive insulating layer 3. When the step of removing the first semiconductive insulating layer 3a (S5a) is not performed, the semiconductive insulating layer 3 disposed between the first main surface 11 of the semiconductor substrate 1 and the interlayer insulating layer 4 has a two-layer structure including the first semiconductive insulating layer 3a and the second semiconductive insulating layer 3b.

[0045] When the material forming the second semiconductive insulating layer 3b is the same as the material forming the first semiconductive insulating layer 3a, it is difficult to identify a boundary between the first semiconductive insulating layer 3a and the second semiconductive insulating layer 3b. As a result, the semiconductive insulating layer 3 looks like a single-layer structure. However, a thickness t2 in the z-direction of the semiconductive insulating layer 3 disposed between the first main surface 11 of the semiconductor substrate 1 and the interlayer insulating layer 4 is greater than a thickness t1 in the z-direction of the semiconductive insulating layer 3 disposed between the gate electrode 2b and the interlayer insulating layer 4.Accordingly, it is possible to determine whether or not the semiconductive insulating layer 3 has a two-layer structure comprising the first semiconductive insulating layer 3a and the second semiconductive insulating layer 3b by comparing the thickness t2 in the z-direction of the semiconductive insulating layer 3 disposed between the first main surface 11 of the semiconductor substrate 1 and the interlayer insulating layer 4 with the thickness t1 in the z-direction of the semiconductive insulating layer 3 disposed between the gate electrode 2b and the interlayer insulating layer 4.

[0046] The thicknesses (t1 and t2) in the z-direction of the semiconducting insulating layer 3 may, for example, be greater than or equal to 50 nm and less than or equal to 1 nm.

[0047] Thereafter, the step of forming the interlayer insulating layer 4 (S9a) is carried out. In this step (S9a), as shown in Fig. As shown in Figure 13, the interlayer insulating layer 4 is formed on the semiconducting insulating layer 3. The material forming the interlayer insulating layer 4 may be, for example, silicon dioxide (SiO2) or tetraethylorthosilicate (TEOS).

[0048] Thereafter, the step of forming the contact holes H (S10a) is carried out. In this step (S10a), as shown in Fig. 14, a resist 72 is formed on the front surface 41 of the interlayer insulating layer 4. The resist 72 has an opening 72a. In the plan view of the front surface 41, the opening 72a is located at a position where it overlaps the gate electrode 2b. By etching the interlayer insulating layer 4 and the semiconductive insulating layer 3 using the resist 72 as a mask, as shown in Fig. 15, a first contact hole h1 is formed. The first contact hole h1 reaches the gate electrode 2b from the front surface 41.

[0049] Although not shown, the resist 72 may have an opening 72b (not shown). In the plan view of the front surface 41, the opening 72b is located at a position different from that of the opening 72a. By etching the interlayer insulating film 4 and the semiconductive insulating film 3 using the resist 72 as a mask, a second contact hole h2 (not shown) is formed. The second contact hole h2 reaches the first main surface 11 of the semiconductor substrate 1 from the front surface 41. Thereafter, the resist 72 is removed.

[0050] Then, the step of forming the electrical conductor 5 (S11a) is carried out. In this step (S11a), as shown in Fig. 16, the electrically conductive pattern 5 is formed to fill the contact holes H. A first electrically conductive pattern 5a is connected to the gate electrode 2b, the inner peripheral surface hs1 of the first contact hole h1, and the front surface 41 of the interlayer insulating film 4, with a barrier metal 6 interposed therebetween. Although not shown, a second electrically conductive pattern 5b is connected to the first main surface 11 of the semiconductor substrate 1, the inner peripheral surface hs2 of the second contact hole h2, and the front surface 41 of the interlayer insulating film 4, with the barrier metal 6 interposed therebetween.

[0051] The material forming the electrical wiring 5 may be, for example, any metal. The electrical wiring 5 may be a single layer or may have a structure including a plurality of layers stacked in the z-direction. Specifically, the electrical wiring 5 is formed by stacking an aluminum alloy (for example, an Al-Si-based alloy) on the front surface 41 of the interlayer insulating film 4 and the inner peripheral surfaces of the contact holes H using PVD (Physical Vapor Deposition) such as sputtering or vapor deposition. A nickel alloy (a Ni alloy) may be formed on the aluminum alloy using electroless plating or electrolytic plating. The electrical wiring 5 can be formed by stacking the aluminum alloy and the nickel alloy in this way.

[0052] By using plating, it is easy to form a thick electrical conductor 5. Accordingly, by forming a thick electrical conductor 5, the heat capacity of the electrical conductor 5 increases, and thus the heat resistance of the semiconductor device 100a is improved.

[0053] The above-described electrical conductor 5 is formed on a barrier metal 6. That is, the barrier metal 6 is formed on the contact interface between the electrical conductor 5 and the interlayer insulating layer 4, on the contact interface between the electrical conductor 5 and the gate electrode 2b, and on the contact interface between the electrical conductor 5 and the semiconductor substrate 1. The material forming the barrier metal 6 is, for example, titanium (Ti) or titanium nitride (TiN).

[0054] The thickness t of the semiconducting insulating layer 3 in the z-direction may be less than or equal to 100 nm.

[0055] Thereafter, the step of performing dicing (S12a) is carried out. In this step (S12a), by dicing the semiconductor substrate 1 using a laser dicing or a blade dicing, the Fig. 1 is manufactured. By cutting the semiconductor substrate 1 in a matrix shape, a plurality of semiconductor devices 100a are manufactured.

[0056] Thereby, the charge generated during the process of manufacturing the semiconductor device 100a can be transmitted to the outer peripheral portion of the semiconductor substrate 1 via the semiconductive insulating layer 3. Specifically, during the process of manufacturing the semiconductor device 100a, charging of the first semiconductive insulating layer 3a due to friction between the first main surface 11 of the semiconductor substrate 1 and the gas, water, or deposited film in the step of rotating the semiconductor substrate 1 (S3a) and charging by an ion beam in the step of implanting the impurity into the semiconductor substrate 1 (S4a), that is, charging by a positive charge generated by directing positive ions from the ion beam to the semiconductor substrate 1, are suppressed. Furthermore, addition of carbon dioxide (CO2) in the step of rotating the semiconductor substrate 1 (S3a) is not required.

[0057] As a result, it is possible to obtain a semiconductor device 100a in which no charge accumulates in the gate insulating film 2a and deterioration of the gate insulating film 2a is suppressed.

[0058] Furthermore, the electrical resistivity of the semiconductive insulating layer 3 exhibits a temperature dependence. Accordingly, in a high-temperature state, such as during etching treatment and ion implantation treatment, the semiconductive insulating layer 3 exhibits high conductivity. Thus, the charge generated during the process of manufacturing the semiconductor device 100a can be transferred to the semiconductor substrate 1. On the other hand, in a low-temperature state at a relatively low temperature, such as room temperature or a temperature at which the semiconductor device 100a is operated, the semiconductive insulating layer 3 exhibits high insulation.Thus, it is not necessary to remove the semiconductive insulating layer 3 during the process of manufacturing the semiconductor device 100a, and the semiconductive insulating layer 3 may remain after the manufacturing of the semiconductor device 100a is completed. <Funktion und Effekt>

[0059] The semiconductor device 100a according to the present disclosure includes the semiconductor substrate 1, the gate insulating film 2a, the gate electrode 2b, the first electrically conductive line 5a, and the semiconductive insulating layer 3. The gate insulating film 2a is formed on the semiconductor substrate 1. The gate electrode 2b is formed on the semiconductor substrate 1 with the gate insulating film 2a interposed therebetween. The first electrically conductive line 5a is connected to the gate electrode 2b. The semiconductive insulating layer 3 is connected to the gate electrode 2b and / or the first electrically conductive line 5a.

[0060] Thereby, the charge generated during the process of manufacturing the semiconductor device 100a can be transferred to the outer peripheral portion of the semiconductor substrate 1 via the semiconductive insulating layer 3. Specifically, during the process of manufacturing the semiconductor device 100a, the charging of the first semiconductive insulating layer 3a due to friction between the first main surface 11 of the semiconductor substrate 1 and the gas, water, or deposited film in the step of rotating the semiconductor substrate 1 (S3a), the charging by an ion beam in the step of implanting the impurity into the semiconductor substrate 1 (S4a), and the like are suppressed. Furthermore, the addition of carbon dioxide (CO2) in the step of rotating the semiconductor substrate 1 (S3a) is not required.As a result, it is possible to obtain a semiconductor device 100a in which no charge accumulates in the gate insulating film 2a and deterioration of the gate insulating film 2a is suppressed.

[0061] Furthermore, the electrical resistivity of the semiconductive insulating layer 3 exhibits a temperature dependence. Accordingly, in a high-temperature state, such as during etching treatment and ion implantation treatment, the semiconductive insulating layer 3 exhibits high conductivity. Thus, the charge generated during the process of manufacturing the semiconductor device 100a can be transferred to the semiconductor substrate 1. On the other hand, in a low-temperature state, such as at room temperature or when the semiconductor device 100a is operated, the semiconductive insulating layer 3 exhibits high insulation. Thus, it is not necessary to remove the semiconductive insulating layer 3 during the process of manufacturing the semiconductor device 100a, and the semiconductive insulating layer 3 can remain after the manufacturing of the semiconductor device 100a is completed.

[0062] In the semiconductor device 100a, the electrical resistivity of the semiconductive insulating layer 3 when the semiconductive insulating layer 3 has a temperature of 27°C is higher than the electrical resistivity of the semiconductive insulating layer 3 when the semiconductive insulating layer 3 has a temperature of 150°C.

[0063] As a result, during the manufacturing process of the semiconductor device 100a, the semiconductive insulating layer 3 exhibits high conductivity. Thus, the charge generated during the manufacturing process of the semiconductor device 100a can be transferred to the semiconductor substrate 1. On the other hand, in a low-temperature state, such as when the semiconductor device 100a is operating, the semiconductive insulating layer 3 exhibits high insulation. Thus, it is not necessary to remove the semiconductive insulating layer 3 during the manufacturing process of the semiconductor device 100a, and the semiconductive insulating layer 3 can remain after the manufacturing of the semiconductor device 100a is completed.

[0064] In the semiconductor device 100a, the electrical resistivity of the semiconductive insulating layer 3 when the semiconductive insulating layer 3 has a temperature of 27°C is greater than or equal to 1×10 11Ωcm and less than or equal to 1×10 13 Ωcm.

[0065] As a result, in a room-temperature state, such as when the semiconductor device 100a is operating, the semiconductive insulating layer 3 exhibits high insulation. Thus, it is not necessary to remove the semiconductive insulating layer 3 during the process of manufacturing the semiconductor device 100a, and the semiconductive insulating layer 3 can remain after the manufacturing of the semiconductor device 100a is completed.

[0066] In the semiconductor device 100a, the electrical resistivity of the semiconductive insulating layer 3 when the semiconductive insulating layer 3 has a temperature of 150°C is less than or equal to 1×10 10 Ωcm.

[0067] As a result, the semiconducting insulating layer 3 can have a high conductivity during the process of manufacturing the semiconductor device 100a. Thus, the charge generated during the process of manufacturing the semiconductor device 100a can be transferred to the semiconductor substrate 1.

[0068] In the semiconductor device 100a, the material forming the semiconductive insulating layer 3 includes semiconductive silicon nitride and / or silicon dioxide.

[0069] As a result, during the manufacturing process of the semiconductor device 100a, the semiconductive insulating layer 3 can exhibit high conductivity. Consequently, the charge generated during the manufacturing process of the semiconductor device 100a can be transferred to the semiconductor substrate 1. On the other hand, in a low-temperature state, such as when the semiconductor device 100a is operating, the semiconductive insulating layer 3 exhibits high insulation. Consequently, it is not necessary to remove the semiconductive insulating layer 3 during the manufacturing process of the semiconductor device 100a, and the semiconductive insulating layer 3 can remain after the manufacturing of the semiconductor device 100a is completed.

[0070] In the semiconductor device 100a, the semiconductive insulating layer 3 has a thickness t greater than or equal to 50 nm and less than or equal to 100 nm.

[0071] This allows for stable control of the film thickness in the semiconductive insulating layer 3 during the process of manufacturing the semiconductor device 100a. Furthermore, an increase in the charging capacity of the semiconductor device 100a can be suppressed. Furthermore, the stress applied to the underlying layer of the semiconductive insulating layer 3 decreases, and the occurrence of a crack in the underlying layer can be suppressed. Furthermore, the stress applied to the semiconductor substrate 1 decreases, and deformation of the semiconductor substrate 1 can be suppressed. As a result, the semiconductor device 100a can be stably manufactured.

[0072] The semiconductor device 100a further includes the interlayer insulating layer 4. The interlayer insulating layer 4 is disposed on the semiconductor substrate 1. The interlayer insulating layer 4 has a front surface 41. The front surface 41 is opposite a surface facing the semiconductor substrate 1 and the gate electrode 2b. The first contact hole h1 is formed in the interlayer insulating layer 4. The first contact hole h1 reaches the gate electrode 2b from the front surface 41. The first electrically conductive line 5a is connected to the inner peripheral surface hs1 of the first contact hole h1 and the front surface 41.

[0073] Thereby, the charge generated during the process of manufacturing the semiconductor device 100a can be transferred to the outer peripheral portion of the semiconductor substrate 1 via the semiconductive insulating layer 3. As a result, it is possible to obtain a semiconductor device 100a in which no charge accumulates in the gate insulating film 2a and deterioration of the gate insulating film 2a is suppressed.

[0074] In the semiconductor device 100a, the semiconductive insulating layer 3 includes a first layer 31 and a second layer 32. In a plan view of the semiconductor substrate 1, the first layer 31 and the second layer 32 are arranged so as to be spaced apart from each other.

[0075] This allows the charge to be transferred to the semiconductor substrate 1 while suppressing an increase in the charging capacity of the semiconductor device 100a. Furthermore, the stress applied to the semiconductor substrate 1 when the semiconductive insulating layer 3 is formed in a stripe shape is lower than the stress applied to the semiconductor substrate 1 when the semiconductive insulating layer 3 is formed over the entire first main surface 11. As a result, deformation of the semiconductor substrate 1 can be suppressed.

[0076] A method of manufacturing the semiconductor device 100a according to the present disclosure includes the step of preparing the semiconductor substrate 1 (S1a), the step of forming the first semiconductive insulating layer 3a on the semiconductor substrate 1 (S2a), and the step of rotating the semiconductor substrate 1 (S3a) after the step of forming the first semiconductive insulating layer 3a (S2a).

[0077] As a result, the charge generated during the process of manufacturing the semiconductor device 100a can be transferred to the outer peripheral portion of the semiconductor substrate 1 via the semiconductive insulating layer 3. Specifically, the charging of the first semiconductive insulating layer 3a is suppressed by the friction between the surface of the semiconductor substrate 1 having the first semiconductive insulating layer 3a formed thereon and the gas, water, or deposited film in the step of rotating the semiconductor substrate 1 (S3a). Furthermore, in the step of rotating the semiconductor substrate 1 (S3a), adding carbon dioxide (CO2) to the gas is not required. As a result, it is possible to obtain the semiconductor device 100a in which no charge accumulates in the gate insulating film 2a and deterioration of the gate insulating film 2a is suppressed.

[0078] The method for manufacturing the semiconductor device 100a further includes the step of implanting an impurity into the semiconductor substrate 1 (S4a) after the step of forming the first semiconductive insulating layer 3a (S2a), the step of removing the first semiconductive insulating layer 3a (S5a) after the step of implanting the impurity (S4a), the step of forming the gate electrode 2b on the semiconductor substrate 1 (S7a) after the step of removing the first semiconductive insulating layer 3a (S5a), and the step of forming the second semiconductive insulating layer 3b to cover the gate electrode 2b (S8a) after the step of forming the gate electrode 2b (S7a).

[0079] This allows the charge generated during the process of manufacturing the semiconductor device 100a to be transferred to the outer peripheral portion of the semiconductor substrate 1 via the semiconductive insulating layer 3. Specifically, charging by an ion beam in the step of implanting the impurity into the semiconductor substrate 1 (S4a) and the like are suppressed. As a result, it is possible to obtain the semiconductor device 100a in which no charge accumulates in the gate insulating film 2a and deterioration of the gate insulating film 2a is suppressed. Second embodiment<Konfiguration einer Halbleitervorrichtung>

[0080] Fig. 17 is a schematic cross-sectional view of a semiconductor device 100b according to a second embodiment. Fig. 17 corresponds to Fig. 1. The Fig. 17 has substantially the same configuration as that of the semiconductor device 100b shown in Fig. 1 and differs in that it is not the semiconductor device 100a for an integrated circuit, but rather a semiconductor device 100b for a power semiconductor. If the semiconductor device 100b is intended for a power semiconductor, a drain electrode 8 may be formed on the second main surface 12 of the semiconductor substrate 1, if necessary.

[0081] A material forming the drain electrode 8 may include, for example, an aluminum-silicon alloy, titanium, nickel, and / or gold. The drain electrode 8 may be formed by stacking a variety of metals such as an aluminum-silicon alloy, titanium, nickel, and gold. Furthermore, a metal film formed by PVD may be further formed on a metal film formed by electroless plating or electrolytic plating. The drain electrode 8 may be formed by stacking the metal film formed by PVD and the metal film formed by electroless plating or electrolytic plating in this manner.

[0082] The semiconductive insulating layer 3 may be formed on the front surface 41 of the interlayer insulating layer 4. From another viewpoint, as shown in Fig. 17, the semiconductive insulating layer 3 may be arranged at a position sandwiched between the first electrical conductor 5a and the interlayer insulating layer 4 in the z-direction. <Verfahren zum Herstellen der Halbleitervorrichtung>

[0083] Hereinafter, a method for manufacturing the semiconductor device 100b in the present embodiment will be described. Fig. 18 is a flowchart of the method for manufacturing the semiconductor device 100b according to the second embodiment. Fig. Fig. 19 is a schematic cross-sectional view illustrating a step of the method for manufacturing the semiconductor device 100b according to the second embodiment. First, the same steps as those in Fig. 4 to 11 are performed in the method for manufacturing the semiconductor device 100a according to the first embodiment. That is, the steps from preparing the semiconductor substrate 1 (S1b) to forming the gate electrode 2b (S7b) are performed.

[0084] Then, the step of forming the interlayer insulating film 4 (S8b) is performed. Specifically, the interlayer insulating film 4 is formed to cover the first main surface 11 of the semiconductor substrate 1 and the gate electrode 2b. That is, the back surface 42 of the interlayer insulating film 4 is connected to the first main surface 11 and the gate electrode 2b.

[0085] Thereafter, the step of forming a second semiconductive insulating layer 3b (S9b) is performed. Specifically, the second semiconductive insulating layer 3b is formed to cover the front surface 41 of the interlayer insulating layer 4. The second semiconductive insulating layer 3b may be formed on an end surface 45 connecting the front surface 41 and the back surface 42 of the interlayer insulating layer 4, and on an end surface 15 connecting the first main surface 11 and the second main surface 12 of the semiconductor substrate 1 (see Fig. 19). The shape of the semiconductive insulating layer 3 may be a stripe shape in which a plurality of layers are arranged so as to be spaced apart from each other in the y-direction as viewed from the front surface 41. Each of the plurality of layers may be formed on the end surface 45 of the interlayer insulating layer 4 and on the end surface 15 of the semiconductor substrate 1.

[0086] The step of forming contact holes H (S10b) is then performed. In this step (S10b), the resist 72 is formed on the second semiconductive insulating layer 3b. The resist 72 has an opening 72a. In the plan view of the front surface 41, the opening 72a is located at a position where it overlaps the gate electrode 2b. By etching the interlayer insulating layer 4 and the semiconductive insulating layer 3 using the resist 72 as a mask, a first contact hole h1 is formed. The first contact hole h1 reaches the gate electrode 2b from the front surface 41.

[0087] When the second semiconductive insulating layer 3b is formed on the end face 45 of the interlayer insulating layer 4 and on the end face 15 of the semiconductor substrate 1 as shown in Fig. 19 in the step of forming the second semiconductive insulating layer 3b (S9b), a second contact hole h2 reaching the first main surface 11 of the semiconductor substrate 1 from an upper surface of the semiconductive insulating layer 3 needs not to be formed, as will be described later.

[0088] Then, the step of forming the electrical conductor 5 (S11b) is performed. In this step (S11b), the electrical conductor 5 is formed to fill the contact holes H. A first electrical conductor 5a is connected to the gate electrode 2b, the inner peripheral surface hs1 of the first contact hole h1, and an upper surface of the second semiconductive insulating layer 3b, with the barrier metal 6 interposed therebetween.

[0089] The material forming the electrical wiring 5 may be, for example, any metal. The electrical wiring 5 may be a single layer or may have a structure including a plurality of layers stacked in the z-direction. Specifically, the electrical wiring 5 is formed by depositing an aluminum alloy (for example, an Al-Si-based alloy) on the front surface 41 of the interlayer insulating film 4 and the inner peripheral surfaces of the contact holes H using PVD (Physical Vapor Deposition) such as sputtering or vapor deposition. A nickel alloy (a Ni alloy) may be formed on the aluminum alloy using electroless plating or electrolytic plating. The electrical wiring 5 may be formed by stacking the aluminum alloy and the nickel alloy in this way.

[0090] By using plating, it is easy to form a thick electrical conductor 5. Accordingly, by forming a thick electrical conductor 5, the heat capacity of the electrical conductor 5 increases, and thus the heat resistance of the semiconductor device 100b is improved.

[0091] The formation of the nickel alloy using plating may be performed after the step of forming the drain electrode (S12b) described later.

[0092] Then, the step of forming the drain electrode 8 (S12b) is carried out. In this step (S12b), as shown in Fig. 19, the drain electrode 8 is formed on the second main surface 12 of the semiconductor substrate 1. This step (S12b) is performed when the semiconductor device 100b is manufactured as a semiconductor device for a power semiconductor. The drain electrode 8 is formed by depositing, for example, an aluminum-silicon alloy, titanium, or the like on the second main surface 12 using PVD such as sputtering or vapor deposition.

[0093] The second semiconductive insulating layer 3b is connected to the drain electrode 8. This allows a charge to be transferred to the drain electrode 8 even in the semiconductor device 100b in which the second contact hole h2 connected to the semiconductor substrate 1 is not formed.

[0094] The material forming the drain electrode 8 may include, for example, an aluminum-silicon alloy, titanium, nickel, and / or gold. The drain electrode 8 may be formed by stacking a variety of metals such as an aluminum-silicon alloy, titanium, nickel, and gold. Furthermore, a metal film may be further formed on a metal film formed by PVD by electroless plating or electrolytic plating. The drain electrode 8 may be formed by stacking the metal film formed by PVD and the metal film formed by electroless plating or electrolytic plating in this manner.

[0095] Then, the step of performing dicing (S13b) is performed. This produces the semiconductor device 100b according to the second embodiment as shown in Fig. 17 shown, manufactured. Third embodiment<Konfiguration einer Halbleitervorrichtung>

[0096] Fig. 20 is a schematic cross-sectional view of a semiconductor device 100c according to a third embodiment. Fig. 20 corresponds to Fig. 1. The Fig. 20 has substantially the same configuration as that of the semiconductor device 100c shown in Fig. 1 and has a difference in that the semiconductive insulating layer 3 is formed on the front surface 41 of the interlayer insulating layer 4. The semiconductive insulating layer 3 is not directly connected to the semiconductor substrate 1. Accordingly, the second contact hole h2 is formed, which reaches the first main surface 11 of the semiconductor substrate 1 from the upper surface of the semiconductive insulating layer 3. Specifically, as shown in Fig. 20, the first contact hole h1 and the second contact hole h2 are arranged so as to be adjacent to each other.

[0097] A second electrical conductor 5b provides a line to the semiconductor substrate 1. The second electrical conductor 5b is connected to the first main surface 11 of the semiconductor substrate 1, the inner peripheral surface hs2 of the second contact hole h2, and the upper surface of the semiconductive insulating layer 3, with the barrier metal 6 disposed therebetween.

[0098] When the semiconductive insulating layer 3 is formed on the front surface 41 of the interlayer insulating layer 4, the second electrically conductive path 5b that provides conduction with the semiconductor substrate 1 can be formed by forming the second contact hole h2 that reaches the first main surface 11 of the semiconductor substrate 1 from the upper surface of the semiconductive insulating layer 3. This allows charge to be transferred to the semiconductor substrate 1. As a result, deterioration of the gate insulating film 2a can be further suppressed. <Funktion und Effekt>

[0099] In the semiconductor device 100c, the semiconducting insulating layer 3 is connected to the first electrical conductor 5a and the front surface 41.

[0100] Thereby, the charge generated during the process of manufacturing the semiconductor device 100c can be transferred to the outer peripheral portion of the semiconductor substrate 1 via the semiconductive insulating layer 3. As a result, it is possible to obtain the semiconductor device 100c in which no charge accumulates in the gate insulating film 2a and deterioration of the gate insulating film 2a is suppressed.

[0101] The semiconductor device 100c further includes a second electrically conductive line 5b. The second electrically conductive line 5b is connected to the semiconductive insulating layer 3. The second contact hole h2 is formed in the interlayer insulating layer 4. The second contact hole h2 reaches the semiconductor substrate 1 from the front surface 41. The second electrically conductive line 5b is connected to the inner peripheral surface hs2 of the second contact hole h2 and the front surface 41.

[0102] Thereby, the charge generated during the process of manufacturing the semiconductor device 100c can be transferred to the outer peripheral portion of the semiconductor substrate 1 via the semiconductive insulating layer 3. As a result, it is possible to obtain the semiconductor device 100c in which no charge accumulates in the gate insulating film 2a and deterioration of the gate insulating film 2a is suppressed. Fourth embodiment<Konfiguration einer Halbleitervorrichtung>

[0103] Fig. 21 is a schematic cross-sectional view of a semiconductor device 100d according to a fourth embodiment. Fig. 21 corresponds to Fig. 1. The Fig. 21 has substantially the same configuration as that of the semiconductor device 100d shown in Fig. 1 and has a difference in that the semiconductive insulating layer 3 is formed to cover the front surface 41 and the first electrically conductive line 5a in the plan view of the front surface 41 of the interlayer insulating layer 4. This allows a portion of the charge to be conducted outward from an upper surface of the first electrically conductive line 5a. As a result, deterioration of the gate insulating film 2a can be further suppressed.

[0104] It should be understood that the embodiments disclosed herein are illustrative and not restrictive in all respects. At least two of the embodiments disclosed herein may be combined, provided they are not incompatible. The basic scope of the present disclosure is defined by the scope of the claims, rather than the above description, and is intended to include any modifications within the scope and meaning consistent with the scope of the claims. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2023-183706

[0001] JP 7-245390

[0003]

Claims

[1] A semiconductor device comprising: a semiconductor substrate (1); a gate insulating film (2a) formed on the semiconductor substrate (1); a gate electrode (2b) formed on the semiconductor substrate (1) with the gate insulating film (2a) interposed therebetween; a first electrical conductor track (5a) connected to the gate electrode (2b); and a semiconducting insulating layer (3) connected to at least one of the gate electrode (2b) and the first electrical conductor track (5a). [2] A semiconductor device according to claim 1, wherein the electrical resistivity of the semiconductive insulating layer (3) when the semiconductive insulating layer (3) has a temperature of 27°C is higher than the electrical resistivity of the semiconductive insulating layer (3) when the semiconductive insulating layer (3) has a temperature of 150°C. [3] A semiconductor device according to claim 1 or 2, wherein the electrical resistivity of the semiconductive insulating layer (3) when the semiconductive insulating layer (3) has a temperature of 27°C is greater than or equal to 1×10 11 Ωcm and less than or equal to 1×10 13 Ωcm. [4] A semiconductor device according to any one of claims 1 to 3, wherein the electrical resistivity of the semiconductive insulating layer (3) when the semiconductive insulating layer (3) has a temperature of 150°C is less than or equal to 1×10 10 Ωcm. [5] A semiconductor device according to any one of claims 1 to 4, wherein a material forming the semiconductive insulating layer (3) contains semiconductive silicon nitride and / or silicon dioxide. [6] A semiconductor device according to any one of claims 1 to 5, wherein the semiconductive insulating layer (3) has a thickness (t) greater than or equal to 50 nm and less than or equal to 100 nm. [7] A semiconductor device according to any one of claims 1 to 6, further comprising an interlayer insulating layer (4) disposed on the semiconductor substrate (1), wherein the interlayer insulating layer (4) has a front surface (41) opposite to a surface facing the semiconductor substrate (1) and the gate electrode (2b), a first contact hole (h1) reaching the gate electrode (2b) from the front surface (41) is formed in the interlayer insulating film (4), and the first electrical wiring (5a) is connected to an inner peripheral surface (hs1) of the first contact hole (h1) and the front surface (41). [8] A semiconductor device according to claim 7, wherein the semiconductive insulating layer (3) is connected to the first electrical conductor (5a) and the front surface (41). [9] A semiconductor device according to claim 7 or 8, further comprising a second electrical conductor track (5b) connected to the semiconductive insulating layer (3), wherein a second contact hole (h2) reaching the semiconductor substrate (1) from the front surface (41) is formed in the interlayer insulating layer (4) and the second electrical conductor track (5b) is connected to an inner peripheral surface (hs2) of the second contact hole (h2) and the front surface (41). [10] A semiconductor device according to any one of claims 1 to 9, wherein the semiconducting insulating layer (3) has a first layer (31) and a second layer (32) and in a plan view of the semiconductor substrate (1), the first layer (31) and the second layer (32) are arranged such that they are spaced apart from one another. [11] A method of manufacturing a semiconductor device, the method comprising: Preparing a semiconductor substrate (1) (S1a); Forming a first semiconducting insulating layer (3a) on the semiconductor substrate (1) (S2a); and Rotating the semiconductor substrate (1) (S3a) after forming the first semiconducting insulating layer (3a) (S2a). [12] A method of manufacturing the semiconductor device according to claim 11, further comprising: Implanting an impurity into the semiconductor substrate (1) (S4a) after forming the first semiconducting insulating layer (3a) (S2a); Removing the first semiconducting insulating layer (3a) (S5a) after implanting the impurity (S4a); Forming a gate electrode (2b) on the semiconductor substrate (1) (S7a) after removing the first semiconducting insulating layer (3a) (S5a); and Forming a second semiconductive insulating layer (3b) to cover the gate electrode (2b) (S8a) after forming the gate electrode (2b) (S7a).

Images