3D object reconstruction

Abstract

Devices, systems, and techniques for using one or more neural networks to generate one or more three-dimensional ("3D") objects based at least partially on reflection information. In at least one embodiment, one or more images are processed using a neural network to generate one or more 3D objects that represent objects in the one or more images.

Description

TECHNICAL FIELD

[0001] In at least one embodiment, a neural network is used to generate three-dimensional ("3D") objects using reflection information. BACKGROUND

[0002] Neural networks can generate 3D objects from two-dimensional ("2D") image streams. 2D image streams may not provide complete information about the surfaces of objects in an image to reconstruct an accurate 3D object. 3D object generation can be improved when complete object information is not available. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows an example of a system that can generate and display a 3D object reconstructed from an image stream captured by one or more cameras, according to at least one embodiment; Fig. 2 is an example of a system for generating 3D objects according to at least one embodiment; Fig. 3 is a flow diagram of a system 300 that generates one or more 3D objects from one or more images captured by a device, according to at least one embodiment; Fig. 4 is a flow diagram of a system 400 that trains one or more neural networks to generate a 3D object based on one or more images; Fig. 5 is an example of a system 500 for generating 3D objects from one or more images according to at least one embodiment; Fig. 6 is a block diagram 600 illustrating a driver and / or runtime including one or more libraries to provide one or more application programming interfaces (APIs), according to at least one embodiment; Fig. 7A shows the logic according to at least one embodiment; Fig. 7B shows the logic according to at least one embodiment; Fig. 8 shows the training and deployment of a neural network according to at least one embodiment; Fig. 9 shows an example of a data center system according to at least one embodiment; Fig. 10A shows an example of an autonomous vehicle according to at least one embodiment; Fig. Figure 10B shows an example of camera positions and fields of view for the autonomous vehicle of Fig. 10A, according to at least one embodiment; Fig. 10C is a block diagram showing an example system architecture for the autonomous vehicle of Fig. 10A according to at least one embodiment; Fig. 10D is a diagram illustrating a system for communication between one or more cloud-based servers and the autonomous vehicle of Fig. 10A according to at least one embodiment; Fig. 11 is a block diagram illustrating a computer system according to at least one embodiment; Fig. 12 is a block diagram illustrating a computer system according to at least one embodiment; Fig. 13 shows a computer system according to at least one embodiment; Fig. 14 shows a computer system according to at least one embodiment; Fig. 15A shows a computer system according to at least one embodiment; Fig. 15B shows a computer system according to at least one embodiment; Fig. 15C shows a computer system according to at least one embodiment; Fig. 15D shows a computer system according to at least one embodiment; Fig. 15E and Fig. 15F illustrate a common programming model according to at least one embodiment; Fig. 16 shows exemplary integrated circuits and associated graphics processors according to at least one embodiment; Fig. 17A and Fig. 17B illustrates exemplary integrated circuits and associated graphics processors according to at least one embodiment; Fig. 18A and Fig. 18B illustrates additional exemplary graphics processor logic according to at least one embodiment; Fig. 19 shows a computer system according to at least one embodiment; Fig. 20A shows a parallel processor according to at least one embodiment; Fig. 20B shows a partition unit according to at least one embodiment; Fig. 20C shows a processing cluster according to at least one embodiment; Fig. 20D shows a graphics multiprocessor according to at least one embodiment; Fig. 21 shows a system with multiple graphics processing units (GPU) according to at least one embodiment; Fig. 22 shows a graphics processor according to at least one embodiment; Fig. 23 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment; Fig. 24 shows a deep learning application processor according to at least one embodiment; Fig. 25 is a block diagram illustrating an exemplary neuromorphic processor according to at least one embodiment; Fig. 26 shows at least portions of a graphics processor, according to one or more embodiments; Fig. 27 shows at least portions of a graphics processor according to one or more embodiments; Fig. 28 shows at least portions of a graphics processor according to one or more embodiments; Fig. 29 is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment; Fig. 30 is a block diagram of at least portions of a graphics processor core according to at least one embodiment; Fig. 31A and Fig. 31B illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment; Fig. 32 shows a parallel processing unit ("PPU") according to at least one embodiment; Fig. 33 illustrates a general processing cluster (“GPC”) according to at least one embodiment; Fig. 34 shows a memory partition unit of a parallel processing unit ("PPU") according to at least one embodiment; Fig. 35 shows a streaming multiprocessor according to at least one embodiment; Fig. 36 is an example data flow diagram for an advanced computing pipeline according to at least one embodiment; Fig. 37 is a system diagram for an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment; Fig. 38 includes an example illustration of an advanced computer pipeline 3710A for processing image data in accordance with at least one embodiment; Fig. 39A includes an exemplary data flow diagram of a virtual instrument supporting an ultrasound device, according to at least one embodiment; Fig. 39B includes an example data flow diagram of a virtual instrument supporting a CT scanner, in accordance with at least one embodiment; Fig. 40A shows a data flow diagram for a process for training a machine learning model, in accordance with at least one embodiment; Fig. 40B is an example illustration of a client-server architecture for enhancing annotation tools with pre-trained annotation models, according to at least one embodiment; and Fig. 41 shows components of a system for accessing a large language model according to at least one embodiment. DETAILED DESCRIPTION

[0003] In at least one embodiment, a neural network may generate one or more 3D images of an object based at least in part on reflectance information. In at least one embodiment, a neural network may include a first portion that identifies reflectance properties of a surface of an object in a 2D image stream or video, and a second portion that identifies the depth of an object in frames of a 2D image stream or video. In at least one embodiment, one or more neural networks may identify reflectance properties such as diffuse reflectance, which indicates how much light a surface reflects, and specular reflectance, which indicates how shiny a surface may be.In at least one embodiment, reflection information and depth information may be used as input to a renderer portion of a neural network that uses this information to generate 3D objects.

[0004] In at least one embodiment, a 3D object is an object that has length, width, and height. In at least one embodiment, a 3D object is a virtual object represented by a data structure that has values ​​representing the length, width, and height of the virtual object. In at least one embodiment, a 3D object may be a virtual object in which the shape of the 3D object, as well as its color and appearance, are represented as values ​​stored in a data structure. In at least one embodiment, a 3D image is an image that contains one or more 3D objects.

[0005] In at least one embodiment, a 2D image is an image captured by a camera that represents a 3D environment containing one or more 3D objects. In at least one embodiment, a 2D image is an image that has a length and a width and is represented as values ​​in a 2D data structure. In at least one embodiment, a 2D image is an image that contains one or more 2D objects, where a 2D object is an object that has a length and a width.

[0006] Fig. 1 shows an example of a system 100 that can create and display a 3D object reconstructed from an image stream captured by one or more cameras 102, according to at least one embodiment. In at least one embodiment, the system 100 can include one or more cameras 102, an object reconstruction system 104, and a display device 120. In at least one embodiment, one or more cameras 102 can be a digital camera for capturing images, streaming images, and videos of an environment containing one or more 3D objects. In at least one embodiment, one or more cameras 102 can be monoscopic or stereoscopic cameras and can include one or more light sources. In at least one embodiment, one or more cameras 102 can be a monoscopic camera.In at least one embodiment, a monoscopic camera is a device capable of capturing image data of an environment using an image sensor and a lens, and having a view axis. In at least one embodiment, one or more cameras 102 may be a laparoscopic camera with a light source substantially parallel to a view axis of the laparoscopic camera. In at least one embodiment, one or more cameras 102 may be any device capable of capturing images and / or video in an environment.

[0007] In at least one embodiment, one or more cameras 102 provide one or more images, streaming images, and / or videos to the object reconstruction generator 114. In at least one embodiment, the object reconstruction system may include one or more processors 106, a memory 108, and instructions 110. In at least one embodiment, the instructions include a feature map generator 112, an object reconstruction generator 114, and an object rendering engine 116. In at least one embodiment, the instructions 110 may be stored on a non-transitory, machine-readable medium and may access the memory 108 and be executed by one or more processors 106. In at least one embodiment, the object reconstruction system 114 receives one or more images and / or videos from one or more cameras 102.In at least one embodiment, feature map generator 112 uses one or more images or videos from one or more cameras 102 to generate one or more feature maps that identify one or more features present in the one or more images and / or videos. In at least one embodiment, a feature map may be a data structure containing values ​​representing one or more features and / or properties present and identified in one or more images. In at least one embodiment, an object reconstruction generator 114 may generate a 3D object based on a feature map from feature map generator 112. In at least one embodiment, object reconstruction generator 114 generates a 3D object representing an object in an environment captured by one or more cameras 102.

[0008] In at least one embodiment, the object rendering engine 116 renders and displays one or more 3D objects generated by the object reconstruction generator 114. In at least one embodiment, the object rendering engine 116 causes one or more 3D objects to be displayed on a display device 120. In at least one embodiment, the object rendering engine 116 causes a continuous stream of 3D objects generated by the object reconstruction generator 114 to be displayed on the display device 120. In at least one embodiment, a continuous stream of 3D objects generated by the object reconstruction generator is based on a continuous stream of images and / or videos from one or more cameras 102.In at least one embodiment, the object rendering engine 116 causes the 3D objects generated by the object reconstruction generator 114 to be displayed in real time on the display device 120. In at least one embodiment, the 3D objects generated by the object reconstruction generator 114 are stored in memory 108 and can be stored in a long-term storage device for display on a display device 120 at a later time.

[0009] Fig. Figure 2 is an example of a system 200 for generating 3D objects according to at least one embodiment. In at least one embodiment, the system 200 may include the object reconstruction system 104 of Fig. 1. In at least one embodiment, a feature map generator 202 may generate one or more feature maps that identify features contained in one or more input images and / or videos. In at least one embodiment, the feature map generator 202 may identify features related to depth information, color information, and / or color information. In at least one embodiment, the feature map generator 202 may be the feature map generator 112 of Fig. 1.

[0010] In at least one embodiment, a depth decoder 204 may receive one or more feature maps from the feature map generator 202 and generate a depth map 210. In at least one embodiment, the depth decoder 204 may generate a depth map 210 in which a depth of each feature in a feature map is derived using a neural network trained to derive a depth of pixels based on input from one or more feature maps. In at least one embodiment, the depth decoder 204 may derive depth information, which may be an estimated position in 3D space of one or more objects, one or more features, and / or one or more pixels of one or more images. In at least one embodiment, the depth decoder 204 may generate a depth map 210 based on inputs from an albedo map 212 and / or specularity map 216.In at least one embodiment, the depth decoder 204 may be trained to derive the depth of features and / or pixels using at least one feature map, an albedo map 212, and a specularity map 216.

[0011] In at least one embodiment, an albedo decoder 206 may generate an albedo map 212 that identifies color information based on an input feature map from the feature map generator 202. In at least one embodiment, one or more images from one or more cameras may not accurately capture color information from one or more objects in the one or more images. In at least one embodiment, inaccurate color information captured in one or more images may be due to how one or more objects in the one or more images are illuminated, the reflective surfaces of objects in the one or more images, and / or distortions due to camera intrinsics.In at least one embodiment, the albedo decoder 206 is a neural network trained to derive accurate color information from at least one or more objects, one or more features, and / or one or more pixels of one or more images based on a feature map input. In at least one embodiment, an albedo map 212 includes derived color information representing an estimated true color of a pixel or feature of a feature map. In at least one embodiment, the albedo map 212 is a data structure containing one or more values ​​representing estimated true color information from one or more objects, one or more features, and / or one or more images.

[0012] In at least one embodiment, specularity decoder 208 may generate a specularity map 216 that identifies reflectance information based on an input feature map from feature map generator 202. In at least one embodiment, specularity decoder 208 is a neural network trained to infer the reflectance of one or more features based on an input feature map. In at least one embodiment, a specularity map 216 includes derived reflectance information representing an estimated amount of specular and / or diffuse reflections associated with one or more features included in a feature map. In at least one embodiment, specularity map 216 is a data structure containing values ​​representing reflectance information associated with one or more objects, one or more features, and / or one or more images.

[0013] In at least one embodiment, the 3D mesh 218 may be generated using the depth map 210. In at least one embodiment, the 3D mesh 218 is a 3D representation of shapes of objects in a feature map based on derived depth information represented in the depth map 210. In at least one embodiment, the system 200 may include instructions to generate 3D mesh images and / or objects from one or more depth maps 210.

[0014] In at least one embodiment, normal map 220 may be generated using depth map 210. In at least one embodiment, normal map 220 may identify an orientation of surfaces of objects in a feature map based on one or more depth maps. In at least one embodiment, system 200 may include instructions to identify orientations of surfaces of objects in a feature map based on one or more depth maps 210.

[0015] In at least one embodiment, scene textures 222 are image data representing one or more objects from one or more feature maps. In at least one embodiment, scene textures 222 are based on at least one of an albedo map 212, a specularity map 216, and a normal map 220. In at least one embodiment, system 200 may include instructions for generating image data and / or pixel information of one or more objects in one or more feature maps using at least one albedo map 212, a specularity map 216, or a normal map 220.

[0016] In at least one embodiment, a differentiable renderer 224 may generate one or more 3D objects 226 representing one or more objects contained in one or more feature maps. In at least one embodiment, the differentiable renderer 224 may generate 3D objects 226 based on the 3D mesh 218 and scene textures 222, where image data from scene textures 222 may be combined with 3D object shapes from the 3D mesh. In at least one embodiment, the differentiable renderer 224 may be used in conjunction with ground truth 3D objects to generate gradients of loss functions associated with parameters of at least one of the following decoders: depth decoder 204, albede decoder 206, and speculative decoder 208.In at least one embodiment, the differentiable renderer 224 may provide information associated with loss functions of parameters of the depth decoder 204, the albedo decoder 206, and the speculative decoder 208 simultaneously and / or jointly, such that training of the depth decoder 204, the albedo decoder 206, and the speculative decoder 208 may be performed jointly.

[0017] In at least one embodiment, each of the elements depth decoder 204, albedo decoder 206, specularity decoder 208, depth map 210, albedo map 212, specularity map 216, 3D mesh 218, normal map 220, 3D meshes 222, differentiable renderer 224 and 3D objects 226 can be rendered by the object reconstruction system 104 and / or the object reconstruction generator 114 for Fig. 1 can be executed.

[0018] Fig. 3 is a flow diagram of a system 300 that generates one or more 3D objects from one or more images captured by a device, according to at least one embodiment. In at least one embodiment, the system 300 may be implemented by any component of the system 100 of Fig. 1 and / or the system 200 of Fig. 2 are executed.

[0019] In at least one embodiment, at block 302, system 300 receives an image stream that includes one or more images, where each image may include one or more objects.

[0020] In at least one embodiment, at block 304, the system 300 may generate a feature map from the image stream in which features associated with one or more objects included in one or more images are identified.

[0021] In at least one embodiment, in block 306, the system 300 may generate a depth map, an albedo map, and a specularity map based on an input of one or more feature maps generated from an image vapor.

[0022] In at least one embodiment, in block 308, the system 300 may generate a 3D mesh representing one or more shapes of one or more objects in an image stream and may generate a normal map representing one or more orientations of one or more surfaces of one or more objects in an image stream.

[0023] In at least one embodiment, at block 312, system 300 may generate scene textures containing image data associated with one or more objects included in an image stream based on at least one input of an albedo map, a specularity map, and a normal map.

[0024] In at least one embodiment, at block 310, system 300 may generate a 3D rendering of an image stream including at least one 3D object representing an object included in an image stream based on inputs from a 3D mesh and scene textures.

[0025] Fig. 4 is a flowchart of a system 400 that trains one or more neural networks to generate a 3D object based on one or more images. In at least one embodiment, the system 400 may be implemented by any component of the system 100 of Fig. 1 and / or the system 200 of Fig. 2 are executed.

[0026] In at least one embodiment, in block 402, the system 400 obtains and / or maintains unlabeled ground truth images comprising one or more 2D images and one or more 3D objects representing one or more objects within the 2D images.

[0027] In at least one embodiment, in block 404, the system 400 provides 2D training images of the ground truth to at least one depth decoder, albedo decoder, or specularity decoder to generate at least one depth map, an albedo map, or a specularity map.

[0028] In at least one embodiment, system 400 generates one or more 3D objects using ground truth images in block 406. In at least one embodiment, system 400 generates one or more 3D objects using a depth map, albedo map, and specularity map generated in block 404.

[0029] In at least one embodiment, in block 408, the system 400 compares the 3D object generated in block 406 with the ground truth 3D object to determine the values ​​of the loss function.

[0030] In at least one embodiment, in block 410, system 400 uses a differentiable loss function to adjust the weights and / or parameters of at least one depth decoder, albedo decoder, or speculative decoder. In at least one embodiment, in block 410, system 400 adjusts one or more weights and / or parameters of a depth decoder, albedo decoder, and speculative decoder simultaneously and / or jointly. In at least one embodiment, block 410 of system 400 is repeated until the loss function is minimized or a threshold loss is reached.

[0031] In at least one embodiment, in block 412, the system 400 provides a trained depth decoder, albedo decoder, and speculoos decoder for deriving 3D objects from one or more images.

[0032] Fig. 5 is an example of a system 500 for generating 3D objects from one or more images, according to at least one embodiment. In at least one embodiment, the system 500 includes a processor 502, a memory 504, and a storage 506. In at least one embodiment, a processor 502 performs one or more processes as described herein to generate one or more 3D objects based at least in part on reflection information. In at least one embodiment, the processor 502 performs one or more processes as described in connection with Fig. 1-4. In at least one embodiment, the processor 502 comprises one or more processors as described in connection with Fig. 7-51. In at least one embodiment, processor 502 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof.

[0033] In at least one embodiment, processor 502 includes a feature map module 508, a depth map module 510, an albedo map module 512, a specular map module 514, a training module 516, a 3D mesh module 518, a normal map module 520, a surface texture module 522, a differentiable renderer module 524, and a display module 526, which may be distributed across multiple processors communicating via a bus, a network, by writing to shared memory, and / or any suitable communication method, such as those described herein.In at least one embodiment, as used in an implementation described herein, unless the context indicates otherwise or unless expressly stated otherwise, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functions described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein may include, for example, individually or in any combination, hard-wired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution units, and / or firmware storing instructions executed by programmable circuitry.In at least one embodiment, modules may be implemented collectively or individually as circuits that are part of a larger system, such as an integrated circuit (IC), a system-on-chip (SoC), and so forth. In at least one embodiment, a module performs one or more processes in conjunction with any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof.

[0034] In at least one embodiment, the feature map module 508 may generate a feature map from one or more images, image streams, or videos. In at least one embodiment, the depth map module 510 may derive the depth of features and / or pixels of an image based on at least one feature map, an albedo map, and a specularity map. In at least one embodiment, the albedo module 512 derives true color information of an object from a feature map. In at least one embodiment, the specularity module 514 derives reflectance information of one or more objects from a feature map. In at least one embodiment, the training module 516 trains a neural network comprising a depth map decoder, an albedo decoder, and a specularity decoder. In at least one embodiment, the 3D mesh module 518 may generate a 3D mesh representing objects in an image based on a depth map.In at least one embodiment, the normal map module 520 may generate one or more orientations of surfaces of one or more objects in an image based on a depth map. In at least one embodiment, the surface texture module 522 generates image data associated with one or more objects in an image using at least one albedo map and a specularity map. In at least one embodiment, the differentiable renderer module 524 generates a 3D object of an object in an image based on a 3D mesh and surface textures. In at least one embodiment, the display module 526 causes one or more 3D objects to be translated on a display device, either in real time or from 3D objects stored in memory 506.

[0035] Fig. 6 is a block diagram 600 illustrating a driver and / or runtime including one or more libraries to provide one or more application programming interfaces (APIs) in accordance with at least one embodiment. In at least one embodiment, a software program 602 is a software module. In at least one embodiment, a software program 602 includes one or more software modules. In at least one embodiment, one or more software modules are as in Fig. 5 is not exhaustively described. In at least one embodiment, one or more APIs 610 are sets of software instructions that, when executed, cause one or more processors to perform one or more computational operations. In at least one embodiment, one or more APIs 610 are distributed or otherwise provided as part of one or more libraries 606, runtimes 604, drivers 604, and / or other grouping of software and / or executable code described further herein. In at least one embodiment, one or more APIs 610 perform one or more computational operations in response to being invoked by software programs 602.In at least one embodiment, a software program 602 is a collection of software code, commands, instructions, or other text sequences for instructing a computing device to perform one or more computational operations and / or to invoke one or more other sets of instructions, such as APIs 610 or API functions 612, for execution. In at least one embodiment, the functionality provided by one or more APIs 610 includes software functions 612, such as those that can be used to accelerate one or more portions of software programs 602 using one or more parallel processing units (PPUs), such as graphics processing units (GPUs). In at least one embodiment, a software program is a compiler.

[0036] In at least one embodiment, the APIs 610 are hardware interfaces to one or more circuits to perform one or more computational operations. In at least one embodiment, one or more software APIs 610 described herein are implemented as one or more circuits to perform one or more operations associated with Fig. 1-5. In at least one embodiment, one or more software programs 602 comprise instructions that, when executed, cause one or more hardware devices and / or circuits to perform one or more techniques described further in connection with Fig. 1-5 are described.

[0037] In at least one embodiment, software programs 602, such as user-implemented software programs, use one or more application programming interfaces (APIs) 610 to perform various computational operations, such as memory allocation, matrix multiplication, arithmetic operations, or any computational operation performed by parallel processing units (PPUs), such as graphics processing units (GPUs), as further described herein. In at least one embodiment, one or more APIs 610 provide a set of callable functions 612, referred to herein as APIs, API functions, and / or functions, that individually perform one or more computational operations, such as computational operations related to parallel computing.In at least one embodiment, one or more APIs 610 provide functions 612 for using one or more neural networks to generate one or more 3D objects based at least in part on reflection information. In at least one embodiment, one or more APIs 610 provide functions 612 for causing a neural network to perform one or more operations, for example, by returning a called function to a processor, where the processor invokes a neural network.

[0038] In at least one embodiment, one or more software programs 602 interact or communicate with one or more APIs 610 to perform one or more computational operations using one or more PPUs, such as GPUs. In at least one embodiment, one or more computational operations using one or more PPUs include at least one or more groups of computational operations that are accelerated by being executed at least in part by one or more PPUs. In at least one embodiment, one or more software programs 602 interact with one or more APIs 610 to facilitate parallel computing using a remote or local interface.

[0039] In at least one embodiment, an interface consists of software instructions that, when executed, provide access to one or more functions 612 provided by one or more APIs 610. In at least one embodiment, a software program 602 uses a local interface when a software developer compiles one or more software programs 602 in conjunction with one or more libraries 606 that include or otherwise provide access to one or more APIs 610. In at least one embodiment, one or more software programs 602 are statically compiled in conjunction with precompiled libraries 606 or uncompiled source code that includes instructions for executing one or more APIs 610.In at least one embodiment, one or more software programs 602 are dynamically compiled, and one or more software programs use a linker to link to one or more precompiled libraries 606 that include one or more APIs 610.

[0040] In at least one embodiment, a software program 602 uses a remote interface when a software developer executes a software program that uses or otherwise communicates with a library 606 comprising one or more APIs 610 over a network or other remote communication medium. In at least one embodiment, one or more libraries 606 comprising one or more APIs 610 are executed by a remote computing service, such as a computing resource service provider. In another embodiment, one or more libraries 606 containing one or more APIs 610 are executed by any other computer host that provides one or more APIs 610 to one or more software programs 602.

[0041] In at least one embodiment, a processor executing or using one or more software programs 602 invokes, uses, executes, or otherwise implements one or more APIs 610 to allocate and otherwise manage memory used by software programs 602. In at least one embodiment, one or more software programs 602 use one or more APIs 610 to allocate and otherwise manage memory used by one or more portions of the software programs 602 to be accelerated using one or more PPUs, such as GPUs or another accelerator or processor described further herein. These software programs 602 request a neural network to generate a modified bounding box based at least in part on one or more second bounding boxes.

[0042] In at least one embodiment, an API 610 is an API for facilitating parallel computing. In at least one embodiment, an API 610 is any other API further described herein. In at least one embodiment, an API 610 is provided by a driver and / or a runtime 604. In at least one embodiment, an API 610 is provided by a CUDA user-mode driver. In at least one embodiment, an API 610 is provided by a CUDA runtime. In at least one embodiment, a driver 604 consists of data values ​​and software instructions that, when executed, perform or otherwise facilitate the operation of one or more functions 612 of an API 610 during the loading and execution of one or more portions of a software program 602.In at least one embodiment, a runtime 604 consists of data values ​​and software instructions that, when executed, perform or otherwise facilitate the operation of one or more functions 612 of an API 610 during execution of a software program 602. In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 implemented or otherwise provided by a driver and / or runtime 604 to perform combined arithmetic operations by one or more software programs 602 during execution by one or more PPUs, such as GPUs.

[0043] In at least one embodiment, one or more software programs 602 use one or more APIs 610 provided by a driver and / or runtime 604 to perform combined arithmetic operations of one or more PPUs, such as GPUs. In at least one embodiment, one or more APIs 610 provide combined arithmetic operations via a driver and / or runtime 604, as described above. In at least one embodiment, one or more software programs 602 use one or more APIs 610 provided by a driver and / or runtime 604 to allocate or otherwise reserve one or more memory blocks 614 to one or more PPUs, such as GPUs.In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 provided by a driver and / or runtime 604 to allocate or otherwise reserve memory blocks. In at least one embodiment, one or more APIs 610 perform combined arithmetic operations, as described below in connection with FIGS. Fig. 1-5 described.

[0044] To improve the usability of software programs 602 and / or the optimization of one or more portions of software programs 602 that are to be accelerated by one or more PPUs, such as GPUs, in one embodiment, one or more APIs 610 provide one or more API functions 612 to execute a scheduling system that can be used or utilized by one or more computing devices, as described above and further in connection with Fig. 1-5. In at least one embodiment, a block diagram 600 depicts a processor including one or more circuits for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, a block diagram 600 depicts a system including one or more processors executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. LOGIC

[0045] Fig. 7A shows logic 715, which, as described elsewhere herein, may be used in one or more devices to perform operations such as those discussed herein, according to at least one embodiment. In at least one embodiment, logic 715 is used to perform inferencing and / or training operations associated with one or more embodiments. In at least one embodiment, logic 715 is inference and / or training logic. Further details regarding logic 715 are provided below in connection with Fig. 7A and / or 7B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide the functions or operations described herein, where the logic may be embodied, in whole or in part, as circuitry that forms part of a larger system, such as an integrated circuit (IC), a system-on-chip (SoC), or one or more processors (e.g., CPU, GPU).

[0046] In at least one embodiment, logic 715 may include, without limitation, code and / or data storage 701 to store feedforward and / or output weights and / or input / output data and / or other parameters to configure neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, logic 715 may include or be coupled to code and / or data storage 701 to store graphics code or other software that controls the timing and / or order in which information about weights and / or other parameters is loaded to configure logic, including integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)).In at least one embodiment, code, such as graph code, loads information about weights or other parameters into the processor's ALUs based on the architecture of a neural network to which that code corresponds. In at least one embodiment, the code and / or data storage 701 stores weight parameters and / or input / output data of each layer of a neural network being trained or used in connection with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 701 may include other on-chip or off-chip data stores, including a processor's L1, L2, or L3 cache or system memory.

[0047] In at least one embodiment, any portion of the code and / or data storage 701 may be internal or external to one or more processors or other logical hardware devices or circuits. In at least one embodiment, the code and / or data storage 701 may be a cache memory, dynamic random addressable memory ("DRAM"), static random addressable memory ("SRAM"), non-volatile memory (e.g., flash memory), or other memory.In at least one embodiment, the choice of whether the code and / or code and / or data memory 701 is, for example, internal or external to a processor or comprises DRAM, SRAM, Flash, or another memory type may depend on whether on-chip or off-chip memory is available, the latency requirements of the training and / or inference functions performed, the batch size of the data used in the inference and / or training of a neural network, or a combination of these factors.

[0048] In at least one embodiment, logic 715 may include, without limitation, a code and / or data storage 705 to store backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network being trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 705 stores weight parameters and / or input / output data of each layer of a neural network being trained or used in connection with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments.In at least one embodiment, logic 715 may include or be coupled to code and / or data memory 705 to store graph code or other software to control the timing and / or order in which information about weights and / or other parameters is to be loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0049] In at least one embodiment, code, such as graph code, causes information about weights or other parameters to be loaded into processor ALUs based on a neural network architecture to which that code corresponds. In at least one embodiment, any portion of the code and / or data storage 705 may include other on-chip or off-chip data storage, including the L1, L2, or L3 cache or system memory of a processor. In at least one embodiment, any portion of the code and / or data storage 705 may be internal or external to one or more processors or other hardware logic devices or circuitry. In at least one embodiment, the code and / or data storage 705 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory.In at least one embodiment, the choice of whether the code and / or data memory 705 is, for example, internal or external to a processor, or comprises DRAM, SRAM, flash memory, or another memory type, may depend on the available on-chip memory versus off-chip memory, the latency requirements of the training and / or inference functions performed, the batch size of the data used in inference and / or training of a neural network, or a combination of these factors.

[0050] In at least one embodiment, code and / or data memory 701 and code and / or data memory 705 may be separate memory structures. In at least one embodiment, code and / or data memory 701 and code and / or data memory 705 may be a combined memory structure. In at least one embodiment, code and / or data memory 701 and code and / or data memory 705 may be partially combined and partially separate. In at least one embodiment, each portion of code and / or data memory 701 and code and / or data memory 705 may include other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0051] In at least one embodiment, logic 715 may include, without limitation, one or more arithmetic logic unit(s) ("ALU(s)") 710, including integer and / or floating-point units, to perform logical and / or mathematical operations based at least in part on or specified by training and / or inference code (e.g., graph code), the result of which may produce activations stored in activation memory 720 (e.g., output values ​​of layers or neurons within a neural network) that are functions of input / output and / or weighting parameter data stored in code and / or data memory 701 and / or code and / or data memory 705.In at least one embodiment, activations stored in an activation memory 720 are generated according to linear algebraic and / or matrix-based mathematics executed by ALU(s) 710 in response to execution instructions or other code, using weight values ​​stored in code and / or data memory 705 and / or data memory 701 as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data memory 705 or code and / or data memory 701 or other on-chip or off-chip memory.

[0052] In at least one embodiment, ALU(s) 710 are included in one or more processors or other logical hardware devices or circuits, while in another embodiment, ALU(s) 710 may be external to a processor or other logical hardware device or circuit that uses them (e.g., a co-processor). In at least one embodiment, ALU(s) 710 may be included in the execution units of a processor or otherwise in a bank of ALUs accessible by the execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed functional units, etc.).In at least one embodiment, code and / or data memory 701, code and / or data memory 705, and enable memory 720 may share a processor or other logical hardware device or circuitry, while in another embodiment, they may be located in different processors or other logical hardware devices or circuitry, or in a combination of the same and different processors or other logical hardware devices or circuitry. In at least one embodiment, each portion of enable memory 720 may include other on-chip or off-chip data stores, including a processor's L1, L2, or L3 cache or system memory.Furthermore, the inference and / or training code may be stored along with other code accessible by a processor or other hardware logic or circuitry and retrieved and / or processed using a processor's fetch, decode, schedule, execute, retire, and / or other logic circuitry.

[0053] In at least one embodiment, the activation memory 720 may be a cache memory, a DRAM, an SRAM, a non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the activation memory 720 may be located entirely or partially inside or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the activation memory 720 is located inside or outside a processor, or includes DRAM, SRAM, flash memory, or another type of memory, for example, may depend on the available on-chip versus off-chip memory, the latency requirements of the training and / or inference functions performed, the batch size of the data used in inference and / or training of a neural network, or a combination of these factors.

[0054] In at least one embodiment, the Fig. 7A may be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, the logic 715 shown in Fig. 7A may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate arrays (“FPGAs”).

[0055] Fig. 7B shows logic 715 according to at least one embodiment. In at least one embodiment, logic 715 is inference and / or training logic. In at least one embodiment, logic 715 may include, without limitation, hardware logic in which computational resources associated with weight values ​​or other information corresponding to one or more layers of neurons within a neural network are dedicated or otherwise exclusively used. In at least one embodiment, the logic 715 may Fig. 7B may be used in conjunction with an application-specific integrated circuit (ASIC), such as Google's TensorFlow® Processing Unit, a Graphcore™ Inference Processing Unit (IPU), or a Nervana® processor (e.g., "Lake Crest") from Intel Corp. In at least one embodiment, the logic 715 shown in Fig. 7B may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU), or other hardware, such as field-programmable gate arrays (FPGAs). In at least one embodiment, logic 715 includes, without limitation, code and / or data memory 701 and code and / or data memory 705, which may be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, pulse values, and / or other parameter or hyperparameter information. In at least one embodiment, Fig. 7B, each code and / or data memory 701 and each code and / or data memory 705 is connected to a dedicated computing resource, such as computer hardware 702 and computer hardware 706, respectively. In at least one embodiment, each of the computer hardware 702 and the computer hardware 706 includes one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in the code and / or data memory 701 and the code and / or data memory 705, respectively, and the result of which is stored in the activation memory 720.

[0056] In at least one embodiment, the code and / or data memories 701 and 705 and the corresponding computer hardware 702 and 706 each correspond to different layers of a neural network, such that the resulting activation from one memory / computing pair 701 / 702 of code and / or data memory 701 and computer hardware 702 is provided as input to a next memory / computing pair 705 / 706 of code and / or data memory 705 and computer hardware 706 to reflect a conceptual organization of a neural network. In at least one embodiment, each of the memory / computing pairs 701 / 702 and 705 / 706 may correspond to more than one layer of the neural network. In at least one embodiment, additional memory / compute pairs (not shown) may be included in logic 715 subsequent to or in parallel with memory / compute pairs 701 / 702 and 705 / 706. TRAINING AND DEPLOYMENT OF A NEURAL NETWORK

[0057] Fig. 8 illustrates the training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, an untrained neural network 806 is trained using a training dataset 802. In at least one embodiment, the training framework 804 is a PyTorch framework, while in other embodiments, the training framework 804 is a TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or another training framework. In at least one embodiment, the training framework 804 trains an untrained neural network 806 and facilitates its training with the processing resources described herein to produce a trained neural network 808. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network.In at least one embodiment, the training may be performed in either a supervised, semi-supervised, or unsupervised manner.

[0058] In at least one embodiment, the untrained neural network 806 is trained using supervised learning, where the training data set 802 includes an input paired with a desired output for an input, or where the training data set 802 includes an input with a known output and an output of the untrained neural network 806 is manually evaluated. In at least one embodiment, the untrained neural network 806 is trained in a supervised manner and processes inputs from the training data set 802 and compares the resulting outputs to a set of expected or desired outputs. In at least one embodiment, the errors are then backpropagated through the untrained neural network 806. In at least one embodiment, the training framework 804 adjusts the weights that govern the untrained neural network 806.In at least one embodiment, the training framework 804 includes tools for monitoring the convergence of the untrained neural network 806 into a model, e.g., the trained neural network 808, that can generate correct answers, e.g., in the output 814, based on input data, e.g., a new data set 812. In at least one embodiment, the training framework 804 repeatedly trains the untrained neural network 806, adjusting the weights to refine an output of the untrained neural network 806 using a loss function and an adaptation algorithm, such as stochastic gradient descent. In at least one embodiment, the training framework 804 trains the untrained neural network 806 until the untrained neural network 806 achieves a desired accuracy.In at least one embodiment, the trained neural network 808 may then be used to implement any number of machine learning operations.

[0059] In at least one embodiment, the untrained neural network 806 is trained using unsupervised learning, where the untrained neural network 806 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 802 comprises input data without associated output or "ground truth" data. In at least one embodiment, the untrained neural network 806 can learn groupings within the training dataset 802 and determine how individual inputs relate to the untrained dataset 802. In at least one embodiment, the unsupervised training can be used to generate a self-organizing map in the trained neural network 808 capable of performing operations useful in reducing the dimensionality of the new dataset 812.In at least one embodiment, unsupervised training may also be used to perform anomaly detection, which enables the identification of data points in the new data set 812 that deviate from normal patterns of the new data set 812.

[0060] In at least one embodiment, semi-supervised learning may be used, i.e., a technique in which the training data set 802 includes a mixture of labeled and unlabeled data. In at least one embodiment, the training framework 804 may be used to perform incremental learning, for example, through transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 808 to adapt to a new data set 812 without forgetting the knowledge instilled in the trained neural network 808 during initial training.

[0061] In at least one embodiment, the training framework 804 is a framework processed in conjunction with a software development toolkit such as OpenVINO (Open Visual Inference and Neural Network Optimization). In at least one embodiment, an OpenVINO toolkit is a toolkit such as that developed by Intel Corporation of Santa Clara, CA. In at least one embodiment, OpenVINO includes logic 715 or uses logic 715 to perform the operations described herein. In at least one embodiment, an SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0062] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications, particularly neural network applications, for various tasks and operations, such as human vision emulation, speech recognition, natural language processing, recommender systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries such as OpenCV, OpenCL, and / or variants thereof.

[0063] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., humans and / or objects), monocular depth estimation, image colorization, style transfer, action recognition, colorization, and / or variations thereof.

[0064] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as model optimizers. In at least one embodiment, a model optimizer is a command-line tool that facilitates the transitions between training and deployment of neural network models. In at least one embodiment, a model optimizer optimizes neural network models for execution on different devices and / or processing units, such as GPU, CPU, PPU, GPGPU, and / or variants thereof. In at least one embodiment, a model optimizer generates an internal representation of a model and optimizes the model to generate an intermediate representation. In at least one embodiment, a model optimizer reduces a number of layers of a model. In at least one embodiment, a model optimizer removes layers of a model used for training.In at least one embodiment, a model optimizer performs various operations of a neural network, such as changing inputs to a model (e.g., changing the size of inputs to a model), changing the size of inputs to a model (e.g., changing the batch size of a model), changing a model structure (e.g., modifying layers of a model), normalization, standardization, quantization (e.g., converting weights of a model from a first representation, such as floating point, to a second representation, such as integer), and / or variations thereof.

[0065] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as an inference engine. In at least one embodiment, an inference engine is a C++ library or other suitable library in a programming language. In at least one embodiment, an inference engine is used to derive input data. In at least one embodiment, an inference engine implements various classes for deriving input data and producing one or more results. In at least one embodiment, an inference engine implements one or more API functions to process an intermediate representation, specify input and / or output formats, and / or execute a model on one or more devices.

[0066] In at least one embodiment, OpenVINO provides various capabilities for heterogeneously executing one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems using one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions for executing a program on one or more devices. In at least one embodiment, OpenVINO provides various software functions for executing a program and / or portions of a program on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to execute a first portion of the code on a CPU and a second portion of the code on a GPU and / or FPGA.In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., a first set of layers on a first device, such as a GPU, and a second set of layers on a second device, such as a CPU).

[0067] In at least one embodiment, OpenVINO includes various functionalities similar to those associated with a CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or variants thereof. In at least one embodiment, one or more CUDA programming model operations are performed with OpenVINO. In at least one embodiment, various systems, methods, and / or techniques described herein are implemented using OpenVINO. DATA CENTER

[0068] Fig. Figure 9 shows an exemplary data center 900 in which at least one embodiment may be used. In at least one embodiment, the data center 900 includes a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0069] In at least one embodiment, as in Fig. 9, the data center infrastructure layer 910 may include a resource orchestrator 912, clustered compute resources 914, and node compute resources (“Node CRs”) 916(1)-916(N), where “N” represents a positive integer (which may be a different integer “N” than used in other figures). In at least one embodiment, the Node CRs 916(1)-916(N) may include any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), storage devices 918(1)-918(N) (e.g., dynamic read-only memory, solid-state storage, or hard disk drives), network input / output devices (“NW I / O”), network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more Node CRs among the Node CRs 916(1)-916(N) may be a server that has one or more of the computing resources mentioned above.

[0070] In at least one embodiment, the grouped computing resources 914 may include separate groupings of node CRs housed in one or more racks (not shown) or multiple racks housed in data centers in different geographic locations (also not shown). In at least one embodiment, separate groupings of node CRs within the grouped computing resources 914 may include grouped computing, networking, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, multiple node CRs, including CPUs or processors, may be grouped in one or more racks to provide computing resources to support one or more workloads.In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0071] In at least one embodiment, resource orchestrator 912 may configure or otherwise control one or more node CRs 916(1)-916(N) and / or grouped computing resources 914. In at least one embodiment, resource orchestrator 912 may include a software design infrastructure ("SDI") management entity for data center 900. In at least one embodiment, resource orchestrator 912 may include hardware, software, or a combination thereof.

[0072] In at least one embodiment, as in Fig. 9, the framework layer 920 includes a job scheduler 922, a configuration manager 924, a resource manager 926, and a distributed file system 928. In at least one embodiment, the framework layer 920 may include a framework for supporting the software 932 of the software layer 930 and / or one or more applications 942 of the application layer 940. In at least one embodiment, the software 932 or the application(s) 942 may include web-based service software or applications such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 920 may be some type of free and open-source software web application framework such as, but not limited to, Apache Spark™ (hereinafter "Spark"), which may utilize a distributed file system 928 for processing large amounts of data (e.g., "Big Data").In at least one embodiment, the job scheduler 922 may include a Spark driver to facilitate the scheduling of workloads supported by different layers of the data center 900. In at least one embodiment, the configuration manager 924 may be capable of configuring different layers, such as the software layer 930 and the framework layer 920, which include Spark and the distributed file system 928 to support processing large amounts of data. In at least one embodiment, the resource manager 926 may be capable of managing clustered or grouped compute resources allocated to support the distributed file system 928 and the job scheduler 922. In at least one embodiment, the clustered or grouped compute resources may include grouped compute resources 914 in the data center infrastructure layer 910.In at least one embodiment, the resource manager 926 may be coordinated with the resource orchestrator 912 to manage these allocated or assigned computing resources.

[0073] In at least one embodiment, the software 932 included in software layer 930 may include software used by at least portions of node CRs 916(1)-916(N), clustered computer systems 914, and / or distributed file system 928 of framework layer 920. In at least one embodiment, one or more types of software may include, but are not limited to, internet website search software, email virus scanning software, database software, and streaming video content software.

[0074] In at least one embodiment, the application(s) 942 included in the application layer 940 may include one or more types of applications used by at least portions of the node CRs 916(1)-916(N), clustered computing resources 914, and / or the distributed file system 928 of the framework layer 920. In at least one embodiment, one or more types of applications may include any number of a genome application, a cognitive computing application, and a machine learning application, including, but not limited to, training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in connection with one or more embodiments.

[0075] In at least one embodiment, configuration manager 924, resource manager 926, and resource orchestrator 912 may implement any number and type of self-modifying actions based on any amount and type of data collected in any technically feasible manner. In at least one embodiment, self-modifying actions may relieve an operator of a data center 900 from making potentially poor configuration decisions and potentially avoid underutilized and / or malfunctioning portions of a data center.

[0076] In at least one embodiment, data center 900 may include tools, services, software, or other resources to train one or more machine learning models or to predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weighting parameters according to a neural network architecture using software and computational resources described above with respect to data center 900.In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 900 by using weighting parameters calculated by one or more training techniques described herein.

[0077] In at least one embodiment, the data center may utilize CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inference using the resources described above. Furthermore, one or more of the software and / or hardware resources described above may be configured as a service to enable users to train or infer information, such as image recognition, speech recognition, or other artificial intelligence services.

[0078] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in data center 900 may be used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0079] In at least one embodiment, the data center 900 may be used to implement the system 100 (see Fig. 1), of the System 200 (see Fig. 2), of the System 300 (see Fig. 3), of the System 400 (see Fig. 4), of the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6) may be used. In at least one embodiment, at least a portion of the Fig. 9 depicted system(s) to implement one or more systems, techniques, functions and / or processes that are used in conjunction with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 9 may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described. AUTONOMOUS VEHICLE

[0080] Fig. 10A shows an example of an autonomous vehicle 1000 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1000 (alternatively referred to herein as "vehicle 1000") may be, without limitation, a passenger vehicle, such as a car, a truck, a bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, the vehicle 1000 may be a semi-trailer truck used for transporting goods. In at least one embodiment, the vehicle 1000 may be an aircraft, a robotic vehicle, or another type of vehicle.

[0081] Autonomous vehicles may be described in terms of automation levels defined by the National Highway Traffic Safety Administration ("NHTSA"), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers ("SAE") "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, published June 15, 2018, Standard No. J3016-201609, published September 30, 2016, and prior and future versions of this standard). In at least one embodiment, the vehicle 1000 may be capable of performing functions according to one or more of Levels 1 through Level 5 of autonomous driving. For example, in at least one embodiment, the vehicle 1000 may be capable of conditionally automated (Level 3), highly automated (Level 4), and / or fully automated (Level 5), depending on the embodiment.

[0082] In at least one embodiment, vehicle 1000 may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle 1000 may include, without limitation, a propulsion system 1050, such as an internal combustion engine, a hybrid-electric power plant, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1050 may be connected to a drivetrain of vehicle 1000, which may include, without limitation, a transmission, to enable propulsion of vehicle 1000. In at least one embodiment, propulsion system 1050 may be controlled in response to receiving signals from one or more gas pedals / accelerators 1052.

[0083] In at least one embodiment, a steering system 1054, which may include, without limitation, a steering wheel, is used to steer the vehicle 1000 (e.g., along a desired path or route) when the propulsion system 1050 is operating (e.g., when the vehicle 1000 is in motion). In at least one embodiment, the steering system 1054 may receive signals from the steering actuator(s) 1056. In at least one embodiment, a steering wheel may be optional for full automation functionality (Level 5). In at least one embodiment, a brake sensor system 1046 may be used to apply the vehicle brakes in response to receiving signals from brake actuator(s) 1048 and / or brake sensors.

[0084] In at least one embodiment, the controller(s) 1036, which may include, without limitation, one or more system-on-chips (“SoCs”) (in Fig. 10A not shown) and / or graphics processing unit(s) ("GPU(s)"), send signals (e.g., representative of commands) to one or more components and / or systems of the vehicle 1000. For example, in at least one embodiment, the controller(s) 1036 may send signals to actuate the vehicle brakes via the brake actuator(s) 1048, to actuate the steering system 1054 via the steering actuator(s) 1056, and to actuate the propulsion system 1050 via the accelerator pedal(s) 1052. In at least one embodiment, the controller(s) 1036 may include one or more built-in (e.g., integrated) computing devices that process sensor signals and issue operational commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in driving the vehicle 1000.In at least one embodiment, controller(s) 1036 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for emergency redundancy, and / or other controllers. In at least one embodiment, a single controller may perform two or more of the above functions, two or more controllers may perform a single function, and / or any combination thereof.

[0085] In at least one embodiment, the controller(s) 1036 provide(s) signals to control one or more components and / or systems of the vehicle 1000 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be obtained, for example and without limitation, from one or more of GNSS sensor(s) 1058 (e.g., Global Positioning System sensor(s)), RADAR sensor(s) 1060, ultrasonic sensor(s) 1062, LIDAR sensor(s) 1064, Inertial Measurement Unit (“IMU”) sensor(s) 1066 (e.g., accelerometer(s), gyroscope(s), magnetic compass(es), magnetometer(s), etc.), microphone(s) 1096, stereo camera(s) 1068, wide-angle camera(s) 1070 (e.g., fisheye cameras), infrared camera(s) 1072, environmental camera(s) 1074 (e.g., 360-degree cameras), long-range cameras (not Fig. 10A), mid-range camera(s) (not shown in Fig. 10A), speed sensor(s) 1044 (e.g., for measuring the speed of the vehicle 1000), vibration sensor(s) 1042, steering sensor(s) 1040, brake sensor(s) (e.g., as part of the brake sensor system 1046), and / or other types of sensors.

[0086] In at least one embodiment, one or more controllers 1036 may receive inputs (e.g., represented by input data) from an instrument cluster 1032 of the vehicle 1000 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1034, an audible annunciator, a speaker, and / or via other components of the vehicle 1000. In at least one embodiment, the outputs may include information such as vehicle speed, RPM, time, map information (e.g., a high-resolution map (in Fig. 10A not shown)), location data (e.g., the position of the vehicle 1000, e.g., on a map), direction, location of other vehicles (e.g., an occupancy grid), information about objects and the status of objects as perceived by the controller(s) 1036, etc. For example, in at least one embodiment, the HMI display 1034 may include information about the presence of one or more objects (e.g., a road sign, a warning sign, a changing traffic light, etc.) and / or information about maneuvers the vehicle has performed, is performing, or will perform (e.g., lane change now, exit 34B in two miles, etc.).

[0087] In at least one embodiment, the vehicle 1000 further includes a network interface 1024 that may utilize wireless antenna(s) 1026 and / or modem(s) to communicate over one or more networks. For example, in at least one embodiment, the network interface 1024 may be capable of communicating over Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communication ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, the wireless antenna(s) 1026 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area networks such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or low-power wide area networks ("LPWANs") such as LoRaWAN, SigFox, etc.

[0088] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in vehicle 1000 may be used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0089] In at least one embodiment, the autonomous vehicle 1000 may be used to implement the system 100 (see Fig. 1), the System 200 (see Fig. 2), the System 300 (see Fig. 3), the System 400 (see Fig. 4), the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6). In at least one embodiment, at least a portion of the Fig. 10A to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 10A may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes associated with any of the Fig. 1-6 are described.

[0090] Fig. 10B shows an example of camera positions and fields of view for the autonomous vehicle 1000 of Fig. 10A, according to at least one embodiment. In at least one embodiment, the cameras and the respective fields of view represent an exemplary embodiment and are not to be considered limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be arranged at different locations of the vehicle 1000.

[0091] In at least one embodiment, the camera types for cameras may include, but are not limited to, digital cameras that may be adapted for use with components and / or systems of the vehicle 1000. In at least one embodiment, the camera(s) may operate at Automotive Safety Integrity Level ("ASIL") B and / or another ASIL. In at least one embodiment, the camera types may achieve any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the cameras may use rolling shutter, global shutter, another shutter type, or a combination thereof.In at least one embodiment, the color filter array may comprise a red-clear-clear color filter array ("RCCC"), a red-clear-blue color filter array ("RCCB"), a red-blue-green clear color filter array ("RBGC"), a Foveon X3 color filter array, a Bayer sensor color filter array ("RGGB"), a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, clear-pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, may be used to increase light sensitivity.

[0092] In at least one embodiment, one or more cameras may be used to implement advanced driver assistance systems ("ADAS") (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multifunction mono camera may be installed, including functions such as lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more of the cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0093] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (three-dimensional ("3D") printed) assembly, to eliminate stray light and reflections from inside the vehicle 1000 (e.g., reflections from the dashboard reflected in the windshield mirrors) that may impair the camera's ability to capture images. In at least one embodiment, exterior mirror assemblies may be custom 3D printed so that a camera mounting plate conforms to the shape of an exterior mirror. In at least one embodiment, camera(s) may be integrated into the exterior mirrors. In at least one embodiment, for side-facing cameras, the camera(s) may also be integrated into four pillars at each corner of the cabin.

[0094] In at least one embodiment, cameras with a field of view encompassing portions of an environment in front of the vehicle 1000 (e.g., forward-facing cameras) may be used for the surrounding view to help identify forward paths and obstacles, and to provide, with the assistance of one or more controllers 1036 and / or control SoCs, information critical to establishing an occupancy grid and / or determining preferred vehicle paths. In at least one embodiment, forward-facing cameras may be used to perform many similar ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance.In at least one embodiment, forward-facing cameras may also be used for ADAS features and systems, including, without limitation, lane departure warnings (“LDW”), autonomous cruise control (“ACC”), and / or other features such as traffic sign recognition.

[0095] In at least one embodiment, a plurality of cameras may be used in a forward-facing configuration, including, for example, a monocular camera platform comprising a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a wide-angle camera 1070 may be used to detect objects entering view from the periphery (e.g., pedestrians, crossing traffic, or bicycles). Although in Fig. 10B shows only one wide-angle camera 1070, in other embodiments, the vehicle 1000 may include any number (including zero) of wide-angle cameras. In at least one embodiment, any number of long-range cameras 1098 (e.g., a long-range stereo camera pair) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range camera(s) 1098 may also be used for object detection and classification, as well as basic object tracking.

[0096] In at least one embodiment, any number of stereo cameras 1068 may also be in a forward-facing configuration. In at least one embodiment, one or more of the stereo cameras 1068 may include an integrated control unit comprising a scalable processing unit that may provide a field-programmable logic (“FPGA”) and a multi-core microprocessor with an integrated controller area network (“CAN”) or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to create a 3D map of the environment of the vehicle 1000 that includes a distance estimate for all points in an image.In at least one embodiment, one or more of the stereo camera(s) 1068 may comprise, without limitation, compact stereo vision sensors, which may comprise, without limitation, two camera lenses (one each on the left and right) and an image processing chip that can measure the distance between the vehicle 1000 and the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo camera(s) 1068 may be used in addition to or alternatively to those described herein.

[0097] In at least one embodiment, cameras with a field of view that includes portions of the environment on the sides of the vehicle 1000 (e.g., side cameras) may be used for the environment view and provide information used to create and update an occupancy grid and to generate side impact warnings. In at least one embodiment, for example, environment camera(s) 1074 (e.g., four environment cameras, as in Fig. 10B) may be positioned on the vehicle 1000. In at least one embodiment, the surround camera(s) 1074 may include, without limitation, any number and combination of wide-angle cameras, fisheye cameras, 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras may be positioned on the front, rear, and sides of the vehicle 1000. In at least one embodiment, the vehicle 1000 may utilize three surround camera(s) 1074 (e.g., left, right, and rear) and utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround camera.

[0098] In at least one embodiment, cameras with a field of view encompassing portions of an environment behind the vehicle 1000 (e.g., rearview cameras) may be used for parking assistance, surround view, rear collision warnings, and creating and updating an occupancy grid. In at least one embodiment, a variety of cameras may be used, including, but not limited to, cameras that are also suitable as forward-facing cameras (e.g., long-range cameras 1098 and / or mid-range camera(s) 1076, stereo camera(s) 1068, infrared camera(s) 1072, etc.), as described herein.

[0099] In at least one embodiment, the autonomous vehicle 1000 may be used to implement the system 100 (see Fig. 1), the System 200 (see Fig. 2), the System 300 (see Fig. 3), the System 400 (see Fig. 4), the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6). In at least one embodiment, at least a portion of the Fig. 10B is used to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 10B may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described.

[0100] Fig. 10C is a block diagram illustrating an example system architecture for the autonomous vehicle 1000 of Fig. 10A according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1000 is Fig. 10C as connected via a bus 1002. In at least one embodiment, bus 1002 may include, without limitation, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, a CAN may be a network within vehicle 1000 used to support the control of various features and functions of vehicle 1000, such as brake application, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1002 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1002 may be read to determine steering wheel angle, vehicle speed, engine speed, button positions, and / or other indications of vehicle status.In at least one embodiment, bus 1002 may be a CAN bus that is ASIL B compliant.

[0101] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or alternatively to CAN. In at least one embodiment, there may be any number of buses forming bus 1002, which may include, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses with different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality and a second bus may be used for actuation control.In at least one embodiment, each bus of bus 1002 may communicate with any components of vehicle 1000, and two or more buses of bus 1002 may communicate with corresponding components. In at least one embodiment, each of any number of system(s) on chip(s) ("SoC(s)") 1004 (such as SoC 1004(A) and SoC 1004(B)), each of controllers 1036, and / or each computer within the vehicle may have access to the same input data (e.g., inputs from sensors of vehicle 1000) and be connected to a common bus, such as a CAN bus.

[0102] In at least one embodiment, the vehicle 1000 may include one or more controllers 1036 as described herein with respect to Fig. 10A. In at least one embodiment, the controller(s) 1036 may be used for a variety of functions. In at least one embodiment, the controller(s) 1036 may be coupled to various other components and systems of the vehicle 1000 and used for control of the vehicle 1000, the artificial intelligence of the vehicle 1000, the infotainment for the vehicle 1000, and / or other functions.

[0103] In at least one embodiment, the vehicle 1000 may include any number of SoCs 1004. In at least one embodiment, each of the SoCs 1004 may include, without limitation, central processing units ("CPU(s)") 1006, graphics processing units ("GPU(s)") 1008, processor(s) 1010, cache(s) 1012, accelerators 1014, data storage 1016, and / or other components and features not shown. In at least one embodiment, SoC(s) 1004 may be used to control the vehicle 1000 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 1004 may be combined in a system (e.g., the system of the vehicle 1000) with a high-definition ("HD") card 1022 that may be accessed via the network interface 1024 from one or more servers (in Fig. 10C not shown) can receive map updates and / or updates.

[0104] In at least one embodiment, the CPU(s) 1006 may comprise a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, the CPU(s) 1006 may comprise multiple cores and / or level two ("L2") caches. For example, in at least one embodiment, the CPU(s) 1006 may comprise eight cores in a coherent multiprocessor configuration. In at least one embodiment, the CPU(s) 1006 may comprise four dual-core clusters, each cluster having a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, the CPU(s) 1006 (e.g., CCPLEX) may be configured to support concurrent cluster operations, such that any combination of clusters of CPU(s) 1006 may be active at any given time.

[0105] In at least one embodiment, one or more of the CPU(s) 1006 may implement power management features, including, without limitation, one or more of the following features: Individual hardware blocks may be automatically clocked when idle to conserve dynamic power; each core clock may be clocked when such core is not actively executing instructions due to the execution of Wait for Interrupt ("WFI") / Wait for Event ("WFE") instructions; each core may be independently power-clocked; each core cluster may be independently clock-clocked if all cores are clock-clocked or power-clocked; and / or each core cluster may be independently power-clocked if all cores are power-clocked.In at least one embodiment, the CPU(s) 1006 may further implement an enhanced power state management algorithm, where allowable power states and expected wake-up times are specified, and the hardware / microcode determines which power state is best for the core, cluster, and CCPLEX. In at least one embodiment, the processor cores may support simplified power state entry sequences in software, offloading the work to the microcode.

[0106] In at least one embodiment, the GPU(s) 1008 may comprise an integrated GPU (alternatively referred to herein as an "iGPU"). In at least one embodiment, the GPU(s) 1008 may be programmable and efficient for parallel workloads. In at least one embodiment, the GPU(s) 1008 may utilize an extended Tensor instruction set. In at least one embodiment, the GPU(s) 1008 may comprise one or more streaming microprocessors, where each streaming microprocessor may comprise a Level 1 ("L1") cache (e.g., an L1 cache with a memory capacity of at least 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a memory capacity of 512 KB). In at least one embodiment, the GPU(s) 1008 may comprise at least eight streaming microprocessors.In at least one embodiment, the GPU(s) 1008 may use one or more application programming interfaces (APIs) for computation. In at least one embodiment, the GPU(s) 1008 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0107] In at least one embodiment, one or more of the GPU(s) 1008 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, the GPU(s) 1008 may be fabricated on fin field-effect transistor ("FinFET") circuits. In at least one embodiment, each streaming microprocessor may include a number of mixed-precision compute cores divided into multiple blocks. For example, 64 PF32 cores and 32 FP64 cores could be divided into four processing blocks. In at least one embodiment, each processing block could be assigned 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two NVIDIA Tensor cores with mixed precision for deep learning matrix arithmetic, a level zero ("L0") instruction cache, a scheduler (e.g., warp scheduler) or sequencer, a dispatch unit, and / or a 64 KB register file.In at least one embodiment, streaming microprocessors may include independent parallel integer and floating-point datapaths to enable efficient execution of workloads with a mix of computations and addressing calculations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capability to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, streaming microprocessors may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0108] In at least one embodiment, one or more of the GPU(s) 1008 may include high-bandwidth memory ("HBM") and / or a 16 GB HBM2 memory subsystem to provide, in some examples, a peak memory bandwidth of approximately 900 GB / second. In at least one embodiment, in addition to or alternatively to the HBM memory, a synchronous graphics random-access memory ("SGRAM") may be used, such as a synchronous graphics double-data-rate random-access memory type 5 ("GDDR5").

[0109] In at least one embodiment, the GPU(s) 1008 may include a unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow the GPU(s) 1008 to directly access page tables of the CPU(s) 1006. In at least one embodiment, an address translation request may be transmitted to the CPU(s) 1006 when a GPU of the GPU(s) 1008 memory management unit ("MMU") detects a fault. In response, the CPU of the CPU(s) 1006 may look up a virtual-physical mapping for an address in its page tables and transmit the translation back to the GPU(s) 1008, in at least one embodiment.In at least one embodiment, unified memory technology may enable a single unified virtual address space for the memory of both the CPU(s) 1006 and the GPU(s) 1008, simplifying programming of the GPU(s) 1008 and porting applications to the GPU(s) 1008.

[0110] In at least one embodiment, the GPU(s) 1008 may include any number of access counters that can track the frequency of access by the GPU(s) 1008 to the memory of other processors. In at least one embodiment, access counters can help ensure that memory pages are moved to the physical memory of a processor that accesses pages most frequently, thereby improving the efficiency of memory regions shared between processors.

[0111] In at least one embodiment, one or more of the SoC(s) 1004 may include any number of cache(s) 1012, including those described herein. For example, in at least one embodiment, the cache(s) 1012 could include a Level 3 ("L3") cache available to both the CPU(s) 1006 and the GPU(s) 1008 (e.g., connected to the CPU(s) 1006 and GPU(s) 1008). In at least one embodiment, the cache(s) 1012 may include a write-back cache that can track the states of lines, for example, using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, an L3 cache may include 4 MB of memory or more, depending on the embodiment, although smaller cache sizes may also be used.

[0112] In at least one embodiment, one or more of the SoC(s) 1004 may include one or more accelerators 1014 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoC(s) 1004 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB of SRAM) may enable a hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, a hardware acceleration cluster may be used to supplement the GPU(s) 1008 and offload some tasks from the GPU(s) 1008 (e.g., to free up more cycles of the GPU(s) 1008 to perform other tasks).In at least one embodiment, the accelerator(s) 1014 could be used for targeted workloads (e.g., perception, convolutional neural networks ("CNNs"), recurrent neural networks ("RNNs"), etc.) that are robust enough to be suitable for acceleration. In at least one embodiment, a CNN may include a region-based or regional neural network ("RCNN") and a fast RCNN (e.g., as used for object detection), or another type of CNN.

[0113] In at least one embodiment, the accelerator(s) 1014 (e.g., hardware acceleration clusters) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, the DLA(s) may include, without limitation, one or more tensor processing units ("TPUs") that may be configured to provide an additional tens of trillion operations per second for deep learning applications and inferencing. In at least one embodiment, TPUs may be accelerators configured and optimized to perform image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, the DLA(s) may be further optimized for a particular set of neural network types and floating-point operations, as well as for inferencing.In at least one embodiment, the design of DLA(s) can provide more performance per millimeter than a typical general-purpose GPU, typically far exceeding the performance of a CPU. In at least one embodiment, the TPU(s) can perform multiple functions, including a single-instance convolution function, supporting, for example, INT8, INT16, and FP16 data types for both features and weights, as well as post-processing functions.In at least one embodiment, DLA(s) can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for a variety of functions, including, for example and without limitation: a CNN for object identification and recognition using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for emergency vehicle detection and identification and recognition using data from microphones; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and / or a CNN for safety-relevant and / or security-related events.

[0114] In at least one embodiment, the DLA(s) may perform any function of the GPU(s) 1008, and by using an inference accelerator, a developer may, for example, dedicate either the DLA(s) or the GPU(s) 1008 to each function. For example, in at least one embodiment, a developer may focus the processing of CNNs and floating-point operations on the DLA(s) and leave other functions to the GPU(s) 1008 and / or accelerator(s) 1014.

[0115] In at least one embodiment, the accelerator(s) 1014 may comprise a programmable image processing accelerator ("PVA"), which may also be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate image processing algorithms for advanced driver assistance systems ("ADAS") 1038, autonomous driving, augmented reality ("AR"), and / or virtual reality ("VR") applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may comprise, without limitation, any number of reduced instruction set ("RISC") cores, direct memory access ("DMA") cores, and / or any number of vector processors.

[0116] In at least one embodiment, RISC cores may interact with image sensors (e.g., image sensors of cameras described herein), image signal processor(s), etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, the RISC cores may use any number of protocols, depending on the embodiment. In at least one embodiment, RISC cores may execute a real-time operating system ("RTOS"). In at least one embodiment, RISC cores may be implemented with one or more integrated circuits, application-specific integrated circuits ("ASICs"), and / or memory devices. In at least one embodiment, RISC cores could, for example, include an instruction cache and / or tightly coupled RAM.

[0117] In at least one embodiment, DMA may enable components of the PVA to access system memory independently of the CPU(s) 1006. In at least one embodiment, DMA may support any number of features used to optimize a PVA, including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA may support up to six or more dimensions of addressing, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0118] In at least one embodiment, vector processors may be programmable processors that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing functions. In at least one embodiment, a PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, a vector processing subsystem may operate as the primary processing engine of a PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM").In at least one embodiment, the VPU core may include a digital signal processor, such as a single instruction multiple data ("SIMD") and very long instruction word ("VLIW") digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may increase throughput and speed.

[0119] In at least one embodiment, each of the vector processors may include an instruction cache and be connected to dedicated memory. Consequently, in at least one embodiment, each of the vector processors may be configured to operate independently of other vector processors. In at least one embodiment, vector processors included in a particular PVA may be configured to use data parallelism. For example, in at least one embodiment, a plurality of vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may concurrently execute different image processing algorithms for an image, or even different algorithms for successive images or portions of an image.In at least one embodiment, among other things, any number of PVAs may be included in a hardware acceleration cluster, and each PVA may include any number of vector processors. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to increase the security of the overall system.

[0120] In at least one embodiment, the accelerator(s) 1014 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high-bandwidth, low-latency SRAM for the accelerator(s) 1014. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, including, for example and without limitation, eight field-configurable memory blocks accessible by both a PVA and a DLA. In at least one embodiment, each pair of memory blocks may include an extended peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used.In at least one embodiment, a PVA and a DLA may access the memory via a backbone that provides high-speed access to the memory for a PVA and a DLA. In at least one embodiment, a backbone may include an on-chip computer vision network that interconnects a PVA and a DLA to the memory (e.g., using APB).

[0121] In at least one embodiment, an on-chip computer vision network may include an interface that determines that both a PVA and a DLA are providing ready and valid signals before transmitting control signals / addresses / data. In at least one embodiment, an interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst communication for continuous data transmission. In at least one embodiment, an interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0122] In at least one embodiment, one or more of the SoC(s) 1004 may include a hardware accelerator for real-time ray tracing. In at least one embodiment, the real-time ray tracing hardware accelerator may be used for quickly and efficiently determining positions and extents of objects (e.g., within a world model), generating real-time visualization simulations, radar signal interpretation, sound propagation synthesis and / or analysis, simulating sonar systems, general wave propagation simulation, comparing with lidar data for localization and / or other functions, and / or for other purposes.

[0123] In at least one embodiment, the accelerator(s) 1014 may have a wide range of uses for autonomous driving. In at least one embodiment, a PVA may be used for critical processing steps in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of a PVA are well suited to algorithmic domains that require predictable, low-power, and low-latency processing. In other words, a PVA is well suited for semi-dense or dense regular computations, even on small datasets, that require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in vehicle 1000, PVAs may be designed to execute classical computer vision algorithms because they can be efficient at object detection and processing integer mathematical data.

[0124] Algorithms because they are efficient at object detection and can work with integer mathematics.

[0125] For example, according to at least one embodiment of the technology, a PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, Level 3-5 autonomous driving applications utilize motion estimation / stereo matching while driving (e.g., structure from motion, pedestrian detection, lane detection, etc.). In at least one embodiment, a PVA may perform computer stereo vision functions on inputs from two monocular cameras.

[0126] In at least one embodiment, a PVA may be used to perform dense optical flow. For example, in at least one embodiment, a PVA could process raw radar data (e.g., using a 4D Fast Fourier Transform) to provide processed radar data. In at least one embodiment, a PVA is used for depth-of-flight processing, processing raw time-of-flight data to provide, for example, processed time-of-flight data.

[0127] In at least one embodiment, a DLA may be used to power any type of network to improve control and driving safety, including, for example and without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, confidence may be represented or interpreted as a probability, or as the relative "weight" of each detection compared to other detections. In at least one embodiment, a confidence measure allows the system to make further decisions about which detections should be considered true positives and which should be considered false positives. In at least one embodiment, a system may set a threshold for the confidence measure and consider only detections that exceed the threshold as true positives.In an embodiment using an automatic emergency braking ("AEB") system, false positive detections would cause the vehicle to automatically perform emergency braking, which is clearly undesirable. In at least one embodiment, highly confident detections can be considered as triggers for AEB. In at least one embodiment, a DLA can employ a neural network to regress the confidence value.In at least one embodiment, the neural network may use as input at least a subset of parameters, such as the dimensions of the bounding box, the ground plane estimate obtained (e.g., from another subsystem), the output of the IMU sensor(s) 1066 correlated with the orientation of the vehicle 1000, the range, the 3D position estimates of the object obtained from the neural network and / or other sensors (e.g., LIDAR sensor(s) 1064 or RADAR sensor(s) 1060), and others.

[0128] In at least one embodiment, one or more SoC(s) 1004 may include one or more data stores 1016 (e.g., memories). In at least one embodiment, the data store(s) 1016 may be on-chip memory of the SoC(s) 1004, which may store neural networks to be executed on the GPU(s) 1008 and / or a DLA. In at least one embodiment, the data store(s) 1016 may be large enough to store multiple instances of neural networks for redundancy and security. In at least one embodiment, the data store(s) 1016 may include L2 or L3 cache(s).

[0129] In at least one embodiment, one or more of the SoC(s) 1004 may include any number of processor(s) 1010 (e.g., embedded processors). In at least one embodiment, the processor(s) 1010 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and associated security enforcement. In at least one embodiment, a boot and power management processor may be part of a boot sequence of SoC(s) 1004 and provide runtime power management services.In at least one embodiment, a processor for boot power and management may provide clock and voltage programming, support for low-power state transitions, management of the thermal and temperature sensors of the SoC(s) 1004, and / or management of the power states of the SoC(s) 1004. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and SoC(s) 1004 may use ring oscillators to sense the temperatures of CPU(s) 1006, GPU(s) 1008, and / or accelerator(s) 1014.In at least one embodiment, when temperatures are determined to exceed a threshold, a boot and power management processor may enter a temperature fault routine and place the SoC(s) 1004 into a lower power state and / or place the vehicle 1000 into a chauffeur-to-safe stop mode (e.g., bring the vehicle 1000 to a safe stop).

[0130] In at least one embodiment, the processor(s) 1010 may further comprise a set of embedded processors that may serve as an audio processing engine, which may be an audio subsystem enabling full hardware support for multi-channel audio across multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, an audio processing engine is a dedicated processor core including a digital signal processor with dedicated RAM.

[0131] In at least one embodiment, the processor(s) 1010 may further include an "always on" processor engine that may provide the necessary hardware functions to support low-power sensor management and wake use cases. In at least one embodiment, an "always on" processor engine may include, without limitation, a processor core, tightly coupled memory, supporting peripherals (e.g., timers and interrupt controllers), various I / O control peripherals, and routing logic.

[0132] In at least one embodiment, the processor(s) 1010 may further comprise a safety cluster engine, including, without limitation, a dedicated processor subsystem for handling safety management for automotive applications. In at least one embodiment, a safety cluster engine may include, without limitation, two or more processor cores, tightly coupled memory, supporting peripherals (e.g., timers, an interrupt controller, etc.), and / or routing logic. In a safety mode, two or more cores may, in at least one embodiment, operate in a lockstep mode, functioning as a single core with comparison logic to detect any differences between their operations.In at least one embodiment, the processor(s) 1010 may further comprise a real-time camera engine, which may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, the processor(s) 1010 may further comprise a high dynamic range signal processor, which may include, without limitation, an image signal processor that is a hardware engine that is part of a camera processing pipeline.

[0133] In at least one embodiment, processor(s) 1010 may include a video image compositor, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image for a player window. In at least one embodiment, a video image compositor may perform lens distortion correction on the wide-angle camera(s) 1070, the surround camera(s) 1074, and / or the in-cabin surveillance camera(s) sensors. In at least one embodiment, the in-cabin surveillance camera(s) sensor(s) is / are preferably monitored by a neural network running on another instance of SoC 1004 and configured to detect and respond to events in the cabin.In at least one embodiment, a system in the cabin may perform lip reading without limitation to activate cellular service and place a call, dictate emails, change a vehicle's destination, activate or change a vehicle's infotainment system and settings, or enable voice-activated internet browsing. In at least one embodiment, certain functions are available to the driver when a vehicle is operating in an autonomous mode and are disabled otherwise.

[0134] In at least one embodiment, a video image compositor may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment where motion occurs in a video, the noise reduction appropriately weights spatial information and reduces the weight of information provided by neighboring frames. In at least one embodiment where an image or portion of an image does not include motion, the temporal noise reduction performed by the video image compositor may use information from a previous frame to reduce noise in the current frame.

[0135] In at least one embodiment, a video image compositor may also be configured to perform stereo rectification on the input stereo lens images. In at least one embodiment, a video image compositor may further be used for interface composition when an operating system desktop is in use and the GPU(s) 1008 are not needed to continuously render new surfaces. In at least one embodiment, a video image compositor may be used to offload the GPU(s) 1008 to improve performance and responsiveness when the GPU(s) 1008 are turned on and actively performing 3D rendering.

[0136] In at least one embodiment, one or more of SoC(s) 1004 may further include a Mobile Industrial Processor Serial Interface ("MIPI") for receiving video and input from cameras, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functions. In at least one embodiment, one or more of SoC(s) 1004 may further include one or more input / output controllers that may be controlled by software and may be used to receive I / O signals that are not tied to a specific role.

[0137] In at least one embodiment, one or more of SoC(s) 1004 may further include a wide range of peripheral interfaces to enable communication with peripherals, audio encoders / decoders ("codecs"), power management, and / or other devices. In at least one embodiment, SoC(s) 1004 may be used to receive data from cameras (e.g., via Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., LIDAR sensor(s) 1064, RADAR sensor(s) 1060, etc., which may be connected via Ethernet channels), data from bus 1002 (e.g., speed of vehicle 1000, steering wheel position, etc.), data from GNSS sensor(s) 1058 (e.g., connected via an Ethernet bus or a CAN bus), etc.In at least one embodiment, one or more of SoC(s) 1004 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and which may be used to free the CPU(s) 1006 from routine data management tasks.

[0138] In at least one embodiment, the SoC(s) 1004 may be an end-to-end platform with a flexible architecture spanning automation levels 3-5, thereby providing a comprehensive functional safety architecture, leveraging computer vision and ADAS techniques for diversity and redundancy, and providing a platform for a flexible, reliable driving software stack along with deep learning tools. In at least one embodiment, the SoC(s) 1004 may be faster, more reliable, and even more power and space efficient than conventional systems. For example, in at least one embodiment, the accelerator(s) 1014, when combined with the CPU(s) 1006, the GPU(s) 1008, and the memory(s) 1016, may provide a fast, efficient platform for Level 3-5 autonomous vehicles.

[0139] In at least one embodiment, computer vision algorithms may be executed on CPUs that can be configured with a high-level programming language, such as C, to execute a variety of processing algorithms for a wide variety of visual data. However, in at least one embodiment, CPUs are often unable to meet the performance requirements of many image processing applications, such as execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles.

[0140] The embodiments described herein enable multiple neural networks to be executed simultaneously and / or sequentially and the results to be combined to enable Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executing on a DLA or a discrete GPU (e.g., GPU(s) 1020) may include text and word recognition enabling the reading and understanding of traffic signs, including signs for which a neural network has not been specifically trained. In at least one embodiment, a DLA may further include a neural network capable of identifying, interpreting, and semantically understanding a sign and passing this semantic understanding to path planning modules running on a CPU complex.

[0141] In at least one embodiment, multiple neural networks may run simultaneously, such as in Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign reading "Caution: Flashing lights indicate icy conditions" along with an electric light may be interpreted independently or jointly by multiple neural networks. At least in one embodiment, such a warning sign may itself be identified as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "Flashing lights indicate icy conditions" may be interpreted by a second deployed neural network, which informs a vehicle's path planning software (preferably running on a CPU complex) that, when flashing lights are detected, icy conditions are present.In at least one embodiment, a turn signal may be identified by operating a third neural network over multiple frames, which informs a vehicle's path planning software of the presence (or absence) of turn signals. In at least one embodiment, all three neural networks may run concurrently, for example, within a DLA and / or on GPU(s) 1008.

[0142] In at least one embodiment, a facial recognition and vehicle owner identification CNN may use data from camera sensors to identify the presence of an authorized driver and / or owner of vehicle 1000. In at least one embodiment, an "always on" sensor processing engine may be used to unlock a vehicle when an owner approaches a driver's door and turns on the lights, and to disable such a vehicle in a security mode when an owner exits such a vehicle. In this way, the SoC(s) 1004 provide security against theft and / or carjacking.

[0143] In at least one embodiment, a CNN for detecting and identifying emergency vehicles may use data from microphones 1096 to detect and identify emergency vehicle sirens. In at least one embodiment, the SoC(s) 1004 use a CNN to classify environmental and urban noise, as well as to classify visual data. In at least one embodiment, a CNN running on a DLA is trained to detect a relative approach speed of an emergency vehicle (e.g., using a Doppler effect). In at least one embodiment, a CNN may also be trained to identify emergency vehicles specific to a local area in which a vehicle is traveling, as identified by GNSS sensor(s) 1058.In at least one embodiment, when deployed in Europe, a CNN will attempt to detect European sirens, and when deployed in North America, a CNN will attempt to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine, slow a vehicle, pull over to the side of the road, park a vehicle, and / or idle a vehicle using the ultrasonic sensor(s) 1062 until the emergency vehicles pass by.

[0144] In at least one embodiment, the vehicle 1000 may include one or more CPU(s) 1018 (e.g., discrete CPU(s) or dCPU(s)) that may be connected to the SoC(s) 1004 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the CPU(s) 1018 may include, for example, an x86 processor. The CPU(s) 1018 may be used to perform a variety of functions, including reconciling potentially conflicting results between ADAS sensors and SoC(s) 1004 and / or monitoring the status and health of the controller(s) 1036 and / or an infotainment system on a chip (“infotainment SoC”) 1030, for example. In at least one embodiment, the SoC(s) 1004 includes one or more interconnects, and an interconnect may include a Peripheral Component Interconnect Express (PCIe).

[0145] In at least one embodiment, the vehicle 1000 may include GPU(s) 1020 (e.g., discrete GPU(s) or dGPU(s)) that may be coupled to SoC(s) 1004 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the GPU(s) 1020 may provide additional artificial intelligence functionality, such as by executing redundant and / or distinct neural networks, and may be used to train and / or update neural networks based at least in part on inputs (e.g., sensor data) from sensors of a vehicle 1000.

[0146] In at least one embodiment, the vehicle 1000 may further include a network interface 1024, which may include, without limitation, one or more wireless antennas 1026 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, the network interface 1024 may be used to enable wireless connection to internet cloud services (e.g., to server(s) and / or other network devices), to other vehicles, and / or to computing devices (e.g., passenger client devices). In at least one embodiment, a direct connection between the vehicle 1000 and another vehicle and / or an indirect connection (e.g., via networks and the internet) may be established for communication with other vehicles.In at least one embodiment, direct connections may be established via a vehicle-to-vehicle communication link. In at least one embodiment, a vehicle-to-vehicle communication link may provide vehicle 1000 with information about vehicles in the vicinity of vehicle 1000 (e.g., vehicles in front of, to one side of, and / or behind vehicle 1000). In at least one embodiment, this aforementioned functionality may be part of a cooperative adaptive cruise control function of vehicle 1000.

[0147] In at least one embodiment, the network interface 1024 may include a SoC that provides modulation and demodulation functions and enables the controller(s) 1036 to communicate over wireless networks. In at least one embodiment, the network interface 1024 may include a radio frequency front-end for upconversion from baseband to radio frequency and downconversion from radio frequency to baseband. In at least one embodiment, the frequency conversions may be performed in any technically feasible manner. For example, frequency conversions may be performed by known methods and / or using superheterodyne techniques. In at least one embodiment, the radio frequency front-end functionality may be provided by a separate chip.In at least one embodiment, the network interfaces may include wireless capabilities for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0148] In at least one embodiment, the vehicle 1000 may further include one or more data stores 1028, which may include, without limitation, off-chip memory (e.g., off-SoC(s) 1004). In at least one embodiment, the data store(s) 1028 may include, without limitation, one or more memory elements, including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, hard drives, and / or other components and / or devices capable of storing at least one bit of data.

[0149] In at least one embodiment, the vehicle 1000 may further include GNSS sensor(s) 1058 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, sensing, occupancy grid generation, and / or path planning. In at least one embodiment, any number of GNSS sensor(s) 1058 may be used, including, for example, and without limitation, a GPS using a USB port with an Ethernet-to-serial bridge (e.g., RS-232).

[0150] In at least one embodiment, the vehicle 1000 may further include RADAR sensor(s) 1060. In at least one embodiment, the RADAR sensor(s) 1060 may be used by the vehicle 1000 for vehicle detection over long distances, even in darkness and / or adverse weather conditions. In at least one embodiment, the RADAR functional safety levels may be ASIL B. In at least one embodiment, the RADAR sensor(s) 1060 may use a CAN bus and / or bus 1002 (e.g., for transmitting data generated by the RADAR sensor(s) 1060) for control and access to object tracking data, with raw data being accessed via Ethernet channels in some examples. In at least one embodiment, a wide range of RADAR sensors may be used.For example, and without limitation, radar sensor(s) 1060 may be suitable for use as front, rear, and side radar. In at least one embodiment, one or more sensors of radar sensor(s) 1060 are pulse-Doppler radar sensors.

[0151] In at least one embodiment, the RADAR sensor(s) 1060 may include different configurations, such as long range with a narrow field of view, short range with a wide field of view, short range side coverage, etc. In at least one embodiment, long range RADAR may be used for adaptive cruise control functionality. In at least one embodiment, long range RADAR systems may provide a wide field of view realized by two or more independent scans, for example, within a range of 250 m (meters). In at least one embodiment, RADAR sensor(s) 1060 may assist in distinguishing between static and moving objects and may be used by the ADAS system 1038 for emergency braking assistance and forward collision warning.In at least one embodiment, the sensor(s) 1060 included in a long-range radar system may comprise, without limitation, a monostatic multimodal radar with multiple (e.g., six or more) fixed radar antennas and a high-speed CAN and FlexRay interface. In at least one embodiment with six antennas, four antennas in the center may create a focused beam pattern used to detect the vehicle's surroundings at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, two additional antennas may expand the field of view, allowing for rapid detection of vehicles entering or exiting a lane of vehicle 1000.

[0152] For example, in at least one embodiment, medium-range radar systems may include a range of up to 160 m (front) or 80 m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range radar systems may include, without limitation, any number of radar sensors 1060 that may be installed at either end of a rear bumper. In at least one embodiment, a radar sensor system, when installed at either end of a rear bumper, may create two beams that continuously monitor blind spots to the rear and to the side of a vehicle. In at least one embodiment, short-range radar systems may be used in ADAS system 1038 for blind spot detection and / or lane change assistance.

[0153] In at least one embodiment, the vehicle 1000 may further include ultrasonic sensor(s) 1062. In at least one embodiment, the ultrasonic sensor(s) 1062, which may be arranged at a front, rear, and / or side location of the vehicle 1000, may be used for parking assistance and / or for creating and updating an occupancy grid. In at least one embodiment, a plurality of ultrasonic sensors 1062 may be used, and different ultrasonic sensors 1062 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensor(s) 1062 may operate at functional safety levels of ASIL B.

[0154] In at least one embodiment, the vehicle 1000 may include the LIDAR sensor(s) 1064. In at least one embodiment, the LIDAR sensor(s) 1064 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor(s) 1064 may operate at the ASIL B functional safety level. In at least one embodiment, the vehicle 1000 may include multiple LIDAR sensors 1064 (e.g., two, four, six, etc.) that may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0155] In at least one embodiment, the LIDAR sensor(s) 1064 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, the commercially available LIDAR sensor(s) 1064 may have an advertised range of approximately 100 m, with an accuracy of 2 cm to 3 cm, and with support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, the LIDAR sensor(s) 1064 may comprise a small device that can be embedded in a front, rear, side, and / or corner position of the vehicle 1000.In at least one embodiment, the LIDAR sensor(s) 1064 in such an embodiment can provide a horizontal field of view of up to 120 degrees and a vertical field of view of up to 35 degrees with a range of 200 m, even for low-reflectivity objects. In at least one embodiment, the front-mounted LIDAR sensor(s) 1064 can be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0156] In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR, may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 1000 up to a distance of approximately 200 m. In at least one embodiment, a flash LIDAR unit includes, without limitation, a receptor that records the time of flight of the laser pulse and the reflected light at each pixel, which in turn corresponds to a distance from the vehicle 1000 to objects. In at least one embodiment, flash LIDAR may enable highly accurate and distortion-free images of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of the vehicle 1000.In at least one embodiment, 3D flash LIDAR systems include, without limitation, a solid-state 3D star array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per image and collect the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0157] In at least one embodiment, the vehicle 1000 may further include one or more IMU sensors 1066. In at least one embodiment, the IMU sensor(s) 1066 may be located at the center of a rear axle of the vehicle 1000. In at least one embodiment, the IMU sensor(s) 1066 may include, for example, and without limitation, accelerometers, magnetometers, gyroscopes, a magnetic compass, magnetic compasses, and / or other types of sensors. In at least one embodiment, such as in six-axis applications, the IMU sensor(s) 1066 may include, without limitation, accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, the IMU sensor(s) 1066 may include, without limitation, accelerometers, gyroscopes, and magnetometers.

[0158] In at least one embodiment, the IMU sensor(s) 1066 may be implemented as a miniaturized, high-performance GPS-based inertial navigation system ("GPS / INS") that combines microelectromechanical systems ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filter algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor(s) 1066 may enable the vehicle 1000 to estimate its heading without requiring input from a magnetic sensor by directly observing velocity changes from a GPS and correlating them with the IMU sensor(s) 1066. In at least one embodiment, the IMU sensor(s) 1066 and the GNSS sensor(s) 1058 may be combined into a single integrated unit.

[0159] In at least one embodiment, the vehicle 1000 may include one or more microphones 1096 disposed in and / or around the vehicle 1000. In at least one embodiment, the microphone(s) 1096 may be used, among other things, for detecting and identifying emergency vehicles.

[0160] In at least one embodiment, the vehicle 1000 may further include any number of camera types, including stereo camera(s) 1068, wide-angle camera(s) 1070, infrared camera(s) 1072, surround camera(s) 1074, long-range camera(s) 1098, medium-range camera(s) 1076, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around the entire perimeter of the vehicle 1000. In at least one embodiment, the types of cameras used depend on the vehicle 1000. In at least one embodiment, any combination of camera types may be used to provide the required coverage around the vehicle 1000. In at least one embodiment, the number of cameras employed may vary depending on the embodiment.In at least one embodiment, the vehicle 1000 could include, for example, six, seven, ten, twelve, or any other number of cameras. In at least one embodiment, the cameras can support, for example, and without limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communication. In at least one embodiment, each camera can be configured as previously described herein with respect to . Fig. 10A and Fig. 10B is described in more detail.

[0161] In at least one embodiment, the vehicle 1000 may further include one or more vibration sensors 1042. In at least one embodiment, the vibration sensor(s) 1042 may measure vibrations of components of the vehicle 1000, such as the axle(s). In at least one embodiment, for example, changes in vibrations may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1042 are used, differences between vibrations may be used to determine friction or slippage of the road surface (for example, when there is a difference in vibration between a driven axle and a free-spinning axle).

[0162] In at least one embodiment, the vehicle 1000 may include the ADAS system 1038. In at least one embodiment, the ADAS system 1038 may include, in some examples, without limitation, a SoC. In at least one embodiment, the ADAS system 1038 may include, without limitation, any number and combination of an autonomous / adaptive / automatic cruise control (“ACC”) system, a cooperative adaptive cruise control (“CACC”) system, a forward crash warning (“FCW”) system, an automatic emergency braking (“AEB”) system, a lane departure warning (“LDW”) system, a lane keep assist (“LKA”) system, a blind spot warning (“BSW”) system, a rear cross traffic warning (“RCTW”) system, a forward collision warning (“CW”) system, a lane centering (“LC”) system, and / or other systems, features, and / or functions.

[0163] In at least one embodiment, the ACC system may use RADAR sensor(s) 1060, LIDAR sensor(s) 1064, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, a longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1000 and automatically adjusts the speed of the vehicle 1000 to maintain a safe distance from preceding vehicles. In at least one embodiment, a lateral ACC system provides follow-through and advises the vehicle 1000 to change lanes if necessary. In at least one embodiment, a lateral ACC system is connected to other ADAS applications, such as LC and CW.

[0164] In at least one embodiment, a CACC system utilizes information from other vehicles, which may be received via a network interface 1024 and / or wireless antenna(s) 1026 from other vehicles over a wireless connection or indirectly via a network connection (e.g., over the Internet). In at least one embodiment, direct connections may be provided by a vehicle-to-vehicle ("V2V") communication link, while indirect connections may be provided by an infrastructure-to-vehicle ("I2V") communication link. Generally, V2V communication provides information about immediately ahead vehicles (e.g., vehicles immediately in front of and in the same lane as vehicle 1000), while I2V communication provides information about traffic further ahead.In at least one embodiment, a CACC system may include either one or both I2V and V2V information sources. In at least one embodiment, a CACC system may be more reliable given information about vehicles ahead of vehicle 1000 and has the potential to improve traffic flow and reduce congestion on the road.

[0165] In at least one embodiment, an FCW system is designed to warn a driver of a hazard so that the driver can take corrective action. In at least one embodiment, an FCW system uses a forward-facing camera and / or RADAR sensor(s) 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is / are electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibrating component. In at least one embodiment, an FCW system can provide a warning, for example, in the form of a sound, a visual warning, a vibration, and / or a rapid braking pulse.

[0166] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if a driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system can utilize forward-facing camera(s) and / or RADAR sensor(s) 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, upon detecting a hazard, an AEB system will typically first alert a driver to take corrective action to avoid a collision, and if that driver does not take corrective action, the AEB system can automatically apply the brakes to prevent or at least mitigate the effects of a predicted collision.In at least one embodiment, an AEB system may include techniques such as dynamic brake assistance and / or crash-imminent braking.

[0167] In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 1000 crosses lane markings. In at least one embodiment, an LDW system is not activated when a driver indicates an intentional lane departure, for example, by activating a turn signal. In at least one embodiment, an LDW system may utilize forward-facing cameras coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide feedback to the driver, for example, via a display, speaker, and / or vibrating component. In at least one embodiment, an LKA system is a variation of an LDW system.In at least one embodiment, an LKA system provides a steering or braking input to correct the vehicle 1000 when the vehicle 1000 begins to depart from its lane.

[0168] In at least one embodiment, a BSW system detects and warns the driver of vehicles in the vehicle's blind spot. In at least one embodiment, a BSW system may provide a visual, audible, and / or tactile warning to indicate that merging or changing lanes is unsafe. In at least one embodiment, a BSW system may provide an additional warning when a driver activates a turn signal. In at least one embodiment, a BSW system may utilize rear-facing camera(s) and / or RADAR sensor(s) 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to feedback to the driver, such as a display, speaker, and / or vibrating component.

[0169] In at least one embodiment, an RCTW system may provide a visual, audible, and / or tactile notification when an object is detected outside the range of the rear camera while reversing the vehicle 1000. In at least one embodiment, an RCTW system includes an AEB system to ensure that the vehicle brakes are applied to avoid a crash. In at least one embodiment, an RCTW system may utilize one or more rear-facing RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibrating component.

[0170] In at least one embodiment, conventional ADAS systems may be prone to false positives, which may be annoying and distracting for a driver, but are typically not catastrophic because conventional ADAS systems alert a driver and allow that driver to decide whether a safety condition truly exists and act accordingly. In at least one embodiment, in the case of conflicting results, the vehicle 1000 itself decides whether to consider the result of a primary computer or a secondary computer (e.g., a first controller or a second controller of the controllers 1036). In at least one embodiment, the ADAS system 1038 may, for example, be a backup and / or secondary computer that provides perception information to a rationality module of the backup computer.In at least one embodiment, a backup computer rationality monitor may run redundant, diverse software on hardware components to detect errors in perception and dynamic driving tasks. In at least one embodiment, the outputs of the ADAS system 1038 may be forwarded to a supervisory MCU. In at least one embodiment, if the outputs of a primary computer and the outputs of a secondary computer conflict, a supervisory MCU determines how to resolve the conflict to ensure safe operation.

[0171] In at least one embodiment, a primary computer may be configured to provide a supervising MCU with a score indicating the primary computer's confidence in a selected outcome. In at least one embodiment, the supervising MCU may follow the primary computer's instruction if that confidence score exceeds a threshold, regardless of whether the secondary computer provides a conflicting or inconsistent outcome. In at least one embodiment, in cases where a confidence score does not meet a threshold and where primary and secondary computers indicate different outcomes (e.g., a conflict), a supervising MCU may arbitrate between the computers to determine an appropriate outcome.

[0172] In at least one embodiment, a monitoring MCU may be configured to execute a neural network(s) trained and configured to determine, based at least in part on the outputs of a primary computer and the outputs of a secondary computer, the conditions under which the secondary computer provides false alarms. In at least one embodiment, the neural network(s) in a monitoring MCU may learn when the output of a secondary computer can and cannot be trusted. In at least one embodiment, when the secondary computer is a RADAR-based FCW system, a neural network(s) mayNeural networks in this monitoring MCU can learn when an FCW system identifies metallic objects that are not actually hazards, such as a drain grate or manhole cover, which triggers an alarm. In at least one embodiment, when a secondary computer is a camera-based LDW system, a neural network in a monitoring MCU can learn to override the LDW system when cyclists or pedestrians are present and leaving the lane is actually the safest maneuver. In at least one embodiment, a monitoring MCU can include at least one DLA or GPU suitable for executing neural networks with associated memory. In at least one embodiment, a monitoring MCU can comprise and / or be included as a component of the SoC(s) 1004.

[0173] In at least one embodiment, ADAS system 1038 may include a secondary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, this secondary computer may use classic computer vision (if-then) rules, and the presence of a neural network(s) in a higher-level MCU may improve reliability, safety, and performance. In at least one embodiment, the different implementation and intentional non-identity make the overall system more fault-tolerant, particularly against errors caused by software functions (or software-hardware interfaces).For example, in at least one embodiment, if a software error occurs in the software running on a primary computer and non-identical software code runs on a secondary computer that produces a consistent overall result, then a supervising MCU may have greater confidence that an overall result is correct and a bug in the software or hardware on that primary computer does not cause a significant error.

[0174] In at least one embodiment, an output of the ADAS system 1038 may be fed to the perception block of a primary computer and / or the dynamic driving task block of a primary computer. For example, in at least one embodiment, if the ADAS system 1038 indicates a forward crash warning due to an object immediately ahead, a perception block may use this information in identifying objects. In at least one embodiment, a secondary computer may have its own neural network trained, thus reducing the risk of false alarms, as described herein.

[0175] In at least one embodiment, the vehicle 1000 may further include an infotainment SoC 1030 (e.g., an in-vehicle infotainment system (IVI)). Although illustrated and described as an SoC, in at least one embodiment, the infotainment system SoC 1030 may not be an SoC and may include, without limitation, two or more discrete components. In at least one embodiment, the infotainment SoC 1030 may include, without limitation, a combination of hardware and software that can be used to provide audio (e.g., music, a personal digital assistant, navigation commands, news, radio, etc.), video (e.g., television, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.).) and / or information services (e.g., navigation systems, rear parking assistance, a radio data system, vehicle-related information such as fuel level, total distance traveled, brake fuel level, oil level, door open / close, air filter information, etc.) to the vehicle 1000. The infotainment SoC 1030 could include, for example, radios, record players, navigation systems, video players, USB and Bluetooth connectivity, car computers, in-car entertainment, WiFi, steering wheel audio controls, hands-free voice control, a heads-up display ("HUD"), an HMI display 1034, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, functions, and / or systems), and / or other components.In at least one embodiment, the infotainment SoC 1030 may be further used to provide information (e.g., visual and / or audible) to the user(s) of the vehicle 1000, such as information from the ADAS system 1038, autonomous driving information such as planned vehicle maneuvers, trajectories, environmental information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0176] In at least one embodiment, the infotainment SoC 1030 may include any amount and type of GPU functionality. In at least one embodiment, the infotainment SoC 1030 may communicate with other devices, systems, and / or components of the vehicle 1000 via the bus 1002. In at least one embodiment, the infotainment SoC 1030 may be coupled to a supervisory MCU so that a GPU of an infotainment system may perform some self-driving functions if the primary controller(s) 1036 (e.g., primary and / or backup computers of the vehicle 1000) fail. In at least one embodiment, the infotainment SoC 1030 may place the vehicle 1000 into a chauffeur-to-safe-stop mode, as described herein.

[0177] In at least one embodiment, the vehicle 1000 may further include an instrument cluster 1032 (e.g., a digital instrument cluster, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, the instrument cluster 1032 may include, without limitation, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the instrument cluster 1032 may include, without limitation, any number and combination of instruments, such as, but not limited to, a speedometer, fuel level, oil pressure, tachometer, odometer, turn signals, shift position indicator, seat belt warning light(s), parking brake warning light(s), engine trouble light(s), supplemental restraint system information (e.g., airbags), lighting controls, safety system controls, navigation information, etc.In some examples, information may be displayed and / or shared between infotainment SoC 1030 and instrument cluster 1032. In at least one embodiment, instrument cluster 1032 may be included as part of infotainment SoC 1030, or vice versa.

[0178] In at least one embodiment, the autonomous vehicle 1000 may be used to implement the system 100 (see Fig. 1), the System 200 (see Fig. 2), the System 300 (see Fig. 3), the System 400 (see Fig. 4), the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6). In at least one embodiment, at least a portion of the Fig. 10C is used to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 10C may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described.

[0179] Fig. 10D is a diagram of a system for communication between one or more cloud-based servers and the autonomous vehicle 1000 of Fig. 10A according to at least one embodiment. In at least one embodiment, the system may include, without limitation, server(s) 1078, network(s) 1090, and any number and type of vehicles, including vehicle 1000. In at least one embodiment, server(s) 1078 may include, without limitation, a plurality of GPUs 1084(A)-1084(H) (collectively referred to herein as GPUs 1084), PCIe switches 1082(A)-1082(D) (collectively referred to herein as PCIe switches 1082), and / or CPUs 1080(A)-1080(B) (collectively referred to herein as CPUs 1080). In at least one embodiment, the GPUs 1084, the CPUs 1080, and the PCIe switches 1082 may be interconnected with high-speed interconnects, such as, for example, and without limitation, the NVLink interfaces 1088 and / or PCIe interconnects 1086 developed by NVIDIA.In at least one embodiment, the GPUs 1084 are connected via an NVLink and / or NVSwitch SoC, and the GPUs 1084 and PCIe switches 1082 are connected via PCIe interconnects. Although eight GPUs 1084, two CPUs 1080, and four PCIe switches 1082 are shown, this is not intended to be limiting. In at least one embodiment, each of the servers 1078 may include, without limitation, any number of GPUs 1084, CPUs 1080, and / or PCIe switches 1082 in any combination. For example, in at least one embodiment, the server(s) 1078 could each include eight, sixteen, thirty-two, and / or more GPUs 1084.

[0180] In at least one embodiment, the server(s) 1078 may receive, via the network(s) 1090 and from vehicles, image data representative of images depicting unexpected or changed road conditions, such as recently commenced roadwork. In at least one embodiment, the server(s) 1078 may transmit, via the network(s) 1090 and to the vehicles, updated or other neural network 1092 and / or map information 1094 including, among other things, information about traffic and road conditions. In at least one embodiment, the updates to the map information 1094 may include, without limitation, updates to the HD map 1022, such as information about construction, potholes, detours, flooding, and / or other obstacles.In at least one embodiment, neural networks 1092 and / or map information 1094 may result from new training and / or experience represented in data received from any number of vehicles in an environment and / or may be based at least in part on training performed in a data center (e.g., using server(s) 1078 and / or other servers).

[0181] In at least one embodiment, the server(s) 1078 may be used to train machine learning models (e.g., neural networks) based at least in part on training data. In at least one embodiment, the training data may be generated by vehicles and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., if the associated neural network benefits from supervised learning) and / or subjected to other preprocessing. In at least one embodiment, any amount of training data is unlabeled and / or preprocessed (e.g., if the associated neural network does not require supervised learning).In at least one embodiment, once machine learning models are trained, machine learning models may be used by vehicles (e.g., transmitted to vehicles via network(s) 1090) and / or machine learning models may be used by server(s) 1078 to remotely monitor vehicles.

[0182] In at least one embodiment, the server(s) 1078 may receive data from vehicles and apply the data to real-time neural networks for intelligent inference. In at least one embodiment, the server(s) 1078 may include deep learning supercomputers and / or dedicated AI computers powered by GPU(s) 1084, such as DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, the server(s) 1078 may also include a deep learning infrastructure using CPU-powered data centers.

[0183] In at least one embodiment, the deep learning infrastructure of server(s) 1078 may be capable of performing fast, real-time inferencing and may utilize this capability to evaluate and verify the health of processors, software, and / or associated hardware in vehicle 1000. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1000, such as a sequence of images and / or objects that vehicle 1000 has located in that sequence of images (e.g., via computer vision and / or other machine object classification techniques).In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to objects identified by the vehicle 1000, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1000 is malfunctioning, then the server(s) 1078 may send a signal to the vehicle 1000 instructing a fail-safe computer of the vehicle 1000 to take over control, notify the passengers, and perform a safe parking maneuver.

[0184] In at least one embodiment, the server(s) 1078 may include GPU(s) 1084 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, a combination of GPU-driven servers and inference accelerators may enable real-time responsiveness. In at least one embodiment, for example, when performance is less critical, servers with CPUs, FPGAs, and other processors may be used for inference building. In at least one embodiment, hardware structure(s) 715 are used to perform one or more embodiments. Details regarding hardware structure(s) 715 are described herein in connection with Fig. 7A and / or 7B.

[0185] In at least one embodiment, the autonomous vehicle 1000 may be used to implement the system 100 (see Fig. 1), the System 200 (see Fig. 2), the System 300 (see Fig. 3), the System 400 (see Fig. 4), the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6). In at least one embodiment, at least a portion of the Fig. 10D is used to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 10D may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described. COMPUTER SYSTEMS

[0186] Fig. 11 is a block diagram illustrating an exemplary computer system, which may be a system of interconnected devices and components, a system-on-a-chip (SOC), or a combination thereof, formed with a processor that may include execution units for executing an instruction, according to at least one embodiment. In at least one embodiment, a computer system 1100 may include, without limitation, a component such as a processor 1102 for employing execution units including logic for performing algorithms for processing data in accordance with the present disclosure, as in the embodiment described herein.In at least one embodiment, computer system 1100 may include processors such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, technical workstations, set-top boxes, and the like) may be used. In at least one embodiment, computer system 1100 may run a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical interfaces may also be used.

[0187] Embodiments may be used in other devices such as handheld devices and embedded applications. Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0188] In at least one embodiment, computer system 1100 may include, without limitation, a processor 1102, which may include, without limitation, one or more execution units 1108 to perform machine learning model training and / or inferencing according to the techniques described herein. In at least one embodiment, computer system 1100 is a desktop or server system having a processor, but in another embodiment, computer system 1100 may be a multiprocessor system. In at least one embodiment, processor 1102 may include, without limitation, a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other device, such as a digital signal processor.In at least one embodiment, the processor 1102 may be connected to a processor bus 1110 that may transmit data signals between the processor 1102 and other components in the computer system 1100.

[0189] In at least one embodiment, processor 1102 may include, without limitation, an internal Level 1 ("L1") cache ("cache") 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache may be external to processor 1102. Other embodiments may also include a combination of internal and external caches, depending on the particular implementation and requirements. In at least one embodiment, a register file 1106 may store different data types in various registers, including, without limitation, integer registers, floating-point registers, status registers, and an instruction pointer register.

[0190] In at least one embodiment, execution unit 1108, which includes, without limitation, logic for performing integer and floating-point operations, is also located in processor 1102. In at least one embodiment, processor 1102 may also include microcode read-only memory ("ROM") ("ucode") that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1108 may include logic for handling a packed instruction set 1109. In at least one embodiment, by including packed instruction set 1109 in an instruction set of a general-purpose processor, along with associated instruction execution circuitry, operations used by many multimedia applications may be performed using packed data in processor 1102.In at least one embodiment, many multimedia applications can be accelerated and executed more efficiently by utilizing the full width of a processor's data bus to perform operations on packed data, thereby eliminating the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0191] In at least one embodiment, execution unit 1108 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1100 may include, without limitation, a memory 1120. In at least one embodiment, memory 1120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or another storage device. In at least one embodiment, memory 1120 may store instruction(s) 1119 and / or data 1121 represented by data signals that may be executed by processor 1102.

[0192] In at least one embodiment, a system logic chip may be connected to processor bus 1110 and memory 1120. In at least one embodiment, a system logic chip may include, without limitation, a memory control hub ("MCH") 1116, and processor 1102 may communicate with MCH 1116 via processor bus 1110. In at least one embodiment, MCH 1116 may provide a high-bandwidth memory path 1118 to memory 1120 for instruction and data storage, as well as for graphics command, data, and texture storage. In at least one embodiment, MCH 1116 may route data signals between processor 1102, memory 1120, and other components in computer system 1100, and may bridge data signals between processor bus 1110, memory 1120, and a system I / O interface 1122.In at least one embodiment, a system logic chip may provide a graphics port for connection to a graphics controller. In at least one embodiment, MCH 1116 may be coupled to memory 1120 via a high-bandwidth memory path 1118, and a graphics / video card 1112 may be coupled to MCH 1116 via an Accelerated Graphics Port ("AGP") interconnect 1114.

[0193] In at least one embodiment, computer system 1100 may use system I / O interface 1122 as a proprietary hub interface bus to connect MCH 1116 to an I / O control hub ("ICH") 1130. In at least one embodiment, ICH 1130 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, a local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1120, a chipset, and processor 1102. Examples may include, without limitation, an audio controller 1129, a firmware hub (“Flash BIOS”) 1128, a wireless transceiver 1126, a data store 1124, a legacy I / O controller 1123 with user input and keyboard interfaces 1125, a serial expansion port 1127, such as a Universal Serial Bus (“USB”) interface, and a network controller 1134.In at least one embodiment, data storage 1124 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0194] In at least one embodiment, Fig. 11 a system comprising interconnected hardware devices or “chips”, while in other embodiments Fig. 11 may show an exemplary SoC. In at least one embodiment, the Fig. The devices illustrated in Figure 11 may be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of computer system 1100 are interconnected using Compute Express Link (CXL) interconnects.

[0195] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in computer system 1100 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0196] In at least one embodiment, the computer system 1100 may be used to implement the system 100 (see Fig. 1), of the System 200 (see Fig. 2), of the System 300 (see Fig. 3), of the System 400 (see Fig. 4), of the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6) may be used. In at least one embodiment, at least a portion of the Fig. 11 depicted system(s) to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 11 may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described.

[0197] Fig. 12 is a block diagram illustrating an electronic device 1200 for using a processor 1210 according to at least one embodiment. In at least one embodiment, the electronic device 1200 may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0198] In at least one embodiment, the electronic device 1200 may include, without limitation, a processor 1210 communicatively connected to any number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1210 is coupled via a bus or interface, such as an I2C bus, a System Management Bus ("SMBus"), a Low Pin Count (LPC) bus, a Serial Peripheral Interface ("SPI"), a High Definition Audio ("HDA") bus, a Serial Advance Technology Attachment ("SATA") bus, a Universal Serial Bus ("USB") (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter Bus ("UART"). In at least one embodiment, Fig. 12 a system comprising interconnected hardware devices or “chips”, while in other embodiments Fig. 12 may show an exemplary SoC. In at least one embodiment, the Fig. 12 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of Fig. 12 interconnected using CXL (Compute Express Link) connections.

[0199] At least in one embodiment, Fig. 12 a display 1224, a touchscreen 1225, a touchpad 1230, a Near Field Communications unit (“NFC”) 1245, a sensor hub 1240, a thermal sensor 1246, an Express Chipset (“EC”) 1235, a Trusted Platform Module (“TPM”) 1238, BIOS / Firmware / Flash Memory (“BIOS, FW Flash”) 1222, a DSP 1260, a drive 1220 such as a Solid State Disk (“SSD”) or a Hard Drive (“HDD”), a Wireless Local Area Network unit (“WLAN”) 1250, a Bluetooth unit 1252, a Wireless Wide Area Network unit (“WWAN”) 1256, a Global Positioning System (GPS) unit 1255, a camera (“USB 3.0 Camera”) 1254, such as a USB 3.0 Camera, and / or a Low Power Double Data Rate ("LPDDR") memory unit ("LPDDR3") 1215, implemented, for example, according to an LPDDR3 standard. These components may each be implemented in any suitable manner.

[0200] In at least one embodiment, other components may be communicatively coupled to processor 1210 via components described herein. In at least one embodiment, an accelerometer 1241, an ambient light sensor ("ALS") 1242, a compass 1243, and a gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, a thermal sensor 1239, a fan 1237, a keyboard 1236, and a touchpad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, speakers 1263, headphones 1264, and a microphone ("mic") 1265 may be communicatively coupled to an audio unit ("audio codec and class D amp") 1262, which in turn may be communicatively coupled to DSP 1260. In at least one embodiment, the audio unit 1262 may include, for example and without limitation, an audio encoder / decoder ("codec") and a Class D amplifier.In at least one embodiment, a SIM card ("SIM") 1257 may be communicatively coupled to the WWAN unit 1256. In at least one embodiment, components such as the WLAN unit 1250 and the Bluetooth unit 1252, as well as the WWAN unit 1256, may be implemented in a Next Generation Form Factor ("NGFF").

[0201] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in electronic device 1200 may be used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0202] In at least one embodiment, the electronic device 1200 for implementing the system 100 (see Fig. 1), of the System 200 (see Fig. 2), of the System 300 (see Fig. 3), of the System 400 (see Fig. 4), of the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6) may be used. In at least one embodiment, at least a portion of the Fig. 12 depicted system(s) to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 12 may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described.

[0203] Fig. Figure 13 illustrates a computer system 1300 according to at least one embodiment. In at least one embodiment, the computer system 1300 is configured to implement various processes and methods described in this disclosure.

[0204] In at least one embodiment, computer system 1300 includes, without limitation, at least one central processing unit ("CPU") 1302 connected to a communications bus 1310 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or another bus or point-to-point communications protocol. In at least one embodiment, computer system 1300 includes, without limitation, main memory 1304 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1304, which may take the form of random access memory ("RAM").In at least one embodiment, a network interface subsystem ("network interface") 1322 provides an interface to other computing devices and networks to receive and transmit data from and to other systems with computer system 1300.

[0205] In at least one embodiment, computer system 1300 includes, without limitation, input devices 1308, a parallel processing system 1312, and display devices 1306, which may be implemented using a conventional cathode ray tube ("CRT"), a liquid crystal display ("LCD"), a light-emitting diode ("LED"), a plasma display, or other suitable display technology. In at least one embodiment, user input is provided via input devices 1308 such as a keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein may be packaged on a single semiconductor platform to form a processing system.

[0206] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details of inference and / or training logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in computer system 1300 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0207] In at least one embodiment, the computer system 1300 may be used to implement the system 100 (see Fig. 1), of the System 200 (see Fig. 2), of the System 300 (see Fig. 3), of the System 400 (see Fig. 4), of the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6) may be used. In at least one embodiment, at least a portion of the Fig. 13 depicted system(s) to implement one or more systems, techniques, functions and / or processes that are used in conjunction with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 13 may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described.

[0208] Fig. 14 shows a computer system 1400 according to at least one embodiment. In at least one embodiment, the computer system 1400 includes, without limitation, a computer 1410 and a USB flash drive 1420. In at least one embodiment, the computer 1410 may include, without limitation, any number and type of processor(s) (not shown) and memory (not shown). In at least one embodiment, the computer 1410 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0209] In at least one embodiment, the USB flash drive 1420 includes, without limitation, a processing unit 1430, a USB interface 1440, and USB interface logic 1450. In at least one embodiment, the processing unit 1430 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1430 may include, without limitation, any number and type of compute cores (not shown). In at least one embodiment, the processing unit 1430 includes an application-specific integrated circuit ("ASIC") optimized to perform any number and type of machine learning-related operations.For example, in at least one embodiment, processing unit 1430 is a tensor processing unit ("TPC") optimized for performing machine learning inference operations. In at least one embodiment, processing unit 1430 is a video processing unit ("VPU") optimized for performing video processing and machine learning operations.

[0210] In at least one embodiment, USB interface 1440 may be any type of USB connector or receptacle. For example, in at least one embodiment, USB interface 1440 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1440 is a USB 3.0 Type-A connector. In at least one embodiment, the logic of USB interface 1450 may include any amount and type of logic that enables processing unit 1430 to communicate with devices (e.g., computer 1410) via USB port 1440.

[0211] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in computer system 1400 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or the neural network use cases described herein.

[0212] In at least one embodiment, the computer system 1400 may be used to implement the system 100 (see Fig. 1), of the System 200 (see Fig. 2), of the System 300 (see Fig. 3), of the System 400 (see Fig. 4), of the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6) may be used. In at least one embodiment, at least a portion of the Fig. 14 depicted system(s) to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 14 may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described.

[0213] Fig. 15A illustrates an example architecture in which a plurality of GPUs 1510(1)-1510(N) are communicatively coupled to a plurality of multi-core processors 1505(1)-1505(M) via high-speed interconnects 1540(1)-1540(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed interconnects 1540(1)-1540(N) support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or more. In at least one embodiment, various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure. In at least one embodiment, one or more GPUs in a plurality of GPUs 1510(1)-1510(N) includes one or more graphics cores (also referred to simply as “cores”) 1800, as shown in the Fig. 18A and Fig. 18B. In at least one embodiment, one or more graphics cores 1800 may be referred to as streaming multiprocessors ("SMs"), stream processors ("SPs"), stream processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where a slice in this context may refer to a portion of the processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or scheduler).

[0214] Additionally, and in at least one embodiment, two or more GPUs 1510 are interconnected via high-speed interconnects 1529(1)-1529(2), which may be implemented using similar or different protocols / connections than those used for high-speed interconnects 1540(1)-1540(N). Similarly, two or more multi-core processors 1505 may be interconnected via a high-speed interconnect 1528, which may be symmetric multiprocessor (SMP) buses operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, all communication between the various Fig. 15A using similar protocols / connections (e.g., via a common connection structure).

[0215] In at least one embodiment, each multi-core processor 1505 is communicatively connected to a processor memory 1501(1)-1501(M) via memory interconnects 1526(1)-1526(M), and each GPU 1510(1)-1510(N) is communicatively connected to GPU memory 1520(1)-1520(N) via GPU memory interconnects 1550(1)-1550(N). In at least one embodiment, memory interconnects 1526 and 1550 may use similar or different memory access technologies. For example, the processor memories 1501(1)-1501(M) and the GPU memories 1520 may be volatile memories, such as dynamic random access memories (DRAMs) (including stacked DRAMs), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or they may be non-volatile memories, such as 3D XPoint or Nano-Ram.In at least one embodiment, a portion of processor memory 1501 may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory hierarchy (2LM)).

[0216] As described herein, various multi-core processors 1505 and GPUs 1510 may be physically connected to a particular memory 1501 or 1520, respectively, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as "effective address space") is distributed across different physical memories. For example, processor memories 1501(1)-1501(M) may each comprise 64 GB of system address space, and GPU memories 1520(1)-1520(N) may each comprise 32 GB of system address space, resulting in a total of 256 GB of addressable memory when M=2 and N=4. Other values ​​for N and M are possible.

[0217] Fig. 15B shows additional details for an interconnect between a multi-core processor 1507 and a graphics acceleration module 1546 in accordance with an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1546 may include one or more GPU chips integrated on a line card connected to the processor 1507 via a high-speed interconnect 1540 (e.g., PCIe bus, NVLink, etc.). Alternatively, in at least one embodiment, the graphics acceleration module 1546 may be integrated on a package or die with the processor 1507.

[0218] In at least one embodiment, processor 1507 includes a plurality of cores 1560A-1560D (which may be referred to as "execution units"), each having a translation lookaside buffer ("TLB") 1561A-1561D and one or more caches 1562A-1562D. In at least one embodiment, cores 1560A-1560D may include various other components for executing instructions and processing data, not shown. In at least one embodiment, caches 1562A-1562D may include Level 1 (L1) and Level 2 (L2) caches. Additionally, one or more shared caches 1556 may be included in caches 1562A-1562D that are shared by multiple cores 1560A-1560D. For example, one embodiment of processor 1507 includes 24 cores, each with its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches.In this embodiment, one or more L2 and L3 caches are shared between two adjacent cores. In at least one embodiment, processor 1507 and graphics acceleration module 1546 are coupled to system memory 1514, which includes processor memories 1501(1)-1501(M) of FIG. Fig. 15A may include.

[0219] In at least one embodiment, coherency for data and instructions stored in various caches 1562A-1562D, 1556, and system memory 1514 is maintained via inter-core communication over a coherency bus 1564. For example, in at least one embodiment, each cache may have cache coherency logic / circuitry coupled to it to communicate over the coherency bus 1564 in response to detected reads or writes to specific cache lines. In at least one embodiment, a cache coherency protocol is implemented over the coherency bus 1564 to sniff out cache accesses.

[0220] In at least one embodiment, a proxy circuit 1525 communicatively couples the graphics acceleration module 1546 to the coherence bus 1564, allowing the graphics acceleration module 1546 to participate in a cache coherence protocol as a peer of cores 1560A-1560D. Specifically, in at least one embodiment, an interface 1535 provides connectivity to the proxy circuit 1525 via the high-speed interconnect 1540, and an interface 1537 connects the graphics acceleration module 1546 to the high-speed interconnect 1540.

[0221] In at least one embodiment, an accelerator integration circuit 1536 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546. In at least one embodiment, the graphics processing engines 1531(1)-1531(N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, a plurality of graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546 comprise one or more graphics cores 1800, as described in connection with the Fig. 18A and Fig. 18B. In at least one embodiment, the graphics processing engines 1531(1)-1531(N) may alternatively comprise different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1546 may be a GPU with a plurality of graphics processing engines 1531(1)-1531(N), or the graphics processing engines 1531(1)-1531(N) may be individual GPUs integrated on a common package, line card, or die.

[0222] In at least one embodiment, accelerator integration circuitry 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions, such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing system memory 1514. In at least one embodiment, MMU 1539 may also include a translation lookaside buffer (TLB) (not shown) to cache virtual / effective to physical / real address translations. In at least one embodiment, a cache 1538 may store instructions and data for efficient access by graphics processing engines 1531(1)-1531(N).In at least one embodiment, the data stored in cache 1538 and graphics memories 1533(1)-1533(M) is kept coherent with core caches 1562A-1562D, 1556, and system memory 1514, possibly using a fetch unit 1544. As noted, this may be accomplished via circuitry 1525 on behalf of cache 1538 and memories 1533(1)-1533(M) (e.g., sending updates to cache 1538 regarding changes / accesses to cache lines in processor caches 1562A-1562D, 1556 and receiving updates from cache 1538).

[0223] In at least one embodiment, a set of registers 1545 stores context data for threads executed by graphics processing engines 1531(1)-1531(N), and context management circuitry 1548 manages thread contexts. For example, context management circuitry 1548 may perform save and restore operations to save and restore the contexts of different threads upon context switches (e.g., when a first thread is saved and a second thread is saved to allow a second thread to be executed by a graphics processing engine). For example, upon a context switch, context management circuitry 1548 may save the current register values ​​to a specific region of memory (e.g., identified by a context pointer). The register values ​​may then be restored upon return to a context.In at least one embodiment, an interrupt management circuit 1547 receives and processes interrupts received from system devices.

[0224] In at least one embodiment, virtual / effective addresses from a graphics processing engine 1531 are translated by the MMU 1539 into real / physical addresses in system memory 1514. In at least one embodiment, the accelerator integration circuit 1536 supports multiple (e.g., 4, 8, 16) graphics acceleration modules 1546 and / or other acceleration devices. In at least one embodiment, the graphics acceleration module 1546 may be dedicated to a single application executing on the processor 1507 or shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is depicted in which the resources of the graphics processing engines 1531(1)-1531(N) are shared among multiple applications or virtual machines (VMs).In at least one embodiment, the resources may be divided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0225] In at least one embodiment, accelerator integration circuitry 1536 acts as a bridge to a system for graphics acceleration module 1546 and provides address translation and system memory caching services. Furthermore, in at least one embodiment, accelerator integration circuitry 1536 may provide virtualization facilities to a host processor to manage the virtualization of graphics processing engines 1531(1)-1531(N), interrupts, and memory management.

[0226] Because, in at least one embodiment, the hardware resources of graphics processing engines 1531(1)-1531(N) are explicitly mapped to a real address space seen by host processor 1507, each host processor can directly address these resources via an effective address value. In at least one embodiment, a function of accelerator integration circuitry 1536 is to physically separate graphics processing engines 1531(1)-1531(N) so that they appear to a system as independent entities.

[0227] In at least one embodiment, one or more graphics memories 1533(1)-1533(M) are coupled to each of the graphics processing engines 1531(1)-1531(N), where N=M. In at least one embodiment, the graphics memories 1533(1)-1533(M) store instructions and data processed by each of the graphics processing engines 1531(1)-1531(N). In at least one embodiment, the graphics memories 1533(1)-1533(M) may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or they may be non-volatile memories such as 3D XPoint or Nano-RAM.

[0228] In at least one embodiment, bias techniques may be used to reduce data traffic over high-speed interconnect 1540 to ensure that the data stored in graphics memories 1533(1)-1533(M) is data most frequently used by graphics processing engines 1531(1)-1531(N) and preferably not used by cores 1560A-1560D (at least not frequently). Similarly, in at least one embodiment, a bias mechanism attempts to keep data needed by cores (and preferably not by graphics processing engines 1531(1)-1531(N)) in caches 1562A-1562D, 1556, and system memory 1514.

[0229] Fig. 15C shows another exemplary embodiment in which accelerator integration circuitry 1536 is integrated into processor 1507. In this embodiment, graphics processing engines 1531(1)-1531(N) communicate directly over high-speed interconnect 1540 with accelerator integration circuitry 1536 via interface 1537 and interface 1535 (which may again be any form of bus or interface protocol). In at least one embodiment, accelerator integration circuitry 1536 may perform operations similar to those described in Fig. 15B, but possibly with higher throughput due to its proximity to the coherence bus 1564 and caches 1562A-1562D, 1556. In at least one embodiment, an accelerator integration circuit supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models controlled by the accelerator integration circuit 1536 and programming models controlled by the graphics acceleration module 1546.

[0230] In at least one embodiment, graphics processing engines 1531(1)-1531(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can forward other application requests to graphics processing engines 1531(1)-1531(N), enabling virtualization within a VM / partition.

[0231] In at least one embodiment, the graphics processing engines 1531(1)-1531(N) may be shared between multiple VM / application partitions. In at least one embodiment, shared models may use a system hypervisor to virtualize the graphics processing engines 1531(1)-1531(N) to allow access by any operating system. In at least one embodiment, for systems with a single partition without a hypervisor, the graphics processing engines 1531(1)-1531(N) are owned by an operating system. In at least one embodiment, an operating system may virtualize the graphics processing engines 1531(1)-1531(N) to allow access to any process or application.

[0232] In at least one embodiment, the graphics acceleration module 1546 or an individual graphics processing engine 1531(1)-1531(N) selects a process element via a process handle. In at least one embodiment, the process elements are stored in system memory 1514 and are addressable using an effective address to real address translation technique described herein. In at least one embodiment, a process handle may be an implementation-specific value provided to a host process when it registers its context with the graphics processing engine 1531(1)-1531(N) (i.e., when it calls system software to add a process element to a linked process element list). In at least one embodiment, the lower 16 bits of a process handle may be an offset of a process element within a process element list.

[0233] Fig. 15D shows an example accelerator integration slice 1590. In at least one embodiment, a "slice" comprises a particular portion of the processing resources of accelerator integration circuitry 1536. In at least one embodiment, an effective address space 1582 in system memory 1514 stores process elements 1583. In at least one embodiment, process elements 1583 are stored in response to GPU calls 1581 from applications 1580 executing on processor 1507. In at least one embodiment, a process element 1583 contains the state of the process for the corresponding application 1580. In at least one embodiment, a work description (WD) 1584 contained in process element 1583 may be a single job requested by an application or may contain a pointer to a queue of jobs.In at least one embodiment, the WD 1584 is a pointer to a job request queue in the effective address space 1582 of an application.

[0234] In at least one embodiment, the graphics acceleration module 1546 and / or individual graphics processing engines 1531(1)-1531(N) may be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for establishing process states and sending a WD 1584 to a graphics acceleration module 1546 to start a job in a virtualized environment may be included.

[0235] At least in one embodiment, a dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1546 or an individual graphics processing engine 1531. In at least one embodiment, when the graphics acceleration module 1546 is owned by a single process, a hypervisor initializes the accelerator integration circuit 1536 for an owning partition, and an operating system initializes the accelerator integration circuit 1536 for an owning process when the graphics acceleration module 1546 is allocated.

[0236] In operation, in at least one embodiment, a WD fetch unit 1591 in accelerator integration slice 1590 fetches the next WD 1584, which includes an indication of the work to be performed by one or more graphics processing engines of graphics acceleration module 1546. In at least one embodiment, the data from WD 1584 may be stored in registers 1545 and used by MMU 1539, interrupt management circuitry 1547, and / or context management circuitry 1548, as shown. For example, one embodiment of MMU 1539 includes segment / page browsing circuitry for accessing segment / page tables 1586 within a virtual address space 1585 of the operating system. In at least one embodiment, circuitry 1547 may process interrupt events 1592 received from graphics acceleration module 1546.In at least one embodiment, when performing graphics operations, an effective address 1593 generated by a graphics processing engine 1531(1)-1531(N) is translated into a real address by the MMU 1539.

[0237] In at least one embodiment, registers 1545 are duplicated for each graphics processing engine 1531(1)-1531(N) and / or each graphics acceleration module 1546 and may be initialized by a hypervisor or an operating system. In at least one embodiment, each of these duplicated registers may be included in an accelerator integration slice 1590. Example registers that may be initialized by a hypervisor are shown in Table 1. Table 1 - Initialized hypervisor registers Registter # Beschreibung 1 Slice-Steuerregister (Slice-Steuerregister) 2 Real Address (RA) Pointer to the area for scheduled processes 3 Authority mask override register 4 Interrupt vector table entry offset 5 Interrupt vector table entry boundary 6 Condition register 7 Logical partition ID 8 Real Address (RA) pointer to Hypervisor Accelerator Utilization Record 9 Memory description register

[0238] Example registers that can be initialized by an operating system are shown in Table 2. Table 2 - Initialized operating system registers register # Description 1 Process and thread identification 2 Effective Address (EA) Context Store / Restore Pointer 3 Virtual Address (VA) pointer for the accelerator utilization set 4 Virtual Address (VA) Pointer to the memory segment table 5 Authority mask 6 Job description

[0239] In at least one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engines 1531(1)-1531(N). In at least one embodiment, it contains all the information required by a graphics processing engine 1531(1)-1531(N) to perform work, or it may be a pointer to a memory location where an application has established a command queue of work to be performed.

[0240] Fig.15E shows additional details for an exemplary embodiment of a joint model. This embodiment includes a real hypervisor address space 1598 in which a process element list 1599 is stored. In at least one embodiment, the real hypervisor address space 1598 is accessible via a hypervisor 1596 that virtualizes graphics acceleration engine engines for the operating system 1595.

[0241] In at least one embodiment, shared programming models allow all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 1546. In at least one embodiment, there are two programming models where the graphics acceleration module 1546 is shared among multiple processes and partitions: time-slice sharing and graphics sharing.

[0242] In at least one embodiment, in this model, the system hypervisor 1596 has the graphics acceleration module 1546 and makes its functionality available to all operating systems 1595. In at least one embodiment, a graphics acceleration module 1546 may meet certain requirements to support virtualization by the system hypervisor 1596, such as (1) the job request of an application must be autonomous (i.e.the state does not need to be maintained between jobs), or the graphics acceleration module 1546 must provide a mechanism for saving and restoring the context, (2) the graphics acceleration module 1546 guarantees that an application's job request will be completed in a specified amount of time, including any translation errors, or the graphics acceleration module 1546 provides the ability to preempt the processing of a job, and (3) the graphics acceleration module 1546 must be guaranteed fairness between processes when operating in a directed joint programming model.

[0243] In at least one embodiment, application 1580 must execute an operating system 1595 system call with a graphics acceleration module type, a work description (WD), an authority mask register (AMR) value, and a context save / restore pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes a targeted acceleration function for a system call. In at least one embodiment, the graphics acceleration module type may be a system-specific value. In at least one embodiment, WD is formatted specifically for graphics acceleration module 1546 and may be in the form of a graphics acceleration module instruction, a pointer to the effective address of a user-defined structure, a pointer to the effective address of an instruction queue, or another data structure describing the work to be performed by graphics acceleration module 1546.

[0244] In at least one embodiment, an AMR value is an AMR state to be used for a current process. In at least one embodiment, a value passed to an operating system is comparable to an application setting an AMR. In at least one embodiment, if accelerator integration circuitry 1536 (not shown) and graphics acceleration module 1546 do not support an authority mask override register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. In at least one embodiment, hypervisor 1596 may optionally apply a current authority mask override register (AMOR) value before placing an AMR into process element 1583.In at least one embodiment, CSRP is one of the registers 1545 that contains an effective address of a region in an application's effective address space 1582 for the graphics acceleration module 1546 to save and restore state. In at least one embodiment, this pointer is optional if no state needs to be saved between jobs or if a job aborts prematurely. In at least one embodiment, the context save / restore region may be anchored in system memory.

[0245] Upon receiving a system call, the operating system 1595 may verify whether the application 1580 has and has been granted permission to use the graphics acceleration module 1546. In at least one embodiment, the operating system 1595 then invokes the hypervisor 1596 with the information listed in Table 3. Table 3 - Parameters for calling the operating system to the hypervisor parameter # Description 1 A job description (WD) 2 An Authority Mask Register (AMR) value (possibly masked) 3 An effective address (EA) Context save / restore pointer (CSRP) 4 A process ID (PID) and optionally a thread ID (TID) 5 A virtual address (VA) accelerator utilization set pointer (AURP) 6 Virtual address of the pointer to the memory segment table (SSTP) 7 A logical interrupt service number (LISN)

[0246] In at least one embodiment, upon receiving a hypervisor call, the hypervisor 1596 checks whether the operating system 1595 has and has been granted permission to use the graphics acceleration module 1546. In at least one embodiment, the hypervisor 1596 then places the process element 1583 in a process element list for a corresponding type of graphics acceleration module 1546. In at least one embodiment, a process element may include the information shown in Table 4. Table 4 - Process element information element # Description 1 A job description (WD) 2 An Authority Mask Register (AMR) value (possibly masked). 3 An effective address (EA) Context save / restore pointer (CSRP) 4 A process ID (PID) and optionally a thread ID (TID) 5 A virtual address (VA) accelerator utilization set pointer (AURP) 6 Virtual address of the pointer to the memory segment table (SSTP) 7 A logical interrupt service number (LISN) 8 Interrupt vector table derived from hypervisor call parameters 9 A status register value (SR) 10 A logical partition ID (LPID) 11 A pointer to the hypervisor's accelerator utilization set with real address (RA) 12 Memory Description Register (SDR)

[0247] In at least one embodiment, the hypervisor initializes a plurality of accelerator integration slice 1590 registers 1545.

[0248] As in Fig.15F, in at least one embodiment, a unified memory addressable via a common virtual memory address space is used to access physical processor memories 1501(1)-1501(N) and GPU memories 1520(1)-1520(N). In this implementation, operations performed on GPUs 1510(1)-1510(N) use the same virtual / effective address space to access processor memories 1501(1)-1501(M) and vice versa, simplifying programmability. In at least one embodiment, a first portion of a virtual / effective address space is assigned to processor memory 1501(1), a second portion is assigned to second processor memory 1501(N), a third portion is assigned to GPU memory 1520(1), and so on.In at least one embodiment, this distributes an entire virtual / effective memory space (sometimes referred to as effective address space) across each of the processor memories 1501 and GPU memories 1520, allowing each processor or GPU to access each physical memory with a virtual address associated with that memory.

[0249] In at least one embodiment, the bias / coherence management circuitry 1594A-1594E within one or more MMUs 1539A-1539E ensures cache coherence between the caches of one or more host processors (e.g., 1505) and GPUs 1510 and implements bias techniques that indicate in which physical memories certain data types should be stored. In at least one embodiment, while multiple instances of the bias / coherence management circuitry 1594A-1594E in Fig.15F, the bias / coherence circuitry may be implemented within an MMU of one or more host processors 1505 and / or within the accelerator integration circuitry 1536.

[0250] In one embodiment, GPU memories 1520 may be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without the performance penalty associated with full system cache coherence. In at least one embodiment, the ability to access GPU memories 1520 as system memory without burdensome cache coherence overhead provides a favorable operating environment for GPU offload. In at least one embodiment, this arrangement allows host processor 1505 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient compared to simple memory accesses.In at least one embodiment, the ability to access GPU memory 1520 without cache coherence overheads may be critical to the execution time of an offloaded computation. For example, in at least one embodiment, the cache coherence overhead may significantly reduce the effective write bandwidth of a graphics processor 1510 in cases with significant streaming write memory traffic. In at least one embodiment, operand construction efficiency, result access efficiency, and GPU computation efficiency may play a role in determining the effectiveness of a GPU offload.

[0251] In at least one embodiment, the selection of the GPU bias and the host processor bias is controlled by a bias tracker data structure. For example, in at least one embodiment, a bias table may be used, which may be a page-granular structure (e.g., controlled at the granularity of a memory page) comprising 1 or 2 bits per GPU-attached memory page. In at least one embodiment, a bias table may be implemented in a stolen memory region of one or more GPU memories 1520, with or without a bias cache in a GPU 1510 (e.g., to cache frequently / recently used bias table entries). Alternatively, in at least one embodiment, an entire bias table may be maintained in a GPU.

[0252] In at least one embodiment, a bias table entry associated with each access to GPU-attached memory 1520 is accessed prior to the actual GPU memory access, causing the following operations. In at least one embodiment, local requests from a GPU 1510 that find their page in GPU-biased are forwarded directly to a corresponding GPU memory 1520. In at least one embodiment, local requests from a GPU that find its page in the host's bias are forwarded to the processor 1505 (e.g., over a high-speed connection, as described herein). In at least one embodiment, a request from the processor 1505 that finds a requested page in the host processor's bias is completed like a normal memory read. Alternatively, requests directed to a GPU-biased page may be forwarded to a GPU 1510.In at least one embodiment, a GPU may forward a page to a host processor bias when it is not currently using the page. In at least one embodiment, a page's bias state may be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited number of cases, a purely hardware-based mechanism.

[0253] In at least one embodiment, a mechanism for changing the bias state uses an API call (e.g., OpenCL), which in turn calls a graphics processor's device driver, which in turn sends a message (or command descriptor) to a graphics processor instructing it to change a bias state and, on some transitions, perform a cache flush operation in a host. In at least one embodiment, a cache flush operation is used for a transition from the host processor 1505 bias to the GPU bias, but not for an opposite transition.

[0254] In at least one embodiment, cache coherence is maintained by temporarily uncaching GPU-biased pages from host processor 1505. In at least one embodiment, to access these pages, processor 1505 may request access from GPU 1510, which may or may not grant access immediately. Therefore, in at least one embodiment, to reduce communication between processor 1505 and GPU 1510, it is advantageous to ensure that GPU-biased pages are those required by a GPU but not by the host processor 1505, and vice versa.

[0255] Hardware structure(s) 715 are used to carry out one or more embodiments. Details of hardware structure(s) 715 may be described herein in connection with Fig. 7A and / or 7B must be specified.

[0256] Fig.Figure 16 illustrates exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to the illustrated embodiments, other logic and circuitry may also be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0257] Fig.16 is a block diagram illustrating an exemplary integrated circuit 1600 that may be fabricated using one or more IP cores, in accordance with at least one embodiment. In at least one embodiment, the integrated circuit 1600 includes one or more application processors 1605 (e.g., CPUs), at least one graphics processor 1610, and may additionally include an image processor 1615 and / or a video processor 1620, each of which may be a modular IP core. In at least one embodiment, the integrated circuit 1600 includes peripheral or bus logic, including a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I22S / I22C controller 1640.In at least one embodiment, integrated circuit 1600 may include a display device 1645 coupled to one or more of the following interfaces: an HDMI (High-Definition Multimedia Interface) controller 1650 and a MIPI (Mobile Industry Processor Interface) interface 1655. In at least one embodiment, memory may be provided by a flash memory subsystem 1660, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1665 for accessing SDRAM or SRAM devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1670.

[0258] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in integrated circuit 1600 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0259] In at least one embodiment, the integrated circuit 1600 may be used to implement the system 100 (see Fig. 1), of the System 200 (see Fig. 2), of the System 300 (see Fig. 3), of the System 400 (see Fig. 4), of the System 500 (see Fig.5) and / or the block diagram 600 (see Fig. 6) may be used. In at least one embodiment, at least a portion of the Fig. 16 depicted system(s) to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 16 may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described.

[0260] Fig. 17A and Fig.17B illustrate exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to the illustrated embodiments, other logic and circuitry may also be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0261] Fig. 17A and Fig. 17B are block diagrams illustrating example graphics processors for use in an SoC according to the embodiments described herein. Fig. 17A shows an exemplary integrated circuit graphics processor 1710 for a system on a chip that may be manufactured using one or more IP cores, in accordance with at least one embodiment. Fig.17B shows another exemplary integrated circuit graphics processor 1740 that can be manufactured with one or more IP cores in accordance with at least one embodiment. In at least one embodiment, the graphics processor 1710 is Fig. 17A, a low-power graphics processor core. In at least one embodiment, the graphics processor 1740 is Fig. 17B, ​​a higher performance graphics processor core. In at least one embodiment, each of the graphics processors 1710, 1740 may be a variant of the graphics processor 1610 of Fig. be 16.

[0262] In at least one embodiment, graphics processor 1710 includes a vertex processor 1705 and one or more fragment processors 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D, through 1715N-1, and 1715N). In at least one embodiment, graphics processor 1710 may execute different shader programs via separate logic, such that vertex processor 1705 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1715A-1715N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1705 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data.In at least one embodiment, the fragment processor(s) 1715A-1715N use the primitive and vertex data generated by the vertex processor 1705 to generate a framebuffer displayed on a display device. In at least one embodiment, the fragment processor(s) 1715A-1715N are optimized for executing fragment shader programs as provided in an OpenGL API, which can be used to perform similar operations as a pixel shader program as provided in a Direct 3D API.

[0263] In at least one embodiment, graphics processor 1710 additionally includes one or more memory management units (MMUs) 1720A-1720B, cache(s) 1725A-1725B, and circuit interconnect(s) 1730A-1730B. In at least one embodiment, one or more MMU(s) 1720A-1720B provide virtual-to-physical address mapping for graphics processor 1710, including vertex processor 1705 and / or fragment processor(s) 1715A-1715N, which may reference vertex or image / texture data stored in memory in addition to the vertex or image / texture data stored in one or more cache(s) 1725A-1725B. In at least one embodiment, one or more MMU(s) 1720A-1720B may be synchronized with other MMUs within a system, including one or more MMUs associated with one or more application processors 1605, image processors 1615, and / or video processors 1620 of Fig.16, so that each processor 1605-1620 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B enable the graphics processor 1710 to interface with other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection.

[0264] In at least one embodiment, the graphics processor 1740 includes one or more shader cores 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F, through 1755N-1 and 1755N), as shown in Fig.17B, ​​which provides a unified shader core architecture in which a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1740 includes an inter-core task manager 1745 acting as a thread dispatcher to distribute execution threads to one or more shader cores 1755A-1755N and a tiling unit 1758 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are divided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0265] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in graphics processor 1710 and / or 1740 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0266] In at least one embodiment, the graphics processor 1710 may be used to operate the system 100 (see Fig. 1), the System 200 (see Fig. 2), the System 300 (see Fig. 3), the System 400 (see Fig. 4), the System 500 (see Fig.5) and / or the block diagram 600 (see Fig. 6). In at least one embodiment, at least a portion of the Fig. 17A to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 17A may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes associated with any of the Fig. 1-6 are described.

[0267] In at least one embodiment, the graphics processor 1740 may be used to implement the system 100 (see Fig. 1), of the System 200 (see Fig. 2), of the System 300 (see Fig. 3), of the System 400 (see Fig.4), of the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6) may be used. In at least one embodiment, at least a portion of the Fig. 17B to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 17B may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described.

[0268] Fig. 18A and Fig. 18B illustrate additional exemplary graphics processor logic according to the embodiments described herein. In at least one embodiment, the Fig. 18A and Fig. 18B are integrated into a single system, such as a graphics processing unit (GPU), an SoC, or another processor. Fig. 18A shows a graphics core 1800 that, in at least one embodiment, includes the graphics processor 1610 of Fig. 16 and in at least one embodiment, a unified shader core 1755A-1755N as in Fig. 17B can be. Fig.18B illustrates a highly parallel general-purpose graphics processing unit (“GPGPU,” which may also be referred to as a “graphics processing unit”) 1830, which in at least one embodiment is suitable for use on a multi-chip module. In at least one embodiment, the graphics processing unit 1830 is a GPGPU that includes a graphics processor. In at least one embodiment, the integrated circuit 1600 includes a graphics core 1800, for example, to form an integrated circuit and / or an SoC, such an integrated circuit and / or SoC performing the operations described herein.

[0269] In at least one embodiment, the graphics core 1800 includes a shared instruction cache 1802, a texture unit 1818, and a cache / shared memory 1820 (e.g., L1, L2, L3, last level cache, or other caches) common to the execution resources in the graphics core 1800. In at least one embodiment, the graphics core 1800 may include multiple slices 1801A-1801N or a partition for each core, and a graphics processor may include multiple instances of the graphics core 1800. In at least one embodiment, each slice 1801A-1801N refers to the graphics core 1800. In at least one embodiment, the slices 1801A-1801N include subslices that are part of a slice 1801A-1801N. In at least one embodiment, slices 1801A-1801N are independent of other slices or dependent on other slices.In at least one embodiment, slices 1801A-1801N may include support logic including a local instruction cache 1804A-1804N, a thread scheduler (sequencer) 1806A-1806N, a thread dispatcher 1808A-1808N, and a register set 1810A-1810N. In at least one embodiment, slices 1801A-1801N may include a set of additional functional units (AFUs 1812A-1812N), floating-point units (FPUs 1814A-1814N), integer arithmetic logic units (ALUs 1816A-1816N), address calculation units (ACUs 1813A-1813N), double-precision floating-point units (DPFPUs 1815A-1815N), and matrix processing units (MPUs 1817A-1817N). In at least one embodiment, MPUs 1817A-1817N are referred to as matrix engines.

[0270] In at least one embodiment, each slice 1801A-1801N includes one or more engines for floating-point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large datasets. In at least one embodiment, one or more slices 1801A-1801N include one or more vector engines for computing a vector (e.g., computing mathematical operations on vectors). In at least one embodiment, a vector engine can compute a vector operation in 16-bit floating point (also referred to as "FP16"), 32-bit floating point (also referred to as "FP32"), or 64-bit floating point (also referred to as "FP64").In at least one embodiment, one or more slices 1801A-1801N comprise 16 vector engines paired with 16 matrix math units for computing matrix / tensor operations, where the vector engines and math units are accessible via matrix extensions. In at least one embodiment, a slice comprises a particular portion of the processing resources of a processing unit, for example, 16 cores and a ray tracing unit, or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units for a processor. In at least one embodiment, the graphics core 1800 comprises one or more matrix engines for computing matrix operations, for example, in computing tensor operations.

[0271] In at least one embodiment, one or more slices 1801A-1801N include one or more ray tracing units for computing ray tracing operations (e.g., 16 ray tracing units per slice 1801A-1801N). In at least one embodiment, a ray tracing unit computes ray crossings, triangle intersections, bounding box intersections, or other ray tracing operations.

[0272] In at least one embodiment, one or more slices 1801A-1801N comprise a media slice that encodes, decodes, and / or transcodes data, scales and / or formats data, and / or performs video quality operations on video data.

[0273] In at least one embodiment, one or more slices 1801A-1801N are connected to L2 cache and memory structure, interconnect ports, HBM memory stacks (e.g., HBM2e, HDM3), and a media engine. In at least one embodiment, one or more slices 1801A-1801N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 1801A-1801N have one or more L1 caches. In at least one embodiment, one or more slices 1801A-1801N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data, e.g.,B, which correspond to instructions; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometries for performing operations in geometry pipelines and / or for applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed, combine to form an image represented by shapes); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, a slice 1801A-1801N includes a memory structure, such as an L2 cache.

[0274] In at least one embodiment, the FPUs 1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1815A-1815N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1816A-1816N can perform variable-precision integer operations at 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1817A-1817N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, the MPUs 1817-1817N may perform a variety of matrix operations to accelerate machine learning application frameworks, including support for accelerated generalized matrix-matrix multiplication (GEMM).In at least one embodiment, the AFUs 1812A-1812N may perform additional logical operations not supported by floating point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0275] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in graphics core 1800 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0276] In at least one embodiment, the graphics core 1800 includes an interconnect and a link fabric sublayer connected to a switch and a GPU-to-GPU bridge that enables multiple graphics processors 1800 (e.g., 8) to be interconnected without gluing load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 1800. In at least one embodiment, the interconnects include standardized interconnects (e.g., PCIe) or a combination thereof.

[0277] In at least one embodiment, the graphics core 1800 includes multiple tiles. In at least one embodiment, a tile is a single die or one or more dies, where individual dies may be connected with an interconnect (e.g., Embedded Multi-Die Interconnect Bridge (EMIB)). In at least one embodiment, the graphics core 1800 includes a compute tile, a memory tile (e.g., where a memory tile may be exclusively accessed by different tiles or different chipsets, such as a Rambo tile), a substrate tile, a base tile, an HMB tile, a link tile, and an EMIB tile, where all tiles are grouped together in the graphics core 1800 as part of a GPU. In at least one embodiment, the graphics core 1800 may include multiple tiles in a single package (also referred to as a "multi-tile package").In at least one embodiment, a compute tile may include 8 graphics cores 1800, an L1 cache, and a base tile; a host interface with PCIe 5.0, HBM2e, MDFI, and EMIB; and a link tile with 8 links, 8 ports, and an embedded switch. In at least one embodiment, the tiles are connected using face-to-face (F2F) chip-on-chip bonding via finely pitched 36-micrometer microbumps (e.g., copper pillars). In at least one embodiment, the graphics core 1800 includes a memory structure that includes memory and is a tile accessible by multiple tiles. In at least one embodiment, the graphics core 1800 stores, accesses, or loads its own hardware contexts in memory. A hardware context is a set of data loaded from registers prior to resuming a process, and a hardware context may indicate a state of the hardware (e.g., the state of a GPU).

[0278] In at least one embodiment, the graphics core 1800 includes a serialization / deserialization circuit (SERDES) that converts a serial data stream to a parallel data stream or a parallel data stream to a serial data stream.

[0279] In at least one embodiment, the graphics core 1800 includes a coherent high-speed unified fabric (GPU to GPU), load / store units, bulk data transfer and sync semantics, and GPUs connected via an embedded switch, with a GPU-GPU bridge controlled by a controller.

[0280] In at least one embodiment, the graphics core 1800 executes an API, where the API abstracts the hardware of the graphics core 1800 and accesses libraries of instructions for performing mathematical operations (e.g., math kernel library), deep neural network operations (e.g., deep neural network library), vector operations, collective communication, threading building blocks, video processing, data analysis library, and / or ray tracing operations.

[0281] In at least one embodiment, the graphics core 1800 may be used to implement the system 100 (see Fig. 1), of the System 200 (see Fig. 2), of the System 300 (see Fig. 3), of the System 400 (see Fig. 4), of the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6) may be used. In at least one embodiment, at least a portion of the Fig.18A to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 18A may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described.

[0282] Fig. 18B shows the GPGPU 1830, which in at least one embodiment can be configured to perform highly parallel computational operations by an array of graphics processing units. In at least one embodiment, the GPGPU 1830 can be directly connected to other instances of the GPGPU 1830 to form a multi-GPU cluster and improve training speed for deep neural networks. In at least one embodiment, the GPGPU 1830 includes a host interface 1832 to enable connection to a host processor. In at least one embodiment, the host interface 1832 is a PCI Express interface. In at least one embodiment, the host interface 1832 can be a vendor-specific communication interface or communication fabric.In at least one embodiment, the GPGPU 1830 receives instructions from a host processor and uses a global scheduler 1834 (which may be referred to as a thread sequencer and / or asynchronous compute engine) to distribute the execution threads associated with those instructions among a number of compute clusters 1836A-1836H. In at least one embodiment, the compute clusters 1836A-1836H share a cache 1838. In at least one embodiment, the cache 1838 may serve as a high-level cache for caches in compute clusters 1836A-1836H. In at least one embodiment, the compute clusters 1836A-1836H comprise a slice or are referred to as "slices." In at least one embodiment, the GPGPU 1830 is part of an SoC, such as part of the integrated circuit 1600 (. Fig. 16).

[0283] In at least one embodiment, GPGPU 1830 includes memory 1844A-1844B coupled to compute clusters 1836A-1836H via a series of memory controllers 1842A-1842B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 1844A-1844B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate memory (GDDR).

[0284] In at least one embodiment, the compute clusters 1836A-1836H each include a set of graphics cores, such as the graphics core 1800 of Fig. 18A, which may include multiple types of integer and floating-point logic units capable of performing computational operations at a range of precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of floating-point units in each of compute clusters 1836A-1836H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of floating-point units may be configured to perform 64-bit floating-point operations.

[0285] In at least one embodiment, multiple instances of the GPGPU 1830 can be configured to operate as a compute cluster. In at least one embodiment, the communication used by the compute clusters 1836A-1836H for synchronization and data exchange varies between embodiments. In at least one embodiment, multiple instances of the GPGPU 1830 communicate via the host interface 1832. In at least one embodiment, the GPGPU 1830 includes an I / O hub 1839 that couples the GPGPU 1830 to a GPU interconnect 1840 that enables direct connection to other instances of the GPGPU 1830. In at least one embodiment, the GPU interconnect 1840 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of the GPGPU 1830.In at least one embodiment, GPU interconnect 1840 is coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1830 are located in separate computing systems and communicate via a network interface accessible via host interface 1832. In at least one embodiment, GPU interconnect 1840 may be configured to enable connection to a processor in addition to, or alternatively to, host interface 1832.

[0286] In at least one embodiment, GPGPU 1830 may be configured to train neural networks. In at least one embodiment, GPGPU 1830 may be used within an inferencing platform. In at least one embodiment where GPGPU 1830 is used for inferencing, GPGPU 1830 may include fewer compute clusters 1836A-1836H than when GPGPU 1830 is used for training a neural network. In at least one embodiment, the memory technology associated with memory 1844A-1844B may differ between inference and training configurations, with higher-bandwidth memory technologies being allocated to training configurations. In at least one embodiment, an inferencing configuration of GPGPU 1830 may support inferencing-specific instructions.For example, in at least one embodiment, an inference configuration may provide support for one or more 8-bit integer dot product instructions that may be used during inference operations for deployed neural networks.

[0287] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in GPGPU 1830 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0288] In at least one embodiment, the GPGPU 1830 may be used to implement the system 100 (see Fig. 1), of the System 200 (see Fig. 2), of the System 300 (see Fig. 3), of the System 400 (see Fig. 4), of the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6) may be used. In at least one embodiment, at least a portion of the Fig. 18B to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 18B may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described.

[0289] Fig. 19 is a block diagram illustrating a computer system 1900 according to at least one embodiment. In at least one embodiment, computer system 1900 includes a processing subsystem 1901 having one or more processors 1902 and a system memory 1904 communicating via an interconnect path that may include a memory hub 1905. In at least one embodiment, memory hub 1905 may be a separate component within a chipset component or integrated with one or more processors 1902. In at least one embodiment, memory hub 1905 is coupled to an I / O subsystem 1911 via a communications link 1906. In at least one embodiment, I / O subsystem 1911 includes an I / O hub 1907 that may enable computer system 1900 to receive input from one or more input devices 1908.In at least one embodiment, the I / O hub 1907 may enable a display controller, which may be included in one or more processors 1902, to provide output to one or more display devices 1910A. In at least one embodiment, one or more display devices 1910A connected to the I / O hub 1907 may comprise a local, internal, or embedded display device.

[0290] In at least one embodiment, the processing subsystem 1901 includes one or more parallel processors 1912 connected to the storage hub 1905 via a bus or other communication link 1913. In at least one embodiment, the communication link 1913 may use any number of standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication structure. In at least one embodiment, one or more parallel processors 1912 form a computationally focused parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a Many Integrated Core (MIC) processor.In at least one embodiment, some or all of the parallel processors 1912 form a graphics processing subsystem that can output pixels to one or more display devices 1910A coupled via the I / O hub 1907. In at least one embodiment, the parallel processor(s) 1912 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1910B. In at least one embodiment, the parallel processor(s) 1912 include one or more cores, such as the graphics cores 1800 discussed herein.

[0291] In at least one embodiment, a system storage unit 1914 may be connected to the I / O hub 1907 to provide a storage mechanism for the computer system 1900. In at least one embodiment, an I / O switch 1916 may be used to provide an interface that enables connections between the I / O hub 1907 and other components, such as a network interface 1918 and / or a wireless network interface 1919 that may be integrated into the platform, and various other devices that may be added via one or more add-in devices 1920. In at least one embodiment, the network adapter 1918 may be an Ethernet adapter or other wired network adapter.In at least one embodiment, the wireless network adapter 1919 may include one or more of the following devices: Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices that include one or more wireless radios.

[0292] In at least one embodiment, the computer system 1900 may include other components not explicitly shown, including USB or other connectors, optical storage drives, video capture devices, and the like, which may also be connected to the I / O hub 1907. In at least one embodiment, communication paths connecting various components in Fig. 19 interconnection may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI Express) or other bus or point-to-point communication links and / or protocols, such as NV-Link high-speed links or interconnection protocols.

[0293] In at least one embodiment, the parallel processor(s) 1912 include circuitry optimized for graphics and video processing, such as video output circuitry, and form a graphics processing unit (GPU). For example, the parallel processor(s) 1912 includes a graphics core 1800. In at least one embodiment, the parallel processor(s) 1912 include circuitry optimized for general processing. In at least one embodiment, components of the computer system 1900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, the parallel processor(s) 1912, the memory hub 1905, the processor(s) 1902, and the I / O hub 1907 may be integrated into a system-on-a-chip (SoC) integrated circuit.In at least one embodiment, the components of computer system 1900 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computer system 1900 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computer system.

[0294] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in computer system 1900 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0295] In at least one embodiment, the computer system 1900 may be used to implement the system 100 (see Fig. 1), of the System 200 (see Fig. 2), of the System 300 (see Fig. 3), of the System 400 (see Fig. 4), of the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6) may be used. In at least one embodiment, at least a portion of the Fig. 19 depicted system(s) to implement one or more systems, techniques, functions and / or processes that are used in conjunction with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 19 may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described. PROCESSORS

[0296] Fig. 20A shows a parallel processor 2000 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 2000 can be implemented using one or more integrated circuits, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the parallel processor 2000 shown is a variant of one or more parallel processors 1912 implemented in Fig. 19 according to an exemplary embodiment. In at least one embodiment, a parallel processor 2000 includes one or more graphics cores 1800.

[0297] In at least one embodiment, parallel processor 2000 includes a parallel processing unit 2002. In at least one embodiment, parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of parallel processing unit 2002. In at least one embodiment, I / O unit 2004 can be connected directly to other devices. In at least one embodiment, I / O unit 2004 is connected to other devices via a hub or switch interface, such as a storage hub 2005. In at least one embodiment, the connections between storage hub 2005 and I / O unit 2004 form a communication link 2013.In at least one embodiment, the I / O unit 2004 is coupled to a host interface 2006 and a memory crossbar 2016, wherein the host interface 2006 receives commands directed to performing processing operations and the memory crossbar 2016 receives commands directed to performing memory operations.

[0298] In at least one embodiment, when the host interface 2006 receives a command buffer via the I / O unit 2004, the host interface 2006 may forward work operations to a front end 2008 for execution of those commands. In at least one embodiment, the front end 2008 is coupled to a scheduler 2010 (which may also be referred to as a sequencer) configured to dispatch commands or other work items to a processing cluster array 2012. In at least one embodiment, the scheduler 2010 ensures that the processing array 2012 is properly configured and in a valid state before dispatching tasks to a cluster of the processing array 2012. In at least one embodiment, the scheduler 2010 is implemented via firmware logic executing on a microcontroller.In at least one embodiment, the microcontroller-implemented scheduler 2010 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on the processing array 2012. In at least one embodiment, host software may allocate workloads for scheduling on the processing cluster array 2012 via one of several graphics processing paths. In at least one embodiment, workloads may then be automatically distributed across the processing array cluster 2012 by the logic of the scheduler 2010 within a microcontroller that includes the scheduler 2010.

[0299] In at least one embodiment, the processing array 2012 may include up to "N" processing clusters (e.g., cluster 2014A, cluster 2014B, through cluster 2014N), where "N" represents a positive integer (which may be a different integer "N" than used in other figures). In at least one embodiment, each cluster 2014A-2014N of the processing array 2012 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2010 may allocate work to the clusters 2014A-2014N of the processing array 2012 using various scheduling and / or work distribution algorithms, which may vary depending on the workload incurred for each type of program or computation.In at least one embodiment, scheduling may be performed dynamically by scheduler 2010 or assisted at least in part by compiler logic during compilation of program logic configured for execution by processing cluster array 2012. In at least one embodiment, different clusters 2014A-2014N of processing cluster array 2012 may be allocated for processing different types of programs or for performing different types of computations.

[0300] In at least one embodiment, the processing cluster array 2012 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2012 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2012 may include logic to perform processing tasks, including filtering video and / or audio data, performing modeling operations, including physics operations, and performing data transformations.

[0301] In at least one embodiment, the processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2012 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2012 may be configured to execute graphics processing-related shader programs, such as vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2002 may transfer data from system memory via the I / O unit 2004 for processing.In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) during processing and then written back to system memory.

[0302] In at least one embodiment, when the graphics processing unit 2002 is used to perform graphics processing, the scheduler 2010 may be configured to divide a processing load into approximately equal-sized tasks to enable better distribution of graphics processing operations across multiple clusters 2014A-2014N of the processing cluster array 2012. In at least one embodiment, portions of the processing cluster array 2012 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display.In at least one embodiment, intermediate data generated by one or more of the clusters 2014A-2014N may be stored in buffers to allow intermediate data to be transferred between the clusters 2014A-2014N for further processing.

[0303] In at least one embodiment, processing cluster array 2012 may receive processing tasks to be executed via scheduler 2010, which receives commands defining processing tasks from frontend 2008. In at least one embodiment, the processing tasks may include indices of the data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands that define how the data is to be processed (e.g., which program is to be executed). In at least one embodiment, scheduler 2010 may be configured to retrieve or receive indices corresponding to the tasks from frontend 2008.In at least one embodiment, the front end 2008 may be configured to ensure that the processing cluster array 2012 is configured in a valid state before initiating a workload specified by incoming command buffers (e.g., batch buffers, push buffers, etc.).

[0304] In at least one embodiment, each of one or more instances of parallel processing unit 2002 may be coupled to a parallel processor memory 2022. In at least one embodiment, parallel processor memory 2022 may be accessed via a memory crossbar 2016, which may receive memory requests from processing cluster array 2012 as well as from I / O unit 2004. In at least one embodiment, memory crossbar 2016 may access parallel processor memory 2022 via a memory interface 2018. In at least one embodiment, memory interface 2018 may include a plurality of partition units (e.g., partition unit 2020A, partition unit 2020B, through partition unit 2020N), each of which may be coupled to a portion (e.g., memory unit) of parallel processor memory 2022.In at least one embodiment, a number of partition units 2020A-2020N is configured to be equal to a number of storage units, such that a first partition unit 2020A has a corresponding first storage unit 2024A, a second partition unit 2020B has a corresponding storage unit 2024B, and an Nth partition unit 2020N has a corresponding Nth storage unit 2024N. In at least one embodiment, the number of partition units 2020A-2020N may not be equal to the number of storage units.

[0305] In at least one embodiment, the memory units 2024A-2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate memory (GDDR). In at least one embodiment, the memory units 2024A-2024N may also include 3D stacks, including, but not limited to, high width memory (HBM), HBM2e, or HDM3. In at least one embodiment, rendering targets, such as frame buffers or texture units, may be stored across the memory units 2024A-2024N so that the partition units 2020A-2020N can write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2022.In at least one embodiment, a local instance of parallel processor memory 2022 may be eliminated in favor of a unified memory design that utilizes system memory in conjunction with the local cache memory.

[0306] In at least one embodiment, each of the clusters 2014A-2014N of the processing array 2012 may process data written to each of the storage units 2024A-2024N in the parallel processor memory 2022. In at least one embodiment, the storage crossbar 2016 may be configured to transfer an output of each cluster 2014A-2014N to any partition unit 2020A-2020N or to another cluster 2014A-2014N that may perform additional processing on an output. In at least one embodiment, each cluster 2014A-2014N may communicate with the storage interface 2018 via the storage crossbar 2016 to read from or write to various external devices.In at least one embodiment, the memory crossbar 2016 includes a connection to the memory interface 2018 to communicate with the I / O unit 2004, as well as a connection to a local instance of the parallel processor memory 2022, which enables the processing units within different processing clusters 2014A-2014N to communicate with system memory or other memory not local to the parallel processing unit 2002. In at least one embodiment, the memory crossbar 2016 may use virtual channels to separate traffic flows between clusters 2014A-2014N and partition units 2020A-2020N.

[0307] In at least one embodiment, multiple instances of the parallel processing unit 2002 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2002 may be configured to interoperate even if the different instances have different numbers of processor cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2002 may include higher-precision floating-point units compared to other instances.In at least one embodiment, systems including one or more instances of the parallel processing unit 2002 or the parallel processor 2000 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0308] Fig. 20B is a block diagram of a partition unit 2020 according to at least one embodiment. In at least one embodiment, the partition unit 2020 is an instance of one of the partition units 2020A-2020N of Fig. 20A. In at least one embodiment, the partition unit 2020 includes an L2 cache 2021, a frame buffer interface 2025, and a ROP 2026 (raster operation unit). In at least one embodiment, the L2 cache 2021 is a read / write cache configured to perform load and store operations received from the memory crossbar 2016 and the ROP 2026. In at least one embodiment, read misses and urgent writeback requests are issued from the L2 cache 2021 to the frame buffer interface 2025 for processing. In at least one embodiment, updates may also be sent to a frame buffer via the frame buffer interface 2025 for processing. In at least one embodiment, the frame buffer interface 2025 has an interface to one of the memory units in the parallel processor memory, such as the memory units 2024A-2024N of Fig. 20A (for example, within the parallel processor memory 2022).

[0309] In at least one embodiment, ROP 2026 is a processing unit that performs raster operations such as stenciling, Z-testing, blending, etc. In at least one embodiment, ROP 2026 then outputs processed graphics data, which is stored in graphics memory. In at least one embodiment, ROP 2026 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic using one or more of several compression algorithms. In at least one embodiment, the type of compression performed by ROP 2026 may vary based on the statistical properties of the data to be compressed.For example, in at least one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0310] In at least one embodiment, ROP 2026 is in each processing cluster (e.g., clusters 2014A-2014N of Fig. 20A) instead of in the partition unit 2020. In at least one embodiment, read and write requests for pixel data are transmitted via the memory crossbar 2016 instead of pixel fragment data. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 1910 of Fig. 19, for further processing by processor(s) 1902 or for further processing by one of the processing units within the parallel processor 2000 of Fig. 20A.

[0311] Fig. 20C is a block diagram of a processing cluster 2014 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of the processing clusters 2014A-2014N of Fig. 20A. In at least one embodiment, the processing cluster 2014 may be configured to execute many threads in parallel, where "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single instruction, multiple data (SIMD) instruction dispatch techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single-instruction-multiple-thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit configured to dispatch instructions to a set of processing engines within each processing cluster.

[0312] In at least one embodiment, the operation of the processing cluster 2014 may be controlled by a pipeline manager 2032, which distributes the processing tasks among parallel SIMT processors. In at least one embodiment, the pipeline manager 2032 receives instructions from the scheduler 2010 of Fig. 20A and manages the execution of these instructions via a graphics multiprocessor 2034 and / or a texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included in the processing cluster 2014. In at least one embodiment, one or more instances of the graphics multiprocessor 2034 may be included in a processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 may process data, and a data crossbar 2040 may be used to distribute processed data to one of several possible destinations, including other shader units.In at least one embodiment, the pipeline manager 2032 may facilitate the distribution of processed data by specifying destinations for processed data to be distributed across the data crossbar 2040.

[0313] In at least one embodiment, each graphics multiprocessor 2034 within the processing cluster 2014 may include an identical set of functional execution logic (e.g., arithmetic logic units, load / store units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipeline in which new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and the computation of various algebraic functions. In at least one embodiment, the same hardware with functional units may be used to perform different operations, and any combination of functional units may be present.

[0314] In at least one embodiment, the instructions transferred to the processing cluster 2014 form a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program with different input data. In at least one embodiment, each thread within a thread group may be assigned to a different engine within a graphics multiprocessor 2034. In at least one embodiment, a thread group may include fewer threads than a number of processing engines within the graphics multiprocessor 2034.In at least one embodiment, when a thread group includes fewer threads than a number of processing engines, one or more of the processing engines may be idle during the cycles in which that thread group is processing. In at least one embodiment, a thread group may also include more threads than a number of processing engines in the graphics multiprocessor 2034. In at least one embodiment, when a thread group includes more threads than the number of processing engines in the graphics multiprocessor 2034, processing may occur in consecutive clock cycles. In at least one embodiment, multiple thread groups may execute concurrently on a graphics multiprocessor 2034.

[0315] In at least one embodiment, the graphics multiprocessor 2034 includes an internal cache for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2034 may forgo an internal cache and use a cache (e.g., L1 cache 2048) within the processing cluster 2014. In at least one embodiment, each graphics multiprocessor 2034 also has access to L2 caches within partition units (e.g., partition units 2020A-2020N of Fig. 20A) that are shared by all processing clusters 2014 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2034 can also access off-chip global memory, which can include one or more of the parallel processor local memories and / or system memories. In at least one embodiment, any memory external to parallel processing unit 2002 can be used as global memory. In at least one embodiment, processing cluster 2014 includes multiple instances of graphics multiprocessor 2034 and can share common instructions and data that can be stored in L1 cache 2048.

[0316] In at least one embodiment, each processing cluster 2014 may include a memory management unit (MMU) 2045 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2045 may reside within the memory interface 2018 of Fig. 20A. In at least one embodiment, the MMU 2045 includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile, and optionally a cache line index. In at least one embodiment, the MMU 2045 may include address translation lookaside buffers (TLBs) or caches, which may be located in the graphics multiprocessor 2034 or the L1 2048 cache or the processing cluster 2014. In at least one embodiment, a physical address is processed to distribute access to surface data locally to enable efficient interleaving of requests between partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or miss.

[0317] In at least one embodiment, a processing cluster 2014 may be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 to perform texture mapping operations, such as determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, the texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034 and retrieved from an L2 cache, local parallel processor memory, or system memory as needed.In at least one embodiment, each graphics multiprocessor 2034 issues processed tasks to the data crossbar 2040 to make the processed task available to another processing cluster 2014 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 2016. In at least one embodiment, a pre-raster operations unit (preROP) 2042 is configured to receive data from the graphics multiprocessor 2034 and forward data to ROP units, which may be arranged with partition units as described herein (e.g., partition units 2020A-2020N of FIG. Fig. 20A). In at least one embodiment, the preROP unit 2042 may perform optimizations for mixing colors, organizing pixel color data, and performing address translations.

[0318] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in processing cluster 2014 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0319] In at least one embodiment, the parallel processor 2000 may be used to implement the system 100 (see Fig. 1), of the System 200 (see Fig. 2), of the System 300 (see Fig. 3), of the System 400 (see Fig. 4), of the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6) may be used. In at least one embodiment, at least a portion of the Fig. 20A-20C to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 20A-20C may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described.

[0320] Fig. 20D illustrates a graphics multiprocessor 2034 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2034 is coupled to the pipeline manager 2032 of the processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 includes an execution pipeline including, among other things, an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more general purpose graphics processing units (GPGPU cores) 2062, and one or more load / store units 2066, where one or more load / store units 2066 may perform load / store operations to load / store instructions corresponding to performing an operation.In at least one embodiment, the GPGPU cores 2062 and the load / store units 2066 are coupled to the cache memory 2072 and the shared memory 2070 via a memory and cache interconnect 2068. In at least one embodiment, the GPGPU cores 2062 are part of an SoC, such as part of the integrated circuit 1600 in FIG. Fig. 16.

[0321] In at least one embodiment, instruction cache 2052 receives a stream of instructions for execution from pipeline manager 2032. In at least one embodiment, the instructions are cached in instruction cache 2052 and forwarded for execution by an instruction unit 2054. In at least one embodiment, instruction unit 2054 may dispatch instructions in the form of thread groups (e.g., warps, wavefronts, waves), where each thread of a thread group is associated with a different execution unit within GPGPU cores 2062. In at least one embodiment, an instruction may access a local, shared, or global address space by specifying an address within a unified address space.In at least one embodiment, address mapping unit 2056 may be used to translate addresses in a unified address space into a unique memory address accessible by load / store units 2066.

[0322] In at least one embodiment, register file 2058 provides a set of registers for functional units of graphics multiprocessor 2034. In at least one embodiment, register file 2058 provides temporary storage for operands associated with data paths of functional units (e.g., GPGPU cores 2062, load / store units 2066) of graphics multiprocessor 2034. In at least one embodiment, register file 2058 is partitioned between individual functional units so that each functional unit is assigned a separate portion of register file 2058. In at least one embodiment, register file 2058 is partitioned among different warps (which may be referred to as wavefronts and / or waves) executed by graphics multiprocessor 2034.

[0323] In at least one embodiment, the GPGPU cores 2062 may each include floating-point units (FPUs) and / or integer arithmetic logic units (ALUs) used to execute instructions of the graphics multiprocessor 2034. In at least one embodiment, the GPGPU cores 2062 may be similar in architecture or different in architecture. In at least one embodiment, a first portion of the GPGPU cores 2062 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU cores includes a double-precision FPU. In at least one embodiment, the FPUs may implement IEEE 754-2008 standard floating-point arithmetic or enable variable-precision floating-point arithmetic.In at least one embodiment, the graphics multiprocessor 2034 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or blending pixels. In at least one embodiment, one or more of the GPGPU cores 2062 may also include fixed-function logic or special-function logic.

[0324] In at least one embodiment, GPGPU cores 2062 include SIMD logic capable of applying a single instruction to multiple data sets. In at least one embodiment, GPGPU cores 2062 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores can be generated at compile time by a shader compiler or automatically during the execution of programs written and compiled for SPMD or SIMT (Single Program Multiple Data) architectures. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0325] In at least one embodiment, the memory and cache interconnect 2068 is an interconnect network that connects each functional unit of the graphics multiprocessor 2034 to the register file 2058 and the shared memory 2070. In at least one embodiment, the memory and cache interconnect 2068 is a crossbar interconnect that enables the load / store unit 2066 to perform load and store operations between the shared memory 2070 and the register file 2058. In at least one embodiment, the register file 2058 may operate at the same frequency as the GPGPU cores 2062, so that data transfer between the GPGPU cores 2062 and the register file 2058 may have very low latency. In at least one embodiment, the shared memory 2070 may be used to enable communication between threads executing on functional units within the graphics multiprocessor 2034.For example, in at least one embodiment, cache 2072 may be used as a data cache to cache texture data transferred between functional units and texture unit 2036. In at least one embodiment, shared memory 2070 may also be used as a program-managed cache. In at least one embodiment, threads executing on GPGPU cores 2062 may programmatically store data in shared memory in addition to the automatically cached data stored in cache 2072.

[0326] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to host processor cores to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, a GPU may be communicatively coupled to the host processor cores via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, an SoC includes a parallel processor or GPGPU, as described herein, with the parallel processor or GPGPU executing on the SoC. In at least one embodiment, a GPU may be integrated on a package or die as cores and communicatively interconnected to the cores via an internal processor bus / interconnect within a package or die.In at least one embodiment, regardless of how a GPU is connected, the processor cores can assign work to that GPU in the form of sequences of instructions contained in a work description. In at least one embodiment, the GPU then uses special circuitry / logic to efficiently process these instructions / instructions.

[0327] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in graphics multiprocessor 2034 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0328] In at least one embodiment, the graphics multiprocessor 2034 may be used to implement the system 100 (see Fig. 1), of the System 200 (see Fig. 2), of the System 300 (see Fig. 3), of the System 400 (see Fig. 4), of the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6) may be used. In at least one embodiment, at least a portion of the Fig. 20D to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 20D may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described.

[0329] Fig. 21 shows a multi-GPU computer system 2100 according to at least one embodiment. In at least one embodiment, the multi-GPU computer system 2100 may include a processor 2102 connected to a plurality of general-purpose graphics processing units (GPGPUs) 2106A-D via a host interface switch 2104. In at least one embodiment, the host interface switch 2104 is a PCI Express switch device that connects the processor 2102 to a PCI Express bus over which the processor 2102 can communicate with the GPGPUs 2106A-D. In at least one embodiment, the GPGPUs 2106A-D may be interconnected via a series of high-speed point-to-point GPU-to-GPU interconnects 2116. In at least one embodiment, the GPU-to-GPU connections 2116 are connected to each of the GPGPUs 2106A-D via a dedicated GPU connection.In at least one embodiment, P2P GPU connections 2116 enable direct communication between the individual GPGPUs 2106A-D without requiring communication through the host interface 2104 to which the processor 2102 is connected. In at least one embodiment where GPU-to-GPU traffic is routed on P2P GPU connections 2116, the host interface bus 2104 remains available for accessing system memory or for communicating with other instances of the multi-GPU computer system 2100, for example, via one or more network devices. While in at least one embodiment the GPGPUs 2106A-D are connected to the processor 2102 via a host interface switch 2104, in at least one embodiment the processor 2102 includes direct support for P2P GPU connections 2116 and can be connected directly to the GPGPUs 2106A-D.In at least one embodiment, the GPGPUs 2106A-D are part of a SoC, such as part of the integrated circuit 1600 in . Fig. 16, wherein the GPGPUs 2106A-D perform the operations described herein.

[0330] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in multi-GPU computing system 2100 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0331] In at least one embodiment, the multi-GPU computer system 2100 includes one or more graphics cores 1800.

[0332] In at least one embodiment, computer system 2100 may be used to implement system 100 (see Fig. 1), the System 200 (see Fig. 2), the System 300 (see Fig. 3), the System 400 (see Fig. 4), the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6). In at least one embodiment, at least a portion of the Fig. 21 depicted system(s) to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 21 may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described.

[0333] Fig. 22 is a block diagram of a graphics processor 2200 according to at least one embodiment. In at least one embodiment, the graphics processor 2200 includes a ring interconnect 2202, a pipelined front end 2204, a media engine 2237, and graphics cores 2280A-2280N. In at least one embodiment, the ring interconnect 2202 connects the graphics processor 2200 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2200 is one of many processors integrated into a multi-core processing system. In at least one embodiment, the graphics processor 2200 includes the graphics core 1800.

[0334] In at least one embodiment, graphics processor 2200 receives batches of commands via ring interconnect 2202. In at least one embodiment, the incoming commands are interpreted by a command streamer 2203 in pipeline front-end 2204. In at least one embodiment, graphics processor 2200 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2280A-2280N. In at least one embodiment, command streamer 2203 provides commands to geometry pipeline 2236 for 3D geometry processing commands. In at least one embodiment, command streamer 2203 provides commands to a video front-end 2234 coupled to media engine 2237 for at least some media processing commands.In at least one embodiment, the media engine 2237 includes a video quality engine (VQE) 2230 for post-processing videos and images and a multi-format encode / decode (MFX) 2233 engine to enable hardware-accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 2236 and the media engine 2237 each generate execution threads for thread execution resources provided by at least one graphics core 2280.

[0335] In at least one embodiment, graphics processor 2200 includes scalable threaded execution resources with graphics cores 2280A-2280N (which may be modular and sometimes referred to as core slices), each having a plurality of sub-cores 2250A-2250N, 2260A-2260N (sometimes referred to as a core slice). In at least one embodiment, graphics processor 2200 may include any number of graphics cores 2280A. In at least one embodiment, graphics processor 2200 includes a graphics core 2280A having at least a first sub-core 2250A and a second sub-core 2260A. In at least one embodiment, graphics processor 2200 is a low-power processor with a single sub-core (e.g., 2250A). In at least one embodiment, the graphics processor 2200 includes a plurality of graphics cores 2280A-2280N, each including a set of first sub-cores 2250A-2250N and a set of second sub-cores 2260A-2260N.In at least one embodiment, each subcore in the first subcores 2250A-2250N includes at least a first set of execution units 2252A-2252N and media / texture units 2254A-2254N. In at least one embodiment, each subcore in the second subcores 2260A-2260N includes at least a second set of execution units 2262A-2262N and samplers 2264A-2264N. In at least one embodiment, each subcore 2250A-2250N, 2260A-2260N shares a set of shared resources 2270A-2270N. In at least one embodiment, the shared resources include a shared cache and pixel operation logic. In at least one embodiment, the graphics processor 2200 includes load / store units in the pipeline front-end 2204.

[0336] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, logic 715 in graphics processor 2200 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0337] In at least one embodiment, the graphics processor 2200 may be used to implement the system 100 (see Fig. 1), of the System 200 (see Fig. 2), of the System 300 (see Fig. 3), of the System 400 (see Fig. 4), of the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6) may be used. In at least one embodiment, at least a portion of the Fig. 22 depicted system(s) to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 22 may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described.

[0338] Fig. 23 is a block diagram illustrating the microarchitecture of a processor 2300 that may include logic circuitry for executing instructions in accordance with at least one embodiment. In at least one embodiment, the processor 2300 may execute instructions including x86 instructions, ARM instructions, special instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2300 may include registers for storing packed data, such as 64-bit wide MMX™ registers in microprocessors employing MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, which are available as both integer and floating-point registers, may operate on packed data elements accompanying Single Instruction, Multiple Data (SIMD) and Streaming SIMD Extensions (SSE) instructions.In at least one embodiment, 128-bit XMM registers related to SSE2, SSE3, SSE4, AVX, or beyond technologies (commonly referred to as "SSEx") may contain such packed data operands. In at least one embodiment, processor 2300 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inferencing.

[0339] In at least one embodiment, processor 2300 includes an in-order front-end ("front-end") 2301 for fetching instructions to be executed and preparing instructions to be used later in a processor pipeline. In at least one embodiment, front-end 2301 may include multiple units. In at least one embodiment, an instruction prefetcher 2326 fetches instructions from memory and passes them to an instruction decoder 2328, which in turn decodes or interprets instructions. In at least one embodiment, instruction decoder 2328, for example, decodes a received instruction into one or more operations, referred to as "micro-instructions" or "micro-operations" (also called "microOps" or "uOps" or "µOps"), that can be executed by a machine.In at least one embodiment, instruction decoder 2328 decomposes an instruction into opcode and corresponding data and control fields that can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, a trace cache 2330 may assemble decoded uOps into program-ordered sequences or traces in a uOps queue 2334 for execution. In at least one embodiment, when trace cache 2330 encounters a complex instruction, a microcode ROM 2332 provides uOps needed to complete an operation.

[0340] In at least one embodiment, some instructions may be converted into a single micro-op, while others may require multiple micro-ops to perform a complete operation. In at least one embodiment, instruction decoder 2328 may access microcode ROM 2332 to execute the instruction if more than four micro-ops are required to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-ops for processing in instruction decoder 2328. In at least one embodiment, an instruction may be stored in microcode ROM 2332 if a number of micro-ops are required to perform such an operation.In at least one embodiment, trace cache 2330 refers to a programmable logic array ("PLA") as an entry point to determine a correct microinstruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM 2332 according to at least one embodiment. In at least one embodiment, after microcode ROM 2332 finishes sequencing microinstructions for an instruction, front-end 2301 of a machine may resume fetching microinstructions from trace cache 2330.

[0341] In at least one embodiment, the out-of-order execution engine 2303 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic includes a series of buffers to smooth and reorder the flow of instructions to optimize performance as they traverse a pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 2303 includes, without limitation, an allocator / register renamer 2340, a memory uOps queue 2342, an integer / floating-point queue 2344, a memory scheduler 2346, a fast scheduler 2302, a slow / general FP scheduler 2304, and a simple FP scheduler 2306.In at least one embodiment, the fast scheduler 2302, the slow / general floating-point scheduler 2304, and the simple floating-point scheduler 2306 are also collectively referred to herein as "uOps scheduler 2302, 2304, 2306." In at least one embodiment, the allocator / register renamer 2340 allocates machine buffers and resources required by each uOps for its execution. In at least one embodiment, the allocator / register renamer 2340 renames logical registers to entries in a register file. In at least one embodiment, allocator / register renamer 2340 also assigns each uOps an entry in one of two uOps queues, the memory uOps queue 2342 for memory operations and the integer / floating point uOps queue 2344 for non-memory operations, which precedes the memory scheduler 2346 and the uOps schedulers 2302, 2304, 2306.In at least one embodiment, schedulers 2302, 2304, 2306 determine the readiness of a uOp for execution based on the readiness of its dependent input register operand sources and the availability of the execution resources required by the uOps to complete their operation. In at least one embodiment, fast scheduler 2302 may schedule in each half of a main clock cycle, while slow / general floating-point scheduler 2304 and simple floating-point scheduler 2306 may schedule once per main clock cycle of the processor. In at least one embodiment, schedulers 2302, 2304, 2306 arbitrate for dispatch ports to schedule uOps for execution.

[0342] In at least one embodiment, execution block 2311 includes, without limitation, an integer register file / bypass network 2308, a floating-point register file / bypass network (“FP register file / bypass network”) 2310, address generation units (“AGUs”) 2312 and 2314, fast arithmetic logic units (ALUs) (“fast ALUs”) 2316 and 2318, a slow arithmetic logic unit (“slow ALU”) 2320, a floating-point shift unit (“FP”) 2322, and a floating-point move unit (“FP move”) 2324. In at least one embodiment, integer register file / bypass network 2308 and floating-point register file / bypass network 2310 are also referred to herein as “register files 2308, 2310.”In at least one embodiment, the AGUSs 2312 and 2314, the fast ALUs 2316 and 2318, the slow ALU 2320, the floating-point ALU 2322, and the floating-point shift unit 2324 are also referred to herein as "execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324." In at least one embodiment, the execution block 2311 may include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units in any combination.

[0343] In at least one embodiment, register networks 2308, 2310 may be arranged between uOps schedulers 2302, 2304, 2306 and execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324. In at least one embodiment, integer register file / bypass network 2308 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2310 performs floating-point operations. In at least one embodiment, each of register networks 2308, 2310 may include, without limitation, a bypass network that can bypass just-completed results that have not yet been written to a register file or forward them to new dependent uOps. In at least one embodiment, register networks 2308, 2310 may exchange data with each other.In at least one embodiment, the integer register / bypass network 2308 may include, without limitation, two separate register files, one register file for 32 low-order data bits and a second register file for 32 high-order data bits. In at least one embodiment, the floating-point register file / bypass network 2310 may include, without limitation, 128-bit wide entries, since floating-point instructions typically have operands 64 to 128 bits wide.

[0344] In at least one embodiment, execution units 2312, 2314, 2316, 2318, 2320, 2322, 2324 may execute instructions. In at least one embodiment, register networks 2308, 2310 store integer and floating-point data operand values ​​required for microinstruction execution. In at least one embodiment, processor 2300 may include, without limitation, any number and combination of execution units 2312, 2314, 2316, 2318, 2320, 2322, 2324. In at least one embodiment, floating-point ALU 2322 and floating-point shift unit 2324 may perform floating-point, MMX, SIMD, AVX, and SSE operations or other operations, including special machine learning instructions. In at least one embodiment, the floating-point ALU 2322 may include, without limitation, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations.In at least one embodiment, instructions involving a floating-point value may be processed with floating-point hardware. In at least one embodiment, ALU operations may be forwarded to fast ALUs 2316, 2318. In at least one embodiment, fast ALUs 2316, 2318 may perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2320, as slow ALU 2320 may include, without limitation, integer execution hardware for long-latency operations, such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations may be performed by AGUs 2312, 2314.In at least one embodiment, the fast ALU 2316, the fast ALU 2318, and the slow ALU 2320 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2316, the fast ALU 2318, and the slow ALU 2320 can be implemented to support a variety of data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2322 and the floating-point shift unit 2324 can be implemented to support a variety of operands having bits of different widths, such as 128-bit packed data operands in conjunction with SIMD and multimedia instructions.

[0345] In at least one embodiment, the uOps schedulers 2302, 2304, 2306 dispatch dependent operations before a parent load has completed execution. In at least one embodiment where uOps may be speculatively scheduled and executed in the processor 2300, the processor 2300 may also include logic to handle memory misses. In at least one embodiment, when a data load fails in a data cache, there may be dependent operations in a pipeline that have left a scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks instructions that use incorrect data and reexecutes them. In at least one embodiment, dependent operations may be required to reexecute while independent operations are allowed to complete.In at least one embodiment, a scheduler and a replay mechanism of at least one embodiment of a processor may also be configured to intercept instruction sequences for text string comparison operations.

[0346] In at least one embodiment, the term "registers" may refer to onboard memory locations of the processor that may be used as part of instructions to identify operands. In at least one embodiment, the registers may be those that may be used from outside a processor (from a programmer's perspective). In at least one embodiment, the registers may not be limited to a particular circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein.In at least one embodiment, the registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, 32-bit integer data is stored in integer registers. A register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0347] In at least one embodiment, the processor 2300 or each core of the processor 2300 includes one or more pre-fetchers, one or more fetchers, one or more pre-decoders, one or more decoders for decoding data (e.g., instructions), one or more instruction queues for processing instructions (e.g., corresponding to operations or API calls), one or more micro-operation (µOP) caches for storing µOPs, one or more micro-operation (µOP) queues, an in-order execution engine, one or more load buffers, one or more store buffers, one or more reorder buffers, one or more fill buffers, an out-of-order execution engine, one or more ports, one or more shift and / or shifter units, one or more fused multiply accumulate units (FMA), one or more load / store units (“LSU”) for performing of load / store operations,corresponding to loading / storing data (e.g., instructions) to perform an operation (e.g., executing an API, an API call), one or more matrix multiplication-accumulation (MMA) units, and / or one or more shuffle units to perform any functions further described herein with respect to the processor 2300. In at least one embodiment, the processor 2300 may access, use, perform, or execute instructions corresponding to the call to an API.

[0348] In at least one embodiment, processor 2300 includes one or more ultrapath interconnects (UPIs), such as a point-to-point processor interconnect; one or more PCIe; one or more accelerators for accelerating computations or operations; and / or one or more memory controllers. In at least one embodiment, processor 2300 includes a shared last-level cache (LLC) coupled to one or more memory controllers, which may enable shared memory access across processor cores.

[0349] In at least one embodiment, the processor 2300 or a core of the processor 2300 has a mesh architecture in which processor cores, on-chip caches, memory controllers, and I / O controllers are organized in rows and columns, with wires and switches connecting them at each intersection to enable turns. In at least one embodiment, the processor 2300 has one or more higher bandwidth memory blocks (HMBs, e.g., HMBe) to store or cache data, for example, in Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM). In at least one embodiment, one or more components of the processor 2300 are interconnected via Compute Express Link (CXL) interconnects. In at least one embodiment, a memory controller uses a least recently used (LRU) approach to determine what is stored in a cache.In at least one embodiment, the processor 2300 includes one or more PCIe interfaces (e.g., PCIe 5.0).

[0350] Logic 715 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 715 are described herein in connection with Fig. 7A and / or 7B. In at least one embodiment, some or all of logic 715 may be integrated into execution block 2311 and other memory or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may utilize one or more of the ALUs shown in execution block 2311. Furthermore, weighting parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution block 2311 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0351] In at least one embodiment, the processor 2300 may be used to implement the system 100 (see Fig. 1), of the System 200 (see Fig. 2), of the System 300 (see Fig. 3), of the System 400 (see Fig. 4), of the System 500 (see Fig. 5) and / or the block diagram 600 (see Fig. 6) may be used. In at least one embodiment, at least a portion of the Fig. 23 depicted system(s) to implement one or more systems, techniques, functions and / or processes that are used in conjunction with Fig. 1-6. For example, in at least one embodiment, at least one Fig. 23 may be used to generate one or more 3D objects and / or 3D images in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-6 are described.

[0352] Fig. 24 shows a deep learning application processor 2400 according to at least one embodiment. In at least one embodiment, the deep learning application processor 2400 uses instructions that, when executed by the deep learning application processor 2400, cause the deep learning application processor 2400 to perform some or all of the processes and techniques described in this disclosure. In at least one embodiment, the deep learning application processor 2400 is an application-specific integrated circuit (ASIC). In at least one embodiment, the processor 2400 performs matrix multiplication operations either "hard-wired" in hardware as a result of the execution of one or more instructions, or both.In at least one embodiment, the deep learning application processor 2400 includes, without limitation, processing clusters 2410(1)-2410(12), inter-chip links ("ICLs") 2420(1)-2420(12), inter-chip controllers ("ICCs") 2430(1)-2430(2), second-generation high-width memory ("HBM2") 2440(1)-2440(4), memory controllers ("Mem CtrIrs") 2442(1)-2442(4), high-width memory physical layer ("HBM PHY") 2444(1)-2444(4), a management control CPU 2450, a serial peripheral interface, inter-integrated circuit, and general purpose input / output block ("SPI, I2C, GPIO") 2460, an express controller for the interconnection of peripheral components and a block for direct memory access ("PCIe Controller and DMA") 2470, and a sixteen-lane Express Port for the interconnection of peripheral components (PCI Express x 16") 2480.

[0353] In at least one embodiment, processing clusters 2410 may perform deep learning operations, including inference or prediction operations based on weighting parameters calculated using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2410 may include, without limitation, any number and type of processors. In at least one embodiment, deep learning application processor 2400 may include any number and type of processing clusters 2400. In at least one embodiment, inter-chip interconnects 2420 are bidirectional.In at least one embodiment, inter-chip links 2420 and inter-chip controllers 2430 enable multiple deep learning application processors 2400 to exchange information, including activation information resulting from the execution of one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2400 may include any number (incl...

Claims

[1] Processor comprising: one or more circuits for using one or more neural networks to generate one or more three-dimensional ("3D") objects based at least in part on reflection information. [2] The processor of claim 1, wherein the one or more neural networks are to generate the one or more 3D objects based at least in part on derived color information. [3] The processor of claim 1, wherein the one or more neural networks are to generate the one or more 3D objects based at least in part on derived depth information. [4] The processor of claim 1, wherein the one or more neural networks are to generate the one or more 3D objects based at least in part on a neural network for deriving depth information using a feature map, a specularity map, and an albedo map. [5] The processor of claim 1, wherein the one or more neural networks are to generate the one or more 3D objects based at least in part on a derived depth map, albedo map, and specularity map. [6] The processor of claim 1, wherein the one or more neural networks are to generate the one or more 3D objects based at least in part on one or more jointly trained neural networks to derive a depth map, an albedo map, and a specularity map. [7] The processor of claim 1, wherein the one or more neural networks generate the one or more 3D objects based at least in part on a feature map generated from one or more images captured by a monoscopic device. [8] System comprising: one or more processors to cause one or more circuits to use one or more neural networks to generate one or more three-dimensional ("3D") objects based at least in part on reflection information. [9] The system of claim 8, wherein the one or more neural networks are to generate the one or more 3D objects based at least in part on derived color information. [10] The system of claim 8, wherein the one or more neural networks are to generate the one or more 3D objects based at least in part on derived depth information. [11] The system of claim 8, wherein the one or more neural networks are to generate the one or more 3D objects based at least in part on a neural network for deriving depth information using a feature map, a specularity map, and an albedo map. [12] The system of claim 8, wherein the one or more neural networks are to generate the one or more 3D objects based at least in part on a depth map, an albedo map, and a specularity map. [13] The system of claim 8, wherein the one or more neural networks are to generate the one or more 3D objects based at least in part on jointly trained neural networks to derive a depth map, an albedo map, and a specularity map. [14] The system of claim 8, wherein the one or more neural networks are to generate the one or more 3D objects based at least in part on a feature map generated from one or more images captured by a monoscopic camera device. [15] Method comprising: Generating one or more three-dimensional ("3D") objects based, at least in part, on reflection information using one or more neural networks. [16] The method of claim 15, further comprising using the one or more neural networks to generate the one or more 3D objects based at least in part on derived color information. [17] The method of claim 15, further comprising using the one or more neural networks to generate the one or more 3D objects based at least in part on derived depth information. [18] The method of claim 15, wherein the one or more neural networks generate the one or more 3D objects based at least in part on depth information derived using a feature map, a specularity map, and an albedo map. [19] The method of claim 15, further comprising using the one or more neural networks to generate the one or more 3D objects based at least in part on a depth map, an albedo map, and a specularity map. [20] The method of claim 15, further comprising jointly training a first neural network for deriving a depth map, a second neural network for deriving an albedo map, and a third neural network for deriving a specularity map.

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