Latency-controlled shared buffer algorithm

Abstract

A network device, a network interface controller, and a switch are provided. In one example, a shared buffer includes a plurality of sections, one or more ports read data from and write data to the shared buffer, and control circuitry correlates output ports with available sections from the plurality of sections that are as close as possible to a respective output port.

Description

AREA OF DISCLOSURE

[0001] This disclosure relates generally to networks, and more particularly to network devices, switches, and methods of operating the same. BACKGROUND

[0002] Switches and similar network devices are a core component of many communications, security, and computer networks. Switches are commonly used to connect multiple devices, device types, networks, and network types.

[0003] Devices, including but not limited to personal computers, servers, or other types of data processing devices, can be interconnected via network devices such as switches. These interconnected units form a network that enables data communication and shared resource use among the nodes. SUMMARY

[0004] The invention is defined by the claims. To illustrate the invention, aspects and embodiments are described herein, which may or may not fall within the scope of the claims.

[0005] In accordance with one or more embodiments described herein, a computer system, such as a switch, may enable a plurality of systems, such as switches, servers, personal computers, and other computing devices, to communicate over a network. Multiple blocks or memories of the computer system may act as a shared buffer, allowing multiple ports of the computer system to share buffer space.

[0006] Each port of the computer system may be connected to an input queue of packets and / or data in other formats received through the port. Each port may store the data in one or more memory blocks of a shared buffer memory selected based on a general algorithm, local RAM usage, physical location (e.g., location relative to an associated output port for the data), shared buffer configuration / schemes, etc. A shared buffer control and balancing system may be used to control which port writes to and / or reads from which particular block of the shared buffer.

[0007] The shared buffer rebalancing capabilities described herein enable the dynamic binding of input ports to sections of a shared buffer to implement a shared buffer abstraction. In embodiments, an input port is dynamically bound to one or more available sections of the shared buffer that are closest to the output port associated with the data to be transmitted. The latency-controlled shared buffer algorithm of the present disclosure improves the rebalancing algorithm by taking into account the "locality" or distance of the forwarding (e.g.,the physical location of an output port or group of output ports Tq / Set-of-Tqs with respect to a corresponding input port) and redistributes it to the "nearest available" section(s) of a shared buffer between the input port and a destination input port Tq / Set-Of-Tq.

[0008] As described here, traffic can be selectively routed through one or more specific ports of a computer system based on a variety of factors (e.g., fairness, minimum buffer requirements, quality of service (QoS) requirements, prioritization of important data flows, congestion control, etc.). By evaluating factors and changing the weighting of ports or queues, the switching hardware of a computer system can be enabled to route traffic effectively through the computer system.

[0009] The present disclosure describes a system and method that enables a switch or other computer system to correlate output ports with the next available portions of a shared buffer. Embodiments of the present disclosure aim to improve forwarding latency and other issues by implementing an improved buffer allocation approach. The buffering approach illustrated and described herein may be applied to a switch, a router, or any other suitable type of network device, either known or yet to be developed.

[0010] In one illustrative example, a system is disclosed comprising a shared buffer, the shared buffer comprising a plurality of sections; and a plurality of ports, each port of the plurality of ports comprising a forwarding database to correlate an output port with at least one of the plurality of sections of the shared buffer.

[0011] In another example, a network device is disclosed that includes a shared buffer, the shared buffer including a plurality of sections; and a plurality of ports, each port of the plurality of ports comprising a forwarding database to correlate an output port with at least one of the plurality of sections of the shared buffer.

[0012] In another example, a method is disclosed that includes writing packets to a shared buffer, the shared buffer comprising a plurality of sections; and forwarding the packets using a plurality of ports, each port of the plurality of ports having a forwarding database correlating an output port with at least one of the plurality of sections of the shared buffer.

[0013] Each of the above example aspects includes routing a packet to an available buffer section of the plurality of sections that is as close as possible to an output port associated with the packet, based on a shared buffer algorithm and a forwarding database, and a nearest available shared buffer section is different from a shared buffer section closest to the output port associated with the packet. In other words, buffer allocation fairness between ports is maintained, and packets are routed to an available buffer section closest to the associated output port.

[0014] Each of the above example aspects includes that the multiple sections of the shared buffer are distributed across different physical locations within a device, and that a packet is directed to a portion of the multiple sections that is available and as close as possible to an output port associated with the packet.

[0015] Each of the example aspects above involves determining each forwarding database based at least in part on reducing latency and maintaining minimum shared buffer requirements.

[0016] Each of the above example aspects includes that each input port or group of input ports contains a forwarding database, and each forwarding database maps each input port to an available portion of the shared buffer as close as possible to a respective output port.

[0017] Each of the above example aspects includes each terminal of the plurality of terminals being a target output (Tq) and a target input (Rq).

[0018] Each of the above example aspects includes the control circuit selectively correlating an output terminal with at least one of the plurality of portions of the shared buffer. Each of the above

[0019] Each of the above example aspects includes the shared buffer being one of a plurality of shared buffers. Example aspects include storing data received from a first port of the one or more ports in the shared buffer before being transmitted from a second port of the one or more ports.

[0020] A network device, a network interface controller, and a switch are provided. In one example, a shared buffer includes a plurality of sections, one or more ports read data from and write data to the shared buffer, and control circuitry correlates output ports with available sections from the plurality of sections as close as possible to a respective output port.

[0021] Any feature of one aspect or embodiment may be applied to other aspects or embodiments, in any suitable combination. In particular, any feature of a method aspect or embodiment may be applied to a device aspect or embodiment, and vice versa.

[0022] Further features and advantages are described here and can be seen from the following description and figures. BRIEF DESCRIPTION OF THE DIFFERENT VIEWS OF THE DRAWINGS

[0023] The present disclosure is described in conjunction with the accompanying figures, which are not necessarily drawn to scale: Fig. 1 is a block diagram illustrating an exemplary configuration of a switch in accordance with at least some embodiments of the present disclosure; Fig. 2 is a block diagram illustrating an exemplary configuration of a shared buffer in accordance with at least some embodiments of the present disclosure; Fig. 3 is a block diagram illustrating an exemplary configuration of a shared buffer in accordance with at least some embodiments of the present disclosure; Fig. 4 is a block diagram illustrating an exemplary configuration of a network of switches according to at least some embodiments of the present disclosure; and Fig. 5 is a flowchart showing an illustrative configuration of a method according to at least some embodiments of the present disclosure.

[0024] The same reference numbers and designations in the various drawings indicate the same elements. DETAILED DESCRIPTION

[0025] The following description contains only exemplary embodiments and is not intended to limit the scope, applicability, or form of the claims. Rather, the following description is intended to provide a guide to the person skilled in the art for implementing the described embodiments. It is understood that various changes in the function and arrangement of the elements may be made without departing from the spirit and scope of the appended claims.

[0026] From the following description and for reasons of computational efficiency, it is clear that the components of the system can be arranged at any suitable location within a distributed network of components without affecting the operation of the system.

[0027] Furthermore, the various connections connecting the elements may be cables, printed circuit boards, or wireless connections, or any combination thereof, or any other suitable element known or later developed capable of delivering and / or transmitting data to and from the connected elements. Transmission media may include, for example, any suitable electrical signal carrier, including coaxial cable, copper wire and optical fiber, electrical traces on a printed circuit board (PCB), or the like.

[0028] As used herein, the terms "at least one," "one or more," "or," and "and / or" are indefinite terms that can be used both conjunctively and disjunctively. For example, each of the terms "at least one of A, B, and C," "at least one of A, B, or C," "one or more of A, B, and C," "one or more of A, B, or C," "A, B, and / or C," and "A, B, or C" means A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

[0029] The term "automatic" and variations thereof, as used herein, refers to any suitable process or operation that is performed without substantial human input when the process or operation is performed. However, a process or operation can be automatic even if performance of the process or operation requires tangible or intangible human input if the input is received before the process or operation is performed. Human input is considered substantial if it affects the performance of the process or operation. Human input that consents to the performance of the process or operation is not considered "substantial."

[0030] The terms “determine,” “calculate,” and “compute,” and their variations, are used interchangeably herein and include any appropriate methodology, process, procedure, or technique.

[0031] Various aspects of the present disclosure are described herein with reference to drawings that are schematic representations of idealized configurations.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is further understood that terms as defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant prior art and this disclosure.

[0033] As used herein, the singular forms "a," "an," and "the" include the plural forms unless the context clearly indicates otherwise. It is further understood that the terms "comprise," "comprises," and / or "including," when used in this specification, specify the presence of certain features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The term "and / or" includes all combinations of one or more of the listed items.

[0034] In the Fig. 1-5, various systems and methods for managing a shared buffer in a computer system are described. The shared buffer management concepts illustrated and described herein can be applied to any type of computer system capable of receiving and / or transmitting data, regardless of whether the computer system includes one or more ports. Such a computer system may be a switch, but of course, any type of computer system may be used. The term "packet" as used herein should be understood to mean any suitable discrete amount of digitized information. The data stored in a shared buffer may be in the form of a single packet, multiple packets, or unpacketized data, without departing from the scope of the present disclosure.Furthermore, it should be noted that the described features and functions of a centralized architecture can also be applied in a distributed architecture or vice versa.

[0035] In accordance with one or more embodiments described herein, a switch 103, as shown in Fig. 1, a variety of systems, such as switches, servers, personal computers, and other data processing devices, communicate over a network. Although the data processing device in Fig. 1 is described here as switch 103, the data processing device in Fig. 1 may be any data processing device capable of receiving data via ports 106a-d. Such a switch 103, as described herein, may be, for example, a switch or any computing device comprising a plurality of ports 106a-d for connecting nodes in a network.

[0036] Ports 106a-d of switch 103 may act as communication endpoints, allowing switch 103 to manage multiple concurrent network connections to one or more nodes. Each port 106a-d may be used to receive data associated with one or more flows or communication sessions. Upon receiving data, each port 106a-d may be capable of writing the data to a cell 121a-d within a shared buffer 112. Ports 106a-d of switch 103 may be physical connection points that allow network cables to connect switch 103 to one or more network nodes. The connection may be established using any known or yet-to-be-identified communication protocol (e.g., Ethernet, InfiniBand (IB), NVLink, etc.).

[0037] Once the packets (or data in other formats) are received from ports 106a-d of switch 103, the packets may be temporarily stored in shared buffer 112. Shared buffer 112 may comprise a temporary storage space within switch 103. Physically, the storage space of shared buffer 112 may comprise a plurality of cells 121a-d or blocks, each of which may be, for example, a RAM (random access memory) chip. Shared buffer 112 may act as an intermediate storage area that allows switch 103 to manage and control the forwarding of packets from buffer 112. Packet buffering allows a switch to account for latency in forwarding decisions, egress congestion, scheduling considerations (e.g., QoS), etc.

[0038] The shared buffer may have a specific memory size, e.g., 156 MB, 256 MB, etc., and may include a plurality of RAM devices. Each RAM device may be a type of computer memory that can be used to store data, e.g., packets received via ports 106a-d. The smallest unit of RAM may be a cell 121a-d, and each cell stores one bit or byte of data. Each cell 121a-d in shared buffer 112 may include a transistor and a capacitor. The transistor may act as a switch, allowing the switch's control circuitry to read the capacitor or change its state. The capacitor may operate to hold one bit of information, either a 0 or a 1.

[0039] Shared buffer 112 may include cells located anywhere within switch 103. Cells 121a-d may, for example, be portions of arrays or memory blocks, e.g., 1 MB per block. Memory blocks may include cells 121a-d arranged in rows and columns.

[0040] The shared buffer 112 may consist of a RAM device organized into one or more cell arrays.

[0041] Each cell 121a-d can be assigned a specific address, which can be used by the components of switch 103 to access each individual cell 121a-d or to instruct other components to access it. When the processor needs to read or write a specific bit of data, it sends the corresponding memory address to RAM. In some implementations, each block of shared buffer 112 can be assigned an address, and the components can refer to a specific block generally, as opposed to the more specific cell reference. In some embodiments, the address of a cell (e.g., a RAM location) 121a-d can indicate which block the cell 121a-d is located in, as well as a row and column for the cell 121a-d within the block.In this way, a processor 115, a control system for the shared buffer 109, and / or another component of the switch 103 may be enabled to reference a particular cell 121a-d and / or all cells of a particular block of the shared buffer 112.

[0042] In some implementations, the cells 121a-d of the shared buffer 112 may form a single, fragmented logical unit. To a port 106a-d, the shared buffer 112 may appear as a single storage unit. Each port 106a-d may write data to one of the cells 121a-d in the shared buffer memory 118. Which cell 121a-d a particular port 106a-d writes a received packet to may be controlled by a shared buffer control system 109. For example, the shared buffer control system 109 may instruct each port 106a-d to write to a particular cell 121a-d. In some implementations, the shared buffer control system 109 may be capable of correlating particular cells 121a-d and / or particular blocks of the shared buffer 112 with output ports.In embodiments, the cells 121a-d and the output terminals are correlated based on “locality” or relative position to each other.

[0043] To read data from a cell 121a-d, the control circuitry of switch 103 can cause the transistor to drain the capacitor's charge to a bit line. Buffered packets can be organized into queues in some implementations, e.g., in conjunction with a dedicated queue per output port while the packets await transmission.

[0044] The shared buffer control system 109 may be in communication with or controlled by a processor 115. For example, the switch 103 may include a processor 115, such as a central processing unit (CPU), a microprocessor, or any circuit or device capable of reading instructions from the memory 118 and performing actions. The processor 115 may execute software instructions to control the operation of the switch 103.

[0045] The processor 115 may act as the central processing unit of the switch 103 and perform operational functions of the switch 103. The processor 115 may communicate with other components of the switch 103, including the shared buffer 109 control system, for example, to manage and perform computational operations.

[0046] Processor 115 may be configured to perform a wide range of computing tasks. The capabilities of processor 115 may include executing program instructions, managing data within the system, and controlling the operation of other hardware components, such as the shared buffer 109 control system. Processor 115 may be single-core or multi-core and may include one or more processing units depending on the specific design and requirements of switch 103. The design of processor 115 may enable instruction execution, data processing, and overall system management, which may enhance the performance and utility of switch 103 in various applications.In addition, the processor 115 can be programmed or customized to perform specific tasks and operations according to application requirements, potentially enhancing the versatility and customizability of the switch 103.

[0047] The switch 103 may also include one or more memory components 118 in which data, such as a shared buffer control and balancing algorithm 124, may be stored. The memory 118 may be configured to communicate with the processor 115 of the switch 103. Communication between the memory 118 and the processor 115 may enable various operations, including, but not limited to, data exchange, instruction execution, and memory management. In accordance with the implementations described herein, the memory 118 may be used to store data, such as the shared buffer control and balancing algorithm 124 related to the utilization of the cells 121a-d of the shared buffer 112 of the switch 103.

[0048] The memory 118 may consist of various physical components, depending on their specific type and design. The memory 118 may include one or more memory cells capable of storing data in the form of binary information. Such memory cells may consist of transistors, capacitors, or other suitable electronic components, depending on the memory type, e.g., dynamic random access memory (DRAM), static random access memory (SRAM), or flash memory. To enable data transfer and communication with other parts of the switch 103, the memory 118 may also include data lines or buses, address lines, and control lines, which may be Fig. 1 are not shown. These physical components may together form the memory 118 and / or the shared buffer 112 and contribute to their ability to store and manage data, such as the shared buffer control and the balancing algorithm 124

[0049] The shared buffer control and balancing algorithm 124, which may be stored in memory 118, may include information about various aspects of the usage of the shared buffer 112. Such information may include, among other things, data about the current buffer usage and the location of available sections. For example, the shared buffer control and balancing algorithm 124 may include the current number of active cells 121a-d, the total number of cells 121a-d, the current number of inactive cells 121a-d, and / or other data, as described in more detail below.

[0050] The shared buffer control and balancing algorithm 124 may be accessed and used by the processor 115 and / or the shared buffer control system 109 to manage the shared buffer and ports 106a-d. For example, the processor 115 could use the shared buffer control and balancing algorithm 124 to manage the network traffic received by ports 106a-d by determining which cells are closest to the output ports for particular portions of the traffic, as described in more detail below. Therefore, the memory 118, in possible conjunction with the processor 115, may play a critical role in optimizing the utilization and performance of the ports 106a-d of the switch 103.

[0051] In one or more embodiments of the present disclosure, a processor 115 or the shared buffer control system 109 of a switch 103 may perform polling operations to retrieve data regarding the activity of cells 121a-d, for example, by polling cells 121a-d, shared buffer 112, shared buffer control and balancing algorithm 124, shared buffer control system 109, and / or other components of switch 103, as described herein. As used herein, polling may involve processor 115 periodically or continuously polling or requesting data from shared buffer 109, or may involve processor 115 or shared buffer control system 109 periodically or continuously polling or requesting data from cells 121a-d or memory 118.In some implementations, the query process may involve processor 115 sending a request to shared buffer control system 109 to retrieve the desired data. Upon receiving the request, shared buffer control system 109 may assemble the requested data and return it to processor 115.

[0052] As in Fig. 2, similar to ports 106a-d, the input ports 203a and the output ports 203b of a switch 203 can write / read data to / from a shared buffer 212. Each port 203a or 203b can write / read to a specific cell 121 of the shared buffer 212 based on instructions received from a shared buffer control system 109. In other words, each input port 203a can be dynamically bound to available section(s) 121 of the shared buffer 112 closest to the output port 203b associated with the data to be transferred.Instead of each input port 203a always writing data to specific portion(s) of shared buffer 121, the correlations between input ports 203a and portions 121 are dynamic and can be adjusted based on availability (occupancy of each portion 121), the destination for the data, etc. For example, input port 1 may have data for output port 1 and output port 8, so that input port 1 can be dynamically bound to the closest available portions 121 to output port 1 and output port 8. At other times, input port 1 may have data for output port 3 and output port 6, so that input port 1 can be dynamically bound to the closest available portions 121 of output port 3 and output port 6.Ports 203a-b may also report buffer usage to shared buffer control system 109. Buffer usage information may be used to rebalance shared buffer 212 via rebalance process 200.

[0053] As described herein, data, such as packets, may be selectively sent to cells 121 of shared buffer 212 via one or more of ports 203a based on a variety of factors. A shared buffer control system 109 of switch 203 may include one or more application-specific integrated circuits (ASICs) or microprocessors to perform tasks such as determining which cell 121 a received packet should be sent to. Shared buffer control system 109 may include various components, such as port controllers that manage the operation of each port, network interface cards that facilitate data transmission, and internal data paths that control the flow of data within switch 203.The shared buffer control system 109 may also include memory elements for temporarily storing data and management software for controlling the operation of the switch 203. Such a configuration may enable the shared buffer control system 109 to accurately track shared buffer usage and provide data to the processor 115 of the switch 103 upon request.

[0054] The shared buffer control system 109 may control the management and balancing of the shared buffer 212 by determining which port writes to each block of the shared buffer. The decision as to which port 203 writes to which cell 121 of the shared buffer 112 may be based on factors such as the occupancy of the shared buffer 112, location, quotas, required pool size, µBurst conditions, etc.

[0055] As in Fig. 3, data arriving at input port 303a (diagonal lines) may be destined for output port 303b (with corresponding diagonal lines). Input port 303a includes a forwarding database 303c (e.g., a forwarding table) that specifies the nearest available sections 121a-c of shared buffer 312 for output port 303b. As shown in the figure, section 121d is closest to output port 303b, but the gray-shaded sections 121 are used / unavailable sections of shared buffer 312. In addition to forwarding databases 303c, flows are generally routed based on a control plan that includes shared buffer algorithms, forwarding tables, and dynamic / static or complex stateful rules.Each forwarding database 303c is implemented to map the corresponding best possible section (e.g., the nearest available) of the shared buffer 312 for each output port 303b.

[0056] As in Fig. 4, a switch 103a may be connected to a number of nodes, such as other switches 103b, 103c, and / or other computing devices 403a, 403b, forming a network. The systems and methods described herein may be executed by one switch 103a-c in a network of interconnected nodes. Multiple switches 103a-c and / or other computing devices 403a, 403b may be interconnected in a variety of topologies, such as a star, ring, or mesh, depending on the specific requirements and resiliency required for the network. For example, in a star topology, a plurality of switches may be connected to a central switch, while in a ring topology, each switch may be connected to two other switches in a closed loop. In a mesh topology, each switch may be connected to any other switch in the network.These robust structures provide a degree of redundancy because data is transmitted over multiple paths, ensuring network functionality can be maintained even if a switch fails.

[0057] Each switch 103a-c may be a switch 103 as shown in Fig. 1, or any type of data processing device. Each port 106a-l of each switch 103a-c may be connected to the same or a different node. In the Fig. In the example illustrated in Figure 4, a first switch 103a is connected via two ports 106a-b to two ports 106g-h of a second switch 103b and via two ports 106c-d to two ports 106i-j of a third switch 103c. Each of the second and third switches 103b-c is connected to other computing devices 403a-b via two ports 106e, 106f, 106k, 106l. Each of the switches 103a-c may include a corresponding shared buffer 112a-c. When a packet is received via a port 106a-l of a switch 103a-c, the packet may be stored in a shared buffer 112a-c of the respective switch 103a-c.

[0058] As in Fig. 5, a method 500 as described herein may be performed by a switch 103 or other computing device according to one or more of the embodiments described herein. The method 500 includes identifying information about the usage of a shared buffer, determining available portions of the shared buffer, and correlating available portions of the shared buffer with output ports by location (e.g., correlating available portions closest to a particular output port). Although the features of the method 500 are described as being performed by a shared buffer control system 109 of a switch 103, 203, and 303, it should be understood that one or more of the functions may be performed by a processor 115, a balancing system, orreconciliation system 300 or other computing device associated with or in communication with a switch 103, 203, and 303.

[0059] In some implementations, the method may be performed by a network device such as a NIC, a switch, a control circuit of a switch, or any computing device having a shared buffer. Data received by a first port of a plurality of ports may, in some implementations, be stored in a shared buffer before being transmitted by a second port of the one or more ports. Although the description provided herein refers to ports using a shared buffer, any computing system element capable of writing data to memory may use a shared buffer in the same or similar manner as described herein. Therefore, the systems and methods described herein may be used by any device that uses a shared buffer.Also, the shared buffer may be one of multiple shared buffers. A controller, such as a microprocessor, an ASIC, or other type of computing element, may selectively enable and disable memory cells of each of the shared buffers according to the method 500 described herein.

[0060] In step 503, the occupancy of a shared buffer 112 of switch 103 may be determined by shared buffer control system 109. For example, shared buffer control system 109 may query switch 103 about the occupancy of shared buffer 112. This may include the occupancy / availability of each cell / share 121.

[0061] Determining the occupancy of the shared buffer 112 of the switch 103 may include querying the occupancy of the shared buffer 112. Querying the occupancy may involve a processor 115 or a control system 109 for the shared buffer within the switch 103 repeatedly querying or checking the current state of the shared buffer 112 to measure how much of the capacity is being used at a given time. The query process may occur at regular intervals or be event-driven, i.e., triggered by certain conditions or changes in the state of the switch. The query process may lead to a quantitative measurement of the buffer occupancy, e.g., the occupancy of the individual sections 121 of the shared buffer 112.

[0062] In step 506, a plurality of output ports are correlated with a plurality of sections of a shared buffer. For example, the shared buffer control system 109 correlates the output ports 303b with the available sections 121 of the shared buffer 112 that are closest to the respective output port 303b.

[0063] In step 509, one or more packets are received at an input port 303a for forwarding.

[0064] In step 512, the shared buffer control system 109 or processor 115 identifies the nearest available section 121 of the shared buffer 112 for the output port 303b associated with the received packet(s). In embodiments, a forwarding database 303c associated with the input port 303a is used to determine which section 121 of the shared buffer 112 the packet(s) should be written to.

[0065] In step 515, the shared buffer control system 109 or the processor 115 sends the received packet(s) to the identified section(s) 121 of the shared buffer 112. For example, the packets are written to one of the sections 121a-c.

[0066] In step 518, the shared buffer control system 109 or the processor 115 forwards the received packet(s) through the associated output port.

[0067] In one or more embodiments of the present disclosure, the method 500 may return to 503 after execution and begin the process again. In some embodiments, the repetition of the method 500 may occur without delay. In such cases, once completed, the method 500 may immediately begin the next iteration. This arrangement could enable continuous execution of the method 500. In some embodiments, a pause for a specified period of time may be inserted between successive iterations of the method 500. The duration of the pause may be set depending on the operational needs of the method, e.g., by a user.

[0068] The present disclosure encompasses methods with less than all of the Fig. 5 (and the corresponding description of the procedure) as well as procedures that include additional steps beyond those in Fig. 5 (and the corresponding description of the method). The present disclosure also encompasses methods comprising one or more steps from the methods described herein and one or more steps from any other method described herein.

[0069] Embodiments of the present disclosure include a system comprising: a shared buffer, wherein the shared buffer comprises a plurality of sections; and a plurality of ports, wherein each port of the plurality of ports comprises a forwarding database to correlate an output port with at least one of the plurality of sections of the shared buffer.

[0070] Embodiments of the present disclosure also include a network device with shared buffer capabilities, comprising: a shared buffer, wherein the shared buffer comprises a plurality of sections; and a plurality of ports, wherein each port of the plurality of ports comprises a forwarding database to correlate an output port with at least one of the plurality of sections of the shared buffer.

[0071] Embodiments of the present disclosure also include a method for rebalancing a shared buffer, comprising: writing packets to a shared buffer, wherein the shared buffer comprises a plurality of sections; and forwarding the packets using a plurality of ports, wherein each port of the plurality of ports has a forwarding database correlating an output port with at least one of the plurality of sections of the shared buffer.

[0072] Aspects of the above system, apparatus, switch, and / or method include routing a packet to a portion of the shared buffer based at least in part on the forwarding database to an available portion among the plurality of portions that is as close as possible to an output port associated with the packet, and wherein a nearest available portion of the shared buffer is different from a portion of the shared buffer that is closest to the output port associated with the packet.

[0073] Aspects of the above system, apparatus, switch, and / or method include where the multiple portions of the shared buffer are distributed among different physical locations within a device, and where a packet is directed to a portion of the multiple portions that is available and as close as possible to an output port associated with the packet.

[0074] Aspects of the above system, apparatus, switches, and / or methods include determining each forwarding database based at least in part on reducing latency and maintaining minimum shared buffer requirements.

[0075] Aspects of the above system, apparatus, switch, and / or method include each forwarding database mapping each output port to an available portion of the shared buffer as close as possible to a respective output port.

[0076] Aspects of the above system, apparatus, switch, and / or method include each port of the plurality of ports being a target output port (Tq) and a target input port (Rq).

[0077] Aspects of the above system, apparatus, switch, and / or method include the control circuit selectively correlating an output port with at least one of the plurality of portions of the shared buffer.

[0078] Aspects of the above system, apparatus, switch, and / or method include storing data received from a first port of the one or more ports in the shared buffer before being transmitted from a second port of the one or more ports.

[0079] Aspects of the above system, apparatus, switch, and / or method include the shared buffer being one of a plurality of shared buffers.

[0080] Each feature described herein may be claimed in combination with one or more other features described herein, regardless of whether the features originate from the same described embodiment.

[0081] In the description, specific details have been set forth in order to provide a thorough understanding of the embodiments. However, it will be apparent to one skilled in the art that the embodiments may be practiced without these specific details. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be set forth without unnecessary detail in order not to obscure the embodiments.

[0082] While illustrative embodiments of the disclosure have been described in detail herein, it is to be understood that the inventive concepts may be embodied and utilized in other ways, and the appended claims are intended to be construed to include such variations unless limited by the prior art.

[0083] It is to be understood that the aspects and embodiments described above are exemplary only and that changes in detail may be made within the scope of the claims.

[0084] Each device, method, and feature disclosed in the description and (where appropriate) in the claims and drawings may be provided independently or in any suitable combination.

[0085] The reference numbers contained in the claims are for illustrative purposes only and do not limit the scope of the claims.

[0086] The disclosure of this application also includes the following numbered sentences: Sentence 1. A system consisting of: a shared buffer, the shared buffer comprising a plurality of sections; and a plurality of ports, each port of the plurality of ports comprising a forwarding database to correlate an output port with at least one of the plurality of portions of the shared buffer. Sentence 2: The system of sentence 1, wherein a packet is routed to a portion of the shared buffer based at least in part on the forwarding database to an available portion of the plurality of portions that is as close as possible to an output port associated with the packet, and wherein a nearest available portion of the shared buffer is different from a portion of the shared buffer that is closest to the output port associated with the packet. Clause 3: The system of clause 1, wherein the plurality of sections of the shared buffer are distributed among different physical locations within a device, and wherein a packet is directed to a portion of the plurality of sections that is available and as close as possible to an output port associated with the packet. Sentence 4: The system of sentence 3, wherein the device comprises a network switch. Sentence 5: The system of Sentence 1, wherein each forwarding database is determined based at least in part on reducing latency and maintaining minimum shared buffer requirements. Clause 6. The system of clause 1, wherein each forwarding database maps each output port to an available portion of the shared buffer that is as close as possible to a respective output port. Theorem 7: The system of Theorem 1, wherein each terminal of the plurality of terminals is a destination for the output (Tq) and a destination for the input (Rq). Sentence 8: A network device with shared buffering capabilities, the network device comprising: a shared buffer, the shared buffer comprising a plurality of sections; and a plurality of ports, each port of the plurality of ports comprising a forwarding database to correlate an output port with at least one of the plurality of portions of the shared buffer. Sentence 9: The network device of sentence 8, wherein a packet is routed to a portion of the shared buffer based at least in part on the forwarding database to an available portion of the shared buffer that is as close as possible to an output port associated with the packet, and wherein a nearest available portion of the shared buffer is not a portion of the shared buffer that is closest to the output port associated with the packet. Clause 10: The network device of clause 8, wherein the plurality of portions of the shared buffer are distributed among different physical locations within a device, and wherein a packet is directed to a portion of the shared buffer that is available and as close as possible to an output port associated with the packet. Sentence 11: The network device of Sentence 8, wherein each forwarding database is determined based at least in part on reducing latency and maintaining minimum shared buffer requirements. Clause 12: The network device of Clause 8, wherein each forwarding database maps each output port to an available portion of the shared buffer that is as close as possible to a respective output port. Sentence 13: The network device according to sentence 8, wherein the network device comprises a network switch. Sentence 14: The network device according to Sentence 8, wherein each terminal of the plurality of terminals is a target output (Tq) and a target input (Rq). Sentence 15: A method for shared buffer reconciliation, the method comprising: Writing packets to a shared buffer, the shared buffer containing a plurality of sections; and Forwarding the packets using a plurality of ports, each port of the plurality of ports having a forwarding database correlating an output port with at least one of the plurality of portions of the shared buffer. Sentence 16: The method of sentence 15, wherein a packet is routed to a portion of the shared buffer based at least in part on the forwarding database to an available portion of the shared buffer that is as close as possible to an output port associated with the packet, and wherein a nearest available portion of the shared buffer is not a portion of the shared buffer that is closest to the output port associated with the packet. Clause 17: The method of clause 15, wherein the plurality of portions of the shared buffer are distributed across different physical locations within a device, and wherein a packet is directed to a portion of the shared buffer that is available and as close as possible to an output port associated with the packet. Sentence 18: The method of sentence 17, wherein the device comprises a network switch. Sentence 19: The method of Sentence 15, wherein each forwarding database is determined based at least in part on reducing latency and maintaining minimum shared buffer requirements. Clause 20: The method of Clause 15, wherein each forwarding database maps each output port to an available portion of the shared buffer that is as close as possible to a respective output port.

Claims

[1] System comprising: a shared buffer, the shared buffer comprising a plurality of sections; and a plurality of ports, each port of the plurality of ports comprising a forwarding database to correlate an output port with at least one of the plurality of portions of the shared buffer. [2] The system of claim 1, wherein a packet is routed to a portion of the shared buffer based at least in part on the forwarding database to an available portion of the plurality of portions that is as close as possible to an output port associated with the packet, and wherein a nearest available portion of the shared buffer is different from a portion of the shared buffer that is closest to the output port associated with the packet. [3] The system of claim 1 or 2, wherein the plurality of sections of the shared buffer are distributed across different physical locations within a device, and wherein a packet is directed to a section of the plurality of sections that is available and as close as possible to an output port associated with the packet. [4] The system of claim 3, wherein the device comprises a network switch. [5] The system of any of claims 1 to 4, wherein each forwarding database is determined based at least in part on reducing latency and maintaining minimum shared buffer requirements. [6] A system according to any one of claims 1 to 5, wherein each forwarding database maps each output port to an available portion of the shared buffer as close as possible to a respective output port. [7] The system of any one of claims 1 to 6, wherein each terminal of the plurality of terminals is a target output (Tq) and a target input (Rq). [8] A network device with shared buffering capabilities, the network device comprising: a shared buffer, the shared buffer comprising a plurality of sections; and a plurality of ports, each port of the plurality of ports comprising a forwarding database for correlating an output port with at least one of the plurality of portions of the shared buffer. [9] The network device of claim 8, wherein a packet is routed to a portion of the shared buffer based at least in part on the forwarding database to an available portion of the shared buffer that is as close as possible to an output port associated with the packet, and wherein a nearest available portion of the shared buffer is not a portion of the shared buffer that is closest to the output port associated with the packet. [10] A network device according to claim 8 or 9, wherein the plurality of portions of the shared buffer are distributed across different physical locations within a device, and wherein a packet is directed to a portion of the shared buffer that is available and as close as possible to an output port associated with the packet. [11] The network device of claim 8, 9 or 10, wherein each forwarding database is determined based at least in part on reducing latency and maintaining minimum shared buffer requirements. [12] A network device according to claims 8 to 11, wherein each forwarding database maps each output port to an available portion of the shared buffer that is as close as possible to a respective output port. [13] The network device according to claim 8 to 12, wherein the network device comprises a network switch. [14] The network device according to claim 8 to 13, wherein each port of the plurality of ports is a destination output (Tq) and a destination input (Rq). [15] A method for shared buffer matching, the method comprising: Writing packets to a shared buffer, the shared buffer containing a plurality of sections; and Forwarding the packets using a plurality of ports, each port of the plurality of ports having a forwarding database correlating an output port with at least one of the plurality of portions of the shared buffer. [16] The method of claim 15, wherein a packet is routed to a portion of the shared buffer based at least in part on the forwarding database to an available portion of the shared buffer that is as close as possible to an output port associated with the packet, and wherein a nearest available portion of the shared buffer is different from a portion of the shared buffer that is closest to the output port associated with the packet. [17] The method of claim 15 or 16, wherein the multiple portions of the shared buffer are distributed across different physical locations within a device, and wherein a packet is directed to a portion of the shared buffer that is available and as close as possible to an output port associated with the packet. [18] The method of claim 17, wherein the device comprises a network switch. [19] The method of any of claims 15 to 18, wherein each forwarding database is determined based at least in part on reducing latency and maintaining minimum shared buffer requirements. [20] A method according to any one of claims 15 to 19, wherein each forwarding database maps each output port to an available portion of the shared buffer as close as possible to a respective output port.

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