TRANSPARENT DISPLAY DEVICE

Abstract

In a display device (100), each subpixel (SP1, SP2, SP3) may comprise: a first-mode subpixel (SP1-1, SP2-1, SP3-1) having a first viewing angle and comprising a first light-emitting element (ED1), a second-mode subpixel (SP1-2, SP2-2, SP3-2) having a second viewing angle and comprising a second light-emitting element (ED2), a driver transistor (DT) connected to the first or second light-emitting element (ED2), mode selection lines providing a first-mode selection signal (MS1) and a second-mode selection signal (MS2), a first transistor controlling a connection between the first light-emitting element (ED1) and the driver transistor (DT) based on the first-mode selection signal (MS1), and a second transistor controlling a connection between the second light-emitting element (ED2) and the driver transistor (DT) based on the second mode selection signal (MS2).The first light-emitting element (ED1) is connected to the driver transistor (DT) during a first display drive period (DP1). The second light-emitting element (ED2) is connected to the driver transistor (DT) during a second display drive period (DP2).

Description

REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to Korean Patent Application No. 10-2023-0169375, filed on November 29, 2023. BACKGROUND 1. Technical field

[0002] The present disclosure relates to an electronic device, particularly, for example, without limitation, a display device capable of controlling a viewing angle. 2. Discussion of related technology

[0003] Recently, the problem of information leakage to third parties through image information displayed on a display device has emerged. To solve this problem, security films are being developed that provide image information only to specific people in front of the display device.

[0004] By attaching a security film to the display device, the user can prevent a nearby third party from viewing the image information displayed on the display device, and by removing the security film from the display device, the user can allow a nearby third party to view the image information displayed on the display device. The user is inconvenienced by having to carry and manage the security films separately, and it is difficult to partially obscure image information or provide it to the third party.

[0005] The description of related art should not be considered prior art simply because it is mentioned or associated with this section. The description of related art includes information describing one or more aspects of the subject technology, and the description in this section does not limit the invention. OVERVIEW

[0006] One or more aspects of the present disclosure aim to provide a display device capable of controlling a viewing angle without a security film.

[0007] Furthermore, one or more aspects of the present disclosure are directed to providing a display device capable of partially controlling a viewing angle within a display area.

[0008] Furthermore, one or more aspects of the present disclosure are directed to providing a display device capable of implementing environmental / social / governance (ESG) considerations by reducing the generation of greenhouse gases that may be generated by a manufacturing process.

[0009] The problems to be solved by the examples of the present disclosure are not limited to those mentioned above, and other problems not mentioned will be apparent to a person skilled in the art to which the technical aspects of the present disclosure belong from the following description.

[0010] A display device according to an exemplary embodiment of the present disclosure includes: a display panel provided with a plurality of subpixels that display images in a display drive period, each of the plurality of subpixels including: a first-mode subpixel having a first viewing angle and a first light-emitting element, a second-mode subpixel having a second viewing angle and a second light-emitting element, a drive transistor connected to the first light-emitting element or the second light-emitting element, a first-mode selection line extending in a first direction and providing a first-mode selection signal, a second-mode selection line extending in the first direction and providing a second-mode selection signal, a first control transistor,which controls a connection between the first light-emitting element and the driver transistor based on the first mode selection signal, and a second control transistor which controls a connection between the second light-emitting element and the driver transistor based on the second mode selection signal, wherein the display drive period is temporally divided into a first display drive period and a second display drive period, and wherein the first light-emitting element is connected to the driver transistor in the first display drive period and the second light-emitting element is connected to the driver transistor in the second display drive period.

[0011] A display device according to another exemplary embodiment of the present disclosure includes: a display panel provided with a plurality of subpixels including a first-mode subpixel and a second-mode subpixel in a display area, and a display controller that outputs first pixel data for the first-mode subpixel and second pixel data for the second-mode subpixel to the display panel, wherein the display panel supplies the first pixel data to the first-mode subpixel in a first display drive period and the second pixel data to the second-mode subpixel in a second display drive period, and wherein the first display drive period and the second display drive period are separated in time.

[0012] Additional features, advantages, and aspects of the present disclosure will be set forth in part in the description which follows, and in part will be obvious from this disclosure, or may be learned by application of the inventive concepts provided herein. Other features, advantages, and aspects of the present disclosure may be learned and attained by or from the descriptions provided in this disclosure, and the claims hereof, as well as the drawings. It is intended that all such features, advantages, and aspects be included in this description, be within the scope of the present disclosure, and be protected by the following claims. Nothing in this section should be construed as a limitation on these claims. Additional aspects and advantages are discussed below in connection with embodiments of the present disclosure.

[0013] It is to be understood that both the foregoing and following descriptions of the present disclosure are exemplary and are intended to provide further explanation of the claimed disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are intended to provide a further understanding of the present disclosure, are incorporated in and constitute a part of this disclosure, illustrate aspects and embodiments of the present disclosure, and together with the description serve to explain principles and examples of the disclosure. Fig. 1 is a perspective view showing a display device according to an exemplary embodiment of the present disclosure. Fig. 2 is a block diagram schematically showing a configuration of a display device according to an exemplary embodiment of the present disclosure. Fig. 3 is a plan view showing an example of a pixel in a display device according to an exemplary embodiment of the present disclosure. Fig. 4 is a cross-sectional view showing an example of a first-mode subpixel according to II' in Fig. 3 shows. Fig. 5 is a cross-sectional view showing an example of a second-mode subpixel according to II-II' in Fig. 3 shows. Fig. 6 is an equivalent circuit diagram showing a circuit configuration of each subpixel in a display panel according to an embodiment. Fig. 7 is a plan view showing an example of a set of scan lines and mode selection lines arranged on a display panel according to an embodiment of the present disclosure. Fig. 8 is a diagram showing an example of a driving waveform for subpixels arranged on a display panel according to an embodiment of the present disclosure. Fig. 9 is a diagram showing another example of a driving waveform for subpixels arranged on a display panel according to an embodiment of the present disclosure. Fig. 10 is a diagram illustrating various examples in which one frame is temporally divided into a first display drive period and a second display drive period, which are driven when image data is input in frame units. Fig. 11 is a plan view illustrating an example of mode selection lines and data lines arranged on a display panel according to an exemplary embodiment of the present disclosure. Fig. 12A is a diagram showing an example of a first mode display area and a second mode display area. Fig. 12B is a diagram showing an example of first pixel data input in a first display drive period. Fig. 12C is a diagram showing an example of second pixel data input in the second display driving period. Fig. 13A is a diagram showing another example of a first mode display area and a second mode display area. Fig. 13B is a diagram showing another example of first pixel data input in the first display driving period. Fig. 13C is a diagram showing another example of second pixel data input in the second display driving period. Fig. 14A is a diagram showing another example of a first mode display area and a second mode display area. Fig. 14B is a diagram showing an example of a drive waveform for the Fig. 14A shows the subpixels shown.

[0015] Throughout the drawings and detailed description, unless otherwise noted, the same drawing reference numbers should be understood to refer to the same elements, features, and structures. The sizes, lengths, and thicknesses of layers, regions, and elements, as well as their representation, may be exaggerated for clarity, illustration, and / or convenience. DETAILED DESCRIPTION

[0016] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be shown in the accompanying drawings. In the following description, where a detailed description of well-known methods, functions, structures, or configurations might unnecessarily obscure aspects of the present disclosure, the detailed description may be omitted for the sake of brevity. Furthermore, repetitive descriptions may be omitted for the sake of brevity. The sequence of processing steps and / or operations described is a non-limiting example.

[0017] The sequence of steps and / or acts is not limited to the sequence set forth herein and may occur in a different order than that described, except for steps and / or acts that necessarily occur in a particular order. In one or more examples, two acts may be performed sequentially at substantially the same time, or the two acts may be performed in reverse or in a different order, depending on the function or act involved.

[0018] Unless otherwise noted, like reference numbers may refer to like elements even if they are shown in different drawings. Unless otherwise noted, the same reference numbers may be used to refer to the same or substantially the same elements throughout the description and drawings. In one or more aspects, identical elements (or elements with identical names) in different drawings may have the same or substantially the same functions and characteristics unless otherwise noted. The names of the respective elements used in the following explanations are chosen for convenience only and may therefore differ from those used in actual products.

[0019] The advantages and features of the present disclosure and the corresponding implementation methods are made clear by the embodiments described with reference to the accompanying drawings. However, the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are examples and are provided so that this disclosure will be thorough and complete to aid those skilled in the art in understanding the inventive concepts, without limiting the protected scope of the present disclosure. Furthermore, the present disclosure is defined by the scope of the claims and their equivalents.

[0020] The shapes, dimensions (e.g., sizes, lengths, widths, heights, thicknesses, positions, radii, diameters, and areas), proportions, ratios, angles, numbers, the number of elements, and the like disclosed herein, including those shown in the drawings, are merely examples, and therefore, the present disclosure is not limited to the details shown. However, it should be noted that the relative dimensions of the components shown in the drawings are part of the present disclosure.

[0021] When the term "comprise," "having," "include," "contain," "represent," "made of," "formed of," "composed of," or the like is used with reference to one or more elements (e.g., layers, films, components, electrodes, structures, transistors, portions, elements, parts, regions, areas, sections, steps, operations, and / or the like), one or more other elements may be added unless a term such as "only" or the like is used. The terms used in the present disclosure are used merely to describe particular embodiments and are not intended to limit the scope of the present disclosure. The singular terms may also appear in the plural unless the context clearly indicates otherwise. For example, an element may be one or more elements. An element may include multiple elements.The word "exemplary" is used to serve as an example or illustration. Embodiments are exemplary embodiments. Aspects are exemplary aspects. In one or more implementations, "embodiments," "examples," "aspects," and the like should not be construed as being preferable or more advantageous than other implementations. An embodiment, example, exemplary embodiment, aspect, or the like may refer to one or more embodiments, one or more examples, one or more exemplary embodiments, one or more aspects, or the like, unless otherwise noted. Furthermore, the term "may" includes all meanings of the term "can."

[0022] Unless explicitly stated otherwise, in one or more aspects, an element, characteristic, or corresponding information (e.g., a level, range, dimension, size, or the like) is interpreted as having a margin of error or tolerance, even if no explicit description of such a margin of error or tolerance is provided. A margin of error or tolerance may be caused by various factors (e.g., process factors, internal or external influences, noise, or the like). When interpreting a numerical value, the value is assumed to have a margin of error unless explicitly stated otherwise.

[0023] When a positional relationship between two elements (e.g., layers, films, components, electrodes, structures, transistors, sections, elements, parts, regions, areas, portions, and / or the like) is described using any of the terms "on," "on top of," "upon," "on top of," "over," "below," "above," "upper," "at an upper portion," "at an upper side," "below," "lower," "at a lower portion," "at a lower side," "beneath," "near," "close to," "adjacent to," "beside," "next to," "on or to a side of," and / or the like, which indicate a position or location, one or more other elements may be located between the two elements unless a more restrictive term such as "immediate," "direct," or "close" is used. For example, ifWhen an element and another element are described using any of the above terms, this description should be construed to include both a case where the elements are in direct contact with each other and a case where one or more additional elements are disposed or interposed therebetween. Furthermore, spatially relative terms such as the above terms, as well as other terms such as "front," "back," "rear," "left," "right," "top," "bottom," "upper," "lower," "downward," "upward," "up," "down," "column," "row," "vertical," "horizontal," "diagonal," and the like, refer to any frame of reference. These terms may be used, for example, for an example understanding of a relative relationship between elements, including a correlation, as illustrated in the drawings. However, the embodiments of the disclosure are not limited thereby or to them.The spatially relative terms are to be understood as terms that include different orientations of the elements in use or in operation, in addition to the orientation shown in the drawings or described herein. For example, if a lower element or an element positioned below another element is inverted, the element may be referred to as an upper element or as an element positioned above another element. For example, the term "below" or "below" may include within its meaning the term "above" or "above". An example term such as "below" or the like may include all directions, including "below", "above", and diagonal directions. Likewise, an example term such as "above", "on", or the like may include all directions, including "above", "on", "below", and diagonal directions.

[0024] When describing a temporal relationship, where the temporal sequence is described as, for example, "after," "following," "subsequent," "next," "before," "previous," "prior," or the like, an instance that is non-consecutive or non-sequential may also have one or more other events occurring in between, unless a more restrictive term such as "just," "immediate," or "direct" is used.

[0025] It is understood that although the terms "first," "second," and the like may be used herein to describe various elements (e.g., layers, films, components, electrodes, structures, transistors, sections, elements, parts, regions, areas, portions, steps, operations, and / or the like), these elements should not be limited by these terms, e.g., to any particular order, precedence, or number of elements. These terms are used only to distinguish one element from another. For example, a first element may refer to a second element, and likewise, a second element may refer to a first element, without departing from the scope of the present disclosure. Furthermore, the first element, the second element, and the like may be named as desired and as appropriate by those skilled in the art without departing from the scope of the present disclosure.For clarity, the functions or structures of these elements (e.g., the first element, the second element, etc.) are not limited by atomic numbers or the names prefixed to the elements. Furthermore, a first element may have one or more first elements. Likewise, a second element, or the like, may have one or more second elements, or the like.

[0026] When describing elements of the present disclosure, the terms "first," "second," "A," "B," "(a)," "(b)," or the like may be used. These terms are intended to distinguish the corresponding element(s) from another element(s) and are not used to define the nature, basis, order, or number of the elements.

[0027] For example, the expression that an element (e.g., layer, film, component, electrode, structure, transistor, section, member, part, region, area, portion, or the like) is "engaged" with another element can be understood to mean that the element is engaged with the other element, either directly or indirectly. The term "is engaged" or similar expressions can refer to a term such as "covers," "surrounds," "contacts," "overlaps," "crosses," "intersects," "is connected," "is coupled," "is attached," "adheres to," "is combined," "is linked," "is provided," "is arranged," "interacts," or the like. The engagement can include one or more intervening elements disposed or interposed between the element and the other element, unless otherwise noted.Furthermore, the element may be at least partially or fully engaged (or wholly engaged) with the other element, unless otherwise stated. Furthermore, the element may be included in at least one of two or more elements that are engaged with each other. Likewise, the other element may be included in at least one of two or more elements that are engaged with each other. When the element is engaged with the other element, at least a portion of the element may be engaged with at least a portion of the other element. The term "with another element" or similar expressions may be understood as "another element" or "with, to, in, or on another element" depending on the context. Likewise, the term "with each other" may be understood as "each other" or "with, to, or on each other" depending on the context.

[0028] The expression “through” can, for example, be understood to mean that it is at least partially or completely through.

[0029] Terms such as "line" or "direction" should not be interpreted solely based on a geometric relationship in which the respective lines or directions are parallel, orthogonal, diagonal, or oblique to each other, and may be understood as lines or directions that include broader directions within the range in which the components of the present disclosure can functionally operate. For example, the terms "first direction," "second direction," and the like should not be interpreted solely based on a geometric relationship in which the respective directions are parallel, orthogonal, diagonal, or oblique to each other, and may be understood as directions that include broader directions within the range in which the components of the present disclosure can functionally operate.

[0030] The term "at least one" should be understood to include all combinations of one or more of the listed elements. For example, each of the phrases "at least one of a first, a second, or a third element" and "at least one of a first, a second, and a third element" may represent: (i) a combination of elements provided by two or more of the first, second, and third elements; or (ii) only one of the first, second, or third elements. Furthermore, at least one of a plurality of elements may represent (i) an element of the plurality of elements, (ii) some elements of the plurality of elements, or (iii) all elements of the plurality of elements.Further, “at least some,” “at least some sections,” “at least some parts,” “at least one section,” “at least one or more sections,” “at least one part,” “at least one or more parts,” “at least some elements,” “one or more,” or the like of multiple elements may represent: (i) one element of the multiple elements, (ii) one section (or part) of the multiple elements, (iii) one or more sections (or parts) of the multiple elements, (iv) multiple elements of the multiple elements, or (v) all of the multiple elements.In addition, “at least some,” “at least some sections,” “at least some parts,” “at least one section,” “at least one or more sections,” “at least one part,” “at least one or more parts,” or the like of an Element may represent (i) a section (or part) of the Element, (ii) one or more sections (or parts) of the Element, or (iii) the Element or all sections of the Element.

[0031] The expression: a first element, a second element "and / or" a third element should be understood as any one of the first, second and third elements, or as any or all combinations of the first, second and third elements. For example, A, B and / or C can refer to only A, only B, only C, to A, B and C (e.g., A, B or C), to a combination of A, B and C (e.g., A and B; A and C or B and C), or all of A, B and C. Furthermore, the expression "A / B" can be understood as A and / or B. For example, the expression "A / B" can refer to only A, only B, A or B or A and B.

[0032] In one or more aspects, the terms "between" and "among" may be used interchangeably for convenience unless otherwise noted. For example, an expression "between multiple elements" may be understood as "among multiple elements." In another example, an expression "among multiple elements" may be understood as "between multiple elements." In one or more examples, the number of elements may be two. In one or more examples, the number of elements may be more than two. Additionally, when an element is referred to as being "between" at least two elements, the element may be the only element between the at least two elements, or there may also be one or more intervening elements.

[0033] In one or more aspects, the terms "themselves" and "each other" may be used interchangeably for convenience unless otherwise indicated. For example, the term "different from each other" may be understood as "differ." In another example, the term "different from each other" may be understood as "different from each other." In one or more examples, the number of elements included in the above expression may be two. In one or more examples, the number of elements included in the above expression may be more than two.

[0034] In one or more aspects, the terms “one or more of” and “one or more of” may be used interchangeably simply for convenience, unless otherwise specified.

[0035] The term "or" means "including or" and not "exclusively or." That is, unless otherwise specified or clear from the context, the phrase "x uses a or b" means any of the natural, inclusive permutations. For example, "a or b" can mean "a," "b," or "a and b." For example, "a, b, or c" can mean "a," "b," "c," "a and b," "b and c," "a and c," or "a, b, and c."

[0036] A phrase such as “substantially the same” or “almost the same” may indicate that they are considered equivalent, taking into account minor differences due to defects in the manufacturing process.

[0037] Features of various embodiments of the present disclosure may be partially or fully coupled or combined with one another, may be technically interconnected, and may be differently operated, connected, or driven in various ways. Embodiments of the present disclosure may be implemented or performed independently of one another, or may be implemented or performed together in a dependent or related relationship. In one or more aspects, the components of each device and apparatus are operably coupled and configured according to various embodiments of the present disclosure.

[0038] Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning commonly understood by a person skilled in the art to which the exemplary embodiments belong. It is further understood that terms as defined in commonly used dictionaries should be interpreted to have a meaning consistent, for example, with their meaning in the context of the relevant technology and should not be interpreted in an idealized or overly formal sense, unless expressly defined otherwise herein. For example, the term "part" or "unit" may, for example,to a separate circuit, component or structure, an integrated circuit, a computational block of a circuit device, or a structure configured to perform a described function, as should be understood by a person skilled in the art.

[0039] The terms used herein have been chosen to be generic to the technical field concerned; however, other terms may exist depending on the development and / or change of technology, convention, preference of technicians, etc. Therefore, the terms used herein should not be construed as limiting technical concepts, but rather as examples of terms for describing exemplary embodiments.

[0040] Furthermore, a term may be arbitrarily selected by an applicant in a particular case, and in this case, the detailed meaning of the term is described herein. Therefore, the terms used herein should be understood not only based on the name of the terms, but also based on the meaning of the terms and the content of those terms.

[0041] In the following description, various exemplary embodiments of the present disclosure are described in more detail with reference to the accompanying drawings. With regard to reference numerals to elements in the individual drawings, the same elements may be shown in other drawings, and like reference numerals may refer to like elements unless otherwise noted. The same or similar elements may be identified by the same reference numerals even though they are shown in different drawings. Furthermore, for ease of description, the scale, dimension, size, and thickness of each of the elements shown in the accompanying drawings may differ from the actual scale, dimension, size, and thickness, so that the embodiments of the present disclosure are not limited to the scale, dimension, size, and thickness shown in the drawings.

[0042] Fig. 1 is a perspective view showing a display device according to an exemplary embodiment of the present disclosure, and Fig. 2 is a block diagram schematically showing a configuration of a display device according to an exemplary embodiment of the present disclosure. Fig. 3 is a plan view showing an example of a pixel in a display device according to an exemplary embodiment of the present disclosure.

[0043] While the display device 100 according to an exemplary embodiment of the present disclosure has been described with a focus on its implementation as an organic light-emitting display, it may also be implemented as a liquid crystal display, a quantum dot light-emitting diode, or an electrophoresis display.

[0044] With reference to the Fig. 1 and Fig. 2, the display device 100 according to an exemplary embodiment of the present disclosure includes: a display panel 110, a gate driver 120 embedded in the display panel 110, a data driver 130 connected to the display panel 110, a timer controller 160 controlling the gate driver 120 and the data driver 130, a gamma voltage generator 175, and a power circuit 180. In one embodiment, the display device 100 may further include a level converter 170 connected between the timer controller 160 and the gate driver 120. In one embodiment, the data driver 130, the timer controller 160, the gamma voltage generator 175, and the level converter 170 may be integrated into a display driver.

[0045] The display panel 110 includes a first substrate 111 and a second substrate 112. The second substrate 112 may be an encapsulation substrate. The first substrate 111 may be, but is not necessarily limited to, a plastic film or a glass substrate. The first substrate 111 may also be made of a semiconductor material, such as a silicon wafer. The second substrate 112 may be a plastic film, a glass substrate, or an encapsulation film (or protective film).

[0046] The display device 100 according to an exemplary embodiment of the present disclosure may emit light in a so-called top-emission type in which the emitted light is emitted upward, but is not necessarily limited thereto. When the display device 100 emits light in a top-emission type, the material of the first substrate 111 may include both an opaque and a translucent material. When the display device 100 emits light in a bottom-emission type in which the emitted light is emitted downward, the material of the first substrate 111 may include a transparent material. Hereinafter, for the convenience of explanation, it is assumed that the display device 100 emits light in the top-emission type, but is not necessarily limited thereto.

[0047] The display panel 110 has a display area DA and an aperture area BZ. The aperture area BZ surrounds the display area DA and is arranged on a perimeter. The display panel 110 displays images in the display area DA using a plurality of subpixels SP arranged in a matrix. The plurality of subpixels SP may include: a plurality of rows having subpixels SP arranged in a first direction (e.g., X-axis direction) and a plurality of columns having subpixels SP arranged in a second direction (e.g., Y-axis direction).

[0048] As in Fig. 3, each of the subpixels SP may be one of, but is not necessarily limited to, a first subpixel SP1 emitting red light, a second subpixel SP2 emitting green light, and a third subpixel SP3 emitting blue light. A unit pixel P may have at least two or more subpixels SP. In one example, as shown in Fig. As shown in Figure 3, the unit pixel P may include the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. The unit pixel P may further include a fourth subpixel that emits white light. Furthermore, the arrangement order of the subpixels SP1, SP2, and SP3 may be varied.

[0049] In contrast, each of the subpixels SP1, SP2, and SP3 may have two or more mode subpixels that have different viewing angles. For example, as shown in Fig. 3, each of the subpixels SP1, SP2, and SP3 may comprise a first-mode subpixel SP1-1, SP2-1, and SP3-1 and a second-mode subpixel SP1-2, SP2-2, and SP3-2. The first-mode subpixels SP1-1, SP2-1, and SP3-1 may have a first viewing angle and include a first emitting element, and the second-mode subpixels SP1-2, SP2-2, and SP3-2 may have a second viewing angle and include a second emitting element. The first viewing angle and the second viewing angle may differ in at least one direction and an angular range. In one example, the second viewing angle may have a smaller angular range than the first viewing angle. In another example, the first viewing angle may be 30 degrees to the left from 0 degrees forward, and the second viewing angle may be 30 degrees to the right from 0 degrees forward.

[0050] Each subpixel SP1, SP2, and SP3 can selectively drive one of the first emitting element and the second emitting element to control a viewing angle. In one example, each subpixel SP1, SP2, and SP3 can implement a first viewing angle mode by driving the first emitting element of the first-mode subpixel SP1-1, SP2-1, and SP3-1. In one embodiment, the first viewing angle mode can be a wide-viewing angle mode or a split mode. In another example, each subpixel SP1, SP2, and SP3 can implement a second viewing angle mode by driving the second emitting element of a second-mode subpixel SP1-2, SP2-2, and SP3-2. In one embodiment, the second viewing angle mode can be a narrow-viewing angle mode or a privacy mode, wherein the narrow-viewing angle mode or the privacy mode can limit the angular range of the viewing angle to a lesser extent than the first viewing angle mode.

[0051] The display panel 110 may include a plurality of signal lines including: data lines 22, gate lines 12, 16, 42, and 44, and power lines 24, 32, and 34 connected to respective ones of the subpixel SPs.

[0052] The data lines 22 may be arranged to extend in the second direction (e.g., in the Y-axis direction) to supply each subpixel SP with a data voltage Vdata supplied by the data driver 130.

[0053] Gate lines 12, 16, 42, 43, and 44 may be arranged to cross data lines 22 to supply signals supplied by gate driver 120 to each subpixel SP. In particular, some of gate lines 12, 16, 42, 43, and 44 (12, 16, referred to herein as "scan lines") may supply scan signals SCAN1 and SCAN2 supplied by scan driver 122 to each subpixel SP. Another portion of gate lines 12, 16, 42, 43, and 44 (42, referred to herein as "emission control lines") may supply emission signals EM supplied by emission control driver 124 to each subpixel SP.

[0054] The other portion of the gate lines 12, 16, 42, 43, 44 (43, 44, hereinafter referred to as "mode selection lines") can supply mode selection signals MS1 and MS2 supplied from the mode selection driver 126 to each subpixel SP. The first mode selection line 43 among the mode selection lines 43 and 44 can supply a first mode selection signal MS1 to each subpixel SP to drive the first emission element of the first mode subpixel SP1-1, SP2-1, and SP3-1. The second mode selection line 44 among the mode selection lines 43 and 44 can supply a second mode selection signal MS2 to each subpixel SP to drive the second emission element of the second mode subpixel SP1-2, SP2-2, and SP3-2.

[0055] In this example, the display device 100 can control the viewing angle of each subpixel SP by selectively driving the first emission element and the second emission element of each subpixel SP using the first mode selection signal MS1 and the second mode selection signal MS2. A detailed description will be given later.

[0056] The initialization voltage line 24 among the power lines 24, 32, and 34 can supply an initialization voltage Vref supplied by the power circuit 180 to each subpixel SP. A first power line 32 can supply a first supply voltage (or high-potential supply voltage) EVDD to each subpixel SP. The second power line 34 can supply a second supply voltage (or low-potential supply voltage) EVSS to each subpixel SP via a common electrode (or cathode electrode).

[0057] The gate driver 120 may be disposed in at least one of the plurality of aperture regions BZ1 to BZ2 arranged at the edge of the display region DA. For example, the gate driver 120 may be disposed in one of the first and second aperture regions BZ1 and BZ2, which are opposite to each other, with the display region DA in between, or may be disposed on both sides of the first and second aperture regions BZ1 and BZ2. The gate driver 120 may be disposed in a gate-in-panel (GIP) type formed from transistors formed in the same process as the transistors arranged in the display region DA.

[0058] The gate driver 120 may include: the scan driver 122 that drives a plurality of gate lines 12 and 16 connected to the subpixels SPs of each row line, an emission control driver 124 that drives an emission control line 42 connected to the subpixels SPs of each row line, and a mode selection driver 126 that drives a plurality of mode selection lines 43 and 44 connected to the subpixels SPs of each row line.

[0059] Each of the scan driver 122, the emission control driver 124, and the mode selection driver 126 may receive a plurality of control signals supplied via the level shifter 170 from the timing controller 160 to operate. In one embodiment, each of the scan driver 122, the emission control driver 124, and the mode selection driver 126 may receive the plurality of control signals from the timing controller 160.

[0060] The level shifter 170 can receive control signals from the timing controller 160. By shifting the level of the control signals or performing a logic process on the control signals, a plurality of gate control signals GCS, a plurality of emission control signals ECS, and a plurality of mode control signals MCS can be generated, which are supplied to the scan driver 122, the emission control driver 124, and the mode selection driver 126, respectively.

[0061] The scan driver 122 may supply at least one scan signal SCAN1 and SCAN2 to each of the plurality of row lines using the gate control signal GCS supplied from the level converter 170 or the timing controller 160. The scan driver 122 may supply the scan signals SCAN1 and SCAN2 to the plurality of scan lines 12 and 16 connected to the subpixels SP of each row line.

[0062] The emission control driver 124 may provide an emission signal EM to each of the plurality of row lines using the emission control signal ECS provided by the level converter 170 or the timing controller 160. The emission control driver 124 may provide the emission signal EM to the emission control line 42 connected to the subpixels SP of each of the row lines.

[0063] The mode selection driver 126 may supply the mode selection signals MS1 and MS2 to each of the plurality of row lines using the mode control signals MCS supplied from the level converter 170 or the timing controller 160. The mode selection driver 126 may supply the mode selection signals MS1 and MS2 to the mode selection lines 43 and 44 connected to the subpixels SP of each of the row lines.

[0064] The gamma voltage generator 175 may generate a plurality of reference gamma voltages having different voltage levels and supply them to the data driver 130. The gamma voltage generator 175 may generate the plurality of reference gamma voltages corresponding to a gamma characteristic of the display device under the control of the timing controller 160 and supply them to the data driver 130. In one embodiment, the gamma voltage generator 175 may adjust the levels of the reference gamma voltages according to gamma data supplied by the timing controller 160 and output them to the data driver 130.

[0065] The data driver 130 receives pixel data DATA and a data control signal DCS from the timing controller 160. The data driver 130 converts the pixel data DATA into analog positive / negative data voltages Vdata using the data control signals DCS and supplies them to the subpixels SP via the data lines 22.

[0066] As in Fig. 1, the data driver 130 may include a plurality of data driver ICs 131. Each of the plurality of data driver ICs 131 may be mounted on a circuit film 140 in a chip-on-film (COF) type, chip-on-plastic (COP) type, flexible printed circuit (FPC) type, or flexible flat cable (FFC) type. The circuit film 140 is mounted using an anisotropic conductive film on pads arranged in a non-display area NDA of the display panel 110, so that the plurality of data driver ICs 131 may be connected to the pads.

[0067] The circuit board 150 may be attached to the circuit film 140. A plurality of circuits embodied as drive chips may be attached to the circuit board 150. For example, the timer controller 160 may be attached to the circuit board 150. The circuit board 150 may be a printed circuit board or a flexible printed circuit board.

[0068] The timing controller 160 receives digital video data and timing signals from the host system. The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a dot clock, and the like. The vertical synchronization signal is a signal that defines the duration of one frame. A horizontal synchronization signal is a signal that defines a period of a horizontal period required to supply data voltages to the pixels of a horizontal row of the display panel DIS. The data enable signal defines the period in which valid data is input. The dot clock is a signal that repeats at a predetermined short interval.

[0069] Based on the timing signals, the timing controller 160 can supply the data control signal DCS to control the operating timing of the data driver 130, the gate control signal GCS to control the operating timing of the scan driver 122, the emission control signal ECS to control the operating timing of the emission control driver 124, and the mode control signal MCS to control the operating timing of the mode selection driver 126. The timing controller 160 can supply the gate control signal GCS to the scan driver 122, the emission control signal ECS to the emission control driver 124, and the mode control signal MCS to the mode selection driver 126. In addition, the timing controller 160 can supply the data control signal DCS to the data driver 130.The timer controller 160 according to one embodiment may generate and supply control signals for the timer controller to the level converter 170, so that the level converter 170 may generate and supply a plurality of control signals GCS, ECS, and MCS to the scan driver 122, the emission control driver 124, and the mode selection driver 126.

[0070] Furthermore, the timing controller 160 may convert the digital video data into pixel data DATA by aligning the digital video data to match the pixel structure formed on the display panel 110. The pixel data DATA may include first pixel data for the first-mode subpixels SP1-1, SP2-1, and SP3-1 and second pixel data for the second-mode subpixels SP1-2, SP2-2, and SP3-2.

[0071] The digital video data input from the host system may include information about an image to be displayed in the display area DA. The image may include a first image displayed by the first-mode subpixels SP1-1, SP2-1, and SP3-1, and a second image displayed by the second-mode subpixels SP1-2, SP2-2, and SP3-2. The first image and the second image may be implemented as separate digital video data, or the first image and the second image may be integrated to be implemented as a single digital video data.

[0072] In one example, the digital video data may include first digital video data including information about a first image, and second digital video data including information about a second image. In this example, the first digital video data and the second digital video data may be input from the host system to the timing controller 160. The timing controller 160 may align the first digital video data to convert it into first pixel data DATA1 and align the second digital video data to convert it into second pixel data DATA2. The timing controller 160 may provide the first pixel data DATA1 and the second pixel data DATA2 along with a data control signal DCS to the data driver 130.

[0073] In another example, the digital video data may include the individual digital video data in which the first image and the second image are integrated. In this example, the timing controller 160 may receive position information of an area where the first image or the second image is displayed along with the integrated individual digital video data from the host system. The timing controller 160 may convert the digital video data into first pixel data DATA1 and second pixel data DATA2 by using the position information of the area where the first image or the second image is displayed. The timing controller 160 may supply the first pixel data DATA1 and the second pixel data DATA2 along with the data control signal DCS to the data driver 130.

[0074] The power circuit 180 can generate and supply a plurality of drive voltages required for the operation of all circuit configurations of the display device 100 using the input voltage. The power circuit 180 can generate and supply the first supply voltage EVDD, the second supply voltage EVSS, and the initialization voltage Vref (or a reference voltage) to the display panel 110. The power circuit 180 can generate and supply various drive voltages required for the operation of the gate driver 120, the data driver 130, the timing controller 160, the level converter 170, and the gamma voltage generator 175.

[0075] Fig. 4 is a cross-sectional view showing an example of a first-mode subpixel according to II' in Fig. 3 shows, and Fig. 5 is a cross-sectional view showing an example of a second-mode subpixel according to II-II' in Fig. 3 shows.

[0076] Each of the subpixels SP1, SP2, and SP3 arranged in the display panel 110 according to an embodiment of the present disclosure may include the first-mode subpixels SP1-1, SP2-1, and SP3-1 and the second-mode subpixels SP1-2, SP2-2, and SP3-2 having different viewing angles. There are various ways to implement different viewing angles of the first-mode subpixels SP1-1, SP2-1, and SP3-1 and the second-mode subpixels SP1-2, SP2-2, and SP3-2. In one example, as shown in the Fig. 4 and Fig. 5, the first-mode subpixels SP1-1, SP2-1 and SP3-1 and the second-mode subpixels SP1-2, SP2-2 and SP3-2 can be implemented with different viewing angles using the lenses LZ1 and LZ2.

[0077] As in the Fig. 4 and Fig. 5, a display panel 110 according to an embodiment includes: the first substrate 111, a circuit element layer including transistors ET1 and ET2 disposed on the first substrate 111, an emission element layer including emission elements ED1 and ED2 disposed on the circuit element layer, an encapsulation layer 800 disposed on the emission element layer, and a lens layer including lenses LZ1 and LZ2 disposed on the encapsulation layer 800. The display panel 110 according to an embodiment may further include a touch sensor layer disposed between the encapsulation layer 800 and the lens layer. The display panel 110 according to an embodiment may further include a color filter layer including a color filter and a black matrix disposed between the touch sensor layer and the lens layer.

[0078] Each subpixel SP1, SP2 and SP3 may have a first lens area LA1 which is Fig. 4, and a second lens area LA2, which is shown in Fig. 5 is shown.

[0079] With reference to Fig. 4, the first lens region LA1 may include: a first control transistor ET1 of the pixel circuit, a first emission element ED1 (also referred to as a first light emission element ED1) connected to the first control transistor ET1, and a first lens LZ1 arranged to overlap a first light emission region EA1 on the first emission element ED1.

[0080] With reference to Fig. 5, the second lens region LA2 may include: a second control transistor ET2 of the pixel circuit, a second emission element ED2 (also referred to as a second light emission element ED2) connected to the second control transistor ET2, and a plurality of second lenses LZ2 arranged to overlap a plurality of second light emission regions EA2 on the second emission element ED2.

[0081] In the display panel 110 according to one embodiment, the circuit element layer disposed on the first substrate 111 may include a plurality of insulating layers stacked on the first substrate 111. For example, the plurality of insulating layers may include a buffer layer 210, a gate insulating layer 220, an interlayer insulating layer 230, a protective layer 240, and a planarization layer 250.

[0082] The first substrate 111 may comprise an insulating material, such as glass or plastic. The plastic substrate may be formed from a flexible material. For example, the first substrate 111 may comprise an organic insulating material made of at least one of an acrylic-based resin, an epoxy-based resin, a siloxane-based resin, a polyimide-based resin, and a polyamide-based resin.

[0083] Buffer layer 210 may have a single-layer or multi-layer structure comprising an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or aluminum oxide (Al2O3). Buffer layer 210 may prevent hydrogen from flowing through first substrate 111 into semiconductor layers 211 and 221.

[0084] The control transistors ET1 and ET2 may be arranged on the buffer layer 210.

[0085] The first control transistor ET1 includes a semiconductor layer 211, a gate electrode 213, a source electrode 215, and a drain electrode 217 disposed on the buffer layer 210. The second control transistor ET2 includes a semiconductor layer 221, a gate electrode 223, a source electrode 225, and a drain electrode 227 disposed on the buffer layer 210. A gate insulating layer 220 may be disposed between the semiconductor layers 211 and 221 and the gate electrodes 213 and 223. An interlayer insulating layer 230 may be disposed between the gate electrodes 213 and 223 and the source and drain electrodes 215, 217, 225, and 227. Each of the source electrode 215 and the drain electrode 217 of the first control transistor ET1 can be connected to a source region ora drain region of the semiconductor layer 211 through respective contact holes penetrating the interlayer insulating layer 230 and the gate insulating layer 220. Each of the source electrode 225 and the drain electrode 227 of the second control transistor ET2 may be connected to a source region and a drain region of the semiconductor layer 221, respectively, through respective contact holes penetrating the interlayer insulating layer 230 and the gate insulating layer 220.

[0086] The semiconductor layers 211 and 221 may comprise polycrystalline silicon or an oxide semiconductor material. The semiconductor layers 211 and 221 may comprise low-temperature polysilicon (LPTS). The semiconductor layers 211 and 221 may comprise an oxide semiconductor material made of at least one of the following materials: IZO (InZnO), IGO (InGaO), ITO (InSnO), IGZO (InGaZnO), IGZTO (InGaZnSnO), GZTO (GaZnSnO), GZO (GaZnO), and ITZO (InSnZnO). A light-blocking layer may also be arranged below the semiconductor layers 211 and 221.

[0087] The gate insulating layer 220 may comprise an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The gate insulating layer 220 may comprise a material having a high dielectric constant. For example, the gate insulating layer 220 may comprise a high-k dielectric material such as hafnium oxide (HfO). The gate insulating layer 220 may have a multilayer structure.

[0088] The gate lines connected to the gate electrodes 213 and 223 may be arranged on the gate insulating layer 220.

[0089] The interlayer insulating layer 230 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The interlayer insulating layer 230 may have a multilayer structure.

[0090] On the interlayer insulating layer 230, data lines and power lines may be arranged, which are connected to the source electrodes 215 and 225 or the drain electrodes 217 and 227.

[0091] A protective layer 240 and a planarization layer 250 may be stacked on the first and second control transistors ET1 and ET2. The protective layer 240 may comprise an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The planarization layer 250 may comprise an organic insulating material different from the insulating layer 240 and provide a planar surface.

[0092] The emission element layer comprising the first emission element ED1 and the second emission element ED2 may be arranged on the planarization layer 250.

[0093] The first emission element ED1 includes a first electrode 311 disposed on the planarization layer 250, a light emission layer 312 disposed on the first electrode 311, and a second electrode 313 disposed on the light emission layer 312. The second emission element ED2 includes a first electrode 321 disposed on the planarization layer 250, a light emission layer 322 disposed on the first electrode 321, and a second electrode 323 disposed on the light emission layer 322. The first emission element ED1 and the second emission element ED2, disposed in each subpixel SP1, SP2, and SP3, can emit light of the same color.

[0094] The first electrode 311 of the first emission element ED1 may be connected to any of the source electrode 215 and the drain electrode 217 of the first control transistor ET1 via the contact hole penetrating the protective layer 240 and the planarization layer 250. The first electrode 321 of the second emission element ED2 may be connected to any of the source electrode 225 and the drain electrode 227 of the second control transistor ET2 through the contact hole penetrating the protective layer 240 and the planarization layer 250.

[0095] The first electrodes 311 and 321 may include a conductive material with high reflectivity. The first electrodes 311 and 321 may include metals such as aluminum (Al), silver (Ag), titanium (Ti), and silver-palladium-copper (APC) alloys. The first electrodes 311 and 321 may further include a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the first electrodes 311 and 321 may include a multilayer structure (Ti / Al / Ti) of titanium (Ti) and aluminum (Al), a multilayer structure (ITO / Al / ITO) of a multilayer structure of ITO and aluminum (Al), or a multilayer structure (ITO / APC / ITO) of ITO and APC.

[0096] The light-emitting layers 312 and 322 may include an emission material layer EML containing an emission material. The emission material may include an organic material, an inorganic material, or a hybrid material. The light-emitting layer 312 of the first emission element ED1 and the light-emitting layer 322 of the second emission element ED2 may be spaced apart from each other. Accordingly, light emission due to a leakage current can be prevented.

[0097] The light-emitting layers 312 and 322 may have a multi-layer structure. For example, the light-emitting layers 312 and 322 may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0098] The second electrodes 313 and 323 may comprise a conductive material that transmits light. The second electrodes 313 and 323 may comprise a transparent conductive material such as ITO or IZO. The second electrodes 313 and 323 may comprise aluminum (Al), magnesium (Mg), silver (Ag), or an alloy thereof and have a small thickness that can transmit light. Accordingly, light generated by each of the light-emitting layers 312 and 322 can be emitted by each of the second electrodes 313 and 323.

[0099] The first electrode 311 of the first emission element ED1 may be spaced apart from the first electrode 321 of the second emission element ED2, and a bank 260 may be disposed between the first electrodes 311 and 321. The bank 260 may cover an edge of each of the first electrodes 311 and 321. The bank 260 may include an organic insulating material. The bank 260 may include an organic material different from the planarization layer 250 and may have a single-layer structure or a double-layer structure.

[0100] The bank 260 may define a first emission region EA1 by having an opening through which the first electrode 311 is exposed. The light-emitting layer 312 and the second electrode 313 of the first emission element ED1 may be stacked on the first electrode 311 exposed through the opening of the bank 260.

[0101] Bank 260 may define a second emission region EA2 by having an opening through which first electrode 321 of second emission element ED2 is exposed. In one embodiment, bank 260 may define a plurality of second emission regions EA2 by having a plurality of openings on first electrode 321 of second emission element ED2. Light emission layer 322 and second electrode 323 of second emission element ED2 may be stacked on first electrode 321 exposed through the openings of bank 260. Emission layer 322 and second electrode 323 of second emission element ED2 may overlap first electrode 321 with bank 260 disposed therebetween.In the second lens region LA2, the plurality of second emission regions EA2 may be spaced apart and arranged independently of each other by the bank 260, but may share the first electrode 321, the light-emitting layer 322, and the second electrode 323 of the second emission element ED2. Accordingly, the light-emitting efficiency of the second light-emitting region EA2 can be improved. The size of the second light-emitting region EA2 may be smaller than the size of the first light-emitting region EA1.

[0102] The second electrode 313 of the first emission element ED1 may be a common electrode electrically connected to the second electrode 323 of the second emission element ED2.

[0103] The encapsulation layer 800 may be disposed on the emissive element layer including the first emissive element ED1 and the second emissive element ED2. The encapsulation layer 800 may prevent damage to the emissive elements ED1 and ED2 due to moisture and external influences. The encapsulation layer 800 may have a multi-layer structure. The encapsulation layer 800 may include, for example, but is not limited to, a first encapsulation layer 810, a second encapsulation layer 820, and a third encapsulation layer 830 stacked one after the other. The first encapsulation layer 810, the second encapsulation layer 820, and the third encapsulation layer 830 may include an insulating material. The second encapsulation layer 820 may include a different material than the first encapsulation layer 810 and the third encapsulation layer 830.For example, the first encapsulation layer 810 and the third encapsulation layer 830 may be inorganic encapsulation layers comprising an inorganic insulating material, and the second encapsulation layer 820 may be an organic encapsulation layer comprising an organic insulating material. Accordingly, the emission elements ED1 and ED2 can be more effectively prevented from being damaged by moisture and external influences.

[0104] The lens layer, which has a first lens LZ1 and a second lens LZ2, can be arranged on the encapsulation layer 800.

[0105] The first lens LZ1 may be arranged on the first emission element ED1 of the first-mode subpixel SP1-1, SP2-1, and SP3-1, and may be arranged on the light propagation path of the first emission element ED1. The second lens LZ2 may be arranged on the second emission element ED2 of the second-mode subpixel SP1-2, SP2-2, and SP3-2, and may be arranged on the light propagation path of the second emission element ED2.

[0106] In each of the subpixels SP1, SP2, and SP3, the second emission element ED2 may include a plurality of second emission elements ED2 or the plurality of second emission regions, and the plurality of second lenses LZ2 may be individually arranged on the plurality of second emission elements ED2 or the plurality of second emission regions EA2. In each of the subpixels SP1, SP2, and SP3, the plurality of second emission elements ED2 or the plurality of second emission regions EA2 may be connected in parallel.

[0107] The first lens LZ1 and the second lens LZ2 can control (limit) a viewing angle differently in at least one direction. In one example, the first lens LZ1 and the second lens LZ2 can control (limit) the viewing angle differently in the first direction (e.g., the X-axis direction) and control (limit) the viewing angle identically in the second direction (e.g., the Y-axis direction).

[0108] For example, the first lens LZ1 does not limit the propagation path of the light emitted by the first emission element ED1 to a specific angle in the first direction (e.g., the X-axis direction), and thus the viewing angle can be controlled to have a wide field of view. The second lens LZ2 limits the propagation path of the light emitted by the second emission element ED2 to a specific angle in the first direction (e.g., the X-axis direction), so the viewing angle can be adjusted to a narrow field of view.

[0109] When the first emission element ED1 is driven in each of the subpixels SP1, SP2, and SP3, the corresponding subpixel can operate in a wide viewing angle mode that does not limit the viewing angle in the first direction (e.g., the X-axis direction). When the second emission element ED2 is driven in each of the subpixels SP1, SP2, and SP3, the corresponding subpixel can operate in a narrow viewing angle mode that limits the viewing angle in the first direction (e.g., the X-axis direction).

[0110] That is, each subpixel SP1, SP2, and SP3 can drive a first emission element ED1 to implement the first viewing angle mode, the wide viewing angle mode, or a split mode via the first lens area LA1. Each of the subpixels SP1, SP2, and SP3 can drive the second emission element ED2 to implement the second viewing angle mode, the narrow viewing angle mode, or the privacy mode that limits a viewing angle smaller than that of the wide viewing angle mode, through the second lens area LA2.

[0111] A lens protection layer 600 may be disposed on the first lens LZ1 and the second lens LZ2 of each subpixel SP1, SP2, and SP3. The lens protection layer 600 may comprise an organic insulating material. The refractive index of the lens protection layer 600 may be smaller than the refractive index of the first lens LZ1 and the refractive index of the second lens LZ2. Accordingly, the light passing through the first lens LZ1 and the second lens LZ2 cannot be reflected toward the first substrate 111 due to the difference in refractive indices with the lens protection layer 600.

[0112] Fig. 6 is an equivalent circuit diagram showing a circuit configuration of each subpixel in a display panel according to an exemplary embodiment of the present disclosure.

[0113] With reference to Fig. 6, each subpixel SP1, SP2 and SP3 may comprise a pixel circuit 10 comprising a plurality of transistors DT and T1 to T8 and the first and second emission elements ED1 and ED2.

[0114] The Fig. The pixel circuit 10 shown in Figure 6 may include, but is not limited to, eight switching transistors T1 to T8, a driver transistor DT, a storage capacitor Cst, and the first and second emission elements ED1 and ED2. Fig. 6, the switching transistor T6 can also be referred to as the first control transistor T6 and with the Fig. 4, and the switching transistor T8 can also be referred to as the second control transistor T8 and connected to the first control transistor ET1 shown in Fig. 5 correspond to the second control transistor ET2.

[0115] Each of the transistors DT and T1 to T8 of each subpixel SP includes a gate electrode, a source electrode, and a drain electrode. Since the source electrode and the drain electrode are not fixed and can be changed according to the direction of the voltage and current applied to the gate electrode, one of the source electrode and the drain electrode can be represented as a first electrode and the other can be represented as a second electrode. The transistors DT and T1 to T8 of each subpixel SP can use at least one of a polysilicon semiconductor, an amorphous silicon semiconductor, and an oxide semiconductor. The transistors can be P-type or N-type, or a mixture of P-type and N-type.

[0116] The first electrode of the driver transistor DT may be connected to the first power line 32, which supplies the first supply voltage EVDD. The first supply voltage EVDD may be supplied by the power circuit 180 to Fig. 2. The second electrode of the driver transistor DT can be connected to the first electrodes of the first and second control transistors T6 and T8 via the fourth switching transistor T4. The driver transistor DT can drive the first emission element ED1 via the fourth switching transistor T4 and the first control transistor T6, or the second emission element ED2 via the fourth switching transistor T4 and the second control transistor T8. The driver transistor DT can control the drive current according to the drive voltage Vg of the storage capacitor Cst. Thereby, the driver transistor DT can control the emission intensity of the first emission element ED1 via the first control transistor T6, or the emission intensity of the second emission element ED2 via the second control transistor T8.

[0117] The storage capacitor Cst can be charged with the drive voltage Vg, which corresponds to the data voltage Vdata. The storage capacitor Cst can supply the charged drive voltage Vg to the driver transistor DT.

[0118] The first switching transistor T1 can be turned on or off in response to a first scan signal SCAN1 supplied to the first scan line 12. The first switching transistor T1 can supply the data voltage Vdata supplied via the data line 22 to the first electrode of the storage capacitor Cst in response to the gate-on voltage of the first scan signal SCAN1. The first scan signal SCAN1 can be input from the scan driver 122 into Fig. 2 will be delivered.

[0119] The second, fifth, and seventh switching transistors T2, T5, and T7 can be turned on or off in response to the second scan signal SCAN2 supplied to the second scan line 16. The second scan signal SCAN2 can be input to the scan driver 122 Fig. 2 will be delivered.

[0120] The second switching transistor T2 can connect the gate electrode and the second electrode of the driver transistor DT in response to the gate-on voltage of the second scan signal SCAN2, so that the driver transistor DT is switched as a diode structure. The second switching transistor T2 can charge and compensate the threshold voltage Vth of the driver transistor DT to the storage capacitor Cst. Accordingly, the storage capacitor Cst can charge a data voltage Vdata+Vth, which compensates the threshold voltage Vth of the driver transistor DT.

[0121] The fifth switching transistor T5 can supply the initialization voltage Vref (or reference voltage) supplied via the initialization voltage line 24 to the anode electrode of the first emission element ED1 in response to the gate-on voltage of the second scanning signal SCAN2.

[0122] The seventh switching transistor T7 can supply the initialization voltage Vref (or reference voltage) via the initialization voltage line 24 to the anode electrode of the second emission element ED2 in response to the gate-on voltage of the second scan signal SCAN2.

[0123] The third and fourth switching transistors T3, T4 can be turned on or off in response to the emission signal EM supplied to the emission control line 42. The emission signal EM can be converted by the emission control driver 124 into Fig. 2 will be delivered.

[0124] The third switching transistor T3 can supply the initialization voltage Vref (or reference voltage) supplied via the initialization voltage line 24 to the first electrode of the storage capacitor Cst in response to the gate-on voltage of the emission signal EM.

[0125] The fourth switching transistor T4 may connect the driver transistor DT and the first or second control transistor T6, T8 in response to the gate-on voltage of the emission signal EM.

[0126] The first and second control transistors T6, T8 can be controlled to be turned on or off by the mode selection signals MS1 and MS2 supplied to the mode selection lines 43 and 44.

[0127] The first control transistor T6 can be controlled to be turned on or off by the first mode selection signal MS1 supplied to the first mode selection line 43. The first control transistor T6 can be turned on when the first mode selection signal MS1 is the gate-on voltage, thereby connecting the driver transistor DT and the first emission element ED1. Accordingly, the first emission element ED1 can be driven to emit light by the drive current from the driver transistor DT. The subpixels SP1, SP2, and SP3 can emit light at the first viewing angle through the first lens LZ1 and operate in the first viewing angle mode, the wide viewing angle mode, or the split mode.

[0128] The second control transistor T8 can be controlled to be turned on or off by the second mode selection signal MS2 supplied to the second mode selection line 44. The second control transistor T8 can be turned on when the second mode selection signal MS2 is the gate-on voltage, thereby connecting the driver transistor DT and the second emission element ED2. Accordingly, the second emission element ED2 can be driven to emit light by the drive current from the driver transistor DT. The subpixels SP1, SP2, and SP3 can emit light at the second viewing angle through the second lens LZ2 and operate in the second viewing angle mode, the narrow viewing angle mode, or the privacy mode.

[0129] Each of the emission elements ED1 and ED2 may include an anode electrode individually connected to each of the control transistors T6 and T8, a cathode electrode receiving the second supply voltage from the second power line 34, and a light-emitting layer between the anode electrode and the cathode electrode. The anode electrode may be an independent electrode for each emission element, while the cathode electrode may be a common electrode shared by all emission elements.When a driving current is supplied to each of the emission elements ED1 and ED2 via the driving transistor DT and each of the control transistors T6 and T8, electrons are injected from the cathode electrode into the light-emitting layer and holes are injected from the anode electrode into the light-emitting layer, and the fluorescent or phosphorescent material can be emitted by the recombination of the electrons and holes in the light-emitting layer, thereby generating light with a brightness proportional to the current value of the driving current.

[0130] The first emission element ED1 can be driven using the first control transistor T6, which is controlled by the first mode selection signal MS1. Specifically, the first emission element ED1 can be driven by connecting it to the driver transistor DT when the first control transistor T6 is turned on by the first mode selection signal MS1 corresponding to the gate-on voltage. The first lens LZ1, arranged in the light propagation direction of the first emission element ED1, can control the viewing angle to be the first viewing angle.

[0131] The second emission element ED2 can be driven using the second control transistor T8, which is controlled by the second mode selection signal MS2. Specifically, the second emission element ED2 can be driven by connecting it to the driver transistor DT when the second control transistor T8 is turned on by the second mode selection signal MS2 corresponding to the gate-on voltage. The second lens LZ2, arranged in the light propagation direction of the second emission element ED2, can control the viewing angle to be the second viewing angle.

[0132] The display panel 110 according to an exemplary embodiment of the present disclosure can select one of the first viewing angle mode and the second viewing angle mode as the viewing angle mode of each of the subpixels SP1, SP2, and SP3 using the first and second mode selection signals MS1 and MS2. Each of the subpixels SP1, SP2, and SP3 provided in the display panel 110 according to an exemplary embodiment of the present disclosure includes: a first-mode subpixel SP1-1, SP2-1, and SP3-1 having the first viewing angle and including the first emission element ED1; and the second-mode subpixel SP1-2, SP2-2, and SP3-2 having the second viewing angle and including the second emission element ED2.

[0133] In each subpixel SP1, SP2, and SP3, only one of the first emission element ED1 and the second emission element ED2 can emit according to the mode selection signals MS1 and MS2 applied through the first mode selection lines 43 and 44. In each subpixel SP1, SP2, and SP3, when the first control transistor T6 connected to the first emission element ED1 is turned on by the first mode selection signal MS1, the first emission element ED1 and the driving transistor DT are connected so that the first emission element ED1 can emit light. Meanwhile, in each of the subpixels SP1, SP2, and SP3, when the second control transistor T8 connected to the second emission element ED2 is turned on by the second mode selection signal MS2, the second emission element ED2 and the driving transistor DT are connected so that the second emission element ED2 can emit light.In the display panel 110 according to an exemplary embodiment of the present disclosure, only one of the first emission element ED1 and the second emission element ED2 can emit because one of the first mode selection signal MS1 and the second mode selection signal MS2 is the gate-on voltage and the other is the gate-off voltage.

[0134] The first emission element ED1 and the second emission element ED2 provided in the same subpixel SP1, SP2, and SP3 cannot emit simultaneously. The first mode selection signal MS1 can be activated according to the gate-on voltage when the corresponding subpixel is controlled in the first viewing angle mode, the wide viewing angle mode, or the split mode. The first mode selection signal MS1 can be deactivated according to the gate-off voltage when the corresponding subpixel is controlled in the second viewing angle mode, the narrow viewing angle mode, or the privacy mode. On the other hand, the second mode selection signal MS2 can be activated according to the gate-on voltage when the corresponding subpixel is controlled in the second viewing angle mode, the narrow viewing angle mode, or the privacy mode.The second mode selection signal MS2 can be deactivated according to the gate off voltage when the corresponding subpixel is controlled to the first viewing angle mode, the wide viewing angle mode, or the split mode.

[0135] Fig. 7 is a plan view showing an example of a set of scan lines and mode selection lines arranged on a display panel according to an exemplary embodiment of the present disclosure, Fig. 8 is a diagram illustrating an example of a driving waveform for subpixels arranged on a display panel according to an exemplary embodiment of the present disclosure, and Fig. 9 is a diagram showing another example of a driving waveform for subpixels arranged on a display panel according to an exemplary embodiment of the present disclosure. Fig. 10 is a diagram showing various examples in which one frame is temporally divided into a first display driving period and a second display driving period, which are driven when image data is input in frame units.

[0136] With reference to Fig. 7, in the display panel 110 according to an exemplary embodiment of the present disclosure, the first mode selection line 43 and the second mode selection line 44 may extend in a first direction (e.g., X-axis direction) parallel to the first scan line 12. The first mode selection line 43 and the second mode selection line 44 may be arranged on each of the plurality of row lines and connected to the subpixels SP in Fig. 2, which are arranged on the row lines.

[0137] When the subpixels SP are arranged on N row lines, the first scan line 12 may include N first scan lines 12-1, ..., and 12-N arranged on respective ones of the N row lines. The scan driver 122 may sequentially supply a first scan signal SCAN1 to the N first scan lines 12-1, ..., and 12-N. The first scan signal SCAN1 supplied to the N first scan lines 12-1, ..., and 12-N may be supplied to subpixels SP arranged on the corresponding row lines.

[0138] The first mode selection line 43 may include N first mode selection lines 43-1, ..., and 43-N arranged on respective ones of the N row lines. The mode selection driver 126 may sequentially supply the first mode selection signal MS1 to the N first mode selection lines 43-1, ..., and 43-N. The first mode selection signals MS1 supplied to the N first mode selection lines 43-1, ..., and 43-N may be supplied to subpixels SP arranged on the corresponding row lines.

[0139] The second mode selection line 44 may include N second mode selection lines 44-1, ..., and 44-N arranged on respective ones of the N row lines. The mode selection driver 126 may sequentially supply the second mode selection signal MS2 to the N second mode selection lines 44-1, ..., and 44-N. The second mode selection signals MS2 supplied to the N second mode selection lines 44-1, ..., and 44-N may be supplied to subpixels SP arranged on the corresponding row lines.

[0140] Although in Fig. 7, the display panel 110 may further include at least one of the second scan line 16 in Fig. 2 and the emission control line 42 in Fig. 2 extending in the first direction (e.g., in the X-axis direction) parallel to the first scan line 12. The second scan line 16 may include the N second scan lines arranged on respective ones of the N row lines. The scan driver 122 may sequentially supply the second scan signal SCAN2 to the N second scan lines 16. The second scan signals SCAN2 supplied to the N second scan lines 16 may be supplied to subpixels SP arranged on the corresponding row lines.

[0141] Furthermore, the emission control lines 42 may comprise N emission control lines 42 arranged on respective ones of the N row lines. The emission control driver 124 in Fig. 2 may sequentially supply the emission signal EM to the N emission control lines 42. The emission signals EM supplied to the N emission control lines 42 may be supplied to subpixels SP arranged on the corresponding row lines.

[0142] With reference to the Fig. 8 and Fig. 9, in the display panel 110 according to an exemplary embodiment of the present disclosure, a display drive period may be driven temporally divided into a first display drive period DP1 and a second display drive period DP2. The first display drive period DP1 may be a period of displaying the first image by the first-mode subpixels SP1-1, SP2-1, and SP3-1, and the second display drive period DP2 may be a period of displaying the second image by the second-mode subpixels SP1-2, SP2-2, and SP3-2.

[0143] The first display drive period DP1 and the second display drive period DP2 may be synchronized with a plurality of frame periods Frame1, Frame2, Frame3, and Frame4. Each of the plurality of frame periods Frame1, Frame2, Frame3, and Frame4 may be separated in synchronization with a vertical synchronization signal VSYNC and have a plurality of time-separated subframe periods 1-1 subframe, 1-2 subframe, 2-1 subframe, and 2-2 subframe. Some (1-1 subframe and 2-1 subframe) of the plurality of subframe periods 1-1 subframe, 1-2 subframe, 2-1 subframe, and 2-2 subframe may correspond to a first display drive period DP1, and the others (1-2 subframe and 2-2 subframe) may correspond to a second display drive period DP2.

[0144] In the display panel 110 according to an exemplary embodiment of the present disclosure, the first scanning signal SCAN1, the second scanning signal SCAN2, and the emission signal EM may be supplied to the subpixels SP via each of the first scanning line 12, the second scanning line 16, and the emission control line 42 during each of the first display driving period DP1 and the second display driving period DP2.

[0145] The scan driver 122 can sequentially activate the first scan signals SCAN1-1, SCAN1-2, ..., and SCAN1-N applied to the N first scan lines 12-1, ..., and 12-N arranged from the first row line to the Nth row line during each of the first display drive period DP1 and the second display drive period DP2. The first scan signals SCAN1-1, SCAN1-2, ..., and SCAN1-N can be activated with the gate-on voltage.

[0146] As in Fig. As shown in Figure 8, a subframe period of 1-1 subframe, 1-2 subframes, 2-1 subframes, and 2-2 subframes may be equal to a frame period of Frame1, Frame2, Frame3, and Frame4. In this example, the gate-on voltage may be supplied to the subpixels SP in each frame period of Frame1, Frame2, Frame3, and Frame4 as the first scan signal SCAN1-1, SCAN1-2, ..., and SCAN1-N.

[0147] In contrast, as in Fig. As shown in Figure 9, a subframe period 1-1 subframe, 1-2 subframes, 2-1 subframes, and 2-2 subframes correspond to 1 / n of a frame period Frame1, Frame2, Frame3, and Frame4. Here, n can be any even number greater than zero. For example, n can be 2. In this example, the gate-on voltage can be supplied to the subpixels SP every 1 / 2 frame period Frame1, Frame2, Frame3, and Frame4 as the first scan signal SCAN1-1, SCAN1-2, ..., and SCAN1-N.

[0148] When the first scan signals SCAN1-1, SCAN1-2, ... and SCAN1-N are activated with the gate-on voltage, the first switching transistor T1 can be Fig. 6 each of the subpixels SP is switched on to receive the data voltage Vdata, which is fed via the data line 22 into Fig. 6 is supplied to the first electrode of the storage capacitor Cst in Fig. 6 to deliver.

[0149] As in the Fig. 8 and Fig. As shown in Figure 9, the gate-on voltage of the first scan signal SCAN1-1, SCAN1-2, ..., and SCAN1-N may be a low voltage, but is not necessarily limited thereto. The gate-on voltage of the first scan signal SCAN1-1, SCAN1-2, ..., and SCAN1-N may be a high voltage. In this example, the gate-off voltage of the first scan signal SCAN1-1, SCAN1-2, ..., and SCAN1-N may be a low voltage.

[0150] Furthermore, the scan driver 122 may sequentially activate second scan signals SCAN2-1, SCAN2-2, ... and SCAN2-N, which are applied to the N second scan lines 16 in Fig. 2 arranged from the first row wiring to the Nth row wiring during each of the first display drive period DP1 and the second display drive period DP2. The second scan signals SCAN2-1, SCAN2-2, ..., and SCAN2-N can be activated by the gate-on voltage.

[0151] If a subframe period 1-1 subframe, 1-2 subframe, 2-1 subframe and 2-2 subframe is equal to a frame period Frame1, Frame2, Frame3 and Frame4, as in Fig. 8, the gate-on voltage can be supplied to the subpixels SP as the second scanning signal SCAN2-1, SCAN2-2, ..., and SCAN2-N in each frame period Frame1, Frame2, Frame3, and Frame4.

[0152] In contrast, as in Fig. 9, a subframe period 1-1 subframe, 1-2 subframe, 2-1 subframe, and 2-2 subframe correspond to 1 / n of a frame period Frame1, Frame2, Frame3, and Frame4. For example, n may be 2. In this example, the gate-on voltage may be supplied to the subpixels SP every 1 / 2 frame period Frame1, Frame2, Frame3, and Frame4 as the second scanning signals SCAN2-1, SCAN2-2, ..., and SCAN2-N.

[0153] When the second scanning signals SCAN2-1, SCAN2-2, ... and SCAN2-N are activated with the gate-on voltage, the second, fifth and seventh switching transistors T2, T5 and T7 of the subpixel SPs can be Fig. 6. The second switching transistor T2 can connect the driver transistor DT as a diode structure by connecting the gate electrode and the second electrode of the driver transistor DT in response to the gate-on voltage of the second scanning signal SCAN2-1, SCAN2-2, ..., and SCAN2-N. The fifth switching transistor T5 can supply the initialization voltage Vref (or reference voltage), supplied via the initialization voltage line 24, to the anode electrode of the first emission element ED1 in response to the gate-on voltage of the second scanning signal SCAN2-1, SCAN2-2, ..., and SCAN2-N. In addition, the seventh switching transistor T7 can supply the initialization voltage Vref (or reference voltage) supplied via the initialization voltage line 24 to the anode electrode of the second emission element ED2 in response to the gate-on voltage of the second scan signal SCAN2-1, SCAN2-2, ..., and SCAN2-N.

[0154] As in the Fig. 8 and Fig. As shown in Figure 9, the gate-on voltage of the second scan signal SCAN2-1, SCAN2-2, ..., and SCAN2-N may be a low voltage, but is not necessarily limited thereto. The gate-on voltage of the second scan signal SCAN2-1, SCAN2-2, ..., and SCAN2-N may be a high voltage. In this example, the gate-off voltage of the second scan signal SCAN2-1, SCAN2-2, ..., and SCAN2-N may be a low voltage.

[0155] The emission control driver 124 can sequentially activate emission signals EM-1, EM-2, ..., and EM-N applied to the N emission control lines 42 arranged from the first row line to the Nth row line during each of the first display drive period DP1 and the second display drive period DP2. The emission signals EM-1, EM-2, ..., and EM-N can be activated by the gate-on voltage.

[0156] As in Fig. 8, when a subframe period 1-1 subframe, 1-2 subframe, 2-1 subframe and 2-2 subframe is equal to a frame period Frame1, Frame2, Frame3 and Frame4, the gate-on voltage can be supplied to the subpixels SP as emission signals EM-1, EM-2, ..., and EM-N in each frame period Frame1, Frame2, Frame3 and Frame4.

[0157] In contrast, as in Fig. As shown in Figure 9, a subframe period of 1-1 subframe, 1-2 subframe, 2-1 subframe, and 2-2 subframe correspond to 1 / n of a frame period of Frame1, Frame2, Frame3, and Frame4. For example, n may be 2. In this example, the gate-on voltage may be supplied to the subpixels SP as emission signals EM-1, EM-2, ..., and EM-N every 1 / 2 frame period of Frame1, Frame2, Frame3, and Frame4.

[0158] When the emission signals EM-1, EM-2, ..., EM-N are activated with the gate-on voltage, the third and fourth switching transistors T3 and T4 can be Fig. 6, each of the subpixels SP can be turned on. The third switching transistor T3 can supply the initialization voltage Vref (or reference voltage), supplied via the initialization voltage line 24, to the first electrode of the storage capacitor Cst in response to the gate-on voltage of the emission signals EM-1, EM-2, ..., and EM-N. The fourth switching transistor T4 can connect the driver transistor DT and the first or second control transistor T6 or T8 in response to the gate-on voltage of the emission signals EM-1, EM-2, ..., and EM-N.

[0159] As in the Fig. 8 and Fig. As shown in Figure 9, the gate-on voltage of the emission signals EM-1, EM-2, ..., and EM-N may be a low voltage, but is not necessarily limited thereto. The gate-on voltage of the emission signals EM-1, EM-2, ..., and EM-N may be a high voltage. In this example, the gate-off voltage of the emission signals EM-1, EM-2, ..., and EM-N may be a low voltage.

[0160] In the display panel 110 according to an exemplary embodiment of the present disclosure, the first mode selection signal MS1 may be supplied to the subpixels SP via the first mode selection line 43 during the first display drive period DP1. In contrast, in the display panel 110 according to an exemplary embodiment of the present disclosure, the second mode selection signal MS2 may be supplied to the subpixels SP through the second mode selection line 44 during the second display drive period DP2.

[0161] The mode selection driver 126 can sequentially activate the first mode selection signals MS1-1, MS1-2, ..., and MS1-N applied to the N first mode selection lines 43-1, ..., and 43-N arranged from the first row line to the Nth row line during the first display drive period DP1. The first mode selection signals MS1-1, MS1-2, ..., and MS1-N can be activated by the gate-on voltage.

[0162] The first mode selection signals MS1-1, MS1-2, ..., and MS1-N may have a different waveform than the emission signals EM-1, EM-2, ..., and EM1-N. The emission signals EM-1, EM-2, ..., and EM-N may be switched from the gate-off voltage to the gate-on voltage during each of the first display drive period DP1 and the second display drive period DP2, and the gate-on voltage may be applied during the first period. The gate-off voltage may be applied during the remaining periods as emission signals EM-1, EM-2, ..., and EM-N. The first period may be shorter than one frame period (Frame1, Frame2, Frame3, and Frame4), and may be shorter than one subframe period (1-1 subframe, 1-2 subframe, 2-1 subframe, and 2-2 subframe).

[0163] The first mode selection signals MS1-1, MS1-2, ..., and MS1-N, unlike the emission signals EM-1, EM-2, ..., and EM-N, can be switched from the gate-off voltage to the gate-on voltage only during the first display drive period DP1. The gate-on voltage is applied as the first mode selection signals MS1-1, MS1-2, ..., and MS1-N during the second period, and the first mode selection signals MS1-1, MS1-2, ..., and MS1-N can be switched from the gate-on voltage to the gate-off voltage during the second display drive period DP2. The second period can be longer than the first period. The second period can be equal to a subframe period of 1-1 subframe, 1-2 subframes, 2-1 subframes, and 2-2 subframes.

[0164] The first mode selection signals MS1-1, MS1-2, ... and MS1-N may have a periodic waveform in which the gate-on voltage and the gate-off voltage are repeated in units of a subframe. As shown in Fig. As shown in Figure 8, a subframe period of 1-1 subframe, 1-2 subframes, 2-1 subframes, and 2-2 subframes may be equal to one frame period of Frame1, Frame2, Frame3, and Frame4. In this example, the first mode selection signals MS1-1, MS1-2, ..., and MS1-N may be activated with the gate-on voltage for one frame period, switched to the gate-off voltage, and then deactivated with the gate-off voltage for one frame period. That is, the first mode selection signals MS1-1, MS1-2, ..., and MS1-N may be switched from the gate-off voltage to the gate-on voltage every two frame periods of Frame1, Frame2, Frame3, and Frame4 to supply the subpixels SP with the gate-on voltage for one frame period. Furthermore, the first mode selection signals MS1-1, MS1-2, ..., and MS1-N can be switched from the gate-on voltage to the gate-off voltage every two frame periods Frame1, Frame2, Frame3 and Frame4 to supply the gate-off voltage to the subpixels SP for one frame period.

[0165] Alternatively, as in Fig. 9, a subframe period 1-1 subframe, 1-2 subframe, 2-1 subframe, and 2-2 subframe correspond to 1 / n of a frame period Frame1, Frame2, Frame3, and Frame4. In one example, n may be 2. In this example, the first mode selection signals MS1-1, MS1-2, ..., and MS1-N may be activated with the gate-on voltage for a duration of half a frame, switched to the gate-off voltage, and then deactivated with the gate-off voltage for a duration of half a frame. That is, the first mode selection signals MS1-1, MS1-2, ..., and MS1-N can be switched from the gate-off voltage to the gate-on voltage every frame period (Frame1, Frame2, Frame3, and Frame4) to supply the gate-on voltage to the subpixels SP for a duration of half a frame. Furthermore, the first mode selection signals MS1-1, MS1-2, ..., and MS1-N are switched from the gate-on voltage to the gate-off voltage every single frame period Frame1, Frame2, Frame3 and Frame4 to supply the gate-off voltage to the subpixels SP for half a frame period.

[0166] When the first mode selection signals MS1-1, MS1-2, ..., and MS1-N are activated with the gate-on voltage, the first control transistor T6 can be Fig. 6, each of the subpixels SP can be turned on. The first control transistor T6 can be turned on when the first mode selection signals MS1-1, MS1-2, ..., and MS1-N are the gate-on voltage, thereby connecting the driver transistor DT and the first emission element ED1. Accordingly, the first emission element ED1 can be driven by the drive current from the driver transistor DT to emit light.

[0167] As in the Fig. 8 and Fig. As shown in Figure 9, the gate-on voltage of the first mode selection signals MS1-1, MS1-2, ..., and MS1-N may be a low voltage, but is not necessarily limited thereto. The gate-on voltage of the first mode selection signals MS1-1, MS1-2, ..., and MS1-N may be a high voltage. In this example, the gate-off voltage of the first mode selection signals MS1-1, MS1-2, ..., and MS1-N may be a low voltage.

[0168] Furthermore, the mode selection driver 126 may sequentially activate the second mode selection signals MS2-1, MS2-2, ..., and MS2-N applied to the N second mode selection lines 44-1, ..., and 44-N arranged from the first row line to the Nth row line during the second display drive period DP2. The second mode selection signals MS2-1, MS2-2, ..., and MS2-N may be activated by a gate-on voltage.

[0169] The second mode selection signals MS2-1, MS2-2, ..., and MS2-N may have a different waveform than the emission signals EM-1, EM-2, ..., and EM-N. The emission signals EM-1, EM-2, ..., and EM-N may be switched from the gate-off voltage to the gate-on voltage during each of the first display drive period DP1 and the second display drive period DP2, and the gate-on voltage may be applied during the first period. The gate-off voltage may be applied during the remaining periods as emission signals EM-1, EM-2, ..., EN-M. The first period may be shorter than one frame period (Frame1, Frame2, Frame3, and Frame4), and may be shorter than one subframe period (1-1 subframe, 1-2 subframe, 2-1 subframe, and 2-2 subframe).

[0170] The second mode selection signals MS2-1, MS2-2, ..., and MS2-N, unlike the emission signals EM-1, EM-2, ..., and EM-N, can only be switched from the gate-off voltage to the gate-on voltage during the second display drive period DP2. The gate-on voltage can be supplied as the second mode selection signals MS2-1, MS2-2, ..., and MS2-N during the third period, and the second mode selection signals MS2-1, MS2-2, ..., and MS2-N can be switched from the gate-on voltage to the gate-off voltage during the first display drive period DP1. The third period can be longer than the first period. The third period may be equal to one of the subframe periods 1-1 subframe, 1-2 subframe, 2-1 subframe, and 2-2 subframe. Furthermore, the third period may be equal to the second period, which is a gate-on voltage period of the first mode selection signal MS1-1, MS1-2, ..., and MS1-N.

[0171] The second mode selection signals MS2-1, MS2-2, ..., and MS2-N may have a periodic waveform in which the gate-on voltage and the gate-off voltage are repeated in units of a subframe. As shown in Fig. As shown in Figure 8, a subframe period of 1-1 subframe, 1-2 subframes, 2-1 subframes, and 2-2 subframes may be equal to one frame period of Frame1, Frame2, Frame3, and Frame4. In this example, the second mode selection signals MS2-1, MS2-2, ..., and MS2-N may be activated with the gate-on voltage for one frame period, switched to the gate-off voltage, and then deactivated with the gate-off voltage for one frame period. That is, the second mode selection signals MS2-1, MS2-2, ..., and MS2-N may be switched from the gate-off voltage to the gate-on voltage every two frame periods (Frame1, Frame2, Frame3, and Frame4) to supply the subpixels SP with the gate-on voltage for one frame period. The second mode selection signals MS2-1, MS2-2, ..., and MS2-N can also be switched from the gate-on voltage to the gate-off voltage every two frame periods Frame1, Frame2, Frame3 and Frame4 to supply the gate-off voltage to the subpixels SP for one frame period.

[0172] Alternatively, as in Fig. As shown in Figure 9, a subframe period of 1-1 subframe, 1-2 subframe, 2-1 subframe, and 2-2 subframe correspond to 1 / n of a frame period of Frame1, Frame2, Frame3, and Frame4. In one example, n may be 2. In this example, the second mode selection signals MS2-1, MS2-2, ..., and MS2-N may be activated with the gate-on voltage for 1 / 2 frame period, switched to the gate-off voltage, and then deactivated with the gate-off voltage for 1 / 2 frame period. That is, the second mode selection signals MS2-1, MS2-2, ..., and MS2-N can switch from the gate-off voltage to the gate-on voltage every frame period (Frame1, Frame2, Frame3, and Frame4) to supply the gate-on voltage to the subpixels SP for 1 / 2 a frame period. Furthermore, the second mode selection signals MS2-1, MS2-2, ...and MS2-N are switched from the gate-on voltage to the gate-off voltage in each of the frame periods Frame1, Frame2, Frame3 and Frame4 to supply the gate-off voltage to the subpixels SP for 1 / 2 frame period.

[0173] When the second mode selection signals MS2-1, MS2-2, ..., and MS2-N are activated with the gate-on voltage, the second control transistor T8 can be Fig. 6, each of the subpixels SP can be turned on. The second control transistor T8 can be turned on when the second mode selection signals MS2-1, MS2-2, ..., and MS1-N are the gate-on voltage, thereby connecting the driver transistor DT and the second emission element ED2. Accordingly, the second emission element ED2 can be driven by the drive current from the driver transistor DT to emit light.

[0174] As in the Fig. 8 and Fig. As shown in Figure 9, the gate-on voltage of the second mode selection signals MS2-1, MS2-2, ..., and MS2-N may be a low voltage, but is not necessarily limited thereto. The gate-on voltage of the second mode selection signals MS2-1, MS2-2, ..., and MS2-N may be a high voltage. In this example, the gate-off voltage of the second mode selection signals MS2-1, MS2-2, ..., and MS2-N may be a low voltage.

[0175] The first-mode selection signals MS1-1, MS1-2, ..., and MS1-N and the second-mode selection signals MS2-1, MS2-2, ..., and MS2-N have a periodic waveform in which the gate-on voltage and the gate-off voltage are repeated in units of one subframe and may have opposite phases to each other. Accordingly, the first emission element ED1 of the first-mode subpixels SP1-1, SP2-1, and SP3-1 and the second emission element ED2 of the second-mode subpixels SP1-2, SP2-2, and SP3-2 included in the same subpixel SP do not emit simultaneously, and one of them may emit selectively. That is, the first emission element ED1 of the first-mode subpixel SP1-1, SP2-1, and SP3-1 may emit during the first display driving period DP1 and may not emit during the second display driving period DP2.The second emission element ED2 of the second-mode subpixel SP1-2, SP2-2 and SP3-2 can emit during the second display driving period DP2 and not emit during the first display driving period DP1.

[0176] In the display panel 110 according to an exemplary embodiment of the present disclosure, the display drive period may be driven, time-divided into the first display drive period DP1 and the second display drive period DP2. The first mode selection signals MS1-1, MS1-2, ..., and MS1-N are activated during the first display drive period DP1, and the first emission elements ED1 of each of the first mode subpixels SP1-1, SP2-1, and SP3-1 may emit. Accordingly, in the display panel 110 according to an exemplary embodiment of the present disclosure, the first image may be displayed by the first mode subpixels SP1-1, SP2-1, and SP3-1 during the first display drive period DP1. The first image may be an image in the first viewing angle mode, the wide viewing angle mode, or the split mode.

[0177] In contrast, during the second display drive period DP2, the second mode selection signals MS2-1, MS2-2, ..., and MS2-N may be activated so that the second emission elements ED2 may emit each of the second mode subpixels SP1-2, SP2-2, and SP3-2. Accordingly, in the display panel 110 according to an exemplary embodiment of the present disclosure, the second image may be displayed by the second mode subpixels SP1-2, SP2-2, and SP3-2 during the second display drive period DP2. The second image may be an image in the second viewing angle mode, the narrow viewing angle mode, or the privacy mode.

[0178] The display panel 110 according to an exemplary embodiment of the present disclosure may receive the first pixel data for the first image and the second pixel data for the second image from the timing controller 160.

[0179] In particular, according to an exemplary embodiment of the present disclosure, the display panel 110 may supply a data voltage corresponding to the first pixel data to the first-mode subpixels SP1-1, SP2-1, and SP3-1 via the data line 22 during the first display drive period DP1.

[0180] Further, according to an exemplary embodiment of the present disclosure, during the second display drive period DP2, the display panel 110 may supply data voltages corresponding to the second pixel data to the second-mode subpixels SP1-2, SP2-2, and SP3-2 via the data lines 22.

[0181] As in Fig. As shown in Figure 10, according to an exemplary embodiment of the present disclosure, the display panel 110 may receive a frame of image data at a rate of 60 Hz from the timing controller 160. In this example, the image data may include the first pixel data and the second pixel data.

[0182] In contrast, the display panel 110 according to an exemplary embodiment of the present disclosure may output the first pixel data and the second pixel data to the subpixels SP at a rate of 120 Hz, which is twice as fast as the rate at which the image data is input. In the display panel 110 according to an exemplary embodiment of the present disclosure, the first display drive period DP1 and the second display drive period DP2 may operate to be delayed by half a frame compared to the input of the image data. This is to prevent the input points I1, at which the image data for each row wiring is input, from intersecting the start points S1 or S2, at which the image data for each row wiring is output when the image data of one frame is input.

[0183] Each of the first display drive period DP1 and the second display drive period DP2 may have a period shorter than the frame period in which the image data is input. For example, as shown in Fig. 10, each of the first display drive period DP1 and the second display drive period DP2 has a period half as long as the period of the frame in which the image data is input.

[0184] As in case 1 of Fig. 10, in the display panel 110 according to an exemplary embodiment of the present disclosure, the first display drive period DP1 may operate to be delayed by half a frame compared to the input of the image data, and then the second display drive period DP2 may operate. In this example, the display panel 110 according to an exemplary embodiment of the present disclosure may output the first pixel data row by row during the first display drive period DP1. In the display panel 110 according to an exemplary embodiment of the present disclosure, the first-mode sub-pixels SP1-1, SP2-1, and SP3-1 are supplied with the first pixel data to display the first image. At this time, the start points S1 at which the first pixel data is output for each row wiring may not overlap with the input points I1 at which the image data is input for each row wiring.

[0185] Subsequently, the display panel 110 according to an exemplary embodiment of the present disclosure may output the second pixel data for each row wiring during the second display drive period DP2. In the display panel 110 according to an exemplary embodiment of the present disclosure, the second-mode subpixels SP1-2, SP2-2, and SP3-2 are supplied with the second pixel data to display the second image. At this time, the starting points S2 at which the second pixel data for each row wiring is output must not intersect with the input points I1 at which the image data for each row wiring is input.

[0186] In the display panel 110 according to an exemplary embodiment of the present disclosure, since the first pixel data can be output during a first display drive period DP1 and the second pixel data can be output during a second display drive period DP2, an image corresponding to one frame of image data input from the timer controller 160 can be displayed.

[0187] Alternatively, as in case 2 of Fig. 10, in the display panel 110 according to an exemplary embodiment of the present disclosure, the second display drive period DP2 may operate to be delayed by half a frame compared to the input of the image data, and then the first display drive period DP1 may operate. In this example, the display panel 110 according to an exemplary embodiment of the present disclosure may output the second pixel data for each row line during the second display drive period DP2. In the display panel 110 according to an exemplary embodiment of the present disclosure, the second-mode sub-pixels SP1-2, SP2-2, and SP3-2 are supplied with the second pixel data to display the second image.At this time, the starting points S2, where the second pixel data for each row line is output, must not overlap with the input points I1, where the image data for each row line is input.

[0188] Then, the display panel 110 according to an exemplary embodiment of the present disclosure may output the first pixel data for each row wiring during the first display drive period DP1. In the display panel 110 according to an exemplary embodiment of the present disclosure, the first-mode subpixels SP1-1, SP2-1, and SP3-1 are supplied with the first pixel data to display the first image. At this time, the starting points S1 at which the first pixel data for each row wiring is output must not overlap with the input points I1 at which the image data for each row wiring is input.

[0189] In the display panel 110 according to an exemplary embodiment of the present disclosure, an image corresponding to one frame of image data input from the timer controller 160 can be displayed because the second pixel data can be output during a second display drive period DP2 and the first pixel data can be output during a first display drive period DP1.

[0190] Case 1 and Case 2 of Fig. 10 show that a rate at which the image data is input and a rate at which the first pixel data and the second pixel data are output to the subpixel SPs are different, but are not necessarily limited thereto. As another example, as in Case 3 of Fig. 10, according to an exemplary embodiment of the present disclosure, the display panel 110 may output the first pixel data and the second pixel data to the subpixel SPs at a rate of 60 Hz, which corresponds to the rate at which the image data is input.

[0191] In addition, Case 1 and Case 2 of Fig. 10, each of the first display drive period DP1 and the second display drive period DP2 has a period of half the frame period in which the image data is input, but is not necessarily limited thereto. As another example, as in Case 4 of Fig. 10, in the display panel 110 according to an exemplary embodiment of the present disclosure, each of the first display drive period DP1 and the second display drive period DP2 has a period of one-quarter of the frame period in which the image data is input.

[0192] In this example, in the display panel 110 according to an exemplary embodiment of the present disclosure, the first display drive period DP1 and the second display drive period DP2 may operate to be delayed by three-quarters of a frame compared to the input of the image data. This is to prevent the timing input points I1 at which the image data for each row line is input from intersecting the starting points S1 or S2 at which the image data for each row line is output.

[0193] As in case 4 of Fig. As shown in Figure 10, in the display panel 110 according to an exemplary embodiment of the present disclosure, the first display drive period DP1 may operate with a delay of three-quarters of a frame compared to the input of the image data, and then the second display drive period DP2 may operate. Then, the first display drive period DP1 may be operated again, followed by the second display drive period DP2.

[0194] The display panel 110 according to an exemplary embodiment of the present disclosure can display an image corresponding to one frame of image data input from the timing controller 160 by outputting the same first pixel data in two first display drive periods DP1 and outputting the same second pixel data in two second display drive periods DP2.

[0195] In contrast, according to an exemplary embodiment of the present disclosure, the display panel 110 may implement a portion of the display area DA in the first viewing angle mode, the wide viewing angle mode, or the split mode, and the remaining portion in the second viewing angle mode, the narrow viewing angle mode, or the privacy mode using the first pixel data and the second pixel data. This will be explained below with reference to Fig. 11 to 14B.

[0196] Fig. 11 is a plan view showing an example of mode selection lines and data lines arranged on a display panel according to an exemplary embodiment of the present disclosure.

[0197] With reference to Fig. 11, the display panel 110 according to an exemplary embodiment of the present disclosure may include the first mode selection line 43 and the second mode selection line 44 extending in the first direction (e.g., in the X-axis direction). The first mode selection line 43 and the second mode selection line 44 may be arranged on respective ones of a plurality of row lines and connected to subpixels SP in Fig. 2, which are arranged on the row lines.

[0198] The first mode selection line 43 may be supplied with the first mode selection signal from the mode selection driver 126. The second mode selection line 44 may be supplied with the second mode selection signal from the mode selection driver 126. The first mode selection signal may be activated during the first display drive period DP1 and deactivated during the second display drive period DP2. The second mode selection signal may be activated during the second display drive period DP2 and deactivated during the first display drive period DP1.

[0199] In contrast, according to an exemplary embodiment of the present disclosure, the display panel 110 may include data lines 22 extending in the second direction (e.g., in the Y-axis direction). The data lines 22 may be arranged on respective ones of the plurality of column lines and may be connected to subpixels SP arranged on the column lines in Fig. 2 be connected.

[0200] Data line 22 may receive a data voltage Vdata from data driver IC 131. Data driver IC 131 may receive the pixel data and the data control signals from timing controller 160. In this example, the pixel data may include the first pixel data for the first-mode subpixels SP1-1, SP2-1, and SP3-1 and the second pixel data for the second-mode subpixels SP1-2, SP2-2, and SP3-2.

[0201] The timing controller 160 may generate the first pixel data and the second pixel data using digital video data input from the external host system. In one example, the external host system may transmit first digital video data including information about the first image and second digital video data including information about the second image to the timing controller 160. In this example, the timing controller 160 may align and convert the first digital video data into the first pixel data. The timing controller 160 may align and convert the second digital video data into the second pixel data. The timing controller 160 may provide the first pixel data and the second pixel data, along with the data control signal, to the data driver IC 131.

[0202] In another example, the external host system may transmit to the timing controller 160 a set of digital video data that integrates a first video and a second video, along with position information of an area where the first image or the second image is displayed. In this example, the timing controller 160 may convert the digital video data into the first pixel data and the second pixel data using the position information of the area where the first image or the second image is displayed. The timing controller 160 may supply the first pixel data and the second pixel data to the data driver IC 131 with a data control signal.

[0203] The data driver IC 131 can convert the first pixel data and the second pixel data into analog positive / negative data voltages Vdata using the data control signals and supply them to the subpixels SP via the data lines 22.

[0204] The data driver IC 131 may supply a data voltage corresponding to the first pixel data to each of the plurality of column lines during the first display drive period DP1. Furthermore, the data driver IC 131 may supply a data voltage corresponding to the second pixel data to each of the plurality of column lines during the second display drive period DP2.

[0205] Fig. 12A is a diagram showing an example of a first mode display area and a second mode display area, Fig. 12B is a diagram showing an example of first pixel data input in a first display drive period, and Fig. 12C is a diagram showing an example of second pixel data input in the second display driving period.

[0206] In the Fig. 12A to 12C, it is assumed that 24 subpixel SPs are arranged in the display area DA for simplifying the description. The display area DA may include a first-mode display area DA1 for displaying the first image by the first-mode subpixels SP1-1, SP2-1, and SP3-1, and a second-mode display area DA2 for displaying the second image by the second-mode subpixels SP1-2, SP2-2, and SP3-2. The first-mode display area DA1 may be an area implemented in the first-view angle mode, the wide-view angle mode, or the split mode. The second-mode display area DA2 may be implemented in the second-view angle mode, the narrow-view angle mode, or the privacy mode.

[0207] The first mode display area DA1 and the second mode display area DA2 may not overlap each other and may have different sizes. Fig. 12A to 12C show that both the first mode display area DA1 and the second mode display area DA2 are included, but are not necessarily limited thereto. In another example, the display area DA may include only the first mode display area DA1 or only the second mode display area DA2. The display area DA may include at least one of the first mode display area DA1 and the second mode display area DA2, depending on the user's selection or settings. Furthermore, the first mode display area DA1 and the second mode display area DA2 may be unfixed in position and size and may be determined by the user's selection or setting.

[0208] As in Fig. 12A, the display panel 110 may designate the area where the center four subpixels SP are arranged as the second-mode display area DA2, and the area where the remaining subpixels SP are arranged as the first-mode display area DA1, according to the user selection or user setting.

[0209] The display panel 110 may supply a data voltage corresponding to the first pixel data to the first-mode subpixels SP1-1, SP2-1, and SP3-1 during the first display drive period. The first pixel data may include pixel data for displaying the first image for the first-mode subpixels SP1-1, SP2-1, and SP3-1 of each of the subpixels arranged in the first-mode display area DA1. On the other hand, the first pixel data may be as shown in Fig. 12B, black data for the first-mode subpixels SP1-1, SP2-1, and SP3-1 of each of the four subpixel SPs arranged in the second-mode display area DA2 may be "0." Thus, the second-mode display area DA2 can only display a black image during the first display drive period. That is, the display panel 110 cannot display an image in the second-mode display area DA2 during the first display drive period.

[0210] On the other hand, during the second display drive period, the display panel 110 may supply a data voltage corresponding to the second pixel data to the second-mode subpixels SP1-2, SP2-2, and SP3-2. The second pixel data may include pixel data for displaying the second image for the second-mode subpixels SP1-2, SP2-2, and SP3-2 of each of the subpixels arranged in the second-mode display area DA2. In contrast, the second pixel data may be as shown in Fig. 12C, black data for the second-mode subpixels SP1-2, SP2-2, and SP3-2 of each of the subpixels SP located in the first-mode display area DA1 may be provided. The black data may be "0." Thus, the first-mode display area DA1 can only display a black image during the second display operation period. That is, the display panel 110 cannot display an image in the first-mode display area DA1 during the second display operation period.

[0211] As a result, in the display panel 110, during the first display drive period and the second display drive period, the first image can be repeatedly and alternately displayed by the first-mode subpixels SP1-1, SP2-1, and SP3-1 in the first-mode display area DA1, and the second image can be repeatedly and alternately displayed by the second-mode subpixels SP1-2, SP2-2, and SP3-2 in the second-mode display area DA2. The first image is displayed by the first-mode subpixels SP1-1, SP2-1, and SP3-1 in the first-mode display area DA1, so that the first viewing angle mode, the wide viewing angle mode, or the split mode can be implemented. The second-mode display area DA2 can display the second image by the second-mode subpixels SP1-2, SP2-2, and SP3-2, thereby implementing the second viewing angle mode, the narrow viewing angle mode, or the privacy mode.

[0212] Fig. 13A is a diagram showing another example of a first mode display area and a second mode display area, Fig. 13B is a diagram showing another example of first pixel data input in the first display drive period, and Fig. 13C is a diagram showing another example of second pixel data input in the second display driving period.

[0213] As in Fig. 13A, in the display panel 110, an area where the 12 subpixel SPs are arranged on the left side may be designated as the first mode display area DA1, and an area where the 12 subpixel SPs are arranged on the right side may be designated as the second mode display area DA2, depending on the selection or setting by the user.

[0214] The display panel 110 may supply a data voltage corresponding to the first pixel data to the first-mode subpixels SP1-1, SP2-1, and SP3-1 during the first display drive period. The first pixel data may include pixel data for displaying the first image for the first-mode subpixels SP1-1, SP2-1, and SP3-1 of each of the twelve subpixels on the left side arranged in the first-mode display area DA1. In contrast, as shown in Fig. 13B, the first pixel data includes black data for the first-mode subpixels SP1-1, SP2-1, and SP3-1 of each of the twelve subpixel SPs on the right side arranged in the second-mode display area DA2. The black data may be "0." Thus, the second-mode display area DA2 can only display a black image during the first display drive period. That is, the display panel 110 cannot display an image in the second-mode display area DA2 during the first display drive period.

[0215] Meanwhile, the display panel 110 may supply a data voltage corresponding to the second pixel data to the second-mode subpixels SP1-2, SP2-2, and SP3-2 during the second display drive period. The second pixel data may include pixel data for displaying the second image for the second-mode subpixels SP1-2, SP2-2, and SP3-2 of each of the twelve subpixels on the left side arranged in the second-mode display area DA2. On the other hand, the second pixel data may be as shown in Fig. 13C, black data for the second-mode subpixel SP1-2, SP2-2, and SP3-2 of each of the twelve subpixel SPs on the right arranged in the first-mode display area DA1 may be included. The black data may be "0." Thus, the first-mode display area DA1 can only display a black image during the second display operation period. That is, the display panel 110 cannot display an image in the first-mode display area DA1 during the second display operation period.

[0216] As a result, in the display panel 110, during the first display drive period and the second display drive period, the first image can be alternately and repeatedly displayed by the first-mode subpixels SP1-1, SP2-1, and SP3-1 in the first-mode display area DA1, and the second image can be displayed by the second-mode subpixels SP1-2, SP2-2, and SP3-2 in the second-mode display area DA2. The first image is displayed by the first-mode subpixels SP1-1, SP2-1, and SP3-1 in the first-mode display area DA1, so that the first-viewing-angle mode, the wide-viewing-angle mode, or the split mode can be implemented. The second-mode display area DA2 can display the second image by the second-mode subpixels SP1-2, SP2-2, and SP3-2, thereby implementing the second-viewing-angle mode, the narrow-viewing-angle mode, or the privacy mode.

[0217] With reference to the Fig. 14A and Fig. 14B, an example of a drive waveform during the first display drive period and the second display drive period will be described in detail below.

[0218] Fig. 14A is a diagram showing another example of a first mode display area and a second mode display area, and Fig. 14B is a diagram showing an example of a driving waveform for the Fig. 14A shows the subpixels shown.

[0219] In the Fig. 14A and Fig. 14B, it is assumed that 16 subpixel SPs are arranged in the display area DA to simplify the description. Four subpixel SPs may be arranged on each of the four row lines. The display panel 110 may include four first-mode selection lines 43-1, 43-2, 43-3, and 43-4 extending in the first direction, four second-mode selection lines 44-1, 44-2, 44-3, and 44-4 extending in the first direction, and four data lines 22-1, 22-2, 22-3, and 22-4 extending in the second direction.

[0220] Four first-mode selection lines 43-1, 43-2, 43-3, and 43-4 are arranged on each of the four row lines and can supply the first-mode selection signals MS1-1, MS1-2, MS1-3, and MS1-4 to the subpixel SPs arranged on the row lines. Furthermore, four second-mode selection lines 44-1, 44-2, 44-3, and 44-4 are arranged on each of the four row lines and can supply the second-mode selection signals MS2-1, MS2-2, MS2-3, and MS2-4 to the subpixel SPs arranged on the row lines.

[0221] Meanwhile, four data lines 22-1, 22-2, 22-3 and 22-4 are arranged on each of the four column lines and can supply data voltages to the subpixels SP arranged on the column lines.

[0222] The first mode selection signals MS1-1, MS1-2, MS1-3, and MS1-4 applied via each of the four first mode selection lines 43-1, 43-2, 43-3, and 43-4 can be activated by the gate-on voltage sequentially supplied during the first display drive period DP1. The first mode selection signal MS1-1 applied via the first mode selection line 43-1, which is located at the top among the first mode selection lines, can be activated with the gate-on voltage, and the gate-on voltage can be supplied for one frame period. The first control transistor T6 in Fig. 6 can be turned on by the gate-on voltage of the first mode selection signal MS1-1 in the subpixels SP11, SP12, SP13 and SP14 arranged on the first row line, and thus the driver transistor DT in Fig. 6 and the first emission element ED1 in Fig. 6 of the first-mode subpixel. Accordingly, the first emission element ED1 can be driven by the drive current from the drive transistor DT to emit light. At this time, the second-mode selection signal MS2-1 applied via the first second-mode selection line 44-1, which is located at the top among the second-mode selection lines, can be deactivated with the gate-off voltage, and the gate-off voltage can be supplied for one frame period. The second-mode selection signal MS2-1 applied via the second-mode selection line 44-1 can have an opposite phase to the first-mode selection signal MS1-1 applied via the first-mode selection line 43-1.

[0223] Next, the first mode selection signals MS1-2 applied via the first mode selection line 43-2, which is arranged second from the top among the first mode selection lines, are shifted by the line width to be activated by the gate-on voltage, and the gate-on voltage can be supplied for one frame period. The first control transistor T6 in Fig. 6 can be turned on by the gate-on voltage of the first mode selection signals MS1-2 in the subpixels SP21, SP22, SP23 and SP24 arranged on the second row line, and thus the driver transistor DT in Fig. 6 and the first emission element ED1 in Fig. 6 of the first-mode subpixel. Accordingly, the first emission element ED1 can be driven by the drive current from the drive transistor DT to emit light. At this time, the second-mode selection signal MS2-2 applied via the second-mode selection line 44-2, which is arranged second from the top among the second-mode selection lines, can be deactivated with the gate-off voltage, and the gate-off voltage can be supplied for one frame period. The second-mode selection signal MS2-2 applied via the second-mode selection line 44-2 may have an opposite phase to the first-mode selection signal MS1-2 applied via the first-mode selection line 43-2.

[0224] Then, the first mode selection signals MS1-3 supplied through the first mode selection line 43-3, which are arranged third from the top among the first mode selection signals, are shifted by the line width to be activated with the gate-on voltage, and the gate-on voltage can be supplied for one frame period. Then, the first mode selection signal MS1-4 supplied through the first mode selection line 43-4, which is arranged fourth from the top among the first mode selection signals, can be shifted by the line width to be activated with the gate-on voltage, and the gate-on voltage can be supplied for one frame period.

[0225] The four data lines 22-1, 22-2, 22-3, and 22-4 can supply data voltages to the first-mode subpixels of the subpixels SP arranged on each of the four column lines during the first display drive period DP1. The first data line 22-1 can sequentially supply data voltages to the subpixels SP11, SP21, SP31, and SP41 arranged on the first column line. Since the subpixels SP11, SP21, SP31, and SP41 arranged on the first column line are all included in the second-mode display area DA2, the first data line 22-1 can supply a data voltage corresponding to black data to the subpixels SP11, SP21, SP31, and SP41 arranged on the first column line during the first display drive period DP1. That is, the first data line 22-1 can supply a data voltage corresponding to “0” to the subpixels SP11, SP21, SP31 and SP41 arranged on the first column line.

[0226] The second data line 22-2 can sequentially supply data voltages to the subpixels SP12, SP22, SP32, and SP42 arranged on the second column line. The fourth data line 22-4 can also sequentially supply data voltages to the subpixels SP14, SP24, SP34, and SP44 arranged on the fourth column line. The subpixels SP12, SP22, SP32, and SP42 arranged on the second column line and the subpixels SP14, SP24, SP34, and SP44 arranged on the fourth column line are all included in the second-mode display area DA2. Accordingly, the second data line 22-2 and the fourth data line 22-4 can supply a data voltage corresponding to black data to the subpixels SP12, SP22, SP32, and SP42 arranged on the second column line and to the subpixels SP14, SP24, SP34, and SP44 arranged on the fourth column line during the first display drive period DP1.That is, the second data line 22-2 and the fourth data line 22-4 can supply a data voltage corresponding to "0" to the subpixels SP12, SP22, SP32 and SP42 arranged on the second column line and to the subpixels SP14, SP24, SP34 and SP44 arranged on the fourth column line.

[0227] The third data line 22-3 can sequentially supply data voltages to the subpixels SP13, SP23, SP33, SP43 arranged on the third column line. Of the subpixels SP13, SP23, SP33, and SP43 arranged on the third column line, some subpixels SP23 and SP33 are included in the first-mode display area DA1, while the other subpixels SP13 and SP43 are included in the second-mode display area DA2. Accordingly, the third data line 22-3 can supply data voltages corresponding to pixel values ​​for displaying the first image to some subpixels SP23 and SP33 arranged on the third column line during the first display drive period DP1. Furthermore, the third data line 22-3 can supply a data voltage corresponding to black data to the other subpixels SP13 and SP43 arranged on the third column line during the first display drive period DP1.That is, the third data line 22-3 can supply a data voltage corresponding to “0” to the other subpixels SP13 and SP43 arranged on the third column line.

[0228] After the first display drive period DP1, the display panel 110 can be operated in the second display drive period DP2. The second mode selection signals MS2-1, MS2-2, MS2-3, and MS2-4 applied via each of the four second mode selection lines 44-1, 44-2, 44-3, and 44-4 can be activated by sequentially supplying them with the gate-on voltage during the second display operation period DP2. The second mode selection signal MS2-1 applied via the second mode selection line 44-1, which is located at the top among the second mode selection lines, can be activated with the gate-on voltage, and the gate-on voltage can be supplied for one frame period. The second control transistor T8 in Fig. 6 can be turned on by the gate-on voltage of the second mode selection signal MS2-1 in the subpixels SP11, SP12, SP13 and SP14 arranged on the first row line, and thus the driver transistor DT in Fig. 6 and the second emission element ED2 in Fig. 6 of the second-mode subpixel. Accordingly, the second emission element ED2 can be driven by the drive current from the drive transistor DT to emit light. At this time, the first-mode selection signal MS1-1 applied via the first-mode selection line 43-1, which is located at the top among the first-mode selection lines, can be deactivated with the gate-off voltage, and the gate-off voltage can be applied for one frame period. The first-mode selection signal MS1-1 applied via the first-mode selection line 43-1 can have an opposite phase to the second-mode selection signal MS2-1 applied via the second-mode selection line 44-1.

[0229] Next, the second mode selection signal MS2-2, which is applied through the second mode selection line 44-2, which is arranged second from the top among the second mode selection lines, is shifted by the line width to be activated with the gate-on voltage, and the gate-on voltage can be supplied for one frame period. The eighth control transistor T8 in Fig. 6 can be turned on by the gate-on voltage of the second mode selection signal MS2-2 in the subpixels SP21, SP22, SP23 and SP24 arranged on the second row line, and thus the driver transistor DT in Fig. 6 and the second emission element ED2 in Fig.6 of the second-mode subpixel. Accordingly, the second emission element ED2 can be driven by the drive current from the drive transistor DT to emit light. At this time, the first mode selection signals MS1-2 applied via the first mode selection line 43-2 arranged second from the top among the first mode selection lines can be deactivated with the gate off voltage, and the gate off voltage can be applied for one frame period. The first mode selection signals MS1-2 applied via the first mode selection line 43-2 can have an opposite phase to the second mode selection signals MS2-2 applied via the second mode selection line 44-2.

[0230] Then, the second mode selection signal MS2-3, applied through the second mode selection line 44-3 located third from the top among the second mode selection lines, is shifted by the line width to be activated with the gate-on voltage, and the gate-on voltage can be supplied for one frame period. Then, the second mode selection signal MS2-4, applied through the second mode selection line 44-4 located fourth from the top among the second mode selection lines, is shifted by the line width to be activated with the gate-on voltage, and the gate-on voltage can be supplied for one frame period.

[0231] The four data lines 22-1, 22-2, 22-3, and 22-4 can supply data voltages to the second-mode subpixels of the subpixels SP arranged on each of the four column lines during the second display drive period DP2. The first data line 22-1 can sequentially supply data voltages to the subpixels SP11, SP21, SP31, and SP41 arranged on the first column line. Since the subpixels SP11, SP21, SP31, and SP41 arranged on the first column line are all included in the second-mode display area DA2, the first data line 22-1 can supply data voltages corresponding to pixel values ​​for displaying the second image to the subpixels SP11, SP21, SP31, and SP41 arranged on the first column line during the second display drive period DP2.

[0232] The second data line 22-2 can sequentially supply data voltages to the subpixels SP12, SP22, SP32, and SP42 arranged on the second column line. The fourth data line 22-4 can also sequentially supply data voltages to the subpixels SP14, SP24, SP34, and SP44 arranged on the fourth column line. The subpixels SP12, SP22, SP32, and SP42 arranged on the second column line and the subpixels SP14, SP24, SP34, and SP44 arranged on the fourth column line are all included in the second-mode display area DA2. Accordingly, the second data line 22-2 and the fourth data line 22-4 can supply data voltages corresponding to pixel values ​​for displaying the second image to the subpixels SP12, SP22, SP32, and SP42 arranged on the second column line and the subpixels SP14, SP24, SP34, and SP44 arranged on the fourth column line during the second display drive period DP2.

[0233] The third data line 22-3 can sequentially supply data voltages to the subpixels SP13, SP23, SP33, and SP43 arranged on the third column line. Among the subpixels SP13, SP23, SP33, and SP43 arranged on the third column line, some subpixels SP23 and SP33 are included in the first-mode display area DA1, while the other subpixels SP13 and SP43 are included in the second-mode display area DA2. Accordingly, the third data line 22-3 can supply a data voltage corresponding to black data to the some subpixels SP23 and SP33 arranged on the third column line during the second display drive period DP2. Furthermore, the third data line 22-3 may supply data voltages corresponding to pixel values ​​for displaying the second image to the other subpixels SP13 and SP43 arranged on the third column line during the second display drive period DP2.

[0234] The display panel 110 according to an exemplary embodiment of the present disclosure may control the first-mode display area DA1 and the second-mode display area DA2 using data output to the subpixels SP during the first display drive period DP1 and the second display drive period DP2. The pixel data for displaying the first image in the first-mode display area DA1 may be output during the first display drive period DP1, and black data may be output to the subpixels SP arranged in the second-mode display area DA2. Accordingly, the display panel 110 according to an exemplary embodiment of the present disclosure may ensure that the first image for the first viewing angle mode is not displayed in the second-mode display area DA2 and that the first image is displayed only in the first-mode display area DA1.

[0235] In contrast, during the second display drive period DP2, pixel data for displaying the second image may be output in the second-mode display area DA2, and black data may be output to the subpixels SP arranged in the first-mode display area DA1. Accordingly, the display panel 110 according to an exemplary embodiment of the present disclosure may ensure that the second image for the second viewing angle mode is not displayed in the first-mode display area DA1 and that the second image is displayed only in the second-mode display area DA2.

[0236] Thus, in the display panel 110 according to an exemplary embodiment of the present disclosure, the position and area of ​​each of the first mode display area DA1 and the second mode display area DA2 can be freely set using the pixel data output to the subpixels SP during the first display drive period DP1 and the second display drive period DP2.

[0237] Furthermore, according to an exemplary embodiment of the present disclosure, the display panel 110 is capable of controlling the viewing angle on a subpixel SP basis, enabling fine control of the viewing angle within the display area DA.

[0238] Furthermore, the display panel 110 according to an exemplary embodiment of the present disclosure can use the two mode selection signals MS1 and MS2 generated in the display panel 110 to control the viewing angle mode of the subpixels. The display panel 110 according to an exemplary embodiment of the present disclosure can minimize externally incoming signals, and the number of signal lines connected to the outside world can be greatly reduced.

[0239] The display panel 110 according to an exemplary embodiment of the present disclosure can control the viewing angle mode of each of the subpixels SP using a minimal number of signal lines. Accordingly, the display panel 110 according to an exemplary embodiment of the present disclosure can reduce production energy and greenhouse gas generation by reducing the number of signal lines, thereby implementing ESG (Environmental / Social / Governance) considerations.

[0240] Since the viewing angle mode areas can be controlled using data, in one or more aspects of the present disclosure, the position and range of the viewing angle mode areas can be freely adjusted.

[0241] Furthermore, in one or more aspects of the present disclosure, the viewing angle may be controlled in sub-pixel units, wherein the viewing angle may be precisely controlled within the display area.

[0242] Furthermore, in one or more aspects of the present disclosure, by using two mode selection signals generated within the display panel to control the viewing angle mode of the subpixel, external signal inputs can be minimized. Accordingly, in one or more aspects of the present disclosure, the number of signal lines connected to the outside world can be significantly reduced.

[0243] Furthermore, in one or more aspects of the present disclosure, by reducing the number of signal lines formed in the display panel, energy consumption in production and the generation of greenhouse gases can be reduced, thereby implementing ESG (Environmental / Social / Governance). QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2023-0169375

[0001]

Claims

[1] Display device (100) comprising: a display panel (110) provided with a plurality of subpixels (SP1, SP2, SP3) for displaying images in a display drive period, wherein each of the plurality of subpixels (SP1, SP2, SP3) comprises: a first-mode subpixel (SP1-1, SP2-1, SP3-1) having a first viewing angle and comprising a first light-emitting element (ED1); a second-mode subpixel (SP1-2, SP2-2, SP3-2) having a second viewing angle and comprising a second light-emitting element (ED2); a driver transistor (DT) connected to the first light emitting element (ED1) or the second light emitting element (ED2); a first mode selection line (43) extending in a first direction and providing a first mode selection signal (MS1); a second mode selection line (44) extending in the first direction and providing a second mode selection signal (MS2); a first control transistor (T6) for controlling a connection between the first light-emitting element (ED1) and the driver transistor (DT) based on the first mode selection signal (MS1); and a second control transistor (T8) for controlling a connection between the second light-emitting element (ED2) and the driver transistor (DT) based on the second mode selection signal (MS2), wherein the display drive period is to be divided in time into a first display drive period (DP1) and a second display drive period (DP2), and wherein the first light emitting element (ED1) is configured to be connected to the driver transistor (DT) in the first display driving period (DP1), and the second light emitting element (ED2) is configured to be connected to the driver transistor (DT) in the second display driving period (DP2). [2] The display device (100) according to claim 1, wherein a gate-on voltage is to be supplied as the first mode selection signal (MS1) in the first display drive period (DP1) and the gate-on voltage is to be supplied as the second mode selection signal (MS2) in the second display drive period (DP2). [3] The display device (100) according to claim 1 or 2, wherein each of the first mode selection signal (MS1) and the second mode selection signal (MS2) is a signal in which a gate-on voltage and a gate-off voltage are provided to be repeated in subframe units. [4] The display device (100) according to claim 3, wherein a period of each of the subframe units is equal to a period of a frame period or corresponds to 1 / n of a frame period, where n is an even number greater than 0. [5] The display device (100) according to any one of claims 1 to 4, wherein the first mode selection signal (MS1) and the second mode selection signal (MS2) have opposite phases to each other. [6] Display device (100) according to one of claims 1 to 5, further comprising: an emission control line (42) for supplying an emission signal (EM); and a switching transistor (T4) for controlling a connection between the driver transistor (DT) and the first control transistor (T6) and between the driver transistor (DT) and the second control transistor (T8) based on the emission signal (EM). [7] The display device (100) according to claim 6, wherein a gate-on voltage is to be applied as the emission signal (EM) during a first period in each of the first display drive period (DP1) and the second display drive period (DP2). [8] Display device (100) according to claim 7, wherein the gate-on voltage is provided for application as the first mode selection signal (MS1) during a second period longer than the first period in the first display drive period (DP1), and wherein the gate-on voltage is provided for application as the second mode selection signal (MS2) during a third period longer than the first period in the second display drive period (DP2). [9] Display device (100) according to one of claims 1 to 8, further comprising: a data line (22) extending in a second direction for supplying a data voltage (Vdata) to the first-mode subpixel (SP1-1, SP2-1, SP3-1) in the first display drive period (DP1) and for providing a data voltage (Vdata) to the second-mode subpixel (SP1-2, SP2-2, SP3-2) in the second display drive period (DP2). [10] Display device (100) according to claim 9, wherein the display panel (110) has a display area (DA) in which the plurality of subpixels (SP1, SP2, SP3) are arranged, wherein the display area (DA) has a first-mode display area (DA1) for displaying a first image by the first-mode subpixel (SP1-1, SP2-1, SP3-1) and a second-mode display area (DA2) for displaying a second image by the second-mode subpixel (SP1-2, SP2-2, SP3-2), wherein the data line (DL) is configured to supply a data voltage (Vdata) corresponding to black data to the first-mode subpixel (SP1-1, SP2-1, SP3-1) arranged in the second-mode display area (DA2) in the first display drive period (DP1) and to supply a data voltage (Vdata) corresponding to black data to the second-mode subpixel (SP1-2, SP2-2, SP3-2) arranged in the first-mode display area (DA1) in the second display drive period (DP2). [11] The display device (100) according to any one of claims 1 to 10, wherein the first viewing angle and the second viewing angle differ in at least one direction and one angular range. [12] Display device (100) according to one of claims 1 to 11, further comprising: a first mode selection driver arranged in a non-display area (NDA) for supplying the first mode selection signal (MS1) to the first mode selection line (43); and a second mode selection driver arranged on one side of the first mode selection driver in the non-display area (NDA) for supplying the second mode selection signal (MS2) to the second mode selection line (44). [13] Display device (100) comprising: a display panel (110) provided with a plurality of subpixels (SP1, SP2, SP3) having a first-mode subpixel (SP1-1, SP2-1, SP3-1) and a second-mode subpixel (SP1-2, SP2-2, SP3-2) in a display area (DA); and a timing control device (160) for outputting first pixel data for the first mode subpixel (SP1-1, SP2-1, SP3-1) and second pixel data for the second mode subpixel (SP1-2, SP2-2, SP3-2) to the display panel (110), wherein the display panel (110) is configured to supply the first pixel data to the first-mode subpixel (SP1-1, SP2-1, SP3-1) in a first display drive period (DP1) and the second pixel data to the second-mode subpixel (SP1-2, SP2-2, SP3-2) in a second display drive period (DP2), and wherein the first display drive period (DP1) and the second display drive period (DP2) are separated in time. [14] Display device (100) according to claim 13, wherein the display area (DA) has a first-mode display area (DA1) for displaying a first image by the first-mode subpixel (SP1-1, SP2-1, SP3-1) and a second-mode display area (DA2) for displaying a second image by the second-mode subpixel (SP1-2, SP2-2, SP3-2), wherein a value of the first pixel data for the first mode subpixel (SP1-1, SP2-1, SP3-1) arranged in the second mode display area (DA2) is 0, wherein a value of the second pixel data for the second mode subpixel (SP1-2, SP2-2, SP3-2) arranged in the first mode display area (DA1) is 0. [15] The display device (100) according to claim 14, wherein the first mode display area (DA1) and the second mode display area (DA2) do not overlap each other. [16] The display device (100) according to claim 14 or 15, wherein the timing control means (160) is configured to receive video data and position information of the first mode display area (DA1) or the second mode display area (DA2) from the outside and generate the first pixel data and the second pixel data based on the received video data and the received position information of the first mode display area (DA1) or the second mode display area (DA2). [17] Display device (100) according to one of claims 13 to 16, wherein the first-mode subpixel (SP1-1, SP2-1, SP3-1) has a first viewing angle and comprises a first emission element (ED1), wherein the second-mode subpixel (SP1-2, SP2-2, SP3-2) has a second viewing angle and comprises a second emission element (ED2), and wherein the first viewing angle and the second viewing angle differ in at least one direction and one angular range. [18] Display device (100) according to claim 17, wherein the display panel (110) comprises: a first mode selection line (43) for supplying a first mode selection signal (MS1); a second mode selection line (44) for supplying a second mode selection signal (MS2); a first control transistor (T6) configured to be turned on or off in response to the first mode selection signal (MS1) and having a source electrode or a drain electrode connected to the first emission element (ED1); and a second control transistor (T8) configured to be turned on or off in response to the second mode selection signal (MS2) and having a source electrode or a drain electrode connected to the second emission element (ED2). [19] The display device (100) according to claim 18, wherein a gate-on voltage is provided to be supplied as the first mode selection signal (MS1) in the first display drive period (DP1), and a gate-on voltage is provided to be supplied as the second mode selection signal (MS2) in the second display drive period (DP2). [20] The display device (100) according to claim 19, wherein each of the first mode selection signal (MS1) and the second mode selection signal (MS2) is a signal in which the gate-on voltage and a gate-off voltage are arranged to be repeated in subframe units, and wherein the first mode selection signal (MS1) and the second mode selection signal (MS2) have opposite phases to each other.

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