SILICON FUNCTIONAL CONTROL

Abstract

This document describes a fault detection circuit for detecting an anomaly within a semiconductor device operating synchronously with a clock signal by detecting a signal path delay in the semiconductor device relative to the clock signal. The fault detection circuit comprises a first flip-flop element configured to receive a first input data signal and provide a first output data signal corresponding to the first input data signal in response to the clock signal. The fault detection circuit also comprises a second flip-flop element configured to receive a second input data signal and provide a second output data signal corresponding to the second input data signal in response to the clock signal.Additionally, the fault detection circuit also includes a delay unit that is coupled between the first flip-flop element and the second flip-flop element and is configured to receive the first output data signal from the first flip-flop element and to provide the second input data signal to the second flip-flop element as a delayed version of the first output data signal, whereby under normal operating conditions the second input data signal is delayed by the path delay of a predefined number of logic gates with respect to the first output data signal.

Description

Technical field

[0001] This document relates to a semiconductor device. In particular, this document relates to a circuit and a method for controlling the function of a semiconductor device, such as a semiconductor chip with an integrated circuit (IC). background

[0002] Semiconductor devices that contain a complete system on a chip (i.e., SoCs) enable the miniaturization of electronic products and the reduction of product costs by combining semiconductor elements with various functions onto a single chip. Examples of SoC devices include application-specific integrated circuits (ASICs), which combine several different circuits all on one chip to allow for custom programmability, combining multiple related functions that together perform a specific overall task. On the other hand, field-programmable gate arrays (FPGAs) offer flexibility and rapid prototyping through reconfigurable logic gates and programming capabilities.

[0003] Typically, system-on-a-chip (SoC) chips are manufactured using metal-oxide-semiconductor (MOS) technology, and therefore factors such as process corners, voltage, aging, and / or temperature can affect the SoC device's behavior. For example, thermal effects during device operation and / or a shift in a transistor's threshold voltage due to aging can increase the risk of a potentially catastrophic SoC device failure, thereby impairing the SoC device's functionality / performance. It should also be noted that unexpected failures in semiconductor devices will cause system downtime in electrical systems.

[0004] To address these issues, additional process sensing, voltage monitoring, and / or temperature sensors are required for a semiconductor device to monitor its condition throughout its lifetime, predict failures, and alert users to the need for maintenance before a catastrophic failure event. Generally, device failure can be predicted by monitoring physical or electrical properties of a semiconductor device (e.g., using a sensor), such as device ON resistances, gate leakage currents, drain-source leakage currents, and parasitic capacitances, which can be quantified and monitored by measuring fluctuations in voltage and current.However, measurements of certain physical parameters of a semiconductor device may be unreliable due to their dependence on device temperature and may require monitoring systems that rely on high sensor complexity to measure rapidly changing electrical variables. Conversely, existing temperature sensor-based fault detection approaches for a semiconductor device do not offer sufficient resolution, and additional calibration may be necessary during testing.

[0005] Therefore, there is a need for a simple approach to fault detection to increase the reliability and safety of a semiconductor device. Accordingly, this document addresses the technical problem of providing a simple and accurate silicon functional control scheme / approach for monitoring failures occurring within a semiconductor device.

[0006] JP 2014-45508 A discloses a monitoring circuit with two shift registers, one of which contains a delay element that applies a delay value to a received signal.

[0007] EP 1237282 A1 discloses a clock monitoring circuit comprising a first flip-flop circuit, a second flip-flop circuit and a delay device which delays an output signal of the second flip-flop circuit by a time interval that is shorter than a predetermined period of a clock signal.

[0008] DE 112023000815 T5 discloses a method for testing an integrated circuit, comprising: applying a first clock signal to a first flip-flop with an output to a function circuit, applying a second clock signal to a second flip-flop with an input from the function circuit, and increasing the time interval by adding a delay unit to the first clock signal or subtracting a delay unit from the second clock signal.

[0009] US 2014 / 132293 A1 discloses an integrated circuit with a degradation monitoring circuit comprising a comparator circuit with a programmable delay element having an input coupled to a data node of a time path and an output providing a signal of a data signal of the data node delayed by a programmable amount. Summary

[0010] The scope of protection of the present invention is defined by the accompanying claims. This document is therefore directed toward providing an improved silicon function control scheme / approach for monitoring failures within a semiconductor device (e.g., a SoC device such as an ASIC). In particular, an improved silicon function control circuit and an improved design process are provided to enhance existing measures for ensuring proper silicon behavior of an SoC device using standard digital cells.

[0011] According to one aspect, a fault detection circuit is provided for detecting an anomaly within a semiconductor device. Specifically, the semiconductor device can operate synchronously with a clock signal. The fault detection circuit can detect the anomaly by observing / detecting a signal path delay in the semiconductor device relative to the clock signal. In detail, the fault detection circuit includes a first flip-flop element configured to receive a first input data signal and provide a first output data signal corresponding to the first input data signal in response to the clock signal. The fault detection circuit also includes a second flip-flop element configured to receive a second input data signal and provide a second output data signal corresponding to the second input data signal in response to the clock signal.

[0012] Furthermore, the fault detection circuit includes a delay unit coupled between the first and second flip-flop elements. This delay unit is configured to receive the first output data signal from the first flip-flop element and provide the second input data signal to the second flip-flop element as a delayed version of the first output data signal. According to the disclosure in this document, under normal operating conditions, the second input data signal is delayed by a predefined number of clock cycles relative to the first output data signal. For example, the second input data signal may be delayed by a path delay of a predefined number of logic gates relative to the first output data signal.

[0013] As configured above, the proposed fault detection circuit can accurately monitor the anomaly within the semiconductor device by detecting / observing an increase in the delay provided by the delay unit, thus providing an efficient and reliable silicon functional control means to ensure the functional safety of the semiconductor device.

[0014] In some embodiments, the second input data signal can be delayed by essentially one clock cycle of the clock signal or by a duration slightly shorter than one clock cycle relative to the first output data signal. In this way, the circuit does not trigger anomaly detection under normal operating conditions.

[0015] In some embodiments, the delay unit can comprise a plurality of logic elements cascaded between the first and second flip-flop elements. Specifically, the plurality of logic elements can be configured to provide the signal path delay, introducing a time delay of essentially one clock cycle between the first output data signal and the second input data signal. Additionally, the plurality of logic elements can also include a plurality of cascaded AND gates sharing a common input port as an input port of the delay unit to receive the first output data signal from the first flip-flop element.

[0016] In some embodiments, the second input data signal can be provided to the second flip-flop element from an output port of the last AND gate in the cascade, acting as an output port of the delay unit. Optionally, the time delay between the first output data signal and the second input data signal can depend on the number of logic elements.

[0017] In some embodiments, the second flip-flop element can be configured to feed the second output data signal back to the first flip-flop element.

[0018] In some embodiments, the first flip-flop element may include a first data input port configured to receive the first input data signal and a first data output port configured to provide the first output data signal. Similarly, the second flip-flop element may include a second data input port configured to receive the second input data signal and a second data output port configured to provide the second output data signal. Additionally, the circuit may further include an inverter coupled between the second data output port and the first data input port to feed the second output data signal back to the first flip-flop element. In this case, the first data output port may optionally be coupled to an input port of the delay unit, and the second data input port may be coupled to an output port of the delay unit.

[0019] In some embodiments, the fault detection circuit may further include a fault detection unit configured to generate an interrupt signal indicating an anomaly within the semiconductor device, based on the first output data signal and the second output data signal.

[0020] In some embodiments, the fault detection unit may include a detection flip-flop element configured to receive the first output data signal and provide a detection output data signal from the first output data signal. The fault detection unit may also include an XOR gate coupled to the detection flip-flop element and the second flip-flop element. Specifically, the XOR gate may be configured to compare the detection output data signal and the second output data signal and output a logic value according to the result of the comparison.

[0021] In some embodiments, the fault detection unit may further include a second detection flip-flop element that is coupled to the XOR gate and configured to generate the interrupt signal based on the output logic value.

[0022] In some embodiments, the interrupt signal can be generated in response to a change in the output logic value to 1, caused by a missing sample between the first output data signal and the second output data signal.

[0023] In some embodiments, the anomaly within a semiconductor device may include an excessive temperature / voltage deviation from a normal temperature / voltage for operating the semiconductor device and / or aging of the semiconductor device.

[0024] As configured above, this document proposes a fault detection circuit for a semiconductor device, containing a chain of standard digital cells to control proper timing and prevent malfunctions within the semiconductor device. It is further understood that the proposed fault detection circuit can be used in any SoC device, as it generates an intentional signal path delay from standard logic gates, which can be used in any technology by simply adapting it to the available standard cells.

[0025] According to another aspect, a semiconductor device is provided that is configured to operate synchronously with a clock signal. The semiconductor device may exhibit a signal path delay relative to the clock signal for anomaly detection.

[0026] In particular, the semiconductor device comprises a functional logic unit that includes a plurality of functional logic elements configured to execute logic functions of the semiconductor device synchronously with the clock signal. Specifically, a signal time path between any two functional logic elements is at least one additional interval shorter than one clock cycle of the clock signal.

[0027] Additionally, the semiconductor device also includes a functional control unit which includes a fault detection circuit configured to detect the signal path delay caused by an anomaly within the semiconductor device with respect to the clock signal according to one of the aspects and its associated embodiments described above.

[0028] In some embodiments, the plurality of function logic elements can include two or more function flip-flop elements. Accordingly, the signal timing path can include a timing path between any two function flip-flop elements. In some examples, the additional padding can be essentially 50 ps.

[0029] In some implementations, the fault detection circuit can be configured to detect an increase in signal path delay caused by rising temperature and / or falling voltage during operation of the semiconductor device and / or aging of the semiconductor device.

[0030] As configured above, this document proposes a simple fault detection approach using silicon function control in a semiconductor device. The proposed approach can improve upon existing measures such as voltage or temperature monitoring by using only standard (logic) cells.

[0031] According to another aspect, a method for detecting an anomaly within a semiconductor device is provided. In particular, the semiconductor device can operate synchronously with a clock signal. Thus, the anomaly can be detected by detecting / observing a signal path delay in the semiconductor device with respect to the clock signal.

[0032] According to the disclosure of this document, the method comprises receiving a first input data signal at the first flip-flop element and a second input data signal at the second flip-flop element. The method further comprises providing, through the first flip-flop element, a first output data signal corresponding to the first input data signal in response to the clock signal. Additionally, the method comprises delaying, under normal operating conditions, the first output data signal by a predefined number of clock cycles relative to the second input data signal. In particular, the predefined number of clock cycles can be defined as the delay between the first output data signal and the second input data signal, corresponding to the signal path delay achievable via a predefined number of logic gates.For example, under normal operating conditions, the procedure can involve delaying the first output data signal by the path delay of a predefined number of logic gates as the second input data signal.

[0033] Furthermore, the method includes providing, via the second flip-flop element, a second output data signal according to the second input data signal. Additionally, the method also includes determining a change in the delay between the first output data signal and the second input data signal.

[0034] In some embodiments, the predefined number of clock cycles of the clock signal can essentially be one clock cycle of the clock signal, so that no anomaly detection is triggered under normal operating conditions.

[0035] In some embodiments, the method may further include setting a time delay between the first output data signal and the second input data signal by applying a plurality of logic elements to the first output data signal. In particular, the time delay of essentially one clock cycle of the clock signal may be determined based on a number of logic elements.

[0036] In some embodiments, the second output data signal can be provided to the first flip-flop element as the first input data signal. Optionally, the method can further include inverting the second output data signal before providing it to the first flip-flop element.

[0037] In some embodiments, determining a change in the delay between the first output data signal and the second input data signal may further include providing a detection output data signal from the first output data signal and comparing the detection output data signal and the second output data signal using an XOR operation.

[0038] In some embodiments, the method may further include generating an interrupt signal indicating an anomaly within the semiconductor device in response to an increase in a delay between the first output data signal and the second input data signal, indicated by an output logic value of the XOR operation.

[0039] In some embodiments, the interrupt signal can be generated in response to a change in the output logic value to 1, caused by a missing sample between the first output data signal and the second output data signal. Optionally, the interrupt signal can indicate a rising temperature and / or a falling voltage during operation of the semiconductor device and / or aging of the semiconductor device.

[0040] As configured above, this document proposes a simple fault detection method for monitoring failures occurring within a semiconductor device in order to increase the reliability and safety of the semiconductor device. Accordingly, by applying the method as proposed in this document, the operational state of a SoC device can be monitored in an operating system with improved reliability and accuracy. In particular, it enables the operating system to disable (or turn off) certain functions as needed, based on the monitored result, as indicated, for example, by an interrupt signal.

[0041] It should be noted that the methods and systems, including their preferred embodiments, as set forth in this document, may be used alone or in combination with the other methods and systems disclosed herein. Furthermore, the features described in connection with a system are also applicable to a corresponding method. Moreover, all aspects of the methods and systems described in this document may be combined in any way. In particular, the features of the claims may be combined with one another in any manner.

[0042] In this document, the term "couple" or "coupled" refers to elements that are in electrical communication with each other, whether they are connected directly, e.g., via wires, or in some other way. Brief description of the characters

[0043] The invention is explained below in an exemplary manner with reference to the accompanying drawings, wherein Fig. Figure 1 schematically illustrates an exemplary fault detection circuit 100 for detecting an anomaly within a semiconductor device according to embodiments of the present document; Fig. Figure 2 schematically shows a comparison of the key signals in an exemplary fault detection circuit 100 with a delay unit 103 according to embodiments of the present document; Fig. 3 schematically illustrates an exemplary fault detection circuit 100 with a fault detection unit 300 according to embodiments of the present document; Fig. Figure 4 schematically illustrates an exemplary semiconductor device 400 which uses the proposed fault detection circuit 100 to detect an anomaly within the semiconductor device 400 according to embodiments of this document; Fig. Figure 5 schematically shows a comparison of timing path delays between the logic components / elements within an exemplary semiconductor device 400 with respect to the clock signal according to embodiments of this document; and Fig. Figure 6 shows a flowchart of an exemplary method 600 for detecting an anomaly within a semiconductor device (e.g. the semiconductor device 400) according to embodiments of this document. Detailed description

[0044] As stated above, this document aims to provide an improved silicon function control scheme / approach for monitoring failures within a semiconductor device (e.g., ASICs). Specifically, this document proposes an improved silicon function control circuit and design process to enhance existing measures for ensuring proper silicon behavior of a SoC device using standard digital cells.

[0045] During a chip manufacturing process, timing paths between circuit components / elements can be defined according to the specified shutdown conditions for the associated process. According to the disclosure of this document, it is proposed to generate, in addition to functional timing paths that can be defined with a certain margin (e.g., 50 ps by an additional uncertainty setting), one or more artificial detection paths for detecting / monitoring a failure / anomaly within a chip / device. In particular, it is proposed that some of the artificially generated critical paths (e.g., one or more detection paths generated to perform silicon functional control) can be implemented with essentially no margin, e.g., 5 ps, which is much shorter than for the other functional timing paths.

[0046] According to the embodiments provided in this document, the proposed silicon function control scheme can be implemented, for example, by a chain of standard digital cells, such as AND gates. This chain of gates can be used to generate a specific delay between logic elements (e.g., between two flip-flops) that precisely meets, or substantially meets, the setup timing requirement for a linked clock. For example, if the desired frequency of a linked clock is 100 MHz, a corresponding path delay can be approximately 10 ns (i.e., one clock cycle), which can be used to detect a delay increase due to any circumstance, such as device aging, low voltage, and / or high temperature.In this way, “fault detectors” of this type, adapted for desired clock speeds (i.e., desired operating frequencies of the clock), could be placed at multiple locations on a chip for one or more clock cycles, for example to detect / monitor a failure / anomaly within a semiconductor device.

[0047] It is further understood that by applying the measure / approach proposed in this document, the functional state of a SoC device can be monitored in an operating system with improved reliability and accuracy. Furthermore, based on the monitoring results, the operating system is enabled to disable (switch off) certain functions as needed, which can be indicated by an interrupt signal generated according to the result.

[0048] Fig. Figure 1 schematically illustrates an exemplary fault detection circuit 100 for detecting an anomaly within a semiconductor device according to embodiments of this document. In particular, the semiconductor device (e.g., ASICs) can operate synchronously with a clock signal (not shown). Specifically, the circuit 100 can detect / monitor a failure / anomaly within a semiconductor device by observing or detecting a signal path delay in the semiconductor device with respect to the clock signal, in particular by observing or detecting an increase / decrease in the signal path delay. As shown in Fig. As shown in Figure 1, the circuit 100 can include a first flip-flop element 101, a second flip-flop element 102 and a delay unit 103 coupled between the first flip-flop element 101 and the second flip-flop element 102.

[0049] In detail, the first flip-flop element 101 can be configured to receive a first input data signal 101_i and provide a first output data signal Sig_A according to the first input data signal 101_i in response to the clock signal, and the second flip-flop element 102 can be configured to receive a second input data signal Sig_B and provide a second output data signal 102_o according to the second input data signal Sig_B in response to the clock signal. Furthermore, the delay unit 103 can be configured to receive the first output data signal Sig_A from the first flip-flop element 101 and provide the second input data signal Sig_B, a delayed version of the first output data signal Sig_A, to the second flip-flop element 102.

[0050] It should be noted that under normal operating conditions, the second input data signal Sig_B can be delayed by a predefined number of clock cycles relative to the first output data signal Sig_A. For example, the second input data signal Sig_B can be delayed by essentially one clock cycle or by a time interval slightly shorter than one clock cycle (e.g., 5 ps) relative to the first output data signal Sig_A, so that circuit 100 does not trigger anomaly detection under normal operating conditions.

[0051] As mentioned above, the circuit 100, as proposed in this document, can include a chain of standard digital cells / logic elements (e.g., AND gates) as the delay unit 103 to provide a delay path between the first flip-flop element 101 and the second flip-flop element 102. As in the example of Fig. As illustrated in Figure 1, the delay unit 103 can comprise a variety of AND gates 103-1, 103-2, ..., 103-N, which are cascaded between the first flip-flop element 101 and the second flip-flop element 102, which can be used to generate a time delay of essentially one clock cycle of the clock signal between the first output data signal Sig_A and the second input data signal Sig_B, in order to exactly meet the setup timing control requirement for the clock signal without any margin, or essentially to meet the setup timing control requirement for the clock signal.

[0052] For example, if the desired clock signal frequency is 100 MHz, a corresponding path delay generated by the delay unit 103 can be approximately 10 ns (i.e., one clock cycle) to detect a delay increase due to an anomaly, such as device aging, low voltage, and / or high temperature, within the semiconductor device. Specifically, the anomaly within a semiconductor device can include an excessive temperature / voltage deviation from the normal temperature / voltage range for operating the semiconductor device and / or semiconductor device aging.

[0053] In the example of Fig. 1. The multiple AND gates 103-1, 103-2, ..., 103-N connected in cascade can share a common input port as an input port of the delay unit 103 to receive the first output data signal Sig_A from the first flip-flop element 101. Additionally, the second input data signal Sig_B can be provided to the second flip-flop element 102 from an output port of the last AND gate 103-N in the cascade as an output port of the delay unit 103. It should be noted that the resulting time delay between the first output data signal Sig_A and the second input data signal Sig_B can depend on the number of AND gates, based on which a suitable number of AND gates can be used to design the fault detection circuit 100.

[0054] It is noted that the exemplary implementation of the fault detection circuit 100 mentioned above, using cascaded AND gates as the logic elements for the delay unit 103, is a non-limiting example of generating a suitable time delay between the first flip-flop element 101 and the second flip-flop element 102 to satisfy (exactly or substantially) the setup timing control requirement for the clock signal. It is understood that other types of logic elements / cells and combinations thereof, and / or any number of logic elements, are feasible and fall within the scope of the disclosure in this document.

[0055] Furthermore, how through Fig. As specified in 1, the second flip-flop element 102 can be configured to feed the second output data signal 102_o back to the first flip-flop element 101. In this specific example, the first flip-flop element 101 can have a first data input port configured to receive the first input data signal 101_i and a first data output port configured to provide the first output data signal Sig_A. Furthermore, the second flip-flop element 102 can have a second data input port configured to receive the second input data signal Sig_B and a second data output port configured to provide the second output data signal 102_o. Additionally, an inverter 104 can be coupled between the second data output port and the first data input port to feed the second output data signal 102_o back to the first flip-flop element 101.As the expert will understand, the inverter 104 can provide an inverted second output data signal 102_o' as the first input data signal 101_i to the first flip-flop element 101. In the above case, the first data output port of the first flip-flop element 101 can be coupled to an input port of the delay unit 103, and the second data input port of the second flip-flop element 102 can be coupled to an output port of the delay unit 103.

[0056] It is noted that the above-mentioned exemplary implementation of the fault detection circuit 100 with connections between the flip-flop elements and the logic elements (e.g., the AND gates, the inverter, etc.), as shown in Fig. Figure 1 explicitly illustrates a non-limiting example of generating a suitable signal (timing) path for detecting / monitoring a delay increase due to any circumstance / anomaly, such as device aging, low voltage, and / or high temperature, within a semiconductor device. It is understood that other types of logic elements / cells and combinations thereof, any number of logic elements, and / or other types of connections between the flip-flop elements and the logic elements are feasible and fall within the scope of protection of the disclosure in this document.

[0057] Fig. Figure 2 schematically shows a comparison of the key signals in an exemplary fault detection circuit 100 with a delay unit 103 according to embodiments of this document. Here, the clock signal (as indicated by "CLK"), on the basis of which the semiconductor device is operated, is compared with the first output data signal Sig_A and the second input data signal Sig_B, where the temperature increases over time. As shown in Fig. As illustrated in Figure 2, the first output data signal Sig_A still follows the clock signal CLK (with a small amount of a fixed time delay with respect to the clock signal), whereas with the delay unit 103, the second input data signal Sig_B may lose synchronization with the clock signal CLK due to an increasing delay along a signal path between the first flip-flop element 101 and the second flip-flop element 102, which may result from an increasing cell delay introduced by a rising temperature (as shown in Figure 2a).

[0058] It can be observed that a significant increase in signal path delay due to the increasing cell delay causes the timing of the second input data signal Sig_B (provided by the delay unit 103) to fail shortly after a few cycles (as indicated by 2b). Although Fig. 2 explicitly refers to an increasing cell delay between Sig_A and Sig_B caused by an increasing temperature, it is understood that similar results can be observed with respect to an increasing cell delay caused by another anomaly within the semiconductor device (e.g., aging or decreasing voltage).

[0059] In other words, compared to the first output data signal Sig_A, the second input data signal Sig_B can exhibit an increasing signal path delay due to an accumulation of delays caused by the individual cells / logic elements that make up the delay unit 103 in the event of an anomaly. Thus, by generating a delay path between the flip-flop elements directly at the limit of fulfilling the timing requirement for the clock signal without any margin (e.g., one clock cycle), an increase in delay reflecting an abnormal condition within the semiconductor device can be easily detected / monitored, thereby improving the reliability and accuracy of the proposed fault detection circuit 100.

[0060] To detect an increasing signal path delay of the second input data signal Sig_B, the proposed fault detection circuit 100 can also be a fault detection unit 300, as shown in Fig. Figure 3 illustrates embodiments described in this document. Fig. As shown in Figure 3, the fault detection unit 300 can be configured to generate an interrupt signal 3b, indicating an anomaly within the semiconductor device, based on the first output data signal Sig_A and the second output data signal 102_o.

[0061] In particular, the fault detection unit 300 can comprise a detection flip-flop element 31 and an XOR gate 32 coupled to the detection flip-flop element 31 and the second flip-flop element 102. The detection flip-flop element 31 can be configured to receive the first output data signal Sig_A and provide a detection output data signal 3a from the first output data signal Sig_A. The XOR gate 32 can be configured to compare the detection output data signal 3a and the second output data signal 102_o and output a logic value L according to the result of the comparison.

[0062] Additionally, the fault detection unit 300 can further comprise a second detection flip-flop element 33, which is coupled to the XOR gate 32. The second detection flip-flop element 33 can be configured to generate the interrupt signal 3b based on the output logic value L. In particular, the interrupt signal 3b can be generated in response to a change in the output logic value L to 1, which may be caused by a missing sample between the first output data signal Sig_A and the second output data signal 102_o. Accordingly, the generation of the interrupt signal 3b can be triggered by the XOR gate 32, which compares the output 3a of the detection flip-flop element 31 with the output 102_o of the second flip-flop element 102.

[0063] It is noted that output 3a and output 102_o should normally have the same value when synchronized. However, if the second input data signal Sig_B has lost synchronization with the clock signal CLK due to increasing cell delay introduced by rising temperature (as shown by 2a in Fig. 2), a missing sample will be present between the first output data signal Sig_A and the second output data signal 102_o (as a result of a significant increase in the signal path delay, leading to a timing error for Sig_B, as described in 2b in Fig. (as specified in 2). Accordingly, output 3a and output 102_o can have different values / levels, which then cause the interrupt signal 3b to increase. If output 3a and output 102_o have different values / levels, the output logic value L of the XOR gate 32 can change to 1, which then triggers the generation of the interrupt signal 3b.

[0064] In particular, the second detection flip-flop element 33 can generate the interrupt signal 3b after a small amount of delay, as shown by 2c in Fig. 2 specified (i.e., detection point), although the timing of the second input data signal Sig_B may fail earlier, as shown in 2b in Fig. 2 is specified (and a missing sample value between the first output data signal Sig_A and the second output data signal 102_o can already appear at point 2b). It is further recognized that in the case of an anomaly, such as high temperature, low voltage, and / or device aging, the (total) delay between the first flip-flop element 101 and the second flip-flop element 102 can increase, since the (individual) delay of a single gate (e.g., an AND gate) can depend on the temperature and / or voltage. Either a low voltage or a high temperature can increase the delay of a gate. In this way, it is possible to detect the presence of a problem efficiently and reliably without requiring a highly complex sensor.

[0065] It is noted that the above-mentioned exemplary implementation of the fault detection unit 300, which includes the flip-flop elements 31, 33 and the XOR gate 32 and has connections between the flip-flop elements 31, 33 and the XOR gate 32, as shown in Fig. Figure 3 explicitly illustrates a non-limiting example of generating the interrupt signal as an indication of a detected anomaly in the semiconductor device. It is understood that other types of logic elements / cells and combinations thereof, any number of logic elements, and / or other types of connections between the flip-flop elements and the logic elements are feasible and fall within the scope of the disclosure in this document. Fig. Figure 4 schematically illustrates an exemplary semiconductor device 400 that employs the proposed fault detection circuit 100 to detect an anomaly within the semiconductor device 400 according to embodiments described in this document. As mentioned above, the semiconductor device 400 (e.g., ASICs) can operate synchronously with a clock signal CLK. In particular, the semiconductor device 400 can have a signal path delay with respect to the clock signal CLK for anomaly detection, as described above in relation to the Fig. 1, Fig. 2 to Fig. 3 described.

[0066] In detail, the semiconductor device 400 can include a function logic unit 40 for executing functions of the semiconductor device 400 and a function control unit 41 for detecting an anomaly within the semiconductor device 400. The function logic unit 40 can include a variety of function logic elements 401, 402, ..., 407 configured to execute logic functions (e.g., Universal Asynchronous Receiver-Transmitter, UART, functions) of the semiconductor device 400 synchronously with the clock signal CLK. On the other hand, the function control unit 41 can include a fault detection circuit, as described by the fault detection circuit 100 in Fig. 1 or Fig. Figure 3 illustrates a circuit that can be configured to detect the signal path delay caused by an anomaly within the semiconductor device 400 with respect to the clock signal CLK. In some implementations, the fault detection circuit in the function control unit 41 of the semiconductor device 400 can also include the fault detection unit 300 described above.

[0067] In particular, in the function logic unit 40 of the semiconductor device 400, a signal time path between any two function logic elements can be shorter than a clock cycle of the clock signal CLK by at least one additional margin (e.g., approximately 50 ps or slightly different from 50 ps). In the example of Fig. 4. The semiconductor device 400 can include two or more function flip-flop elements 401 (FF_F), 402 (FF_B), 403 (FF_C), 404 (FF_D) among the function logic elements. Thus, a time path between any two function flip-flop elements 401 to 404 in the function logic unit 40 can be considered a signal time path. Similar to the fault detection circuit, as in Fig. 1 and Fig. As illustrated in Figure 3, the fault detection circuit in the function control unit 41 of the semiconductor device 400 can also be configured to detect an increase in signal path delay caused by an increase in temperature and / or a decrease in voltage during operation of the semiconductor device 400 and / or aging of the semiconductor device 400 (i.e., the anomaly of the semiconductor device 400). In the Fig. In the example shown in Figure 4, it is desirable that a signal time path between any two functional flip-flop elements (e.g., FF_F to FF_B, FF_F to FF_C, and / or FF_F to FF_D) be shorter than the frequency cycle time (i.e., one clock cycle) to meet the timing requirements of a synchronous digital design. In some preferred implementations, this requirement can be improved by including an additional buffer (e.g., 50 ps). Specifically, a signal time path between any two functional flip-flop elements can preferably be configured to be shorter than the frequency cycle time minus the additional buffer, which in practice can be achieved using static timing analysis (STA) tools, for example, by adding an uncertainty setting to the configuration.

[0068] On the other hand, in the function control unit 41, the (signal) time path (as a detection path for monitoring a failure / anomaly of the device 400) between the flip-flop element FF_A (which corresponds to the first flip-flop element 101 in Fig. 1 is similar) and FF_X (which corresponds to the second flip-flop element 102 in Fig. 1 similar) can be set so that it is only slightly smaller than the cycle time (i.e., one clock cycle), as described above in relation to Fig. 1, Fig. 2 to Fig. 3. As explained above, this time path may fail due to a delay increase along the path, e.g., due to a high temperature, while other functional paths (e.g., paths from FF_F to FF_B, from FF_F to FF_C and / or from FF_F to FF_D, etc.) still meet their requirements.

[0069] It is understood that the logical paths FF_F to FF_B, FF_F to FF_C and / or FF_F to FF_D may lie in the function logic (e.g., the function logic unit 40) of a SoC device, e.g., a Universal Asynchronous Receiver-Transmitter, UART, and that the time paths within this function logic may contain a certain margin (e.g., 50 ps) so that these function logic elements can remain functional in the event of a slight temperature increase. As stated above, within the silicon function control logic of the SoC device (e.g., the function control unit 41), FF_X (the second flip-flop element 102) is fed back to FF_A (the first flip-flop element 101), and if the path delay between them increases with the temperature rise, the path delay can become longer than one clock period, and thus the signal from FF_A cannot be inverted (i.e.,The output of FF_A and the output of FF_X are inverted, specifically with different values / levels. By detecting this condition (e.g., using the XOR gate 32, which compares the output of FF_A and the output of FF_X), it is possible to detect that the temperature has increased, the voltage has decreased, or that the semiconductor device 400 is aging.

[0070] It is noted that the above-mentioned exemplary implementation of the semiconductor device 400 with the functional logic unit 40, as in Fig. 4 explicitly illustrated, and using the fault detection circuit, as shown by fault detection circuit 100 in Fig. 1 and Fig. Figure 3, which explicitly illustrates the function control unit 41, is a non-limiting example for detecting and indicating abnormal conditions within the semiconductor device. It is understood that other types of logic elements / cells and combinations thereof, any number of logic elements, and / or other types of connections between the flip-flop elements and the logic elements for implementing the function logic unit 40 / function control unit 41 are feasible and fall within the scope of the disclosure in this document.

[0071] Fig. Figure 5 schematically shows a comparison of timing path delays between the logic components / elements within an exemplary semiconductor device 400 with respect to the clock signal according to embodiments of this document. It can be observed that the timing path delays between the function flip-flop elements (from FF_F to FF_B, from FF_F to FF_C, and from FF_F to FF_D) are shorter than one clock cycle to meet the timing requirements in a synchronous digital design, taking into account an additional margin (e.g., 50 ps). Furthermore, the magnitude of a timing path delay for a path can depend on the number of logic elements in that path.For example, the path (and corresponding path delay) from FF_F to FF_B is considerably longer than the path from FF_F to FF_C, since the path from FF_F to FF_B contains more logic elements than the path from FF_F to FF_C. Furthermore, it is evident that the timing path delay between the function control flip-flop elements, i.e., from FF_A to FF_X, is set to essentially one clock cycle of the clock signal, as above in relation to . Fig. 1, Fig. 2 to Fig. 3 described.

[0072] Fig. Figure 6 shows a flowchart of an exemplary method 600 for detecting an anomaly within a semiconductor device (e.g., the semiconductor device 400) according to embodiments of this document, wherein the semiconductor device 400 is configured to operate synchronously with a clock signal. Furthermore, the anomaly within the semiconductor device can be detected / monitored by detecting / observing a signal path delay in the semiconductor device with respect to the clock signal. It is understood that the method 600 can be carried out, for example, by the fault detection circuit 100, as described in [reference to relevant document]. Fig. 1, Fig. 3 and Fig. 4 illustrates.

[0073] In particular, the method 600 comprises receiving 601 a first input data signal at the first flip-flop element and a second input data signal at the second flip-flop element. The method 600 also comprises providing 602, through the first flip-flop element, a first output data signal in accordance with the first input data signal in response to the clock signal. In particular, the method 600 further comprises delaying 603, under normal operating conditions, the first output data signal by a predefined number of clock cycles of the clock signal around the second input data signal. Additionally, the method 600 comprises providing 604, through the second flip-flop element, a second output data signal in accordance with the second input data signal. Furthermore, the method 600 also comprises determining 605 a change in the delay between the first output data signal and the second input data signal.It is noted that the predefined number of clock cycles of the clock signal can correspond to the delay between the first output data signal and the second input data signal of the signal path delay achievable via a predefined number of logic gates.

[0074] Accordingly, the proposed circuit, along with its methodology, implicitly takes into account process fluctuations, voltage, aging, temperature, and peak-to-peak jitter to detect a failure / anomaly with the semiconductor device. In the event of a failure detection, an interrupt signal can be generated to highlight / indicate a condition that may require urgent attention from the operating system.

[0075] It is further understood that the proposed approach to silicon function control, using only standard cells, is much simpler than using a highly complex sensor to monitor the physical or electrical properties of a semiconductor device. However, the proposed silicon function control approach can also enhance existing measures, such as voltage or temperature monitoring (e.g., for use in a calibration / testing phase), to improve the accuracy / reliability of parameter monitoring.

[0076] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. A person skilled in the art will be able to implement various arrangements which, although not explicitly described or shown here, embody the principles of the invention and are included in its meaning and scope of protection. Furthermore, all examples and embodiments set forth in this document are expressly intended to serve only as illustrations to aid the reader in understanding the principles of the proposed methods and systems. Moreover, all statements herein that provide principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to include equivalents thereof.

Claims

[1] Fault detection circuit for detecting an anomaly within a semiconductor device operating synchronously with a clock signal, by observing a signal path delay in the semiconductor device with respect to the clock signal, the circuit comprising: a first flip-flop element configured to receive a first input data signal and to provide a first output data signal in accordance with the first input data signal in response to the clock signal; a second flip-flop element configured to receive a second input data signal and to provide a second output data signal in accordance with the second input data signal in response to the clock signal; and A delay unit coupled between the first flip-flop element and the second flip-flop element, configured to receive the first output data signal from the first flip-flop element and to provide the second input data signal to the second flip-flop element as a delayed version of the first output data signal, wherein, under normal operating conditions, the second input data signal is delayed by a predefined number of clock cycles relative to the first output data signal, the delay unit comprising a plurality of logic elements cascaded between the first flip-flop element and the second flip-flop element, the plurality of logic elements configured to provide the signal path delay to generate a time delay of essentially one clock cycle between the first output data signal and the second input data signal.wherein the multitude of logic elements comprises a multitude of cascaded AND gates, which share a common input port as an input port of the delay unit to receive the first output data signal from the first flip-flop element. [2] Circuit according to claim 1, wherein the second input data signal is delayed by substantially one clock cycle of the clock signal or by a time period which is somewhat shorter than one clock cycle of the clock signal with respect to the first output data signal, so that the circuit does not trigger anomaly detection under normal operating conditions. [3] Circuit according to claim 1, wherein the second input data signal is provided to the second flip-flop element from an output port of the last AND gate in the cascade as an output port of the delay unit. [4] Circuit according to one of claims 1 to 3, wherein the time delay between the first output data signal and the second input data signal depends on a number of logic elements. [5] Circuit according to one of the preceding claims, wherein the second flip-flop element is configured to return the second output data signal to the first flip-flop element. [6] Circuit according to any of the preceding claims, wherein the first flip-flop element comprises a first data input port configured to receive the first input data signal and a first data output port configured to provide the first output data signal, and the second flip-flop element comprises a second data input port configured to receive the second input data signal and a second data output port configured to provide the second output data signal, wherein the circuit further comprises an inverter coupled between the second data output port and the first data input port to feed the second output data signal back to the first flip-flop element. [7] Circuit according to claim 6, wherein the first data output port is coupled to an input port of the delay unit and the second data input port is coupled to an output port of the delay unit. [8] Circuit according to any of the preceding claims, further comprising a fault detection unit configured to generate an interrupt signal indicating an anomaly within the semiconductor device, based on the first output data signal and the second output data signal. [9] Circuit according to claim 8, wherein the fault detection unit comprises a detection flip-flop element configured to receive the first output data signal and to provide a detection output data signal from the first output data signal; wherein the fault detection unit further comprises an XOR gate coupled to the detection flip-flop element and the second flip-flop element, wherein the XOR gate is configured to compare the detection output data signal and the second output data signal and to output a logic value according to a result of the comparison. [10] Circuit according to claim 9, wherein the fault detection unit further comprises a second detection flip-flop element coupled to the XOR gate and configured to generate the interrupt signal based on the output logic value. [11] Circuit according to claim 10, wherein the interrupt signal is generated in response to a change in the output logic value to 1 caused by a missing sample value between the first output data signal and the second output data signal. [12] Circuit according to any of the preceding claims, wherein the anomaly within a semiconductor device comprises an excessive temperature / voltage deviation from a normal temperature / voltage for operating the semiconductor device and / or aging of the semiconductor device. [13] Semiconductor device configured to operate synchronously with a clock signal, wherein the semiconductor device has a signal path delay with respect to the clock signal for anomaly detection, and the semiconductor device comprises: a functional logic unit comprising a plurality of functional logic elements configured to execute logic functions of the semiconductor device synchronously with the clock signal, wherein a signal time path between any two functional logic elements is at least one additional interval shorter than one clock cycle of the clock signal; and a functional control unit comprising a fault detection circuit configured to detect the signal path delay caused by an anomaly within the semiconductor device with respect to the clock signal according to any one of claims 1 to 12. [14] Device according to claim 13, wherein the plurality of function logic elements comprises two or more function flip-flop elements and wherein the signal time path comprises a time path between any two function flip-flop elements. [15] Device according to claim 13 or claim 14, wherein the additional clearance is essentially 50 ps. [16] Device according to any one of claims 13 to 15, wherein the fault detection circuit is configured to detect an increase in signal path delay caused by an increase in temperature and / or a decrease in voltage during operation of the semiconductor device and / or an aging of the semiconductor device. [17] Method for detecting an anomaly within a semiconductor device operating synchronously with a clock signal, by observing a signal path delay in the semiconductor device with respect to the clock signal, the method comprising: Receiving a first input data signal at the first flip-flop element and a second input data signal at the second flip-flop element; Providing, through the first flip-flop element, a first output data signal according to the first input data signal in response to the clock signal; Delaying, under normal operating conditions, the first output data signal by a predefined number of clock cycles to generate the second input data signal, where the predefined number of clock cycles corresponds to the delay between the first output data signal and the second input data signal, representing the signal path delay achievable via a predefined number of logic gates; Providing, through the second flip-flop element, a second output data signal according to the second input data signal; Determining a change in the delay between the first output data signal and the second input data signal; and Setting a time delay between the first output data signal and the second input data signal by applying a plurality of logic elements to the first output data signal, wherein the plurality of logic elements are cascaded between the first flip-flop element and the second flip-flop element, wherein the plurality of logic elements includes a plurality of cascaded AND gates having a common input port as an input port of the delay unit to receive the first output data signal from the first flip-flop element. [18] Method according to claim 17, wherein the predefined number of clock cycles of the clock signal is essentially one clock cycle of the clock signal, so that no anomaly detection is triggered under normal operating conditions. [19] Method according to claim 18, wherein the time delay of substantially one clock cycle of the clock signal is determined based on a number of logic elements. [20] Method according to any one of claims 17 to 19, wherein the second output data signal is provided to the first flip-flop element as the first input data signal. [21] Method according to claim 20, further comprising inverting the second output data signal before supplying it to the first flip-flop element. [22] Method according to any one of claims 17 to 21, wherein determining a change in the delay between the first output data signal and the second input data signal further comprises providing a detection output data signal from the first output data signal and comparing the detection output data signal and the second output data signal using an XOR operation. [23] Method according to claim 22, further comprising generating an interrupt signal indicating an anomaly within the semiconductor device in response to an increase in a delay between the first output data signal and the second input data signal, indicated by an output logic value of the XOR operation. [24] Method according to claim 23, wherein the interrupt signal is generated in response to a change in the output logic value to 1 caused by a missing sample value between the first output data signal and the second output data signal, wherein the interrupt signal optionally indicates an increasing temperature and / or a decreasing voltage during operation of the semiconductor device and / or an aging of the semiconductor device.

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