System and method for flashing data between a flash station and a target board

Abstract

The invention relates to a method and system (1a, 1b, 1c) comprising a flash station (3) and a first target board (2, 2a) having a non-volatile first target memory (7, 7a) and a first target processor (5, 5a), wherein the non-volatile first target memory (7, 7a) is in communication with the first target processor (5, 5a), wherein the first target board (2, 2a) has a first PCIe target root complex (6, 6a), and wherein the system (1a, 1b, 1c) has a first target RAM (4, 4a) which is connected at least to the first PCIe target root complex (6, 6a), and wherein the flash station (3) has a non-volatile production memory (9) and a production processor (10), wherein the production memory (9) is in communication with the production processor (10), wherein the flash station (3) has a PCIe flash root complex (11), and wherein the production processor (10) is designed toto prepare the data to be flashed in the production memory (9) as flash data, and wherein a first Ethernet connection (13, 13a) is provided between the flash station (3) and the first target board (2, 2a) for authenticating the flash station (3) on the first target board (2, 2a), and wherein the first target processor (5, 5a) is designed to load and execute a flash kernel in the first target main memory (4, 4a) after the authentication, wherein the flash kernel is present in the first target board (2, 2a) or can be transmitted to the first target processor (5, 5a) via the first Ethernet connection (13, 13a), and wherein the first target board (2, 2a) has a first PCIe target endpoint (22) which is connected to the first PCIe target root complex (6, 6a), and wherein the flash station (3) has a PCIe flash endpoint (17) which is connected to the PCIe flash root complex (11) is,for forming a flash connection (15) between the first PCIe target endpoint (22) and the PCIe flash endpoint (17) for flashing the prepared flashed data from the flash station (3) to the target board (2, 2a) for storage in the non-volatile first target memory (7, 7a).,

Description

[0001] The invention relates to a system and a method for flashing data between a flash station and a target board.

[0002] Newly developed functions in the automotive sector require ever-increasing computing power. To meet this demand, more and more high-performance computers are being produced. In production, an equally ever-increasing amount of data from vehicle control software, maps, infotainment data, driving models, etc. must be transferred to the non-volatile memory (NVM) of these devices.

[0003] The installation or reinstallation of, for example, control software on an ECU, the so-called "flashing" of the software, is usually performed using a flash station: The fully assembled target board in the ECU or for the ECU, located on a transport pallet, is transported to a flash station, or vice versa. The flash station contains the software variants to be installed on a memory device. The ECU is then connected to the flash station via cable, and the desired control software is loaded into the ECU's main memory. The ECU is then tested.

[0004] The flash data can be transmitted from the flash station to several control units, for example to separate CAN or CAN FD vehicle buses, in order to be able to flash them.

[0005] Flashing ECUs in vehicle production is required both in-line and off-line. The challenge in production is to quickly distribute flash data to many ECUs via bus systems.

[0006] Please note that common, look-up computer terms have been left in English for ease of understanding.

[0007] DE 102015224829 A1 discloses a device and a method for flashing firmware onto a device having a memory unit, a processing unit, and a communication unit, comprising the following method steps: a. starting the device, b. checking by means of the processing unit whether a flash flag is set in the memory unit, which represents that the device should be put into a flash state, wherein if no, the process continues with step c, or if yes, the process continues with step d, c. checking by means of the processing unit whether valid firmware is present, wherein if no, the process continues with step d, or if yes, the process continues with step e, d. putting the device into a flash state, or otherwise e. putting the device into an application state, and f.Check whether a flash command has been received via the communication unit; if not, proceed to step e; or if yes, proceed to step g. Set a flash flag in the memory unit and proceed to step a.

[0008] It is an object of the invention to provide a simple and economical system and method for flashing a target board.

[0009] The problem is solved by a system having the features of claim 1 and a method having the features of claim 15.

[0010] Advantageous embodiments emerge from the dependent patent claims, the description and the figures.

[0011] The object is achieved by a system for flashing data between a flash station and a target board, the system comprising the flash station and a first target board, wherein the first target board has a non-volatile first target memory and a first target processor, wherein the non-volatile first target memory is in communication with the first target processor, wherein the first target board has a first PCIe target root complex which is connected to the first target processor, and wherein the system has a first target RAM which is connected at least to the first PCIe (Peripheral Component Interconnect Express) target root complex, and wherein the flash station has a non-volatile production memory and a production processor, wherein the non-volatile production memory is in communication with the production processor, wherein the flash station has a PCIe flash root complex connected to the production processor, and wherein the production processor is configured to prepare the data to be flashed in the production memory as flash data, and wherein a first Ethernet connection is provided between the flash station and the first target board for authenticating the flash station on the first target board, and wherein the first target processor is configured to load and execute a flash kernel into the first target memory after authentication, wherein the flash kernel is present in the first target board or can be transmitted to the first target processor via the first Ethernet connection, and wherein the first target board has a first PCIe target endpoint connected to the PCIe target root complex, and wherein the flash station has a PCIe flash endpoint connected to the PCIe flash root complex for forming a flash connection between the first PCIe target endpoint and the PCIe flash endpoint for flashing the prepared flashed data from the flash station to the target board for storage in the non-volatile first target memory.

[0012] Please note that common, look-up computer terms have been left in English for ease of understanding.

[0013] PCI Express (Peripheral Component Interconnect Express, PCIe) is a high-speed serial computer expansion bus standard designed to connect peripheral devices to a main processor chipset (e.g., a central processing unit). PCI Express essentially defines a point-to-point connection. PCI Express also includes subsequent standards / successors based on it, such as PCI 7.0 or PCI-SIG Optical.

[0014] The flash station can also be designed as a board.

[0015] As already described, flashing can be understood as the installation or reinstallation of software on the target board, for example in the control unit.

[0016] The term board can be understood as a printed circuit board / computer board / printed circuit board.

[0017] In a PCI Express (PCIe) system, a root complex connects the CPU and memory subsystem to, for example, one or more endpoints. The root complex generates transaction requests on behalf of the CPU. A root complex (RC) refers to the root of an I / O hierarchy that connects the CPU / memory subsystem to the I / O. The root complex in PCI Express (PCIe) is the intermediary between the central processing unit (CPU), memory, and the PCIe switch fabric, which includes one or more PCIe or PCI devices.

[0018] It is known that pre-flashing NVM (non-volatile memory) storage on computer boards / circuit boards can be a solution for transferring large data packets to the target board cost-effectively. However, the invention recognized that different existing software versions increase the complexity of the logistical processes, as pre-flashed NVM components must be assigned to a specific target board without a unique hardware characteristic (e.g., hardware part number).

[0019] NVM (Non-Volatile Memory Express) is a communications interface and driver that takes advantage of the increased bandwidth offered by PCIe. It is designed for greater performance and efficiency while providing interoperability across a wide range of enterprise and consumer systems.

[0020] It is also known that different endpoints can be coupled via switches. This allows for direct connections between PCI Express devices.

[0021] Likewise, a chipset or system-on-a-chip (SoC) mounted on the computer board may have specific installation routines or security restrictions that require software installation on the running system.

[0022] The invention further recognized that, in practice, significantly lower transfer rates are achieved due to protocol overhead and signal quality. It was recognized that novel NVM can achieve much higher programming rates than the available communication interface speeds. Based on this, the invention recognized that the speed of the communication interface is responsible for reducing the data transfer rate, as it essentially acts as a bottleneck in the flashing process.

[0023] This is now remedied by the system according to the invention. First, a control connection is established via Ethernet between the target board and the flash station by the target processor to authenticate the factory flash station on the target board. This ensures process reliability.

[0024] The target processor then loads a small flash kernel into the target memory via the first Ethernet connection, or the kernel is already available for loading into the target memory. This enables improved communication (in this case, flashing) between the target board and the flash station.

[0025] The target board then starts a data flash connection between the first PCIe target endpoint and the PCIe flash endpoint via PCIe, which is used to transmit the prepared flashed data in the flash station to the PCIe target root complex of the target board.

[0026] The data thus transmitted can then be stored by the PCIe target root complex via the target processor and an NVM controller into the NVM memory, i.e. the first target memory.

[0027] The system according to the invention eliminates the bottleneck “communication interface” between the factory flash station and the target board, as it enables a direct PCIe connection between the target board to be programmed / flashed in the production line and the computer system of the flash station.

[0028] The system according to the invention thus enables direct data transfer via PCIe, which allows the NVM (SSD target memory) of the target board to be programmed at maximum speed.

[0029] The system according to the invention thus significantly reduces the need for investment in production lines. Furthermore, the flash station's production RAM is connected to the target board like a PCIe-capable memory module, which in turn eliminates the need for a separate data transfer protocol such as TCP / IP and the associated data overhead and software development effort.

[0030] In a further embodiment, the flash station has a production RAM, with the production processor configured to mount the data to be flashed into the production RAM. In particular, the production processor is configured to mount the data to be flashed into the production RAM as a virtual drive. This prepares the flash data in the production RAM of the flash station and mounts the data as a virtual drive. The virtual drive is thus presented to the PCIe target root complex of the target board as a peripheral device, for example, as an NVM SSD (computer memory).

[0031] The data transfer speed is therefore limited only by the programming speed of the target NVM (target memory) on the target board when using an SSD in the system. SSD (Solid State Drive) refers to a newer type of computer storage. SSDs use flash memory to digitally read and write data. Because SSDs don't have to mechanically search for data, they enable near-instant booting and loading.

[0032] Furthermore, a non-transparent bridge (NTB) is connected between the PCIe flash endpoint and the PCIe flash root complex, connecting the PCIe flash root complex and the first PCIe target root complex via the flash connection. The PCIe connection to the target board is implemented via a non-transparent bridge (NTB), which connects the root complexes of the flash station and the target board. The non-transparent bridge (NTB) enables isolation between the flash station and the target board while simultaneously enabling data exchange. This allows the flash data to be transmitted securely to the target board.

[0033] In a further embodiment, the flash station includes a PCIe switch connected between the PCIe flash endpoint and the PCIe flash root complex, connecting the PCIe flash endpoint to the first PCIe target root complex via the first PCIe target endpoint. This provides a fully configurable switch with a fully configurable upstream port.

[0034] In a further embodiment, a flash memory is connected to the PCIe switch, so that the flash memory is connected to the first PCIe target root complex via the PCIe switch, and the production processor is configured to load the data to be flashed in the production memory into the flash memory. The flash memory can be configured as a solid-state drive (SSD), in particular as an NVM SSD. The PCIe switch allows the flash memory to be directly connected to the flash data transmission at full bandwidth and speed.

[0035] NVM (Non-Volatile Memory Express) refers to an interface that connects non-volatile memory—a non-volatile mass storage device such as an SSD—to peripheral devices via the PCI Express standard. Thanks to the standard transfer protocol, the NVM SSD does not require additional drivers, enabling exceptionally high transfer rates.

[0036] This enables fast speed transfer, whereby the speed of the flash connection is only reduced by the read speed of the flash memory, e.g. the SSD read speed, on the flash station side and the programming speed of the RAM, e.g. the NVM programming speed, on the target board.

[0037] In a further development, the first target board is configured to load the flash data from the flash memory via the PCIe switch and the flash connection between the PCIe flash endpoint and the PCIe target endpoint. In this process, the data is prepared for flash transfer in the flash memory.

[0038] In a further embodiment, a second target board is provided for forming a multi-board with the first target board, wherein the second target board has a non-volatile second target memory and a second target processor, wherein the non-volatile second target memory is in communication with the second target processor, wherein the second target board has a second PCIe target root complex connected to the second target processor, and a second target RAM connected to at least the second PCIe target root complex, and wherein a second Ethernet connection is provided between the flash station and the second target board for authenticating the flash station on the second target board, and wherein the second target processor is configured to load and execute a flash kernel in the second target RAM after authentication,wherein the flash kernel is present in the second target board or can be transmitted to the second target processor via the second Ethernet connection, wherein a PCIe multi-board switch is provided, which is connected to the first PCIe target root complex and the second PCIe target root complex, and wherein a PCIe multi-target endpoint is provided, which is connected to the PCIe multi-board switch and to the PCIe flash endpoint, for forming a flash connection between the PCIe multi-board switch and the PCIe flash endpoint for flashing the prepared flashed data from the flash station to the first target board and to the second target board.

[0039] The second, virtually identical target board creates a multi-board. Not only one target board, but also several additional target boards can be connected. Each target board is connected to the flash station via a separate Ethernet connection, for authentication of the flash station to the first and second target boards.

[0040] The PCIe target root complexes are connected to each other via a PCIe multi-board switch. This switch is also connected to the PCIe flash endpoint, allowing data to be flashed to the PCIe target root complexes via the PCIe flash endpoint and the PCIe multi-board switch. This system allows the first target board and the second target board to be flashed at maximum PCIe speed.

[0041] Furthermore, both the first target processor is configured to mount a first virtual target drive in the first target memory for receiving the flash data via the first PCIe target root complex and the second target processor is configured to mount a second virtual target drive in the second target memory for receiving the flash data via the second PCIe target root complex.

[0042] In a further embodiment, a production RAM is present, and the production processor is configured to mount the data to be flashed into the production RAM. In particular, the production processor is configured to mount the data to be flashed into the production RAM as a virtual drive. In a further embodiment, a non-transparent bridge is connected between the PCIe flash endpoint and the PCIe flash root complex, connecting the PCIe flash root complex to the first PCIe target root complex and the second PCIe target root complex via the flash connection.

[0043] For the flash connection, the target boards create virtual drives in their respective target memory to receive the flash data via PCIe connection (flash connection). Data transfer from the production RAM to the target RAM is therefore expected to occur at maximum PCIe speed. In a further development, the PCIe multi-board switch is configured to first transmit the flash data to the first target board and then to the second target board, so that the flash data can be executed on the first target board while the flash data is being transmitted to the second target board.

[0044] This means, for example, that after transferring the flash data from the first target board to the first target memory, the PCIe multi-board switch switches its upstream port to the second target board to start the data transfer process for the second target board. Meanwhile, the data installation on the target memory can be performed by the first target board. Depending on the number of target boards arranged, for example, in the high-performance computer, this parallelization can save a significant amount of flash time in production.

[0045] Furthermore, the object is achieved by a method for flashing data between a flash station and the target board, comprising the steps: - Providing a first target board, wherein the first target board has a non-volatile first target memory and a first target processor, wherein the non-volatile first target memory is in communication with the first target processor, wherein the first target board has a first PCIe target root complex connected to the first target processor and a first target memory connected to at least the first PCIe target root complex, and - Providing the flash station, wherein the flash station has a non-volatile production memory and a production processor, wherein the non-volatile production memory is in communication with the production processor, wherein the flash station has a PCIe flash root complex connected to the production processor, - Preparation of the data to be flashed in the production memory as flash data by the production processor, - Providing a first Ethernet connection between the flash station and the first target board for authentication of the flash station on the first target board, - after authentication, loading and executing a flash kernel into the first target memory, whereby the flash kernel is present in the first target board or is transmitted to the first target processor via the first Ethernet connection, - Providing a first PCIe target endpoint on the first target board, which is connected to the PCIe target root complex, - Providing a PCIe flash endpoint on the flash station, which is connected to the PCIe flash root complex to form a flash connection between the first PCIe target endpoint and the PCIe flash endpoint for flashing the prepared flashed data from the flash station to the target board for storage in the non-volatile first target memory.

[0046] The advantages and advantageous features of the system can be transferred to the process.

[0047] Further features and advantages of the present invention will become apparent from the following description with reference to the accompanying figures, which schematically show: Fig. 1: different maximum transmission rates, Fig. 2: a system according to the invention in a first embodiment FGI 3: a system according to the invention in a second embodiment Fig. 4: a system according to the invention in a third embodiment Fig. 5: an application of the systems in comparison.

[0048] Newly developed functions in the automotive sector require ever-increasing computing power. To meet this demand, more and more high-performance computers are being produced. During production, an equally ever-increasing amount of data from vehicle control software, maps, infotainment data, driving models, etc. must be transferred to the non-volatile memory (NVM) of these devices—a process known as flashing.

[0049] By pre-flashing NVM memory and any associated components, large data packets can be transferred to a target board cost-effectively. However, different existing software versions increase the complexity of the logistical processes, as pre-flashed NVM components must be assigned to a specific target board without a unique hardware attribute, such as a hardware part number.

[0050] Flashing can be done via existing communication and / or debug interfaces on the target board.

[0051] Fig. 1 shows the speeds of the storage devices.

[0052] It has been recognized that a PCIe flash connection achieves much higher programming rates than the available communication interface speeds. This makes the communication interface speed the bottleneck of the flash process. Such potential programming speed is in Fig. 1, last line, shown.

[0053] Fig. Figure 2 shows a system 1a according to the invention in a first embodiment. It was recognized that the speed of the communication interface is responsible for a reduction in the data transfer rate, as it acts as a bottleneck for flashing.

[0054] The inventive system 1a for flashing data comprises a flash station 3 and a target board 2. The flash station 3 can also be designed as a computer / board / circuit board.

[0055] The target board 2 comprises a non-volatile target RAM 4, a target processor 5 (CPU), and a PCIe target root complex 6. Furthermore, the target board 2 comprises a target memory 7, which is embodied here as NVM memory. NVM (Non-Volatile Memory Express) is a communication interface and driver that utilizes the increased bandwidth offered by PCIe. An NVM controller 8 is also present. The target processor 5 is connected to the PCIe target root complex 6 and to the target memory 7 via the NVM controller 8 for data transmission. Furthermore, the PCIe target root complex 6 is connected to the target RAM 4 for data transmission.

[0056] PCIe (Peripheral Component Interconnect Express, PCI Express) is a high-speed serial computer expansion bus standard designed to connect peripheral devices to a main processor chipset (e.g., a central processing unit (CPU). PCI Express essentially defines a point-to-point connection. A PCI Express root complex (PCIe) is the intermediary between the central processing unit (CPU), memory, and the PCIe switch fabric, which includes one or more PCIe or PCI devices.

[0057] The flash station 3 has a non-volatile production storage 9 (production storage) and a production processor 10 (CPU), wherein the non-volatile production storage 9 is in communication with the production processor 10. Furthermore, the flash station 3 has a PCIe flash root complex 11, which is connected to the production processor 10 for data transmission.

[0058] The non-volatile production memory 9 contains the software variants / data to be installed on the target memory 7, i.e. the data to be flashed.

[0059] Furthermore, a production RAM 12 is present, which is connected to the production processor 10 via the PCIe flash root complex 11.

[0060] The production processor 10 is designed to mount the data to be flashed in the production memory 9 as flash data in the production main memory 10 as a virtual drive (mount M).

[0061] Furthermore, an Ethernet connection 13 is provided between the flash station 3 and the target board 2. For this purpose, the flash station 3 has an Ethernet controller 14 and an Ethernet connector 16 as an interface. Furthermore, the target board 2 has an Ethernet controller 18 and an Ethernet connector 19 as an interface. Via the Ethernet controller 14 and the Ethernet connector 16 as the interface of the flash station 3, the Ethernet connection 13 is established from the target board 2 to the target processor 5 via the Ethernet controller 18 and the Ethernet connector 19 as the interface.

[0062] The Ethernet connection 13 is a control connection, which can be used to establish the authentication of the flash station 3 on the target board 2. Thus, the flash station 3 is authenticated on the target board 2 via the Ethernet connection 13 as a control connection K between the target board 2 and the flash station 3 to ensure process security. This can be initiated by the target processor 5.

[0063] Furthermore, the target processor 5 is configured to load a flash kernel into the target main memory 4 as a loading process L after authentication and to execute it, for example, by mounting it as a virtual drive. The flash kernel is present in the target board 2 or can be transmitted to the target processor 5 via the Ethernet connection 13. Since the flash kernel has a small data size, it can be transmitted quickly via the Ethernet connection 13.

[0064] The flash kernel is a minimal operating system that provides basic services for flashing data.

[0065] Furthermore, this initializes the flash connection 15 or the flash process (flashing the data).

[0066] Subsequently, a flash connection 15 is established for flashing the FS. For this purpose, a PCIe flash endpoint 17 is configured on the flash station 3 using a PCIe connector and a PCIe repeater. Furthermore, a PCIe target endpoint 22 is present on the target board 3. This can comprise two PCIe connectors and an intermediate PCIe repeater. The supplied PCIe repeaters may be necessary due to the cable length limitation resulting from the high clock frequency of the PCIe bus and the potential loss of signal strength at the PCIe connectors.

[0067] Furthermore, a non-transparent bridge 21 (Non Transparent Bridge, NTB) is connected between the PCIe flash endpoint 17, i.e., after the PCIe repeater, and the PCIe flash root complex 11, for connecting the PCIe flash root complex 11 and the PCIe target root complex 6 via the flash connection 15.

[0068] The PCIe connection to target board 2 is thus realized via the non-transparent bridge 21 (NTB), which connects the root complexes 6, 11 and thus the flash station 3 and the target board 2. The non-transparent bridge 21 (NTB) enables isolation between the flash station 3 and the target board 2 while simultaneously enabling data exchange. This allows the flash data to be transmitted securely to the target board 2.

[0069] The PCIe connection (flash connection 15) establishes a point-to-point connection from the flash station 3 to the target board 2.

[0070] The system 1a according to the invention thus causes the flash data in the production RAM 12 of the flash station 3 to be prepared by the production processor 10 and integrated as a virtual drive. The PCIe connection to the target board 2 is realized via the non-transparent bridge 21 (NTB), which connects the PCIe flash root complex 11 and the PCIe target root complex 6, and thus the flash station 3 and the target board 2. The flash data integrated as a virtual drive is presented to the PCIe target root complex 6 of the target board 2 as a peripheral device, for example, as an NVM SSD (computer memory). The data transfer speed is limited only by the programming speed of the target memory 7 on the target board 2.

[0071] The system 1a according to the invention thus enables direct data transfer via PCIe, whereby the NVM (SSD target memory) of the target board 2 can be programmed at maximum speed

[0072] The system 1a according to the invention thus results in a significantly lower investment requirement for production lines. Furthermore, the production RAM 12 of the flash station 3 is connected to the target board 2 like a PCIe-capable memory module, which in turn eliminates the need for a separate data transmission protocol such as TCP / IP and the associated data overhead and software development effort.

[0073] Fig. Figure 3 shows a second embodiment of a system 1b according to the invention. The system 1b according to the invention for flashing data comprises the flash station 3 and the target board 2.

[0074] The target board 2 comprises the non-volatile target RAM 4 as well as the target processor 5 (CPU) and the PCIe target root complex 6. Furthermore, the target board 2 comprises the target memory 7, which is also designed as NVM memory here.

[0075] Furthermore, the NVM controller 8 is present. The target processor 5 is connected to the PCIe target root complex 6 and to the target memory 7 via the NVM controller 8 for data transmission. Furthermore, the PCIe target root complex 6 is connected to the target RAM 4 for data transmission.

[0076] The flash station 3 has the non-volatile production memory 9 (Production Store) and a production processor 10 (CPU), wherein the non-volatile production memory 9 is in communication with the production processor 10. Furthermore, the flash station 2 has the PCIe flash root complex 11, which is connected to the production processor 10 for data transmission.

[0077] The non-volatile production memory 9 contains the software variants / data to be installed on the target memory 7, i.e., the data to be flashed. Furthermore, a production RAM 12 is provided, which is connected to the production processor 10 via the PCIe flash root complex 11.

[0078] Furthermore, a flash memory 20 is provided, which is connected to a PCIe switch 24, so that the flash memory 20 is connected to the first PCIe target root complex 6 via the PCIe switch 24. The flash memory 20 can be designed as a solid-state drive (SSD), in particular as an NVM SSD.

[0079] The production processor 10 is designed to load the data to be flashed in the production memory 9 into the flash memory 20 (FL).

[0080] Furthermore, an Ethernet connection 13 is provided between the flash station 3 and the target board 2. For this purpose, the flash station 3 has the Ethernet controller 14 and the Ethernet connector 16 as an interface. Furthermore, the target board 2 has the Ethernet controller 18 and the Ethernet connector 19 as an interface. Via the Ethernet controller 14 and the Ethernet connector 16 as the interface of the flash station 3, the Ethernet connection 13 is established from the target board 2 to the target processor 5 via the Ethernet controller 18 and the Ethernet connector 19 as an interface.

[0081] The Ethernet connection 13 in turn serves as a control connection K, by means of which the authentication of the flash station 3 on the target board 2 can be established.

[0082] Thus, via the Ethernet connection 13 as a control connection K between target board 2 and flash station 3, flash station 3 is authenticated on target board 2 in order to ensure process security.

[0083] Furthermore, the target processor 5 is configured to load a flash kernel into the target main memory 4 as a loading process L after authentication and to execute it, for example, by mounting it as a virtual drive. The flash kernel is present in the target board 2 or can be transmitted to the target processor 5 via the Ethernet connection 13. Since the flash kernel has a small data size, it can be transmitted quickly via the Ethernet connection 13.

[0084] The flash kernel is a minimal operating system that provides basic services for flashing data.

[0085] The flash connection 15 for flashing FS 15 is then established. For this purpose, a PCIe flash endpoint 17 is provided on the flash station 3 using a PCIe connector and a PCIe repeater. Furthermore, a PCIe target endpoint 22 is provided on the target board 3. This can comprise two PCIe connectors with a PCIe repeater in between. The included PCIe repeaters may be necessary due to cable length limitations resulting from the high clock frequency of the PCIe bus and the potential loss of signal strength at the PCIe connectors.

[0086] The target board 2 then loads the flash data from the flash memory 20 via the PCIe switch 24, the PCIe flash endpoint 17 and the PCIe target endpoint 22 as the flash connection 15 into the target memory 7 as a load operation L.

[0087] The PCIe connection (flash connection 15) establishes a point-to-point connection from the flash station 3 to the target board 2.

[0088] The system 1b according to the invention uses an NVM SSD as flash memory 20 to store the prepared flash data on the factory side.

[0089] The PCIe switch 24 allows the flash memory 20 to be directly connected to the flash data transfer system, with full bandwidth and speed. The flash memory 20 is configured as a solid-state drive (SSD), specifically an NVM SSD.

[0090] Thanks to the standard transfer protocol, the NVM SSD does not require any additional drivers, achieving exceptionally high transfer rates. Furthermore, the prepared flash data is stored on the flash side. The data is transferred to the flash memory 20 via the PCIe switch 24.

[0091] This enables a fast speed transfer, wherein the speed of the flash connection 15 is only reduced by the read speed of the flash memory 20, for example the SSD read speed, on the flash station 3 side and the programming speed of the target RAM 4, ie the NVM programming speed, on the target board 2.

[0092] Fig. Figure 4 shows a third embodiment of a system 1c according to the invention. The system 1c according to the invention for flashing data comprises the flash station 3, the first target board 2a, and a second identically constructed target board 2b.

[0093] The first target board 2a includes the non-volatile target RAM 4a, the target processor 5a (CPU), and the PCIe target root complex 6a. Furthermore, the first target board 2a includes the target memory 7a, which is also implemented here as NVM memory.

[0094] Furthermore, the NVM controller 8a is present. The first target processor 5a is connected to the first PCIe target root complex 6a for data transmission and to the first target memory 7a via the first NVM controller 8a for data transmission. Furthermore, the first PCIe target root complex 6a is connected to the first target RAM 4a for data transmission.

[0095] The second target board 2b comprises the non-volatile second target RAM 4b, the second target processor 5b (CPU), and the second PCIe target root complex 6b. Furthermore, the second target board 2b comprises the second target memory 7b, which is also embodied as NVM memory.

[0096] Furthermore, the second NVM controller 8b is present. The second target processor 5b is connected to the second PCIe target root complex 6b for data transmission and to the second target memory 7b via the second NVM controller 8b for data transmission. Furthermore, the second PCIe target root complex 6b is connected to the second target RAM 4b for data transmission.

[0097] The flash station 3 includes the non-volatile production memory 9 (Production Store) and the production processor 10 (CPU), with the non-volatile production memory 9 communicating with the production processor 10. Furthermore, the flash station 3 includes the PCIe flash root complex 11, which is connected to the production processor 10 for data transmission.

[0098] The non-volatile production memory 9 contains the software variants / data to be installed on the first target memory 7a and the second target memory 7b, i.e. the data to be flashed.

[0099] Furthermore, the production RAM 12 is present, which is connected to the production processor 10 via the PCIe flash root complex 11.

[0100] The production processor 10 is designed to mount the data to be flashed in the production memory 9 as flash data in the production main memory 12 as a virtual drive (mount M).

[0101] Furthermore, a first Ethernet connection 13a is present between the flash station 3 and the first target board 2a.

[0102] For this purpose, the flash station 3 has the Ethernet controller 14a and the Ethernet connector 16a as an interface. Via the Ethernet controller 14a and the Ethernet connector 16a as the interface of the flash station 3, the first Ethernet connection 13a is established from the first target board 2a to the first target processor 5a via the first Ethernet controller 18a and the first Ethernet connector 19a as the interface. The first Ethernet connection 13a is a control connection K, which can be used to establish the authentication of the flash station 3 on the first target board 2a.

[0103] Furthermore, a second Ethernet connection 13b is present between the flash station 3 and the second target board 2b. For this purpose, the flash station 3 has the Ethernet controller 14b and the Ethernet connector 16b as an interface. Via the second Ethernet controller 14b and the second Ethernet connector 16b as an interface, the second Ethernet connection 13b is established from the second target board 2b to the second target processor 5b via the second Ethernet controller 18b and the second Ethernet connector 19b as an interface. The second Ethernet connection 13b is a control connection K, based on which the authentication of the flash station 3 on the second target board 2b can be established.

[0104] Thus, via the Ethernet connection 13a, 13b as a control connection K between the first target board 2a and the flash station 3 and the second target board 2b and the flash station 3, the flash station 3 is authenticated on the first target board 2a and the second target board 2b in order to ensure process security.

[0105] Furthermore, the first target processor 5a is configured to load and execute a flash kernel into the target main memory 4a as a loading process L after authentication, or to mount it as a virtual drive. The flash kernel is present in the first target board 2a or can be transmitted to the first target processor 5a via the first Ethernet connection 13a.

[0106] Furthermore, the second target processor 5b is configured to load and execute a flash kernel into the target RAM 4b as a loading process L after authentication, or to mount it as a virtual drive. The flash kernel is present in the second target board 2b or can be transmitted to the second target processor 5b via the second Ethernet connection 13b.

[0107] A flash connection 15 is then established for flashing the FS. For this purpose, a PCIe flash endpoint 17 is provided on the flash station 3 using a PCIe connector and a PCIe repeater.

[0108] The PCIe connection to the target board 2a,2b is realized via the non-transparent bridge 21 (Non Transparent Bridge, NTB), the PCIe flash root complex 11 and the PCIe flash endpoint 17.

[0109] Furthermore, a PCIe multi-board switch 23 is provided, which is connected to the first PCIe target root complex 6a and the second PCIe target root complex 6b. A PCIe multi-target endpoint 25 is provided between the PCIe flash endpoint 17 and the PCIe multi-board switch 23, for forming a flash connection 15 between the PCIe multi-board switch 23 and the PCIe flash endpoint 17 for flashing the prepared flashed data from the flash station 3 to the first target board 2a and the second target board 2b.

[0110] Such a system 1c allows flashing of the first target board 2a and the second target board 2b at maximum PCIe speed.

[0111] The PCIe multi-board switch 23 can first transmit the flash data to the first target board 2a and then transmit it to the second target board 2b, so that the flash data can be installed on the first target board 2a while the flash data is being transmitted to the second target board 2b. This means that, for example, after the flash data has been transferred to the first target memory 4a from the first target board 2a, the PCIe multi-board switch 23 switches its upstream port to the second target board 2b to start the data transfer process for the second target board 2b. In the meantime, the data installation on the target memory 7a can be performed by the first target board 2a. Depending on the number of target boards arranged, for example, in the high-performance computer, this parallelization can save a significant amount of flash time in production.

[0112] Fig.Figure 5 shows a flashing process using a system 1a, 1b, 1c according to the invention compared to the prior art. Flash data with a size of 50 GB is to be transferred with a target time of 5 seconds.

[0113] Data transfer over Ethernet would result in a single board flash time of approximately 50*1024 / 313 s = 164 s. This would require 164 / 5 = 33 parallel flash stations to maintain the required cycle time of 5 s.

[0114] Direct data transfer with the system 1a, 1b, 1b according to the invention enables the target memory 7, here embodied as an NVM SSD, to be programmed at maximum speed. This results in a flash time of 50*1024 / 2000 s = 26 s. This would require only 26 / 5 = 5 parallel flash stations in the production line to maintain the required cycle time of 5 s.

[0115] The system 1a, 1b, 1c according to the invention eliminates the “communication interface” bottleneck from the factory flashing process, since this system 1a, 1b, 1c provides a direct PCIe connection of the target boards 2, 2a, 2b to be programmed / flashed in the production line with the flash station 3. List of reference symbols 1a,1b,1c system 2,2a,2b target board 3 Flash Station 4,4a,4b Target memory 5, 5a,5b Target processor 6, 6a, 6b PCIe target root complex 7,7a,7b Target memory 8,8a,8b NVM controller 9 production storage 10 Production Processor 11 PCIe Flash Root Complex 12 production RAM 13,13a,13b Ethernet connection 14, 14a, 14b Ethernet controller of the flash station 15 Flash connection 16, 16a, 16b Ethernet connector of the flash station 17 PCIe flash endpoint 18,18a,18b Ethernet connector of the target board 19, 19a, 19b Ethernet controller of the target board 20 flash memory 21 non-transparent bridge 22 PCIe target endpoint 23 PCIe multiboard switch 24 PCIe switches 25 PCIe multi-target endpoint QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] DE 102015224829 A1

[0007]

Claims

[1] System (1a,1b,1c) for flashing data between a flash station (3) and a target board (2,2a), the system (1a,1b,1c) comprising the flash station (3) and a first target board (2,2a), characterized by , that the first target board (2, 2a) has a non-volatile first target memory (7, 7a) and a first target processor (5, 5a), wherein the non-volatile first target memory (7, 7a) is in communication with the first target processor (5, 5a), wherein the first target board (2, 2a) has a first PCIe target root complex (6, 6a) connected to the first target processor (5, 5a), and wherein the system (1a, 1b, 1c) has a first target memory (4, 4a) connected at least to the first PCIe target root complex (6, 6a), and wherein the flash station (3) has a non-volatile production memory (9) and a production processor (10), wherein the non-volatile production memory (9) is in communication with the production processor (10), wherein the flash station (3) has a PCIe flash root complex (11) which is connected to the production processor (10), and wherein the production processor (10) is designed to prepare the data to be flashed in the production memory (9) as flash data, and wherein a first Ethernet connection (13, 13a) is provided between the flash station (3) and the first target board (2, 2a) for authenticating the flash station (3) on the first target board (2, 2a), and wherein the first target processor (5, 5a) is designed to load and execute a flash kernel into the first target main memory (4, 4a) after authentication, wherein the flash kernel is present in the first target board (2, 2a) or can be transmitted to the first target processor (5, 5a) via the first Ethernet connection 13, 13a), and wherein the first target board (2,2a) has a first PCIe target endpoint (22) which is connected to the first PCIe target root complex (6,6a) and wherein the flash station (3) has a PCIe flash endpoint (17) which is connected to the PCIe flash root complex (11) for forming a flash connection (15) between the first PCIe target endpoint (22) and the PCIe flash endpoint (17) for flashing the prepared flashed data from the flash station (3) to the target board (2,2a) for storage in the non-volatile first target memory (7,7a). [2] System (1a,1b,1c) according to claim 1, characterized bythat the flash station (3) has a production working memory (12), wherein the production processor (10) is designed to mount the data to be flashed in the production working memory (12). [3] System (1a,1b,1c) according to claim 2, characterized by that the production processor (10) is designed to mount the data to be flashed into the production main memory (12) as a virtual drive. [4] System (1a,1b,1c) according to claim 3, characterized by that a non-transparent bridge (21, Non Transparent Bridge, NTB) is connected between the PCIe flash endpoint (17) and the PCIe flash root complex (11), for connecting the PCIe flash root complex (11) and the first PCIe target root complex (6,6a) via the flash connection (15). [5] System (1a,1b,1c) according to claim 1, characterized bythat the flash station (3) has a PCIe switch (24) which is connected between the PCIe flash endpoint (17) and the PCIe flash root complex (11), for connecting the PCIe flash endpoint to the first PCIe target root complex (6,6a) via the first PCIe target endpoint (22). [6] System (1a,1b,1c) according to claim 5, characterized by that a flash memory (20) which is bound to the PCIe switch (24) is present, so that the flash memory (20) is bound to the first PCIe target root complex (6, 6a) via the PCIe switch (24), and wherein the production processor (10) is designed to load the data to be flashed in the production memory (9) into the flash memory (20). [7] System (1a,1b,1c) according to claim 6, characterized by that the flash memory (20) is designed as a solid state drive (SSD). [8] System (1a, 1b, 1c) according to one of the preceding claims 5 to 7, characterized bythat the first target board (2,2a) is designed to load the flash data from the flash memory (20) via the PCIe switch (24) and the flash connection (15) between the PCIe flash endpoint (17) and the first PCIe target endpoint (22). [9] System (1a,1b,1c) according to claim 1, characterized by that a second target board (2b) is provided for forming a multiboard with the first target board (2, 2a), wherein the second target board (2b) has a non-volatile second target memory (7b) and a second target processor (5b), wherein the non-volatile second target memory (7b) is in communication with the second target processor (5b), wherein the second target board (2b) has a second PCIe target root complex (6b) connected to the second target processor (5b), and a second target RAM (4b) connected at least to the second PCIe target root complex (6b), and wherein a second Ethernet connection (13b) is provided between the flash station (3) and the second target board (2b) for authenticating the flash station (3) on the second target board (2b), and wherein the second target processor (5b) is configured to load and execute a flash kernel into the second target RAM (4b) after authentication, wherein the flash kernel is present in the second target board (2b) or can be transmitted to the second target processor (5b) via the second Ethernet connection (13b), and wherein a PCIe multi-board switch (23) is provided, which is connected to the first PCIe target root complex (6, 6a) and the second PCIe target root complex (6b), and wherein a PCIe multi-target endpoint (25) is provided, which is connected to the PCIe multi-board switch (23) as well as to the PCIe flash endpoint (17), for forming a flash connection (15) between the PCIe multi-board switch (23) and the PCIe flash endpoint (17) for flashing the prepared flashed data from the flash station (3) to the first target board (2, 2a) and to the second target board (2b). [10] System (1a,1b,1c) according to claim 9, characterized byin that the first target processor (5, 5a) is designed to mount a first virtual target drive in the first target main memory (4, 4a) for receiving the flash data via the first PCIe target root complex (6, 6a), and wherein the second target processor (5b) is designed to mount a second virtual target drive in the second target main memory (4b) for receiving the flash data via the second PCIe target root complex (6b). [11] System (1a, 1b, 1c) according to claim 9 or 10, characterized by that a production working memory (12) is present and the production processor (10) is designed to mount the data to be flashed into the production working memory (12). [12] System (1a,1b,1c) according to claim 11, characterized by that the production processor (10) is designed to mount the data to be flashed into the production main memory (12) as a virtual drive. [13] System (1a,1b,1c) according to claim 12, characterized bythat a non-transparent bridge (21, non-transparent bridge) is connected between the PCIe flash endpoint (17) and the PCIe flash root complex (11), for connecting the PCIe flash root complex (11) and the first PCIe target root complex (6,6a) as well as the second PCIe target root complex (6b) via the flash connection (15). [14] System (1a, 1b, 1c) according to one of the preceding claims 9 to 13, characterized by that the PCIe multi-board switch (23) is designed to first transmit the flash data to the first target board (2,2a) and then to the second target board (2b), so that the flash data can be executed on the first target board (2,2a) during the transmission of the flash data to the second target board (2b). [15] Method for flashing data between a flash station (3) and the target board (2,2a), comprising the steps: - Providing a first target board (2, 2a), wherein the first target board (2, 2a) has a non-volatile first target memory (7, 7a) and a first target processor (5, 5a), wherein the non-volatile first target memory (7, 7a) is in communication with the first target processor (5, 5a), wherein the first target board (2, 2a) has a first PCIe target root complex (6, 6a) connected to the first target processor (5, 5a) and a first target memory (4, 4a) connected at least to the first PCIe target root complex (6, 6a), and - Providing the flash station, wherein the flash station (3) has a non-volatile production memory (9) and a production processor (10), wherein the non-volatile production memory (9) is in communication with the production processor (10), wherein the flash station (3) has a PCIe flash root complex (11) connected to the production processor (10), - Preparation of the data to be flashed in the production memory (9) as flash data by the production processor (10), - Providing a first Ethernet connection between the flash station (3) and the first target board (2,2a) for authentication of the flash station (3) on the first target board (2,2a), - after authentication, loading and executing a flash kernel into the first target memory (4, 4a), wherein the flash kernel is present in the first target board (2, 2a) or is transmitted to the first target processor (5, 5a) via the first Ethernet connection, - providing a first PCIe target endpoint (22) on the first target board (2, 2a), which is connected to the PCIe target root complex (6, 6a), - Providing a PCIe flash endpoint on the flash station, which is connected to the PCIe flash root complex (11), to form a flash connection (15) between the first PCIe target endpoint (22) and the PCIe flash endpoint (17) for flashing the prepared flashed data from the flash station (3) to the first target board (2, 2a) for storage in the non-volatile first target memory (7, 7a).

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