Vertical wiring of a semiconductor device

Abstract

A method for producing a recess for a via in a semiconductor component is described. The semiconductor component has a semiconductor substrate. The semiconductor component comprises a first electrical insulation layer on its front side, a second electrical insulation layer on the first electrical insulation layer, and a contact area for the semiconductor substrate in or on the second electrical insulation layer. In the method, a blind-hole-like recess is formed through the semiconductor substrate up to the first electrical insulation layer. The first electrical insulation layer is removed within the recess. The recess is widened toward the contact area by partially removing the second electrical insulation layer.A third electrical insulation layer is applied to the inner walls of the extended recess, covering the first electrical insulation layer toward the extended recess. Finally, the second electrical insulation layer is anisotropically vertically etched toward the contact area until the contact area is exposed to the semiconductor substrate. The invention further relates to a method for producing a via in a semiconductor component, a semiconductor component and an X-ray detector module.

Description

[0001] The invention relates to a method for producing a recess for a through-hole in a semiconductor component. The invention also relates to a method for producing a through-hole in a semiconductor component. Furthermore, the invention relates to a semiconductor component. Furthermore, the invention relates to an X-ray detector module comprising such a semiconductor component.

[0002] An X-ray detector comprises several layers with different functions. First, an X-ray detector comprises a sensor layer with a sensor material. In a so-called direct-conversion X-ray detector, X-ray quanta are converted directly in the sensor material into electrical charge pulses, the total charge of which represents a measure of the energy of the X-ray quanta. Cadmium telluride or cadmium zinc telluride is preferably used as the sensor material for such a direct-conversion X-ray detector. The sensor layer forms an active pixel area for detecting X-rays. During an X-ray image, the captured X-rays generate a continuous pulse train in the sensor layer.

[0003] The pulses thus generated are counted at an adjustable counting interval by a counting unit, preferably an ASIC, connected downstream of the sensor layer, and their height is measured. Such a counting unit has a plurality of signal processing channels arranged in a special pixel matrix, so-called subpixels. Each subpixel is intended to measure the number of pulses in the pulse train. The height of the charge pulses is compared with a predetermined set of thresholds, and the corresponding pulse number is recorded. Assuming that the absorption of an X-ray photon triggers exactly one charge pulse, the pulse number corresponds to the number of absorbed X-ray photons. Assuming that the height of the pulse is proportional to the energy of the X-ray photon, the aforementioned threshold can also be equated with an energy threshold.

[0004] The circuits or active circuits of the counting unit, especially the ASICs, are arranged on the top side of a semiconductor substrate of an X-ray detector module, i.e., the side of the semiconductor substrate facing an X-ray source, usually in the so-called CMOS layer (CMOS stands for "complementary metal-oxide-semiconductor"). The active circuits form an integrated circuit with the semiconductor substrate.

[0005] Connected to the ASICs or semiconductor substrate is a carrier substrate, which can be made of ceramic or circuit board material. Vias run through the ASIC layer and the semiconductor substrate, transmitting the counting signals generated by the ASICs to the aforementioned carrier substrate, where charge transfer of counting signals and distribution of control signals and energy flows take place. This carrier substrate is therefore also referred to below as the distribution unit. From the distribution unit, combined signals are forwarded via ribbon cables to an evaluation unit, also known as the "module backplane."

[0006] The active pixel area of an X-ray detector must be as large as possible to detect as much of the X-ray radiation that has passed through the patient as possible. Wiring that limits the usable area for detection can be disruptive. At the same time, the connecting elements used must be robust against mechanical stress and long-term stable without negatively affecting electrical performance (e.g., through resistance or leakage currents). The process for manufacturing the connecting elements must be compatible with the sensors and integrated circuits to be connected. It must be possible to test the manufactured parts after each production step. Test contacts should be connectable to the ASICS and sensors to enable testing of the sensors and ASICS during production.

[0007] If so-called vias are used as connecting elements, it is important that the structure of the sensor chip or the semiconductor component carrying the counting unit is not damaged during the formation of the vias.

[0008] It is an object of the invention to develop a manufacturing process for a semiconductor component and such a semiconductor component, in particular an X-ray detector module with such a semiconductor component, which simplify and make more effective the testability of such a semiconductor component during manufacture.

[0009] This object is achieved by a method for producing a recess for a via in a semiconductor component according to patent claim 1, by a method for producing a via in a semiconductor component according to patent claim 5, by a semiconductor component according to patent claim 10 and an X-ray detector module according to patent claim 13.

[0010] In the method according to the invention for producing a recess for a through-hole in a semiconductor component, a semiconductor component is first provided as the starting product. The semiconductor component already has a plurality of basic elements designed as carriers for electronic circuits, to prevent short-circuit currents, and to test the electronic circuits.

[0011] These basic elements comprise a semiconductor substrate with a back side and a front side. These two sides are formed by the two flat sides of the semiconductor substrate. A first electrical insulation layer is formed on the front side of the semiconductor substrate. A second electrical insulation layer is arranged on the first electrical insulation layer.

[0012] The semiconductor component also comprises a contact area for the semiconductor substrate in or on the second electrical insulation layer and preferably a test contact on the contact area.

[0013] Within the scope of the method according to the invention, a blind hole-like recess is first created or formed through the semiconductor substrate down to the first electrical insulation layer. The first electrical insulation layer is removed within the blind hole-like recess. The recess is widened in the vertical direction, i.e. transversely to the contact area and towards the contact area, preferably by partially removing the second electrical insulation layer. Furthermore, a third electrical insulation layer is applied to inner walls of the widened recess, wherein the first electrical insulation layer is covered towards the widened recess. Finally, an anisotropic vertical etching, i.e. transversely to the layer sequence, of the second electrical insulation layer takes place until the contact area to the semiconductor substrate is exposed and the recess for the through-hole connection is thus completely formed.During anisotropic etching, the second electrical insulation layer and the third electrical insulation layer are completely removed from the contact surface. Advantageously, the first electrical insulation layer is protected against damage during anisotropic etching by the third electrical insulation layer. Without suitable protection, it is often possible that the first electrical insulation layer will be damaged during anisotropic etching, which can contribute to a defect or impaired functional properties of the semiconductor component. In particular, lateral etching into the first electrical insulation layer should be avoided during the anisotropic etching step. Such etching can represent starting points for mechanical cracks in the semiconductor component.Protecting the first electrical insulation layer is particularly effective and useful when the material of the first electrical insulation layer is particularly sensitive to the anisotropic etching step, whereas the material of the second and third electrical insulation layers, which preferably differs from the material of the first electrical insulation layer, reacts relatively robustly to the anisotropic etching, particularly with regard to the lateral undercutting of the respective layer. It should be noted that the recess for a through-hole connection is not limited to application on semiconductor substrates of X-ray detector modules, but can also be used in other sensor components, such as pixel-based sensor components of optical image acquisition units.

[0014] In the method according to the invention for producing a through-hole via in a semiconductor component, the method according to the invention is used to produce a recess for a through-hole via in a semiconductor component. Furthermore, a barrier layer is applied to a surface of the third electrical insulation layer facing away from the first electrical insulation layer and to the contact area in the recess. Preferably, the recess is completely lined with the barrier layer. The barrier layer prevents the conductor material, which is to be applied in the subsequent step, from diffusing into underlying layers and regions.

[0015] A conductor track is then applied to the semiconductor substrate and into the recess on the barrier layer. The conductor track forms an electrical connection between the backside of the semiconductor substrate and the contact surface of the semiconductor component.

[0016] A first passivation layer is then applied to the back of the conductor. This passivation layer protects the conductor from corrosion.

[0017] A contact element is applied to the conductor track, which forms an electrical contact between the semiconductor component and a neighboring electronic component, preferably a sensor unit of an X-ray detector module. The contact element is preferably made of gold, which is electrically conductive and highly corrosion-resistant. The method for producing a via in a semiconductor component shares the advantages of the method for producing a recess for a via in a semiconductor component.

[0018] The semiconductor component according to the invention comprises a semiconductor substrate with a rear side and a front side. As already explained, the two aforementioned sides are formed by the two flat sides of the semiconductor substrate. The semiconductor component has a first electrical insulation layer on the semiconductor substrate and a second electrical insulation layer on the first electrical insulation layer. Furthermore, the semiconductor component comprises a contact area for the semiconductor substrate on or in the second electrical insulation layer. The semiconductor component according to the invention has a recess for a through-connection between the semiconductor substrate and the contact area. The recess extends as far as the contact area.Furthermore, a third electrical insulation layer is formed on inner walls of the recess, wherein the first electrical insulation layer is covered by the third electrical insulation layer towards the recess.

[0019] The X-ray detector module according to the invention comprises a sensor unit and a semiconductor component according to the invention. The semiconductor substrate of the semiconductor component comprises counting electronics, which is electrically connected to the semiconductor component. The X-ray detector module according to the invention also comprises a distribution unit, which is electrically connected to the semiconductor component according to the invention. The X-ray detector module further comprises an evaluation unit, which is electrically connected to the distribution unit, preferably by one or more flat cables. The X-ray detector module shares the advantages of the semiconductor component according to the invention.

[0020] The invention also includes a control device for controlling the steps for executing the inventive method for producing a recess for a through-hole in a semiconductor component and the inventive method for producing a through-hole in a semiconductor component. The control device can, in particular, control a semiconductor production device to execute the steps of the inventive method for producing a recess for a through-hole in a semiconductor component or the inventive method for producing a through-hole in a semiconductor component.

[0021] A large part of the aforementioned control device for controlling the steps of the inventive method for producing a recess for a through-hole in a semiconductor component and of the inventive method for producing a through-hole in a semiconductor component can be implemented entirely or partially in the form of software modules in a processor of a corresponding computer system, e.g., by a control device of a device for producing a semiconductor component or a semiconductor production device. A largely software-based implementation has the advantage that even previously used computer systems for controlling the production of semiconductor components can be easily upgraded to operate in the inventive manner by means of a software update.In this respect, the object is also achieved by a corresponding computer program product with a computer program that can be loaded directly into a computer system, with program sections for executing control processes for implementing the steps of the method according to the invention for producing a recess for a through-hole in a semiconductor component or the method for producing a through-hole in a semiconductor component. In addition to the computer program, such a computer program product may optionally comprise additional components such as documentation and / or additional components, including hardware components such as hardware keys (dongles, etc.) for using the software.

[0022] A computer-readable medium, e.g., a memory stick, a hard disk, or another portable or permanently installed data storage device, on which the program sections of the computer program that can be read and executed by a computer system are stored, can be used for transport to the computer system or control device and / or for storage on or in the computer system or control device. For this purpose, the computer system can, for example, have one or more cooperating microprocessors or the like.

[0023] The dependent claims and the following description each contain particularly advantageous embodiments and developments of the invention. In particular, the claims of one claim category can also be developed analogously to the dependent claims of another claim category. Furthermore, within the scope of the invention, the various features of different embodiments and claims can also be combined to form new embodiments.

[0024] In a preferred variant of the method according to the invention for producing a recess for a through-hole in a semiconductor component, the first electrical insulation layer comprises silicon nitride, and the second and third electrical insulation layers comprise silicon dioxide. Silicon nitride can be used, for example, as a masking and stop material in the structuring of the semiconductor substrate.

[0025] Preferably, the conductor track comprises one of the following materials: - copper, - aluminum, - Tungsten.

[0026] Copper, at 58 MS / m (MS = mega-Siemens), has the best conductivity of the three materials mentioned. Tungsten is particularly resistant. Aluminum is comparatively inexpensive and does not tend to diffuse into the substrate material. Tungsten can be used as a contact material between aluminum conductors and lines made of other materials.

[0027] Particularly preferably, the first rear passivation layer comprises one of the following materials: - Nickel, - silicon dioxide, - Polyimide.

[0028] Nickel is an electrical conductor. Silicon dioxide and lead oxide are electrical insulators. Polyimides are chemically and heat-resistant. Polyimides are used in electrical engineering for their heat resistance, low outgassing, radiation resistance, and insulating properties.

[0029] In one embodiment of the method according to the invention for producing a through-hole via in a semiconductor component, the backside of the semiconductor substrate is structured and provided with a second backside passivation layer on the third electrical insulation layer and on the conductor track. Areas of the backside of the semiconductor substrate not used for contacting are advantageously insulated and protected against corrosion.

[0030] Preferably, the second rear passivation layer comprises one of the following materials: - polyimide, - silicon nitride, - Silicon dioxide.

[0031] The materials mentioned are electrical insulators and relatively durable, and protect the part of the back of the semiconductor substrate not used for contacting against corrosion and leakage currents.

[0032] The invention is explained in more detail below with reference to exemplary embodiments in the accompanying figures. They show: Fig. 1 a schematic representation of an X-ray detector module, Fig. 2 a schematic representation of a semiconductor component which is used as a substrate for a counting unit of an X-ray detector module, Fig. 3 shows a schematic representation of a step for etching a blind hole-like recess in a semiconductor component as part of the method for producing a recess for a through-connection in a semiconductor component according to an embodiment of the invention, Fig. 4 a schematic representation of a step for removing a first electrical insulation layer in the region of the recess in the context of the method for producing a recess for a through-connection in a semiconductor component according to an embodiment of the invention, Fig. 5 shows a schematic representation of a step for applying a third electrical insulation layer in the context of the method for producing a recess for a through-connection in a semiconductor component according to an embodiment of the invention, Fig. 6 shows a schematic representation of a step for anisotropic vertical etching of the second electrical insulation layer until the test contact is exposed in the context of the method for producing a recess for a through-connection in a semiconductor component according to an embodiment of the invention, Fig. 7 shows a schematic representation of a step for applying a barrier layer on the surface of the third electrical insulation layer and on the test contact in the recess as part of the method for producing a via in a semiconductor component according to an embodiment of the invention, Fig. 8 shows a schematic representation of the step of applying a conductor track on a semiconductor substrate and in the recess on the barrier layer in the context of the method for producing a via in a semiconductor component according to an embodiment of the invention, Fig. 9 is a schematic representation of the step of applying a first rear-side passivation layer to the conductor track in the context of the method for producing a via in a semiconductor component according to an embodiment of the invention, Fig. 10 shows a schematic representation of the step for structuring the back side of the semiconductor substrate in the context of the method for producing a via in a semiconductor component according to an embodiment of the invention, Fig. 11 is a schematic representation of the application of contact elements on the back side of the semiconductor substrate in the context of the method for producing a through-connection in a semiconductor component according to an embodiment of the invention, Fig. 12 is a flowchart illustrating a method for forming a via in a semiconductor device according to an embodiment of the invention.

[0033] In Fig. 1 shows a schematic representation of a direct-conversion X-ray detector module 15. Such an X-ray detector module 15 has a sensor unit 30 with a plurality of sensors, which, for example, have cadmium telluride as the sensor material. The sensor unit 30 is connected via so-called solder balls LB to a semiconductor component 1, which comprises a counting unit 20, which is formed on the side of the semiconductor component 1 facing the sensor unit 30 (also referred to as the rear side) and has a plurality of electronic circuits, so-called ASICs (ASIC is an acronym for "application-specific integrated circuit"). The ASICs (in Fig. 1 not shown) are electrically connected to the underside of the semiconductor component 1 via vias.

[0034] The X-ray detector module 15 also includes a distribution unit 40, which comprises a ceramic material and has lines for supplying power to the ASICs in the semiconductor component 1 and for signal distribution. The distribution unit 40 is electrically connected to the semiconductor component 1 via solder balls LB.

[0035] Also part of the X-ray detector module 15 is an evaluation unit 50, which comprises a modular back-wiring system spatially separated from the aforementioned units 1, 30, 40. The evaluation unit 50 is electrically connected to the distribution unit 40 via ribbon cable K and supplies electrical power and control data via the ribbon cable K, as well as signal data generated by the sensor unit 30 and the counting unit 20.

[0036] In Fig. 2 shows a schematic representation of an output stage of a semiconductor component 1 which is used, for example, in an X-ray detector module 15 as a carrier of a counting unit 20 of an X-ray detector module 15 which is used in Fig. 1. The semiconductor component 1 comprises a semiconductor substrate 2 with a front side and a back side. The back side is to be the Fig. 2, the top side of the semiconductor substrate 2 is considered to be the top side, and the bottom side is considered to be the front side. A first narrow electrical insulation layer 3 on the front side of the semiconductor substrate 2 is connected to the semiconductor substrate 2. The first electrical insulation layer 3 comprises, for example, silicon nitride. A second wide electrical insulation layer 4 is connected to the first electrical insulation layer 3. The second electrical insulation layer 4 comprises, for example, silicon dioxide as the insulating material. Integrated into the second electrical insulation layer 4 is a contact surface 5 in the form of a so-called landing pad. The landing pad provides an electrical connection to electronic circuits (not shown) located on the back side of the semiconductor substrate 2. However, for this purpose, a through-hole connection must be created from the back side of the semiconductor substrate 2 to the contact surface 5, which is Fig. 3 to Fig. 11 is illustrated in detail. On the back of the contact area 5 or the landing pad, i.e. on the side of the contact area 5 facing the second electrical insulation layer 4, there is an electrically conductive barrier layer 5a, which can be made of titanium, titanium nitride, or tungsten, for example. Such a barrier layer 5a can be used, for example, as an etch stop layer and protective layer in the subsequent steps for forming a via, in particular to protect the metal of the contact area 5 or the landing pad, for example copper or aluminum. The landing pad or the contact area 5 is connected to a test contact 6, which can be electrically contacted by a test device (not shown) for testing purposes. The test contact 6 comprises, for example, metal compounds made of copper and nickel or palladium or gold.The test contact 6 can be used to test the electronic circuits (not shown) located on the back of the semiconductor substrate 2. A passivation layer 7, made of polyimide or lead oxide, for example, is applied to the front of the semiconductor component 1. This passivation layer 7 omits the test contact 6 so that electrical contacting of the test contact by a test device is still possible.

[0037] In Fig. 3 is a schematic representation of a step for etching a blind-hole-like recess A in a semiconductor component 1 as part of the method for producing a recess A'' for a via in a semiconductor component 1 according to an embodiment of the invention. The blind-hole-like recess A is positioned at a location in the semiconductor substrate 2 of the semiconductor component 1 at which a via is to be formed as an electrical connection between electronic circuits located on the backside of the semiconductor substrate 2 and the landing pad or contact area 5.

[0038] In Fig. 4 is a schematic representation of a step for removing the first electrical insulation layer 3 in the region of the recess A in the context of the method for producing a recess A'' for a through-connection in a semiconductor component 1 according to an embodiment of the invention. Fig. 4 shown step is vividly speaking the bottom of the in the Fig. 3, which is formed by the first electrical insulation layer 3, is removed by etching. Furthermore, the second electrical insulation layer 4 is also etched slightly, but not completely, i.e., in particular, not up to the barrier layer 5a, which separates the second electrical insulation layer 4 from the landing pad or contact area 5.

[0039] In Fig. 5 is a schematic representation of a step for applying a third electrical insulation layer 8 within the scope of the method for producing a recess A'' for a through-hole in a semiconductor component 1 according to an embodiment of the invention. The third electrical insulation layer 8 is introduced into the enlarged blind hole of the recessed recess A' and also formed on the rear side of the semiconductor substrate 2. The third electrical insulation layer 8 comprises silicon dioxide or plastics as material and in particular covers the first electrical insulation layer 3 towards the recessed recess A', so that in the next etching step, which is Fig. 6, the first electrical insulation layer 3 is not etched in the horizontal direction, which could lead to cracks in the semiconductor component 1 and to short circuits or malfunctions of electronic circuits located in the semiconductor component 1.

[0040] In Fig. 6 is a schematic representation of a step for anisotropic vertical etching of the second electrical insulation layer 4 until the barrier layer 5a located on the contact area 5 is exposed, as part of the method for producing a recess A'' in a semiconductor component 1 according to an embodiment of the invention. Anisotropic etching can be realized, for example, by utilizing an orientation of a crystal structure of a material. In any case, directed etching takes place in the vertical direction, i.e., in the direction of the layer sequence up to the barrier layer 5a. By anisotropic etching up to the barrier layer 5a, the recess A'', which is required for forming a via, is completely formed in the semiconductor component 1.

[0041] In Fig. Figure 7 is a schematic illustration of a step for applying a barrier layer 9 to the surface of the third electrical insulation layer 8 and to the barrier layer 5a in the recess as part of the method for producing a via in a semiconductor component according to an embodiment of the invention. The barrier layer 9 comprises, for example, titanium or tungsten as a material. The barrier layer 9 prevents subsequently applied conductor materials from penetrating the third electrical insulation layer 8.

[0042] In Fig. Figure 8 is a schematic illustration of the step of applying a conductor track 10 on the semiconductor substrate 2 and in the recess A'' on the barrier layer 9 as part of the method for producing a via in a semiconductor component 1 according to an embodiment of the invention. The conductor track 10 can, for example, comprise highly electrically conductive materials such as copper, aluminum, or tungsten and can be formed in one or two layers.

[0043] In Fig. Figure 9 is a schematic illustration of the step of applying a first rear-side passivation layer 11 to the conductor track 10 as part of the method for producing a via in a semiconductor component 1 according to an embodiment of the invention. The passivation layer 11 protects the material of the conductor track 10 from corrosion.

[0044] In Fig. 10 is a schematic illustration of the step of structuring the backside of the semiconductor substrate 2 within the scope of the method for producing a via in a semiconductor device according to an embodiment of the invention. The structuring of the backside of the semiconductor substrate 2 (in Fig. 10 the back is the top as in the other Fig. 2 to 9 and 11) comprises in particular the partial removal of the rear passivation layer 11 and also the partial removal of the conductor track 10 and the barrier layer 9.

[0045] In Fig. 11 is a schematic representation of the step of applying a contact element 12 to the back side of the semiconductor substrate 2 as part of the method for producing a through-hole plating in a semiconductor component 1 according to an embodiment of the invention. The contact element 12 can be designed as a so-called solder pad and comprise gold as the material. Furthermore, a second rear-side passivation layer 13 is also applied to the back side of the semiconductor substrate 2 in order to protect the conductor track 10 from corrosion. The contact element 12 can be applied via a so-called solder ball LB (see Fig. 1) with the sensors 1a (see Fig. 1) be electrically connected.

[0046] In Fig. 12 shows a flowchart 1200 illustrating a method for producing a via in a semiconductor device 1 according to an embodiment of the invention.

[0047] In step 12.I, the Fig. 3, the etching step already illustrated is carried out, in which a blind hole-like recess A is formed through the semiconductor substrate 2 of the semiconductor component 1 up to the first electrical insulation layer 3.

[0048] In step 12.II, the first electrical insulation layer 3 within the blind hole-like recess A is removed and the recess A is extended in the vertical direction towards a barrier layer 5a of a contact surface 5 by etching the second electrical insulation layer 4, without reaching the barrier layer 5a, whereby a recessed recess A' is created, as already described in Fig. 4 is illustrated graphically.

[0049] In step 12.III, a third electrical insulation layer 8 is applied to the inner walls of the extended or recessed recess A', whereby the first electrical insulation layer 3 is covered towards the extended recess A'. Step 12.III is already described in Fig. 5 illustrated.

[0050] In step 12.IV, the second electrical insulation layer 4 is anisotropically etched vertically in the region of the recessed cutout A' until the barrier layer 5a of the landing pad 5 or the contact area 5 above the test contact 6 is exposed and the cutout A'' for the through-plating is completely formed, which is already Fig. 6 is shown.

[0051] In step 12.V, a barrier layer 9 is applied to the surface of the third electrical insulation layer 8 and to the test contact 6 in the recess A''. This step is already described in Fig. 7 shown.

[0052] In step 12.VI, a conductor track 10 is applied to the semiconductor substrate 2 and in the recess A'' on the barrier layer. This step is in Fig. 8 is illustrated graphically.

[0053] In step 12.VII, a first rear-side passivation layer 11 is applied to the conductor track 10. This step is already described in Fig. 9 illustrated.

[0054] In step 12.VIII, a structuring S is carried out on the back of the semiconductor substrate 2. This structuring S is in Fig. 10 on the back side of the semiconductor substrate 2 (shown there as the top side).

[0055] In step 12.IX, contact elements 12 are applied to the back side of the semiconductor substrate 2 and a back passivation layer 13 is applied to the back side of the semiconductor substrate 2.

[0056] Finally, it is pointed out once again that the detailed methods and devices described above are exemplary embodiments and that the basic principle can be varied widely by a person skilled in the art without departing from the scope of the invention, insofar as it is defined by the claims. For the sake of completeness, it is also pointed out that the use of the indefinite articles “a” or “an” does not exclude the possibility that the features in question may be present in multiple copies. Likewise, the term “unit” does not exclude the possibility that it consists of several components, which may also be spatially distributed. Regardless of the grammatical gender of a particular term, this includes persons with male, female or other gender identities.

Claims

[1] Method for producing a recess (A'') for a through-hole in a semiconductor component (1), which semiconductor component (1) comprises: - a semiconductor substrate (2) having a back side and a front side, - a first electrical insulation layer (3) on the front side of the semiconductor substrate (2), - a second electrical insulation layer (4) on the first electrical insulation layer (3), - a contact surface (5) for the semiconductor substrate (5) in or on the second electrical insulation layer (4), the method comprising the steps of: - Creating a blind hole-like recess (A) through the semiconductor substrate (2) up to the first electrical insulation layer (3), - removing the first electrical insulation layer (3) within the blind hole-like recess (A), - widening the blind hole-like recess (A) towards the contact surface (5) by partially removing the second electrical insulation layer (4), - applying a third electrical insulation layer (8) to inner walls of the extended recess (A'), wherein the first electrical insulation layer (3) is covered towards the extended recess (A'), - Anisotropic etching of the second electrical insulation layer (4) in the direction of the contact surface (5) until the contact surface (5) is exposed to the semiconductor substrate (2). [2] The method of claim 1, wherein the first electrical insulation layer (3) comprises silicon nitride and the second and third electrical insulation layers (4, 8) comprise silicon dioxide. [3] Method according to claim 1 or 2, wherein the creation of a blind hole-like recess (A) comprises an etching step. [4] Method according to one of claims 1 to 3, wherein the partial removal of the second electrical insulation layer (4) comprises etching the second electrical insulation layer (4). [5] Method for producing a via in a semiconductor component (1), comprising the steps: - Carrying out the method according to one of the preceding claims, - applying a barrier layer (9) on a surface of the third electrical insulation layer (8) facing away from the first electrical insulation layer (3) and on the contact surface (5) in the recess (A''), - applying a conductor track (10) on the semiconductor substrate (2) and in the recess (A'') on the barrier layer (9), - applying a first rear passivation layer (11) on the conductor track (10), - Applying a contact element (12) to the conductor track (10). [6] Method according to claim 5, wherein the conductor track (10) comprises one of the following materials: - copper, - aluminum, - Tungsten. [7] Method according to claim 5 or 6, wherein the first back-side passivation layer (11) comprises one of the following materials: - Nickel, - silicon dioxide, - platinum and / or wherein the contact element (12) comprises gold as material. [8] Method according to one of claims 5 to 7, wherein the back side of the semiconductor substrate (2) is structured and provided with a second back-side passivation layer (13) on the third electrical insulation layer (8) and on the conductor track (10). [9] The method of claim 8, wherein the second backside passivation layer (13) comprises one of the following materials: - polyimide, - silicon nitride, - Silicon dioxide. [10] Semiconductor component (1), comprising: - a semiconductor substrate (2) having a back side and a front side, - a first electrical insulation layer (3) on the front side of the semiconductor substrate (2), - a second electrical insulation layer (4) on the first electrical insulation layer (3), - a contact surface (5) for the semiconductor substrate (2) in or on the second electrical insulation layer (4), - a recess (A'') for a through-connection between the semiconductor substrate (2) and the contact surface (5), wherein the recess (A'') extends as far as the contact surface (5) and a third electrical insulation layer (8) is formed on inner walls of the recess (A''), wherein the first electrical insulation layer (3) is covered by the third electrical insulation layer (8) towards the recess (A''). [11] A semiconductor device according to claim 10, further comprising: - a barrier layer (9) on a surface of the third electrical insulation layer (8) facing away from the first electrical insulation layer (3) and on the contact surface (5) in the recess (A''), - a conductor track (10) on the semiconductor substrate (2) and in the recess (A'') on the barrier layer (9), - a first rear passivation layer (11) on the conductor track (10), - a contact element (12) on the first rear passivation layer (11). [12] A semiconductor device according to claim 11, comprising: - a structured back side of the semiconductor substrate (2), - a second rear passivation layer (13) on the third electrical insulation layer (8) and on the conductor track (10). [13] X-ray detector module (15), comprising: - a sensor unit (30), - a semiconductor component (1) according to one of claims 10 to 12, wherein the semiconductor substrate (2) of the semiconductor component (1) has a counting electronics (20) which is electrically connected to the semiconductor component (1), - a distribution unit (40) which is electrically connected to the semiconductor component (1), - an evaluation unit (50) which is electrically connected to the distribution unit (40). [14] Computer program product comprising a computer program which is directly loadable into a control device of a semiconductor production device, with program code sections to carry out all steps of a method according to one of claims 1 to 9 when the program is executed in the control device. [15] Computer-readable medium on which program sections executable by a computer unit are stored in order to carry out the steps of a method according to one of claims 1 to 9 when the program sections are executed by the computer unit.

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