Method for determining the number of cycles completed by an oscillator in a phase-locked loop

Abstract

The invention relates to a method (100) for determining a number of cycles completed by an oscillator (2) in a phase-locked loop (1), comprising the following steps: - initiating (101) a first recording of a counter reading of a counter (3) of the phase-locked loop (1), - initiating (102) a second recording of the counter reading of the counter (3) of the phase-locked loop (1), the second recording being carried out with a time offset from the first recording, - determining (103) a fractional portion of phase information of the oscillator (2), - checking (104) the first recording and the second recording on the basis of the determined fractional share of the phase information, - Determining (105) the number of cycles of the oscillator (2) completed by selecting the first recording or the second recording based on a result of the testing (104). Furthermore, the invention relates to a computer program, a device and a storage medium for this purpose.

Description

[0001] The invention relates to a method for determining the number of cycles completed by an oscillator in a phase-locked loop. Furthermore, the invention relates to a computer program, a device, and a storage medium for this purpose. State of the art

[0002] A phase-locked loop (PLL) is a control system that stabilizes an output frequency by synchronizing it to a reference frequency. This is achieved by continuously adjusting the phase of the oscillator so that it matches the phase of the reference signal. PLLs are widely used in communications technology, for example, in frequency synthesis, modulation, and demodulation.

[0003] Accurately determining the number of cycles completed in a phase-locked loop (PLL) is important for the following reasons. In many applications, such as telecommunications systems, it is crucial to precisely synchronize the frequency. Correct cycle counting ensures that the PLL accurately targets the desired frequency. In digital communications systems, the integrity of the transmitted data depends on accurate phase and frequency matching. Incorrectly determining the number of cycles can lead to data loss or corruption. Correct cycle tracking is also essential for the long-term stability of the PLL system, especially in applications that require high precision over extended periods.

[0004] However, there are several challenges involved in accurately determining the number of cycles. Noise can cause phase jitter in a phase-locked loop (PLL), making accurate cycle counting difficult. This noise can originate from internal or external sources and causes uncertainty in the phase measurement. Furthermore, distortions in the signal, whether caused by the transmission path or the hardware itself, can affect the accuracy of the cycle count. Furthermore, PLLs are often used in dynamic environments where frequency and phase can change rapidly. Accurately capturing these rapid changes presents another technical challenge.

[0005] Digital PLLs running with a variable clock therefore require, in particular, a way to obtain counter values ​​that are clocked according to a (stable) reference clock. This overlap of clock domains is solved in the state of the art, for example, by clock retimers with high resource requirements, which, however, only reduce the probability of a synchronization error.

[0006] For example, document EP 3 291 447 B1 describes a digital phase-locked loop, DPLL, for phase-locking an output signal with a reference clock signal.

[0007] For example, US 10 007 235 B2 discloses a time-to-digital converter (TDC) that measures a time interval between a leading signal and a trigger signal. Disclosure of the invention

[0008] The subject matter of the invention is a method having the features of claim 1, a computer program having the features of claim 8, a device having the features of claim 9, and a computer-readable storage medium having the features of claim 10. Further features and details of the invention emerge from the respective subclaims, the description, and the drawings. Features and details described in connection with the method according to the invention naturally also apply in connection with the computer program according to the invention, the device according to the invention, and the computer-readable storage medium according to the invention, and vice versa, so that with regard to the disclosure of the individual aspects of the invention, reference is or can always be made to each other.

[0009] The invention particularly relates to a method for determining a number of cycles completed by an oscillator in a phase-locked loop, comprising the following steps, wherein the steps can be carried out repeatedly and / or successively.

[0010] In a first step, a first recording of a counter reading of a counter in the phase-locked loop is preferably initiated. Within the scope of the present invention, the counter reading is preferably determined during the recording based on a respective initiation by an input pulse, which also applies to the second recording described below.

[0011] In a further step, a second recording of the counter reading of the phase-locked loop counter is preferably initiated, with the second recording being performed with a temporal offset from the first recording. The second recording is, in particular, also phase-shifted from the first recording.

[0012] In a further step, a fractional portion of the oscillator's phase information is preferably determined. The fractional portion describes, in particular, a temporally elapsed portion of an oscillation period, or a corresponding portion of a phase shift, of the oscillator at a given measurement time.

[0013] In a further step, the first recording and the second recording are preferably checked based on the determined fractional portion of the phase information. This advantageously makes it possible to determine which of the first or second recordings can provide a reliable value for the number of cycles completed by the oscillator.

[0014] In a further step, the number of cycles of the oscillator passed through is preferably determined by selecting the first recording or the second recording based on a result of the test.

[0015] Furthermore, it can be provided that the first recording is performed on a positive edge and the second recording on a negative edge of a counting clock of the counter of the phase-locked loop. Accordingly, the recordings are aligned with a phase shift of 180° relative to each other. This advantageously provides the greatest possible spacing between the recordings.

[0016] Furthermore, it can be provided within the scope of the invention that the first recording and the second recording are carried out by respective sampling elements, in particular sampling elements of counter components, in the phase-locked loop. A sampling element in an electronic circuit refers in particular to a component that detects or measures signals at specific points in time. For example, a sample-and-hold circuit can be used as a sampling element. This can be used, for example, in analog-to-digital converters to detect an analog signal for a short period of time and hold it constant so that it can be digitized. Furthermore, a multiplexer could select one of several input signals and forward it to a single output. In a time-based scheme, it could function as a sampling element by sequentially sampling different signals.In digital circuits, flip-flops can also serve as sampling elements, capturing and storing the state of a data signal at a specific time (usually synchronized with a clock). A counter component in an electronic circuit is, in particular, a digital sequential logic device that counts a specific number of pulses based on the sampling elements and outputs them, for example, as a binary value. Counter components can be or include special registers that store the count and increment or decrement their value by one with each input pulse.

[0017] According to a further possibility, the first recording and the second recording can be performed within one clock cycle of the phase-locked loop counter. This can advantageously ensure that a possible metastable value of one of the two recordings can be replaced by the value of the other recording.

[0018] According to a further advantage, it can be provided that the determination of the fractional share is carried out by a time-to-digital converter or a phase-to-digital converter. A time-to-digital converter (TDC) is, in particular, an electronic device that converts very short time intervals into digital values. TDCs are designed, for example, to measure a time between two events, typically electrical signals, with high precision. A phase-to-digital converter (PDC) is, in particular, a device or circuit that measures a phase difference between two signals and converts this information into a digital signal. A PDC can be a specialized type of time-to-digital converter (TDC) that is specifically designed to quantify phase information.

[0019] Furthermore, it is conceivable that checking the first recording and the second recording on the basis of the determined fractional share of the phase information comprises the following step: - Comparing the respective fractional share of the phase information with a time point of the first recording and with a time point of the second recording in order to determine metastability in the first recording or in the second recording.

[0020] Metastability can occur at a specific value of the fractional component, particularly at a time when the phase-locked loop counter is incrementing to the next value. Metastability with respect to the counting and sampling mechanism refers specifically to a condition in which the counting or sampling mechanism is at the boundary between two stable states and is unable to settle on one of these states quickly enough. This problematic condition is particularly common in flip-flop-based digital circuits and can be avoided, for example, by maintaining safety margins between the clock edges, which are described by setup and hold times.

[0021] When determining the number of cycles completed by the oscillator, the recording with a lower probability of metastability can then be selected based on the comparison. The lower probability may be present if the respective recording is further away from the time at which the phase-locked loop counter is incremented to the next value.

[0022] Preferably, within the scope of the invention, it can be provided that the selection of the first recording or the second recording is carried out by a multiplexer as part of determining the number of cycles completed by the oscillator. A multiplexer is, in particular, a device in digital electronics that enables multiple input signals to be transmitted via a single output channel. The multiplexer operates, in particular, like a rotating switch in a digital system and, based on control signals, selects one of several input signals to pass through to the output. During operation, the control signal preferably determines which input is connected to the output.

[0023] The invention also relates to a computer program, in particular a computer program product, comprising instructions that, when executed by a computer, cause the computer to carry out the method according to the invention. Thus, the computer program according to the invention provides the same advantages as those described in detail with reference to a method according to the invention.

[0024] The invention also relates to a data processing device configured to carry out the method according to the invention. The device can be, for example, a computer that executes the computer program according to the invention. The computer can have at least one processor for executing the computer program. A non-volatile data memory can also be provided, in which the computer program is stored and from which the computer program can be read by the processor for execution.

[0025] The invention may also provide a computer-readable storage medium that contains the computer program according to the invention and / or includes instructions that, when executed by a computer, cause the computer to carry out the method according to the invention. The storage medium is designed, for example, as a data storage device such as a hard disk and / or a non-volatile memory and / or a memory card. The storage medium can, for example, be integrated into the computer.

[0026] Furthermore, the method according to the invention can also be implemented as a computer-implemented method.

[0027] Further advantages, features, and details of the invention will become apparent from the following description, which describes embodiments of the invention in detail with reference to the drawings. The features mentioned in the claims and in the description may be essential to the invention individually or in any combination. They show: Fig. 1 a schematic visualization of a method, a phase-locked loop with an oscillator, a time-to-digital converter and a phase-to-digital converter, a device, a storage medium and a computer program according to embodiments of the invention, Fig. 2 a schematic representation of a section of a phase-locked loop with a counter and two sampling elements according to embodiments of the invention.

[0028] In Fig. 1, a method 100, a phase-locked loop 1 with an oscillator 2, a time-to-digital converter 5 and a phase-to-digital converter 6, a device 10, a storage medium 15 and a computer program 20 according to embodiments of the invention are schematically illustrated. It should be noted that the phase-locked loop 1, in contrast to Fig. 1 preferably has either a time-to-digital converter 5 or a phase-to-digital converter 6.

[0029] Fig. 1 shows in particular a method 100 for determining a number of cycles completed by an oscillator 2 in a phase-locked loop 1. In a first step 101, a first recording of a counter reading of a counter 3 of the phase-locked loop 1 is initiated. In a second step 102, a second recording of the counter reading of the counter 3 of the phase-locked loop 1 is initiated, wherein the second recording is carried out with a temporal offset from the first recording. In a third step 103, a fractional portion of phase information of the oscillator 2 is determined. In a fourth step 104, the first recording and the second recording are checked based on the determined fractional portion of the phase information. In a fifth step 105, the number of cycles completed by the oscillator 2 is determined by selecting the first recording or the second recording based on a result of the check 104.

[0030] The method according to embodiments of the invention advantageously minimizes a synchronization error when determining the number of cycles 8 completed with very low hardware and energy expenditure.

[0031] Fig. 2 shows a section of a phase-locked loop 1 with a counter 3 and two sampling elements 4 according to an embodiment of the invention, to which reference is made below.

[0032] According to embodiments of the invention, a recording of the counter reading is made with a positively aligned scanning element 4 (in Fig. 2 shown above) and a negatively aligned scanning element 4 (in Fig. 2 shown below). Subsequently, one of the recordings is performed by evaluating the fractional phase measurement, i.e., the fractional portion of the phase information of oscillator 2. In this way, metastability problems can be advantageously prevented.

[0033] Digital PLLs 1 require, in particular, information about the current number of cycles 8 that the oscillator 2 has already completed. This information is obtained, for example, by a counter 3 with an analog counter circuit. This counter 3 preferably runs with the variable oscillator counting clock 9, but must, in particular, be sampled with a reference clock 11. Metastability can become a problem here, which can be circumvented according to embodiments of the invention.

[0034] The reference clock 11 is specifically tuned to a positive and a negative edge of the counting clock 9. These signals can be used to trigger two recordings. Since one of these sampled recordings can be corrupted by metastability, the other is preferably selected by a subsequent multiplexer (MUX) 7 according to step 105 to determine the number of cycles 8 completed. The knowledge required for this selection 105 can originate in the phase-locked loop 1 from the measurement of a fractional portion of phase information from the oscillator 2. The fractional portion can be determined using a time-to-digital converter (TDC) 5 or a phase-to-digital converter (PDC) 6.

[0035] The above explanation of the embodiments describes the present invention exclusively by way of examples. Of course, individual features of the embodiments can be freely combined with one another, provided they are technically feasible, without departing from the scope of the present invention. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] EP 3 291 447 B1

[0006] US 10 007 235 B2

[0007]

Claims

[1] Method (100) for determining a number of cycles completed by an oscillator (2) in a phase-locked loop (1), comprising the following steps: - initiating (101) a first recording of a counter reading of a counter (3) of the phase-locked loop (1), - initiating (102) a second recording of the counter reading of the counter (3) of the phase-locked loop (1), the second recording being carried out with a time offset from the first recording, - determining (103) a fractional portion of phase information of the oscillator (2), - checking (104) the first recording and the second recording on the basis of the determined fractional share of the phase information, - Determining (105) the number of cycles of the oscillator (2) completed by selecting the first recording or the second recording based on a result of the testing (104). [2] Method (100) according to claim 1, characterized by that the first recording is carried out on a positive edge and the second recording on a negative edge of a counting clock of the counter (3) of the phase-locked loop (1). [3] Method (100) according to one of the preceding claims, characterized by that the first recording and the second recording are carried out by respective sampling elements (4) in the phase-locked loop (1). [4] Method (100) according to one of the preceding claims, characterized by that the first recording and the second recording are carried out within one clock cycle of the counter (3) of the phase-locked loop (1). [5] Method (100) according to one of the preceding claims, characterized by that the determination of the fractional share is carried out by a time-to-digital converter (5) or a phase-to-digital converter (6). [6] Method (100) according to one of the preceding claims, characterized by that the checking (104) comprises the following step: - comparing the respective fractional portion of the phase information with a time of the first recording and with a time of the second recording in order to determine a metastability in the first recording or in the second recording, wherein in the determination on the basis of the comparison the recording which has a lower probability of the metastability is selected. [7] Method (100) according to one of the preceding claims, characterized by that the selection of the first recording or the second recording is carried out as part of the determination by a multiplexer (7). [8] Computer program (20) comprising instructions which, when the computer program (20) is executed by a computer (10), cause the computer (10) to carry out the method (100) according to one of the preceding claims. [9] Device (10) for data processing, which is arranged to carry out the method (100) according to one of claims 1 to 7. [10] A computer-readable storage medium (15) comprising instructions which, when executed by a computer (10), cause the computer (10) to carry out the steps of the method (100) according to any one of claims 1 to 7.

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