Power electronics system comprising a power semiconductor module with power conductors and pins

Abstract

A power electronics system comprises: a power semiconductor module comprising: an encapsulation body comprising a first side, an opposite second side, and lateral sides connecting the first and second sides, first and second power lines exposed from a first of the lateral sides, wherein the first power line is configured to provide a first DC+ connection and the second power line is configured to provide a first DC connection, a plurality of power semiconductor dies encapsulated by the encapsulation body and connected to the first and second power lines, first and second pins exposed from the encapsulation body and arranged perpendicular to the first and second power lines, wherein the first pin is configured to provide a second DC+ connection and the second pin is configured,to provide a second DC connection; and a driver board disposed over the first side of the encapsulation body and comprising a driver circuit configured to drive the power semiconductor dies of the power semiconductor module, the driver board further comprising a first capacitor connected to the first and second pins to provide a first commutation loop.

Description

TECHNICAL FIELDThis disclosure relates generally to a power semiconductor module, more particularly to a power semiconductor module that includes power conductors and pins. This disclosure further relates to a power electronics system comprising such a power semiconductor module and to a method for producing such a power semiconductor module.BACKGROUNDSemiconductor modules, in particular power semiconductor modules, may be configured to operate at a high voltage of e.g. 100 V or more, or 500 V or more, or 1.2 kV or more, or 2 kV or more, and / or a high current of e.g. 1 A or more, or 10 A or more, or 100 A or more. Furthermore, semiconductor modules, in particular power semiconductor modules, can be configured for rapid switching. Modules comprising (power) semiconductor dies based on, e.g., SiC or GaN may enable such fast switching speeds. However, in the case of fast switching, parasitic inductances can be problematic, for example, since parasitic inductances in the commutation loop can cause severe voltage overshoot of, for example, the drain-source current of a transistor involved on account of rapid commutation of the currents involved. Such exceeding may exceed the maximum breakdown voltage of the transistor device and may cause damage.DE 10 2019 109 461 A1 teaches an arrangement comprising a power module for a power converter and an intermediate circuit capacitor for the power converter, wherein the intermediate circuit capacitor is connected to the power module by a screw connection. US 2010 / 0 133 667 A1 teaches the use of differently shaped press fit connectors for the connection of the control contacts of a cast power module.SUMMARYVarious aspects relate to a power electronics system comprising: a power semiconductor module comprising: an encapsulation body comprising a first side, an opposite second side and lateral sides connecting the first and second sides, a first and a second power line exposed from a first of the lateral sides, wherein the first power line is configured to provide a first DC+ connection and the second power line is configured to provide a first DC connection, a plurality of power semiconductor dies encapsulated by the encapsulation body and connected to the first and second power lines, a first and a second pin exposed from the encapsulation body and arranged perpendicular to the first and second power lines, wherein the first pin is configured to provide a second DC+ connection and the second pin is configured to provide a second DC+ connection, A method of providing a second DC connection; a DC link capacitor connected to the first and second power lines and forming a first commutation loop; and a driver board disposed over the first side of the encapsulant body and comprising a driver circuit configured to drive the power semiconductor dies of the power semiconductor module, the driver board further comprising a second capacitor connected to the first and second pins to provide a second commutation loop, the second commutation loop having a lower inductance than the first commutation loop.BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings illustrate examples and together with the description serve to explain principles of the disclosure. Other examples and many of the intended advantages of the disclosure will be readily apparent in view of the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. FIGS. 1A and 1B show a top view (FIG. 1A ) and a side view (FIG. 1B ) of a power semiconductor module that includes power conductors and that additionally includes pins that both provide respective DC+ and DC connections. FIGS. 2A and 2B show a perspective view of a power electronic system (FIG. 2A ) and a plan view of a power semiconductor module included in the power electronic system (FIG. 2B ). FIGS. 3A and 3B show a plan view (FIG. 3A ) and a side view (FIG. 3B ) of another power semiconductor module. FIG. 4 is a sectional view of the power semiconductor module of FIGS. 1A and 1B according to a specific example. FIG. 5 is a flowchart of an exemplary method of manufacturing a power semiconductor module.DETAILED DESCRIPTIONIn the following detailed description, well-known structures and elements are shown in schematic form to facilitate the description of one or more aspects of the disclosure. In this regard, directional terminology such as "top", "bottom", "left", "right", "upper", "lower", etc. is used with reference to the orientation of the figure(s) described. Since components of the disclosure may be positioned in a number of different orientations, the directional terminology is used for illustrative purposes only. It should be understood that other examples may be used and structural or logical changes may be made.Moreover, although a particular feature or aspect of an example may be disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for a given or particular application, unless expressly stated otherwise or not technically limited. Furthermore, to the extent that the terms "include," "have," "with," or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise.". The terms "coupled" and "connected" may be used together with derivatives thereof. It will be understood that these terms may be used to indicate that two elements cooperate or interact with each other regardless of whether they are in direct physical or electrical contact or not; intervening elements or layers may be provided between the "bonded", "attached", or "connected" elements. However, it is also possible for the "bonded", "attached" or "connected" elements to be in direct contact with one another. Moreover, the term "exemplary" is intended to be merely an example and not the best or optimum.The semiconductor chip(s) of a power semiconductor module / s may be covered with an electrically insulating encapsulation material to be embedded in an encapsulation. The encapsulation material may for example comprise or consist of any suitable plastic or polymer material and may for example contain inorganic filler materials configured to reduce the thermal resistance of the encapsulation. Various techniques may be used to encapsulate the semiconductor chip(s) with the encapsulation material, for example compression molding, injection molding, transfer molding or laminating.For example, an efficient power semiconductor module, an efficient power electronics system, and an efficient method of manufacturing a power semiconductor module may reduce material consumption, ohmic losses, chemical waste, etc., and thus may allow for energy and / or resource savings. Improved power semiconductor modules, improved power electronics systems and improved methods for manufacturing a power semiconductor module, as indicated in this description, can thus contribute at least indirectly to green technology solutions, i.e. climate-friendly solutions that provide attenuation of the energy and / or resource usage.FIGS. 1A and 1B show a power semiconductor module 100 comprising an encapsulation body 110, a first power line 120, a second power line 130, a plurality of power semiconductor dies 140, a first pin 150 and a second pin 160. FIG. 1A is a plan view and FIG. 1B is a side view of the power semiconductor module 100. The power semiconductor dies 140 are omitted in FIG. 1A and are shown in FIG. 1B with dashed lines, since the encapsulation body 110 obstructs the view of the power semiconductor dies 140.The power semiconductor module 100 may comprise any suitable electrical circuit, for example a converter circuit, an inverter circuit, a half bridge circuit, a full bridge circuit, etc. The power semiconductor module 100 may be configured to operate with a high electrical voltage and / or a high electrical current, for example a voltage of 100 V or more or 500 V or more or 1 kV or more and / or a current of 1 A or more or 10 A or more. The power semiconductor module 100 may be configured for use in automotive applications, for example.The encapsulation body 110 comprises a first side 111, an opposite second side 112 and lateral sides 113 connecting the first and second sides 111, 112. The lateral sides 113 may have a smaller surface area than the first and second sides 111, 112, for example. The first and second sides 111, 112 may have approximately the same surface or exactly the same surface, for example.The power semiconductor module 100 may have any suitable shape and dimensions. For example, the power semiconductor module 100 may have a substantially rectangular or square shape when viewed from above the first side 111. The first side 111 can have an edge length of 1 cm or more, or 5 cm or more, or 10 cm or more, or 15 cm or more, for example.According to one example, the encapsulation body 110 comprises or consists of a molded body. Such a molded body can be produced using, for example, a technique such as compression molding, injection molding, or transfer molding. According to another example, the encapsulation body 110 comprises a plastic frame defining an inner volume, wherein the power semiconductor dies 140 are arranged within the inner volume. A potting material may be deposited on the power semiconductor dies 140 and may at least partially fill the interior volume.The power semiconductor module 100 may be configured for single-side cooling, for example, meaning that a single side of the encapsulation body 110 is configured to be coupled to a heat sink. For example, the second side 112 of the encapsulation body 110 may be configured to be coupled to a heat sink. The first side 111 may be configured to face a driver board, for example. According to another example, the power semiconductor module 100 may be configured for double-side cooling, wherein both the first and second sides 111, 112 are configured to be coupled to heat sinks. In this case, a drive board may be disposed over such a heat sink, for example.The first power line 120 and the second power line 130 are exposed from a first of the lateral sides 113 of the encapsulation body 110. The first and second power lines 120, 130 may be arranged side by side. The first and second power lines 120, 130 may be arranged coplanarly. However, it is also possible for the first and second power lines 120, 130 to be arranged in different planes relative to one another.The first and second power lines 120, 130 may comprise or consist of any suitable metal or metal alloy. The first and second power lines 120, 130 may include or consist of Al or Cu, for example. According to an example, the first and second power lines 120, 130 are coated with a suitable plating, e.g., a Ni plating. According to an example, the first and second power lines 120, 130 are lead frame portions.The first power line 120 is configured to provide a first DC+ connection (i.e., a positive voltage DC connection) to the power semiconductor module 100 (specifically, to the power semiconductor dies 140), and the second power line 130 is configured to provide a first DC connection (i.e., a negative voltage DC connection) to the power semiconductor module 100.According to an example, the power semiconductor module 100 may include a further power line 170, which may be configured, for example, to provide a phase connection for the power semiconductor module 100. The further power line 170 may comprise or consist of the same material as the first and second power lines 120, 130, and may also be a lead frame part. The further power line 170 may be exposed from a second of the lateral sides 113 of the encapsulation body 110, for example. The second lateral side 113 may, for example, be opposite the first lateral side 113 comprising the first and second power lines 120, 130.According to an example, the power semiconductor module 100 may even comprise further power lines. For example, the power semiconductor module 100 may comprise one or more further power lines configured to be part of the first DC+ connection and / or one or more further power lines configured to be part of the first DC connection and / or one or more further power lines configured to be part of the phase connection.The power semiconductor dies 140 are encapsulated by the encapsulation body 110 and electrically connected to the first and second power lines 120, 130. Although the power semiconductor module 100 has been described so far as having at least two power semiconductor dies 140, it is of course also possible for the power semiconductor module 100 to include, for example, two power transistor circuits provided in monolithic integration.The power semiconductor dies 140 may be disposed over one or more carriers (not shown). For example, the power semiconductor dies 140 may be soldered or sintered or bonded to the carrier / s with conductive adhesive. The power lines 120, 130, 170 and possibly the first and second pin 150, 160 and possibly the further pins 180 (see below) may also be arranged over the carrier(s). The power semiconductor dies 140 and the power lines 120, 130, 170 may be electrically connected via the carrier(s), for example.The carrier(s) may be, for example, power electronic substrates, e.g., direct copper bonded (DCB) substrates, direct aluminum bonded (DAB) substrates, active metal bonded (AMB) substrates, insulated metal substrate (IMS) substrates, etc. The carrier(s) may be exposed from the second side 112 of the encapsulant 110, for example. In the case that the power semiconductor module 100 is configured for double-side cooling, another carrier may be exposed from the first side 111.According to an example, the power semiconductor module 100 is configured to switch a load current rapidly in a certain manner. To this end, the power semiconductor module 100 may include, for example, power semiconductor dies 140 including or consisting of SiC or GaN. Due to this fast switching, it may be advantageous to address parasitic inductances in the power semiconductor module 100 as set forth below.The first and second pins 150, 160 are exposed from the encapsulation body 110. In the example shown in FIG. 1, the first and second pins 150, 160 are exposed from the first side 111 of the encapsulation body 110. However, it is also possible for the first and second pins 150, 160 to be exposed, for example, from one or more of the lateral sides 113.The first and second pins 150, 160 are arranged perpendicular to the first and second power lines 120, 130. This may mean that the entire first and second pins 150, 160 or at least an upper end of the first and second pins 150, 160 faces in a direction that is perpendicular to the first and second power lines 120, 130. The first and second pins 150, 160 may be configured to connect to an external device (e.g., a driver board), wherein the external device may be arranged, e.g., over the first side 111 of the encapsulation body 110 (this may be the reason why the first and second pins 150, 160 are arranged perpendicular to the first and second power lines 120, 130).According to an example, the first and second pins 150, 160 are press fit pins configured to provide a press fit connection to an external device. The first and second pins 150, 160 may comprise or consist of any suitable metal or metal alloy, e.g. Al or Cu. The first and second pins 150, 160 may comprise any suitable plating, e.g., a Ni plating.The first pin 150 is configured to provide a second DC+ connection and the second pin 160 is configured to provide a second DC connection of the power semiconductor module 100. This may mean, in particular, that the first pin 150 is electrically connected to the first power line 120 and is at the same electrical potential as the first power line 120 and the second pin 160 is electrically connected to the second power line 130 and is at the same electrical potential as the second power line 130.According to an example, an external device such as a driver board may be arranged over the first side 111 of the encapsulation body 110, wherein the external device comprises a first capacitor (e.g. a fast ceramic capacitor) connected to the first and second pins 150, 160 to provide a first commutation loop. Providing such a commutation loop, wherein the DC+ potential and DC potential of the power lines 120, 130 are connected to the first capacitor, may help to reduce current overshoot, for example. Due to a lower inductance of this commutation loop compared to the connection between the power lines 120, 130 and an external DC link capacitor, the current can commutate more quickly and overshoots between drain-source voltages in the power semiconductor module 100 can be reduced.Since the first and second pins 150, 160 may only be configured to provide this commutation loop, the first and second pins 150, 160 need not necessarily be configured to carry a load current. Thus, for example, the first and second pins 150, 160 may have a smaller cross-section compared to the first and second power lines 120, 130. For example, the cross-section of the first and second pins 150, 160 may be less than half or less than a quarter of the cross-section of the first and second power lines 120, 130.According to an example, the power semiconductor module 100 may include one or more further pins 180 exposed from the encapsulation body 110. The one or more further pins 180 may be configured to transmit control signals for driving the power semiconductor dies 140, for example. Additionally or alternatively, the one or more further pins 180 may be configured to transmit sense signals, e.g., drain voltage sense or source voltage sense signals.FIG. 2A shows a perspective view of a power electronics system 200 including a driver board 210 and a power semiconductor module 220. FIG. 2B shows a plan view of the power semiconductor module 220. The power semiconductor module 220 may be similar or identical to the power semiconductor module 100 except for the differences described below.The power semiconductor module 220 includes the first and second power conductors 120, 130, and the power semiconductor module 220 additionally includes a third power conductor 222. For example, the third power conductor 222 may be configured to be part of the first DC+ connection in parallel with the first power conductor 120 (this example is shown in FIG. 2A ). According to another example, it is reversed, which means that the first and third power conductors 120, 222 provide the first DC connection and the second power conductor 130 provides the first DC+ connection of the power semiconductor module 220.The power semiconductor module 220 further includes the first and second pins 150, 160 and the power semiconductor module 220 additionally includes a third pin 224 and a fourth pin 226. The first pin 150 may be connected in parallel to the first power conductor 120, the second and fourth pins 160, 226 may be connected in parallel to the second power conductor 130, and the third pin 224 may be connected in parallel to the third power conductor 222. The first and third pins 150, 224 may be configured to provide the second DC+ connection, and the second and fourth pins 160, 226 may be configured to provide the second DC connection (this example is shown in FIG. 2A ). According to another example, it is the reverse.The driver board 210 may include, for example, a printed circuit board (PCB). The driver board 210 includes a driver circuit 212 configured to drive the power semiconductor dies of the power semiconductor module 220. In particular, the driver circuit 212 may be connected to gate electrodes of the power semiconductor dies of the power semiconductor module 220. The driver circuit 212 may be connected to the power semiconductor module 220 via one or more further pins 180.The driver board 210 further includes a first capacitor 214 connected to the first and second pins 150, 160 to provide a first commutation loop and a second capacitor 216 connected to the third and fourth pins 224, 226 to provide a second commutation loop. In FIG. 2A, the first and second commutation loops are indicated by dashed lines. The capacitors 214, 216 may be, for example, fast ceramic capacitors. The first, second, and third power lines 120, 130, 222 may be configured to be connected to an external DC link capacitor via, for example, welding, soldering, or screwing. Such a DC link capacitor may be, for example, a foil-wound capacitor and may be comparatively large. Furthermore, such a DC link capacitor can have a comparatively high capacitance. The first and second capacitors 214, 216 may have a smaller capacitance than the DC link capacitor and / or may be faster than the DC link capacitor.According to one example, the first and second capacitors 214, 216 each have a capacitance in the range of about 100 nF to about 1 μF. The lower limit of this range may also be about 200 nF or about 400 nF, and the upper limit may also be about 800 nF or about 600 nF. A DC link capacitor may on the other hand have a capacitance in the range from 100 μF to 1 mF, for example. In other words, the capacitances of the first and second capacitors 214, 216 may be a factor of 100 or more or a factor of 1000 or more less than a capacitance of a dedicated DC link capacitor.FIGS. 3A and 3B show another power semiconductor module 300 that may be similar or identical to the power semiconductor modules 100 and 220 except for the differences described below. FIG. 3A is a plan view of the power semiconductor module 300 and FIG. 3B is a side view taken along the arrow B in FIG. 3A.In the power semiconductor module 300, the first pin 150 and the second pin 160 are exposed from one or more of the lateral sides 113 of the encapsulation body 110. In particular, the first and second pins 150, 160 may be exposed from opposite ones of the lateral sides 113 (see FIG. 3A ). Further, the first and second pins 150, 160 may each include a first portion disposed in a first plane and a second portion disposed in a different second plane, wherein the first and second planes are disposed at a non-zero angle relative to each other. The non-zero angle may be about 90°, for example. The first and second power lines 120, 130 may be arranged in the first plane, for example. In other words, the first and second pins 150, 160 may be bent upwards such that the second portion of the first and second pins is arranged perpendicular to the first and second power lines 120, 130.The power semiconductor module 300 may also include the one or more further pins 180. The one or more further pins 180 may also be exposed from one or more of the lateral sides 113 of the encapsulation body 110 (for example, the one or more further pins 180 may be exposed from the same lateral sides 113 as the first and second pins 120, 130, cf. FIG. 3A ).The power semiconductor module 300 may be configured for double-side cooling, for example. This may mean, in particular, that a first carrier (e.g. a DCB) is exposed from the first side 111 of the encapsulation body 110 and a second carrier (e.g. a DCB) is exposed from the second side 112 of the encapsulation body 110. This may be the reason why the pins 150, 160, 180 are exposed from the lateral sides 113 of the encapsulation body 110.FIG. 4 shows a sectional view of the power semiconductor module 100 according to a specific example.As shown in FIG. 4, the first pin 150 may be in direct contact with the first power line 120. Similarly, the second pin 160 may be in direct contact with the second power line 130. This may mean, for example, that lower ends of the first and second pins 150, 160 are inserted into respective recesses 190 in the first and second power lines 120, 130.According to an example, the first and second power lines 120, 130 are metal clips. The recesses 190 may be formed in the metal clips using any suitable process, e.g., a stamping process or a drilling process. The first and second pins 150, 160 and the recesses 190 may form press fit connections, for example.As shown in FIG. 4, the lower ends of the first and second pins 150, 160 may be tapered to facilitate insertion of the pins 150, 160 into the recesses 190. Upper ends of the pins 150, 160 may also be tapered to facilitate insertion of the pins 150, 160 into through holes of a driver board, such as the driver board 210.According to an example, the first and second power line 120, 130 (and possibly also the further power line 170) and the power semiconductor chip(s) 140 are arranged on a carrier 192. The power lines 120, 130 (and 170) and the power semiconductor chip(s) 140 may be soldered or sintered or bonded to the carrier 192 using conductive adhesive, for example. The carrier 192 may be, for example, a power electronic substrate, e.g. a power electronic substrate of one of the types mentioned further above.FIG. 5 is a flow diagram of a method 500 for manufacturing a power semiconductor module. The method 500 may be used, for example, to manufacture the power semiconductor modules 100, 220 or 300.The method 500 includes, at 501, a process of connecting a plurality of power semiconductor dies to first and second power lines, the first power line configured to provide a first DC+ connection and the second power line configured to provide a first DC connection; at 502, a process of encapsulating the plurality of power semiconductor dies with an encapsulation body, the encapsulation body including a first side, an opposing second side, and lateral sides connecting the first and second sides such that the first and second power lines are exposed from a first of the lateral sides; and at 503, a process of providing first and second pins exposed from the encapsulation body and arranged perpendicular to the first and second power lines, wherein the first pin is configured to provide a second DC+ connection and the second pin is configured to provide a second DC connection.According to an example of the method 500, the first and second pins 150, 160 are provided after the power semiconductor dies 140 are encapsulated. This may include forming (e.g., by molding) the encapsulation body 110 such that openings are provided for the pins. Alternatively, such openings may be formed after the encapsulation body 110 is formed by removing a portion of the encapsulation body 110 by, e.g., drilling, cutting, grinding, etc.EXAMPLESHereinafter, the power semiconductor module, the power electronic system, and the method for manufacturing a power electronic system will be explained using specific examples.Example 1 is a power electronics system comprising: a power semiconductor module comprising: an encapsulating body comprising a first side, an opposing second side, and lateral sides connecting the first and second sides, first and second power lines exposed from a first of the lateral sides, the first power line configured to provide a first DC+ connection, and the second power line configured to provide a first DC connection, a plurality of power semiconductor dies encapsulated by the encapsulating body and connected to the first and second power lines, first and second pins exposed from the encapsulating body and arranged perpendicular to the first and second power lines, the first pin configured to provide a second DC+ connection, and the second pin configured to, to provide a second DC connection; and a driver board arranged over the first side of the encapsulation body and comprising a driver circuit configured to drive the power semiconductor dies of the power semiconductor module, wherein the driver board further comprises a first capacitor connected to the first and second pins to provide a first commutation loop.Example 2 is the power electronics system of example 1, wherein the first and second pins are press fit pins.Example 3 is the power electronics system of example 1 or 2, wherein the first and second power lines are connected to a DC link capacitor via solder joints, welded joints, or joints comprising screws.Example 4 is the power electronics system of any of the preceding examples, wherein the first capacitor has a capacitance in the range of 50 nF to 2000 nF.Example 5 is the power electronics system of any preceding example, wherein the first and second power lines are metal clips, and wherein lower ends of the first and second pins are in direct contact with the metal clips.Example 6 is the power electronics system of example 5, wherein the lower ends of the first and second pins are inserted into recesses in the metal clips.Example 7 is the power electronics system of any of the preceding examples, wherein the first and second pins are exposed from the first side of the encapsulation body.Example 8 is the power electronics system of any of Examples 1 to 6, wherein the first and second pins are exposed from one or more of the lateral sides of the encapsulation body, and wherein the first and second pins are bent upward to be perpendicular to the first and second power lines.Example 9 is the power electronics system according to one of the preceding examples, wherein the encapsulation body is a molded body.Example 10 is the power electronics system of any of Examples 1 to 8, wherein the encapsulation body comprises a plastic frame, wherein the power semiconductor dies are disposed within an interior volume defined by the plastic frame.Example 11 is the power electronics system of any of the preceding examples, wherein a load current flows through the first and second power lines but not through the first and second pins.Example 12 is a power semiconductor module, comprising: an encapsulating body comprising a first side, an opposing second side, and lateral sides connecting the first and second sides; first and second power lines exposed from a first of the lateral sides, the first power line configured to provide a first DC+ connection, and the second power line configured to provide a first DC connection; a plurality of power semiconductor dies encapsulated by the encapsulating body and connected to the first and second power lines; and first and second pins exposed from the encapsulation body and arranged perpendicular to the first and second power lines, wherein the first pin is configured to provide a second DC+ connection and the second pin is configured to provide a second DC connection.Example 13 is the power semiconductor module of example 12, wherein the first and second pins are press fit pins.Example 14 is the power semiconductor module of example 12 or 13, wherein the first and second power lines are configured to be connected to an external device via solder joints, welded joints, or joints comprising screws.Example 15 is the power semiconductor module of any of Examples 12 to 14, wherein the power semiconductor dies are connected to form a half bridge circuit.Example 16 is a method of manufacturing a power semiconductor module, the method comprising: connecting a plurality of power semiconductor dies to first and second power lines, the first power line configured to provide a first DC+ connection and the second power line configured to provide a first DC connection; encapsulating the plurality of power semiconductor dies with an encapsulation body, the encapsulation body comprising a first side, an opposing second side, and lateral sides connecting the first and second sides such that the first and second power lines are exposed from a first of the lateral sides; providing first and second pins exposed from the encapsulation body and arranged perpendicular to the first and second power lines, wherein the first pin is configured to provide a second DC+ connection and the second pin is configured to provide a second DC connection.Example 17 is the method of example 16, wherein the first and second pins are provided after the power semiconductor dies are encapsulated.Example 18 is the method of example 16 or 17, wherein providing the first and second pins comprises inserting lower ends of the first and second pins into recesses in the first and second power lines.Example 19 is an apparatus comprising means for performing the method of any one of Examples 16 to 18.Although the disclosure has been illustrated and described with respect to one or more implementations, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the above-described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a "means") used to describe such components, unless otherwise indicated, are intended to correspond to any component or structure that performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure that performs the function in the example implementations of the disclosure illustrated herein.

Claims

A power electronics system (200) comprising: a power semiconductor module (100, 220, 300) comprising: an encapsulating body (110) comprising a first side (111), an opposite second side (112), and lateral sides (113) connecting the first and second sides (111, 112), first and second power lines (120, 130) exposed from a first of the lateral sides (113), wherein the first power line (120) is configured to provide a first DC+ connection, and the second power line (130) is configured to provide a first DC connection, a plurality of power semiconductor dies (140) encapsulated by the encapsulating body (110) and connected to the first and second power lines (120, 130), a first and a second pin (150, 160), exposing from the encapsulation body (110) and arranged perpendicular to the first and second power lines (120, 130), wherein the first pin (150) is configured to provide a second DC+ connection and the second pin (160) is configured to provide a second DC connection; a DC link capacitor connected to the first and second power lines (120, 130) and forming a first commutation loop; and a driver board (210) arranged over the first side (111) of the encapsulation body (110) and comprising a driver circuit (212) configured to drive the power semiconductor dies (140) of the power semiconductor module (220), wherein the driver board (210) further comprises a second capacitor (214) connected to the first and second pins (150, 160) to provide a second commutation loop, wherein the second commutation loop has a lower inductance than the first commutation loop.The power electronics system (200) of claim 1, wherein the first and second pins (150, 160) are press fit pins.The power electronics system (200) of claim 1 or 2, wherein the first and second power lines (120, 130) are connected to the DC link capacitor via solder joints, welded joints, or joints comprising screws.The power electronics system (200) of any preceding claim, wherein the first capacitor (214) has a capacitance in the range of 50 nF to 2000 nF.The power electronics system (200) of any preceding claim, wherein the first and second power lines (120, 130) are metal clips and wherein lower ends of the first and second pins (150, 160) are in direct contact with the metal clips.The power electronics system (200) of claim 5, wherein the lower ends of the first and second pins (150, 160) are inserted into recesses (190) in the metal clips.The power electronics system (200) of any of the preceding claims, wherein the first and second pins (150, 160) are exposed from the first side (111) of the encapsulation body (110).The power electronics system (200) of any of claims 1 to 6, wherein the first and second pins (150, 160) are exposed from one or more of the lateral sides (113) of the encapsulation body (110), and wherein the first and second pins (150, 160) are bent upwards to be perpendicular to the first and second power lines (120, 130).The power electronics system (200) according to any one of the preceding claims, wherein the encapsulation body (110) is a molded body.The power electronics system (200) of any of claims 1 to 8, wherein the encapsulation body (110) comprises a plastic frame, wherein the power semiconductor dies (140) are arranged within an interior volume defined by the plastic frame.The power electronics system (200) of any preceding claim, wherein a load current flows through the first and second power lines (120, 130) but not through the first and second pins.

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