Field defect transmitter with trench gate structure

Abstract

A field-effect transistor, FET (100), is proposed. The FET (100) comprises a transistor cell (TC) embedded in a semiconductor substrate (102) with a first surface (108). The transistor cell (TC) includes a source region (104) on the first surface (108) of the semiconductor substrate (102). The transistor cell (TC) further comprises a drain region (110) spaced from the source region (104) along a first lateral direction (x1). The transistor cell (TC) also includes a trench-gate structure (112) arranged along the first lateral direction (x1) between the source region (104) and the drain region (110). The trench-gate structure (112) comprises a trench-gate dielectric (1121) and a trench-gate electrode (1122). The transistor cell (TC) further includes a trench-field structure (114) arranged along the first lateral direction (x1) between the trench-gate structure (112) and the drain area (110).A top surface of a first section (11221) of the trench-gate electrode (1122) is arranged below the first surface (108) at a vertical distance (d1) from the first surface (108).

Description

TECHNICAL AREA

[0001] The present disclosure relates to a semiconductor device, in particular a field-effect transistor (FET) comprising a trench-gate structure. BACKGROUND

[0002] The technological development of new generations of semiconductor devices, such as field-effect transistors (FETs), aims to improve the properties of electrical devices and reduce costs by shrinking device geometries. While shrinking device geometries can reduce costs, a variety of trade-offs and challenges must be addressed when increasing device functionality per unit area. For example, a trade-off between area-specific on-resistance, RDS(on), is necessary. onxA and reliability requirements, which are influenced, for example, by avalanche breakthrough behavior or parasitic component behavior, a design optimization.

[0003] Therefore, there is a need for an improved field-effect transistor.

[0004] Document US 2016 / 0093731A1 discloses a semiconductor device with a source region and a drain region arranged on a first primary surface of a substrate. The semiconductor device includes a gate trench with a gate dielectric layer and a gate electrode. The semiconductor device also includes a field plate trench with a field dielectric layer and a field plate. SUMMARY

[0005] An example of the present disclosure relates to a field-effect transistor, FET. The FET comprises a transistor cell embedded in a semiconductor substrate with a first surface. The transistor cell includes a source region on the first surface of the semiconductor substrate. The transistor cell further comprises a drain region spaced apart from the source region along a first lateral direction. The transistor cell further comprises a trench-gate structure arranged along the first lateral direction between the source region and the drain region. The trench-gate structure comprises a trench-gate dielectric and a trench-gate electrode. The transistor cell further comprises a trench field structure arranged along the first lateral direction between the trench-gate structure and the drain region.A top surface of a first section of the trench-gate electrode is positioned below the first surface at a vertical distance from the first surface.

[0006] Another example from the present disclosure relates to a field-effect transistor, FET. The FET comprises a transistor cell embedded in a semiconductor substrate with a first surface. The transistor cell includes a source region on the first surface of the semiconductor substrate. The transistor cell further includes a drain region spaced apart from the source region along a first lateral direction. The transistor cell further includes a trench-gate structure arranged along the first lateral direction between the source region and the drain region. The transistor cell includes a trench-field structure arranged along the first lateral direction between the trench-gate structure and the drain region. The trench-field structure includes a trench-field dielectric and a trench-gate electrode.A top surface of a first section of the trench field electrode is positioned below the first surface at a vertical distance from the first surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the embodiments and are integrated into and form part of this specification. The drawings illustrate examples of semiconductor devices and, together with the description, serve to explain the principles of the examples. Further examples are described in the following detailed description and the claims. Fig. Figure 1 is a schematic top view to illustrate a configuration example of a FET that includes a trench-gate structure and a trench-field structure. Fig. 2A is an exemplary cross-sectional view along line aa' of the in Fig. 1 illustrated FET. Fig. 2B is an exemplary cross-sectional view along line AA' of the in Fig. 1 illustrated FET. Fig. 2C is an exemplary cross-sectional view along line BB' of the in Fig. 1 illustrated FET. Fig. 3A is another exemplary cross-sectional view along line aa' of the in Fig. 1 illustrated FET. Fig. 3B is an exemplary cross-sectional view along line DD' of the in Fig. 1 illustrated FET. Fig. 3C is an exemplary cross-sectional view along line CC' of the in Fig. 1 illustrated FET. Fig. 4 is another exemplary cross-sectional view along line aa' of the in Fig. 1 illustrated FET. DETAILED DESCRIPTION

[0008] The terms "exhibit," "contain," "include," "comprise," and the like are open-ended and indicate the presence of the specified structures, elements, or features, but do not exclude the presence of additional elements or features. The articles "a," "an," and "the" should include both the plural and the singular unless the context clearly indicates otherwise.

[0009] The term "electrically connected" can describe a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or heavily doped semiconductor material. The term "electrically coupled" can imply that one or more intermediate elements, designed for signal and / or power transmission, may be connected between the electrically coupled elements, for example, elements that are controllable to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state. A resistive contact is a non-rectifying electrical junction.

[0010] Ranges specified for physical dimensions can include limit values. For example, a range for a parameter y from a to b is: a ≤ y ≤ b. The same applies to ranges with a limit such as "at most" and "at least".

[0011] The terms "on" and "over" are not to be interpreted as meaning only "directly on" and "directly over". Rather, if an element is positioned "on" or "over" another element (e.g., a layer "on" or "over" another layer, or "on" or "over" a substrate), then another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate if the layer is "on" or "over" the substrate).

[0012] An example of the present disclosure relates to a field-effect transistor, FET. The FET comprises a transistor cell embedded in a semiconductor substrate with a first surface. The transistor cell includes a source region on the first surface of the semiconductor substrate. The transistor cell further comprises a drain region spaced apart from the source region along a first lateral direction. The transistor cell further comprises a trench-gate structure arranged along the first lateral direction between the source region and the drain region. The trench-gate structure comprises a trench-gate dielectric and a trench-gate electrode. The transistor cell further comprises a trench field structure arranged along the first lateral direction between the trench-gate structure and the drain region.A top surface of a first section of the trench-gate electrode can be located below the first surface at a vertical distance from the first surface.

[0013] The source region and the drain region, or part of them, can be of an n-type. In this case, the FET can be, for example, an n-channel FET. In some other examples, the source region and the drain region can be of a p-type. In this case, the FET can be, for example, a p-channel FET.

[0014] For example, the FET can be a lateral FET. In a lateral FET, one load current flow direction is a lateral direction, e.g., the first lateral direction, and the source and drain regions are spaced apart along the first lateral direction. For example, the lateral FET can be a lateral trench FET, such as a lateral trench metal-oxide-semiconductor field-effect transistor or a lateral trench MOSFET. In the trench-gate structure, the trench-gate dielectric can line the sidewalls and bottom of a trench and can electrically isolate a trench-gate electrode from a surrounding portion of the semiconductor substrate. In the lateral trench FET, a channel current can flow, for example, along the first lateral direction on opposite sidewalls and along a bottom of the trench-gate structure.

[0015] For example, the FET can be implemented monolithically using a mixed technology. Such mixed technologies can be used, for example, to form analog circuit blocks on a chip using the bipolar devices included in this technology to provide interfaces to digital systems, to form digital circuit blocks using the complementary metal-oxide-semiconductor (CMOS) devices included in this technology to provide signal processing, and to form low-, medium-, or high-voltage or power blocks using the field-effect transistors included in this technology. Such mixed technologies are known, for example, as bipolar CMOS-DMOS (BCD) technologies or smart power technologies (SPT) and are used in a wide variety of applications in the field of, for example,It is used in lighting, motor control, automotive electronics, power management for mobile devices, audio amplifiers, power supplies, hard drives, and printers. The FET can, for example, be part of a BCD or smart power chip in one of the above application areas.

[0016] The semiconductor substrate can be based on various semiconductor materials, for example silicon (Si), silicon-on-insulator (SOI), silicon-on-sapphire (SOS), silicon-germanium, germanium, gallium arsenide, silicon carbide, gallium nitride, or other compound semiconductor materials. The semiconductor substrate can be based on a semiconductor-based substrate, such as a semiconductor wafer, and may include one or more epitaxial layers deposited on it and / or may be back-thinned.

[0017] To achieve a desired current-carrying capacity, the FET can be implemented with a large number of transistor cells connected in parallel. These parallel transistor cells can, for example, be arranged in the form of a strip or a strip segment. Of course, the transistor cells can also have any other shape, such as circular, elliptical, polygonal (e.g., hexagonal), or octahedral. The transistor cells can be arranged in a transistor cell region of the semiconductor substrate. This transistor cell region can be an active region in which the source region and the drain region of the FET are arranged opposite each other along the first lateral direction. In this active region, a load current can enter or exit the semiconductor substrate of the FET, for example, via contact connectors on the first and / or second surface of the semiconductor substrate.

[0018] The first surface can be, for example, a front surface or a top surface of the semiconductor substrate, and the second surface can be, for example, a rear surface or a back surface of the semiconductor substrate. The semiconductor substrate can, for example, be attached to a conductor frame via the second surface. Bond pads can be arranged over the first and / or second surface of the semiconductor substrate, and bond wires can be bonded to the bond pads.

[0019] The source region and a body contact region can be electrically connected to a source electrode. The source electrode can, for example, be part of a wiring region above the first surface of the semiconductor substrate. The wiring region can include one or more wiring levels, such as two, three, four, or even more. Each wiring level can be formed by a single or a stack of conductive layers, such as metal layer(s). The wiring levels can be, for example, lithographically structured. A dielectric interlayer structure can be arranged between stacked wiring levels. Contact plug(s) or contact leads can be formed in openings in the dielectric interlayer structure to electrically connect parts, such as metal leads or contact regions, of different wiring levels.The source electrode can be formed by one or more elements of the wiring region. Similarly, the FET can also include a drain electrode. The drain electrode can also be formed by one or more elements of the wiring region above the first surface. For example, the source electrode and the drain electrode can be separate parts of a structured first wiring layer, such as a first metal layer. In some examples, the drain electrode can also be formed above the second surface of the semiconductor substrate. In this case, a drain region of the FET can be electrically connected to the drain electrode by a through-contact or trench contact that extends at least partially through the semiconductor substrate.

[0020] The trench-gate dielectric of the trench-gate structure electrically insulates the trench-gate electrode from the surrounding semiconductor substrate. For example, the trench-gate dielectric can be an insulating material, such as an oxide (e.g., SiO₂), a nitride (e.g., Si₃N₄), a high-k dielectric, a low-k dielectric, or any combination thereof. For example, the trench-gate dielectric can be a thermal oxide. The trench-gate electrode can be made of one or more conductive materials, such as metal, metal silicide, a metal compound, or a highly doped semiconductor material, such as highly doped polycrystalline silicon. For example, the trench-gate electrode can be a single layer (e.g., a highly doped polycrystalline layer) or a stack of layers. For example, the source area can adjoin a first side wall of the trench-gate structure.A drift region of the first conductivity type can be located along the first lateral direction between the trench-gate structure and the drain region. The drift region can adjoin a second side wall of the trench-gate structure. The second side wall can be opposite the first side wall along the first lateral direction.

[0021] The trench-field structure is arranged along the first lateral direction between the trench-gate structure and the drain area. The trench-gate structure may be spaced apart from the trench-field structure along the first lateral direction. For example, the width (e.g., the extent along a second lateral direction, which may be perpendicular to the first lateral direction) of the trench-field plate structure may be greater, e.g., by more than 20% and less than 200%, than the width of the trench-gate structure. For example, in a transistor cell area, the spacing of the trench-field structures along the second lateral direction may be equal to the spacing of the trench-gate structures along the second lateral direction. The trench-field plate and the trench-gate structures may or may not be offset from each other along the second lateral direction, e.g., by half the spacing.

[0022] Similar to the trench-gate dielectric, the trench field dielectric electrically insulates, for example, the trench field electrode from a surrounding portion of the semiconductor substrate. The trench field dielectric can, for example, have a greater thickness than the trench-gate dielectric. For example, the trench field dielectric can be an insulating material, such as an oxide (e.g., SiO₂), a nitride (e.g., Si₃N₄), a high-k dielectric, a low-k dielectric, or any combination thereof. For example, the trench field dielectric can be formed as or include a thermal oxide and / or a deposited and annealed oxide. The trench field electrode can be formed from one or more conductive materials, such as metal, metal silicide, a metal compound, or a highly doped semiconductor material, such as highly doped polycrystalline silicon. For example, the trench field electrode can be a single layer, e.g.,It could be a highly doped polycrystalline layer, or a stack of layers. For example, the trench-gate electrode and the trench-field electrode can be made of the same material or a combination of materials. Providing the trench-field structure can further reduce the R-value. on enable xA.

[0023] The top surface of a first section of the trench-gate electrode, positioned below the first surface at a vertical distance from it, can, for example, form a step with a second section of the trench-gate electrode. The vertical distance to the first surface can refer, for example, to a vertical plane on the first surface where there is an interface between a contact, such as a connector or lead, and the source area.

[0024] By positioning the first section of the trench-gate electrode below the first surface, device reliability can be improved by suppressing or avoiding the undesired generation of an inversion channel at the corner of the trench-gate structure. Furthermore, leakage current caused by the inversion channel can be avoided or at least reduced. The inversion channel at the corner can exhibit a lower threshold voltage compared to the device channel at the side wall, and the distortion of the current-voltage characteristic caused by switching on the channel at the corner can thus be suppressed or avoided when the first section of the trench-gate electrode is positioned below the first surface.

[0025] For example, the vertical distance of the first section of the trench-gate electrode from the first surface can have a value in the range of 50 nm to 500 nm. This range of values ​​can, for example, enable advantageous suppression of channel turn-on in the corners of the trench-gate structure.

[0026] For example, the trench-gate dielectric can border the first section of the trench-gate electrode along the first lateral direction. This first lateral direction can be oriented from the source region to the drain region. Thus, the first section of the trench-gate electrode can, for example, be positioned outwards on one side towards the source region. This exemplary arrangement of the first section can, for example, advantageously suppress channel turn-on in the corners of the trench-gate structure on one side of the source region.

[0027] For example, a second section of the trench-gate electrode can extend vertically at least to the first surface of the semiconductor substrate and can be electrically connected to a gate interconnect extending along a second lateral direction. This second lateral direction can be perpendicular to the first lateral direction. The second lateral direction can also be a lateral direction along which a device width is measured. For example, the second section could include a central portion of the trench-gate electrode along the first lateral direction.

[0028] For example, the second section of the trench-gate electrode can have a lateral distance along the first lateral direction from the source region. This lateral distance can have a value in the range of 100 nm to 500 nm. This range of values ​​can, for example, enable advantageous suppression of channel turn-on in the corners of the trench-gate structure.

[0029] For example, the materials of the trench-gate electrode and the gate interconnect can include doped polycrystalline silicon. The doped polycrystalline silicon can, for example, have a high doping concentration, e.g., greater than 10⁻⁵. 19 cm -3 or even larger than 10 21 cm -3 , in order to achieve a reduction in resistance between a gate pad and the trench gate electrode.

[0030] For example, the top surface of a third section of the trench-gate electrode can be positioned below the first surface at a vertical distance from it. The second section of the trench-gate electrode can be positioned along the first lateral direction between the first and third sections of the trench-gate electrode. The vertical distance from the top surface of the first section to the first surface can be equal to the vertical distance from the top surface of the third section to the first surface, for example, if recesses are simultaneously formed in the trench-gate electrode by an etching process.

[0031] For example, the trench field structure can include a trench field dielectric and a trench field electrode. The thickness of the trench field dielectric can be greater than the thickness of the trench-gate dielectric. The top surface of a first section of the trench field electrode can be located below the first surface at a vertical distance from it. This exemplary arrangement of the first section can advantageously reduce the electric field strength at the edge of the mesa region adjacent to the trench field structure. This can improve the reliability of the device by enhancing its electrical breakdown strength.

[0032] For example, the first section of the trench field electrode can be adjacent to the trench field dielectric along the first lateral direction. This first lateral direction can be oriented from the source region to the drain region. Thus, the first section of the trench field electrode can, for example, be positioned outward on one side toward the drain region. This exemplary arrangement of the first section can advantageously reduce the electric field strength at the edge of the mesa region adjacent to the trench field structure. This can improve the reliability of the device by increasing its electrical breakdown strength.

[0033] Details described in relation to the above exemplary FETs, e.g., materials, dimensions, configurations, apply equally to the exemplary FETs described below.

[0034] Another example from the present disclosure relates to another field-effect transistor, FET. The FET comprises a transistor cell embedded in a semiconductor substrate with a first surface. The transistor cell includes a source region on the first surface of the semiconductor substrate. The transistor cell further includes a drain region spaced apart from the source region along a first lateral direction. The transistor cell further includes a trench-gate structure arranged along the first lateral direction between the source region and the drain region. The transistor cell further includes a trench-field structure arranged along the first lateral direction between the trench-gate structure and the drain region. The trench-field structure includes a trench-field dielectric and a trench-field electrode.A top surface of a first section of the trench field electrode can be located below the first surface at a vertical distance from the first surface.

[0035] This exemplary vertical orientation of the top surface of the first section of the trench field electrode can advantageously reduce the electric field strength at the edge of the mesa region adjacent to the trench field structure. This can improve the reliability of the device by enhancing its electrical breakdown strength.

[0036] For example, the vertical distance of the first section of the trench field electrode from the first surface can have a value in the range of 50 nm to 500 nm.

[0037] For example, the first section of the trench field electrode can be adjacent to the trench field dielectric along the first lateral direction. This first lateral direction can be oriented from the source region to the drain region. Thus, the first section of the trench field electrode can, for example, be positioned outward on one side toward the drain region. This exemplary arrangement of the first section can advantageously reduce the electric field strength at the edge of the mesa region adjacent to the trench field structure. This can improve the reliability of the device by increasing its electrical breakdown strength.

[0038] For example, a second section of the trench field electrode can extend vertically at least to the first surface. This second section can be electrically connected to a field electrode connecting wire that extends along a second lateral direction. This second lateral direction can be perpendicular to the first lateral direction. The second lateral direction can also be a lateral direction along which, for example, a component width is measured.

[0039] For example, the second section of the trench field electrode can have a lateral distance along the first lateral direction from the drain region that is greater than 25% of the trench field electrode's extent along the first lateral direction. This range of values ​​can provide a beneficial reduction in electric field strength at the edge of the mesa region adjacent to the trench field structure.

[0040] For example, the top surface of a third section of the trench field electrode can be positioned below the first surface of the semiconductor substrate at a vertical distance from the first surface. The second section of the trench field electrode can be positioned along the first lateral direction between the third and first sections of the trench field electrode. The vertical distance from the top surface of the first section to the first surface can be equal to the vertical distance from the top surface of the third section to the first surface, for example, if recesses are simultaneously formed in the trench field electrode by an etching process.

[0041] For example, the FET can further include an intermediate dielectric located between the first surface of the semiconductor substrate and the field electrode interconnect. The intermediate dielectric can have a greater thickness than the trench field dielectric.

[0042] For example, the trench-gate structure can include a trench-gate dielectric and a trench-gate electrode. The top surface of a first section of the trench-gate electrode can be positioned below the first surface at a vertical distance from the first surface of the semiconductor substrate. By positioning the first section of the trench-gate electrode below the first surface, device reliability can be improved by suppressing or preventing the unwanted generation of an inversion channel at the corner of the trench-gate structure. Furthermore, leakage current caused by the inversion channel can be avoided or at least reduced.The inversion channel at the corner can have a lower threshold voltage compared to the component channel at the side wall, and the distortion of the current voltage property by switching on the channel at the corner can thus be suppressed or avoided if the first section of the trench-gate electrode is located below the first surface.

[0043] For example, the trench-gate dielectric can abut the first section of the trench-gate electrode along the first lateral direction. Thus, the first section of the trench-gate electrode can, for instance, be arranged outwards on one side towards the source region. This exemplary arrangement of the first section can, for example, advantageously suppress channel turn-on in the corners of the trench-gate structure on one side of the source region.

[0044] For example, the FET can further include a body region that borders a bottom surface and each of the opposite side walls of the trench-gate structure. The body region can have a conductivity type different from that of the source region. The body region can be located further away from the drain region than the trench-gate structure along the first lateral direction. For example, the body region can border at least a portion of the bottom surface of the trench-gate structure. Alternatively, the body region can border at least a portion of the bottom surface of the trench-gate structure and at least a portion of the opposite side walls of the trench-gate structure. This can form a channel region on the opposite side walls and the bottom surface of the trench-gate structure.Along the first lateral direction, the body area may border more than 60%, more than 70%, more than 80%, or more than 90% of a lateral extent of the trench-gate structure on the underside along the first lateral direction.

[0045] For example, the source region can be adjacent to a body contact region along the second lateral direction. The second lateral direction can be perpendicular to the first lateral direction. In a transistor cell array containing a multitude of transistor cells, the source and body contact regions can, for example, be arranged alternately along the second lateral direction.

[0046] Details relating to structure, function, or technical benefits of features described above in relation to a semiconductor device, such as a FET, apply equally to the FETs further described below with reference to the figures.

[0047] The description and drawings merely illustrate the principles of revelation. Furthermore, all examples listed here are expressly intended only for illustrative purposes, to assist the reader in understanding the principles of revelation and the concepts contributed by the inventor(s) to the advancement of technology.

[0048] Further examples of field-effect transistors (FETs) are explained below in conjunction with the accompanying drawings. Functional and structural details described in relation to the preceding examples apply equally to the exemplary embodiments illustrated in the figures and described further below.

[0049] Fig. Figure 1 shows a schematic and exemplary top view of a part of transistor cells TC of a FET 100. Fig. Figure 2A shows a schematic and exemplary cross-sectional view along the line aa' of Fig. 1. Fig. Figure 2B shows a schematic and exemplary cross-sectional view along line AA' of Fig. 1. Fig. Figure 2C schematically and exemplarily shows a cross-sectional view along line BB' of Fig. 1.

[0050] With reference to the Fig. 1, Fig. 2A, Fig. 2B and Fig. 2C is each transistor cell TC formed in a semiconductor substrate 102.

[0051] On a first surface 108 of the semiconductor substrate 102, there is an n + A doped source region 104 is formed. A drain region 110 is spaced from the source region 104 along a first lateral direction x1. The drain region 110 can be electrically connected to a second surface of the semiconductor substrate 102 opposite the first surface 108 or to the first surface 108 (not shown). Fig. In Figure 2A and other figures described below, the drain region 110 extends into a section of the semiconductor substrate 102. The drain region 110 is electrically connected via the second surface of the semiconductor substrate 102 (not shown).

[0052] The first surface 108 is a surface of the semiconductor substrate 102, at which, for example, an interface exists between a doped region in the semiconductor substrate 102, e.g., the source region 104, and a contact to the doped region, e.g., a connector or a Fig. Line 124, shown in 2A, is located.

[0053] A trench-gate structure 112 is arranged between the source region 104 and the drain region 110 along the first lateral direction x1. A trench-gate dielectric 1121 of the trench-gate structure 112 electrically isolates a trench-gate electrode 1122 of the trench-gate structure 112 from a surrounding part of the semiconductor substrate 102.

[0054] A p-doped body region 118 borders opposite side walls (see e.g. Fig. 1) and a subpage (see e.g. Fig. 2A) of the trench-gate structure 112. This allows a channel area to be formed on the opposite side walls and on the underside of the trench-gate structure 112. The body area 118 has a distance I1 from the drain area 110 along the first lateral direction x1, which is greater than a distance I2 of the trench-gate structure 112 from the drain area 110.

[0055] Each of the transistor cells TC further includes a trench-field structure 114. The trench-field structure 114 is arranged along the first lateral direction x1 between the trench-gate structure 112 and the drain region 110. The thickness t2 of a trench-field dielectric 1141 is greater than the thickness t1 of a trench-gate dielectric 1121.

[0056] With reference to Fig. 2A includes the trench-gate electrode 1122 with a first section 11221. The first section 11221 is a section located in the direction of the source region 104. Thus, the first section 11221 is a section of the trench-gate electrode 1122 that faces the source region 104.

[0057] The trench-gate electrode 1122 further includes a second section 11222, which extends vertically at least to the first surface 108 of the semiconductor substrate 102.

[0058] With reference to the Fig. 2A and Fig. 2C is the second section 11222 of the trench-gate structure 1122, electrically connected to a gate connection line 116. The gate connection line 116 extends along a second lateral direction x2, which is perpendicular to the first lateral direction x1. The second section 11222 of the trench-gate electrode 1122 has a lateral distance I3 along the first lateral direction x1 from the source region 104.

[0059] With reference to Fig. 2A includes the trench-gate electrode 1122 further comprising a third section 11223. The second section 11222 of the trench-gate electrode 1122 is arranged along the first lateral direction x1 between the first section 11221 of the trench-gate electrode 1122 and the third section 11223 of the trench-gate electrode 1122.

[0060] A top surface of the first section 11221 of the trench-gate electrode 1122 is located below the first surface 108 at a vertical distance d11 from the first surface 108. A top surface of the third section 11223 of the trench-gate electrode 1122 is located below the first surface 108 at a vertical distance d12 from the first surface 108. For example, d11 can be equal to d12, e.g., if recesses are formed in the trench-gate electrode at the same time. The third section 11223 of the trench-gate electrode 1122 can also be omitted. In this case, the trench-gate electrode 1122 can be formed, for example, by the first and second sections 11221, 11222.

[0061] An electrical contact to the body region 118 can be formed, for example, in a body contact region by interrupting the source region 104 along the second lateral direction x2 (not shown). The electrical contact from a source electrode 122 to the source region 104 (and the body region 118) is provided via the contact plug or contact line 124, which extends through an intermediate dielectric 126.

[0062] A trench field electrode 1142 of the trench field structure 114 is electrically connected to a field electrode connecting line 120.

[0063] Other examples of cross-sectional views are in the Fig. 3A to Fig. 3C illustrates. Fig. Figure 3A schematically and exemplarily shows another cross-sectional view along line aa' of Fig. 1. Fig. Figure 3B shows a schematic and exemplary cross-sectional view along the line DD' of Fig. 1. Fig. Figure 3C shows a schematic and exemplary cross-sectional view along line CC' of Fig. 1.

[0064] With reference to Fig. 3A includes the trench field electrode 1142 with a first section 11421. The first section 11421 is a section located in the direction of the drain region 110. Thus, the first section 11421 is a section of the trench field electrode 1142 that faces the drain region 110.

[0065] The trench field electrode 1142 further includes a second section 11422, which extends vertically at least to the first surface 108 of the semiconductor substrate 102.

[0066] With reference to the Fig. 3A and Fig. 3C is the second section 11422 of the trench field structure 1142 electrically connected to a field electrode connecting line 120. The field electrode connecting line 120 extends along the second lateral direction x2, which is perpendicular to the first lateral direction x1. The second section 11422 of the trench field electrode 1142 has a lateral distance I4 along the first lateral direction x1 from the drain region 110.

[0067] With reference to Fig. 3A further includes the trench field electrode 1142 a third section 11423. The second section 11422 of the trench field electrode 1142 is arranged along the first lateral direction x1 between the first section 11421 of the trench field electrode 1142 and the third section 11423 of the trench field electrode 1422.

[0068] With reference to the Fig. 3A and Fig. 3B is a top surface of the first section 11421 of the trench field electrode 1142 arranged below the first surface 108 at a vertical distance d21 from the first surface 108. A top surface of the third section 11423 of the trench field electrode 1142 is arranged below the first surface 108 at a vertical distance d22 from the first surface 108. For example, the distance d21 can be equal to the distance d22, e.g., if recesses are formed in the trench field electrode at the same time. The third section 11423 of the trench field electrode 1142 can also be omitted. In this case, the trench field electrode 1142 can be formed, for example, by the first and second sections 11421, 11422. With reference to Fig. 3C is an intermediate dielectric 121 arranged between the first surface 108 of the semiconductor substrate 102 and the field electrode connecting line 120. The intermediate dielectric 121 has a greater thickness t3 than the trench field dielectric 1141.

[0069] Another example of a cross-sectional view along line aa' of Fig. 1 is in Fig. 4 illustrates.

[0070] Similar to the example of Fig. 3A includes the example of Fig. 4 one or more recessed sections in the trench field electrode 1142, i.e. the first and third sections 11421, 11423. However, one recessed section is omitted in the trench gate electrode 1122.

Claims

[1] Field-effect transistor, FET (100), comprising a transistor cell (TC) in a semiconductor substrate (102) with a first surface (108), wherein the transistor cell (TC) includes: a source region (104) on the first surface (108) of the semiconductor substrate (102); a drain region (110) that is spaced apart from the source region (104) along a first lateral direction (x1); a trench-gate structure (112) arranged along the first lateral direction (x1) between the source region (104) and the drain region (110), wherein the trench-gate structure (112) includes a trench-gate dielectric (1121) and a trench-gate electrode (1122); a trench field structure (114) arranged along the first lateral direction (x1) between the trench gate structure (112) and the drain area (110); and wherein a top surface of a first section (11221, 11223) of the trench-gate electrode (1122) is arranged below the first surface (108) at a vertical distance (d11, d12) from the first surface (108). [2] FET (100) according to the preceding claim, wherein the vertical distance (d11, d12) of the first section (11221, 11223) of the trench-gate electrode (1122) from the first surface (108) has a value in the range of 50 nm to 500 nm. [3] FET (100) according to one of the preceding claims, wherein the trench-gate dielectric (1121) borders the first section (11221) of the trench-gate electrode (1122) along the first lateral direction (x1). [4] FET (100) according to one of the preceding claims, wherein a second section (11222) of the trench-gate electrode (1122) extends vertically at least to the first surface (108) of the semiconductor substrate (102) and is electrically connected to a gate interconnect (116) extending along a second lateral direction (x2), wherein the second lateral direction (x2) is perpendicular to the first lateral direction (x1). [5] FET (100) according to the preceding claim, wherein the second section (11222) of the trench-gate electrode (1122) has a lateral distance (I3) along the first lateral direction (x1) from the source region, which has a value in the range of 100 nm to 500 nm. [6] FET (100) according to one of the two preceding claims, wherein the materials of the trench-gate electrode (1122) and the gate interconnect (116) comprise doped polycrystalline silicon. [7] FET (100) according to one of the two preceding claims, wherein a top surface of a third section (11223) of the trench-gate electrode (1122) is arranged below the first surface (108) at a vertical distance (d12) from the first surface (108), wherein the second section (11222) of the trench-gate electrode (1122) is arranged along the first lateral direction (x1) between the first section (11221) of the trench-gate electrode (1122) and the third section (11223) of the trench-gate electrode (1122). [8] FET (100) according to any of the preceding claims, wherein the trench field structure (114) comprises a trench field dielectric (1141) and a trench field electrode (1142), wherein a thickness (t2) of the trench field dielectric (1141) is greater than a thickness (t1) of the trench gate dielectric (1121), and wherein a top surface of a first section (11421, 11423) of the trench field electrode (1142) is arranged below the first surface (108) at a vertical distance (d21, d22) from the first surface (108). [9] FET (100) according to the preceding claim, wherein the first section (11421) of the trench field electrode (1142) borders the trench field dielectric (1141) along the first lateral direction (x1). [10] Field-effect transistor, FET (100), comprising a transistor cell (TC) in a semiconductor substrate (102) with a first surface (108), wherein the transistor cell (TC) includes: a source region (104) on the first surface (108) of the semiconductor substrate (102); a drain region (110) that is spaced apart from the source region (104) along a first lateral direction (x1); a trench-gate structure (112) arranged along the first lateral direction (x1) between the source area (104) and the drain area (110); a trench field structure (114) arranged along the first lateral direction (x1) between the trench-gate structure (112) and the drain region (110), wherein the trench field structure (114) includes a trench field dielectric (1141) and a trench field electrode (1142); and wherein a top surface of a first section (11421, 11423) of the trench field electrode (1142) is arranged below the first surface (108) at a vertical distance (d21, d22) from the first surface (108). [11] FET (100) according to the preceding claim, wherein the vertical distance (d21, d22) of the first section (11421, 11423) of the trench field electrode (1142) from the first surface (108) has a value in the range of 50 nm to 500 nm. [12] FET (100) according to one of the two preceding claims, wherein the first section (11421) of the trench field electrode (1142) borders the trench field dielectric (1141) along the first lateral direction (x1). [13] FET (100) according to one of the three preceding claims, wherein a second section (11422) of the trench field electrode (1122) extends vertically at least to the first surface (108) and is electrically connected to a field electrode connecting line (120) extending along a second lateral direction (x2), wherein the second lateral direction (x2) is perpendicular to the first lateral direction (x1). [14] FET (100) according to the preceding claim, wherein the second section (11422) of the trench field electrode (1142) has a lateral distance (I4) along the first lateral direction (x1) from the drain region (110) which has a value greater than 25% of the extent of the trench field electrode (1142) along the first lateral direction (x1). [15] FET (100) according to one of the two preceding claims, wherein a top surface of a third section (11423) of the trench field electrode (1142) is arranged below the first surface (108) of the semiconductor substrate (102) at a vertical distance (d22) from the first surface (108), wherein the second section (11422) of the trench field electrode (11422) is arranged along the first lateral direction (x1) between the third section (11421) of the trench field electrode (1122) and the first section (11421) of the trench field electrode (1142). [16] FET (100) according to one of the three preceding claims, further comprising an intermediate dielectric (121) arranged between the first surface (108) of the semiconductor substrate (102) and the field electrode connecting line (120), wherein the intermediate dielectric (121) has a greater thickness (t3) than the trench field dielectric (1141). [17] FET (100) according to one of the seven preceding claims, wherein the trench-gate structure (112) comprises a trench-gate dielectric (1121) and a trench-gate electrode (1122); and a top surface of a first section (11221, 11223) of the trench-gate electrode (1122) is arranged below the first surface (108) at a vertical distance (d11, d21) from the first surface (108) of the semiconductor substrate (102). [18] FET (100) according to the preceding claim, wherein the trench-gate dielectric (1121) borders the first section (11221) of the trench-gate electrode (1122) along the first lateral direction (x1). [19] FET (100) according to any of the preceding claims, further comprising a body region (118) adjoining a bottom surface and each of opposite side walls of the trench-gate structure (112), wherein the body region has a conductivity type different from the source region (104), and wherein the body region (118) has a greater distance (I1) from the drain region (110) than the trench-gate structure (112) along the first lateral direction (x1).

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