GaN gate driver for EMI optimization during power-on and power-off

Abstract

An integrated circuit is provided to drive the gate of a GaN power switching transistor in a switching power converter. During the first part of the on-time period for the GaN power switching transistor, the integrated circuit charges the gate through a relatively high pull-up resistor. During the second part of the on-time period, the integrated circuit charges the gate through a relatively low pull-up resistor. During the first part of the off-time period for the GaN power switching transistor, the integrated circuit discharges the gate through a relatively low pull-down resistor and then discharges the gate through a relatively high pull-down resistor in response to the gate voltage falling below a threshold voltage.

Description

TECHNICAL AREA

[0001] This application relates to switching power converters and in particular a gate driver for a GaN power switching transistor with EMI optimization during both turn-on and turn-off. BACKGROUND

[0002] The use of gallium nitride (GaN) transistors has revolutionized power electronic systems. Compared to a conventional metal-oxide-semiconductor field-effect transistor (MOSFET), a comparable GaN transistor offers improved efficiency, higher power density, and faster switching capabilities. However, the faster switching speed of GaN devices comes at the cost of increased electromagnetic interference (EMI) noise. The rapid voltage transition resulting from the increased switching speed can generate disruptive EMI noise. For example, the power switching transistor in a flyback converter might include an n-type GaN transistor with a drain connected to a primary winding and a source coupled to ground. Before the power switching transistor is turned on, the drain is charged to (or above) the input voltage to the primary winding.The input voltage is rectified by the AC mains supply and can therefore exceed 100 V, depending on the AC mains load. When the power switching transistor is fully switched on, its drain is grounded. The drain of the power switching transistor is thus subjected to a relatively high rate of voltage change (dV / dt) during switch-on. A similar voltage change occurs during switch-off. These rapid changes in the drain voltage of the power switching transistor during switch-on and switch-off can lead to an undesirable level of electromagnetic interference (EMI).

[0003] To reduce EMI from the alternating stress on the power switch, it is conventional to turn on the power switching transistor using a relatively complex drive circuit that includes a high-voltage Miller capacitor, a bipolar transistor, a diode, and external resistors. These drive circuit components increase costs and take up circuit board space. SUMMARY

[0004] According to one aspect of the disclosure, an integrated circuit for a switching power converter is provided, comprising: a gate driver circuit configured to charge a gate of a GaN power switching transistor through a variable pull-up resistor comprising a first pull-up resistor and a second pull-up resistor, and to discharge the gate of the GaN power switching transistor through a variable pull-down resistor comprising a first pull-down resistor and a second pull-down resistor, wherein the first pull-up resistor is greater than the second pull-up resistor, and wherein the second pull-down resistor is greater than the first pull-down resistor;and a gate driver control circuit configured to instruct the gate driver circuit to charge the gate through the first pull-up resistor during an initial first section of a turn-on time period for the GaN power switching transistor and to charge the gate through the second pull-up resistor during a second section of the turn-on time period, wherein the gate driver control circuit is further configured to instruct the gate driver circuit to discharge the gate through the first pull-down resistor during an initial first section of a turn-off time period for the GaN power switching transistor and to discharge the gate through a second pull-down resistor during a second section of the turn-off time period.

[0005] According to another aspect of the disclosure, a method for driving a gate of a GaN power switching transistor in a switching power converter is provided, which includes the following: charging the gate through a first pull-up resistor during an initial section of a turn-on time period for the GaN power switching transistor while the gate voltage of the GaN power switching transistor is less than a first threshold voltage; charging the gate through a second pull-up resistor, which is less than the first pull-up resistor, during a second section of the turn-on time period while the gate voltage is greater than the first threshold voltage; discharging the gate through a first pull-down resistor during an initial section of a turn-off time period for the GaN power switching transistor while the gate voltage is greater than a first threshold voltage;and discharging the gate through a second pull-down resistor during a second section of the turn-off time period in response to the gate voltage falling below the first threshold voltage, where the second pull-down resistor is larger than the first pull-down resistor.

[0006] According to yet another aspect of the disclosure, a switching power converter is provided which includes: an inductor; a GaN power switching transistor connected to the inductor; and an integrated circuit configured to: charge a gate of the GaN power switching transistor through a first pull-up resistor during an initial first section of a turn-on time period for the GaN power switching transistor, charge the gate through a second pull-up resistor during a second section of the turn-on time period, discharge the gate through a first pull-down resistor during an initial first section of a turn-off time period for the GaN power switching transistor, and discharge the gate through a second pull-down resistor during a second section of the turn-off time period.

[0007] These and other aspects of the invention will become clearer upon review of the following detailed description. Other aspects, features, and embodiments will become apparent to the person skilled in the art upon review of the following description of specific exemplary embodiments in conjunction with the accompanying figures. Although features may be discussed below in relation to certain embodiments and figures, all embodiments may incorporate one or more of the advantageous features discussed herein. In other words, although one or more embodiments may be discussed in such a way as to have certain advantageous features, one or more such features may also be used according to the various embodiments discussed herein.Similarly, although exemplary embodiments may be discussed below as device, system or process implementations, it is understood that such exemplary embodiments may be implemented in various devices, systems and processes. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates a flyback converter with an integrated circuit for driving a gate of a GaN power switching transistor according to one aspect of the disclosure. Fig. Figure 2 is a more detailed view of the integrated circuit. Fig. 1 according to one aspect of the revelation. Fig. Figure 3 illustrates some operating waveforms for the integrated circuit of the Fig. 2 according to one aspect of the revelation.

[0008] Embodiments of the present disclosure and their advantages are best understood with reference to the following detailed description. It is understood that the same reference numerals are used to identify identical elements illustrated in one or more of the figures. DETAILED DESCRIPTION

[0009] To avoid the complications of using a Miller capacitor approach, adaptive gate drivers have been developed to drive the gate voltage of silicon-based switching power converters. In such adaptive gate drivers, the output impedance of the gate driver is modified depending on the gate voltage to reduce electromagnetic interference (EMI) noise during the turn-on times of the power switching transistors. As the gate voltage passes through various threshold voltages, the output impedance is varied accordingly. Some or all of the threshold voltages are based on the Miller plateau level of the gate voltage. As is known in MOSFET techniques, a Miller plateau period occurs after the gate-to-source voltage for the power switching transistor reaches the transistor threshold voltage.The drain voltage then begins to decrease due to channel conduction, which tends to pull the gate voltage lower due to a parasitic gate-to-drain capacitance of the power switching transistor M1. This parasitic gate-to-drain capacitance is highly nonlinear, so it is relatively small when the drain voltage begins to decrease and increases in magnitude as the drain voltage approaches ground. The net result is that the gate voltage remains relatively constant during the Miller plateau period, a state that ends once the gate-to-drain capacitance is discharged.

[0010] This dependence on the Miller plateau voltage complicates the porting of a conventional adaptive gate driver for a silicon-based power switching transistor to drive the gate voltage of a GaN power switching transistor. Compared to silicon-based power switching transistors, gallium nitride (GaN) power switching transistors offer improved efficiency, increased power density, and faster switching capabilities. As a result, GaN power switching transistors are a popular choice for AC-DC switching power converters, such as flyback converters. However, the Miller plateau voltage is relatively indistinct for GaN devices. A conventional adaptive gate driver will therefore face challenges in accurately setting its threshold voltages due to the indeterminacy of the Miller plateau voltage for GaN devices.An improved gate driver is provided herein for the alternating load of GaN power switching transistors that does not depend on the detection of the Miller plateau voltage.

[0011] The following discussion is directed toward a gate driver for flyback converter implementations using GaN power switching transistors; however, it is understood that the improved gate driver disclosed herein may advantageously be used to drive any suitable GaN power switching transistor, such as in a buck or boost converter. An exemplary flyback converter 100 is described in Fig. Figure 1 shows an improved gate driver in an integrated circuit 105. The flyback converter 100 includes a transformer T having a primary winding W1 and a secondary winding W2. During operation, the adaptive gate driver 105 charges the gate of an n-type GaN power switching transistor M1, which is connected to the primary winding W1, to turn on the power switching transistor M1 for a turn-on period. The primary winding W1 is also connected to an input voltage rail carrying a rectified input voltage (Vin). When the power switching transistor M1 is turned on, a primary winding current begins to flow through the primary winding W1 and the power switching transistor M1 to ground. Once a desired peak winding current is reached, a primary-side control (not shown) can then control the gate driver 105 to turn off the power switching transistor M1.As used herein, “connected” refers to a direct electrical connection, such as by a conductive wire, whereas “coupled” refers to an electrical connection where the connection may be made through an intervening element, such as a resistor or a diode.

[0012] A secondary-side control device U2 controls a synchronous rectifier (SR) switching transistor coupled between a flyback output terminal and the secondary winding W2. This SR control occurs in response to monitoring a drain-to-source (VDS) voltage across the SR switching transistor. Based on the drain-to-source voltage VDS, the secondary-side control device 110 detects whether the power switching transistor M1 has been turned off, allowing the SR switching transistor to be turned on, thus enabling the secondary winding current to flow and charge an output voltage Vout, which is supported by an output capacitor C1.

[0013] An example of a Gate Driver 200 is in Fig. 2 shown in more detail. For clarity and brevity, the corresponding flyback converter is represented by only one node 201 for the gate voltage Vgs. A modulation control circuit 220 provides a modulation control signal to a gate driver control circuit 205. For example, the modulation control circuit 220 can be a pulse-width modulation (PWM) control circuit that generates a PWM control signal to control the desired turn-on period for the power switching transistor. The modulation control circuit 210 can be part of a primary-side control device or part of a secondary-side control device. If the modulation control circuit 210 is located on the secondary side of the transformer, the PWM control signal would be transmitted via a ground-isolating channel, such as an optoisolator.Regardless of where the modulation control circuit 210 is located, it generates the PWM control signal in response to feedback on the various operating signals, such as the output voltage Vout or the input voltage Vin.

[0014] The adaptive gate driver 200 includes a gate driver circuit 215, which implements a variable gate driver resistor, and a gate voltage monitoring or sensing circuit 202, which monitors the gate voltage (which is equivalent to the gate-to-source voltage Vgs of the power switching transistor, since its source is grounded). The gate voltage sensing circuit 202 includes a comparator 225, a comparator 230, and a comparator 235 for comparing the gate voltage of the power switching transistor with their respective threshold voltages. In particular, the comparator 230 uses a relatively low threshold voltage Vth_lo to set a comparator output signal flag_Vth_lo when the gate voltage has risen to equal Vth_lo. While the switch is turned off, the comparator output signal flag_Vth_low is reset to indicate that the gate voltage has fallen below Vth_lo.Similarly, comparator 225 uses a relatively larger reference voltage Vth_hi to set a comparator output signal flag_Vth_hi when the gate voltage rises to equal to the high threshold voltage Vth_hi during the turn-on period. During the turn-off period, the comparator output signal flag_Vth_hi is reset to indicate that the gate voltage has fallen below Vth_hi. Thus, there are three periods during the turn-on period of the power switching transistor and during the turn-off period of the power switch. A first period T1 extends from the beginning of the turn-on delay until the gate voltage rises to equal to Vth_lo. A second period T2 extends from the end of period T1 until the gate voltage rises to equal to Vth_hi (where Vth_hi is greater than Vth_lo).A final turn-on period T3 extends from the time when the gate voltage has risen above Vth_hi until the end of the turn-on period.

[0015] The off-period following the on-period is analogous in that it includes a period T4, which extends from the end of the on-period until the gate voltage falls below Vth_hi. At the end of period T4, period T5 then extends from the end of period T4 until a timed delay has ended. Finally, period T6 extends from the end of period T5 until the gate voltage has discharged to ground.

[0016] The gate driver circuit 215 drives the gate voltage with a pull-up gate driver resistor during the switch's on period, the value of which varies depending on which of the periods T1, T2, and T3 is active. Similarly, the gate driver circuit discharges the gate voltage with a pull-down gate driver resistor, the value of which varies depending on which of the periods T4, T5, and T6 is active. During periods T1 and T2 of the switch's on period, the gate driver circuit 215 charges the gate through a high pull-up resistor. However, during period T3, the gate driver circuit 215 charges the gate through a relatively low pull-up resistor, which is smaller than the relatively high pull-up resistor used during period T1. During period T4, the gate driver circuit 215 discharges the gate voltage through a relatively low pull-down resistor to reduce the turn-off delay.Then, during period T5, the pull-down resistor switches to a relatively high value. Finally, the gate driver circuit 215 discharges the gate voltage again through a relatively low pull-down resistor during period T6. However, it should be noted that increasing the gate driver resistance during a critical line-side operating mode, where a relatively large amount of power must be delivered to the load, can be undesirable. Therefore, the pull-up gate driver resistance during periods T1 and T2, and the pull-down gate driver resistance during period T5, can be equal to or even lower than the values ​​used in the discontinuous line-side operating mode.

[0017] To implement the various pull-up resistors, the gate driver circuit 215 includes a plurality of n PMOS pull-up transistors, ranging from a first PMOS pull-up transistor P1 to an nth PMOS pull-up transistor Pn, where n is a positive integer. For each pull-up transistor, its source is coupled to a power supply rail, such as a voltage terminal 240, via a corresponding resistor, and its drain is connected to the gate of the power switching transistor M1.For example, in transistor P1, its source is coupled to voltage terminal 240 via a resistor R1, and its drain is connected to the gate of power switching transistor M1. Similarly, in transistor P2, its source is coupled to voltage terminal 240 via a resistor R2, and its drain is connected to the gate of power switching transistor M1, and so on. Thus, in the nth transistor Pn, its source is coupled to voltage terminal 240 via a resistor Rn, and its drain is connected to the gate of power switching transistor M1. In some embodiments, the resistors may be conceptual, as they would be provided by the on-resistance of the respective transistor. Alternatively, the resistors may be external to the transistors. Additionally, in alternative implementations, the resistors may instead couple between the drain of the corresponding transistor and the gate of power switching transistor M1.

[0018] To generate a low pull-up resistance, the driver control circuit 305 can turn on any (or most) of the pull-up transistors P1 to Pn. The gate driver pull-up resistance increases as fewer and fewer of the transistors P1 to Pn are turned on. To control the gate driver pull-up resistance depending on whether period T1, T2, or T3 is active, the gate driver control circuit 205 can include a logic circuit 245. The logic circuit 245 can include a state machine, a microcontroller, or a microprocessor. During the alternating load of the power switching transistor M1, the logic circuit 245 responds to the PWM control signal and then turns on the power switching transistor M1 for the desired turn-on period. For a large pulse width, the turn-on period is relatively long, while for smaller pulse widths it is shorter.The start of the turn-on period can be coordinated by a clock signal from a clock generator 250. The logic circuit 245 controls which of the pull-up transistors P1 to Pn is turned on by a corresponding gate driver signal. For example, the logic circuit 245 grounds a gate driver signal g1_up to turn on pull-up transistor P1, grounds a gate driver signal g2_up to turn on pull-up transistor P2, and so on, so that the logic circuit 245 grounds a gate driver signal gn_up to turn on pull-up transistor Pn. If any of the gate driver signals g1_up to gn_up is charged to a power supply voltage, the corresponding pull-up transistor is turned off. In alternative embodiments, current sources can be used to control the gate driver resistance level during the turn-on period for the power switching transistor M1.

[0019] The pull-down resistor is implemented similarly to, for example, a plurality of NMOS pull-down transistors, each having a source coupled to ground and a drain coupled to the gate of the power switching transistor M1. In the gate driver circuit 215, there are two pull-down transistors, extending from a first pull-down transistor N1 to a second pull-down transistor N2; however, it is understood that more than two pull-down transistors can be used in alternative implementations. In the gate driver 200, the on-resistance of the pull-down transistors N1 and N2 controls the gate driver pull-down resistor; however, it is understood that the pull-down transistors can be arranged in series with a corresponding resistor, analogous to the pull-up transistors shown.To generate a low gate driver pull-down resistance, the driver control circuit 205 can turn on either of the pull-down transistors N1 and N2. The gate driver pull-down resistance increases when only one of transistors N1 or N2 is turned on. To control whether pull-down transistor M1 is turned on, logic circuit 245 applies a gate driver signal g1_dn to the power supply voltage. Conversely, logic circuit 245 grounds the gate driver signal g1_dn to turn off pull-down transistor M1. Similarly, logic circuit 245 applies a gate driver signal g2_dn to the power supply voltage to turn on pull-down transistor M2. Conversely, logic circuit 245 grounds the gate driver signal g2_dn to turn off pull-down transistor M2.

[0020] During period T4, logic circuit 245 switches on both pull-down transistors M1 and M2 to generate the desired low pull-down impedance. During period T5, logic circuit 245 switches on only one of the pull-down transistors M1 and M2 to increase the pull-down impedance. Finally, during period T6, logic circuit 245 again switches on both pull-down transistors to generate the desired low pull-down impedance, thus ending the off-period of power switching transistor M1.

[0021] Regarding the timing of periods T1 to T6, the threshold voltages used by the gate voltage monitor 240 are fixed values. This lack of adjustment of the threshold voltages with respect to the Miller plateau gate voltage of the power switching transistor M1 is actually advantageous due to the ambiguous nature of the Miller plateau voltage for GaN devices. The low threshold voltage Vth_lo is set to ensure that the threshold voltage of the power switching transistor M1 has been reached as soon as the comparator 230 sets the Flag_Vth_lo signal to indicate to the logic circuit 245 that the gate voltage has risen above the low threshold voltage Vth_lo. The duration of period T1, from the start of the turn-on period until the activation of Flag_Vth_lo, thus represents the main turn-on delay for the power switching transistor M1.In both periods T1 and T2, the gate driver circuit 215 implements a relatively high pull-up gate impedance, referred to herein as Rg1. By adjusting Rg1, the logic unit 245 can regulate the duration of period T1 to determine whether the main turn-on delay meets design requirements. If period T1 is too short, the corresponding rate of change for the drain voltage of the power switching transistor M1 may generate excessive EMI noise. Conversely, if period T1 is too long, the switching speed of the power switching transistor M1 may be too slow to adequately regulate the output voltage of the corresponding switching power converter, contributing to higher switching losses.

[0022] Period T1 (and the remaining periods T2 to T6) can be determined by considering the in Fig. This can be better understood from the exemplary timing diagram shown in Figure 3. The PWM control signal is set to signal the logic circuit 245 to control the gate driver circuit 215, causing it to begin charging the gate voltage through the pull-up impedance Rg1 to start period T1, during which the gate voltage (Vgate) rises rapidly. Period T1 continues until the gate voltage rises to the low threshold voltage Vth_lo, whereupon the comparator 230 sets the Flag_Vth_lo signal to signal the start of period T2. Since the threshold voltage is then met for the power switching transistor, the Miller plateau period for the power switching transistor M1 begins during period T2. However, the Miller plateau period for GaN devices is so indistinct that the gate voltage continues to rise at a reduced rate during period T2 compared to the voltage increases during period T1.Period T2 ends when the gate voltage rises above the high threshold voltage Vth_hi, whereupon comparator 225 sets the Flag_Vth_hi signal to begin period T3.

[0023] In response to the setting of the Flag_Vth_hi signal, logic circuit 245 controls gate driver circuit 215 to implement a lower gate driver pull-down resistor, referred to herein as Rg2 (where Rg1 is greater than Rg2), during period T3. Period T3 begins upon setting of the Flag_Vth_hi signal and lasts until the end of the turn-on period for the power switching transistor M1. In some implementations, the gate resistor Rg2 is maintained until the end of period T3. However, gate leakage in enhancement-mode GaN devices such as the power switching transistor M1 is a significant concern. To detect whether the power switching transistor M1 exhibits excessive gate leakage currents, logic circuit 245 begins timing a leakage delay period in response to the setting of the Flag_Vth_hi signal.The leakage delay period is of such magnitude that the gate voltage is set to the power supply voltage before the leakage delay period ends (with the power switching transistor M1 fully switched on).

[0024] The drain-to-source voltage Vds across the power switching transistor exhibits a steep drop during period T1 and the beginning of period T2, before beginning to decrease more slowly until it is grounded and the power switching transistor M1 is fully turned on. At the end of the leakage delay period, logic circuit 245 begins timing a leakage detection period and controls gate driver circuit 215 to increase the gate pull-up impedance from Rg2 to Rg3, where Rg3 is greater than Rg2. If there is excessive gate leakage, the increased gate pull-up impedance, in combination with the leakage current, causes the gate voltage to fall below a gate leakage threshold voltage Vth_leak during the leakage detection period. Referring again to Fig.Comparator 235 sets a Flag_Vth_leak signal in response to the gate voltage exceeding the gate leak threshold voltage Vth_leak. Before the end of the leak delay period (while the gate pull-up impedance is still equal to Rg2), the gate voltage rises above the gate leak threshold voltage to cause the Flag_Vth_leak signal to be set. However, at the end of the leak delay period, the gate pull-up impedance is increased to Rg3 during the leak detection period, which, combined with excessive gate leakage, causes the gate voltage to fall below the gate leak threshold voltage Vth_leak, thus resetting the Flag_Vth_leak signal. As used here, a binary signal is considered set when the signal is logically true, regardless of whether the true state is expressed in an active high or active low convention.Conversely, a binary signal is considered reset if the signal is logically false, regardless of whether the false state is expressed in an active high or an active low convention.

[0025] The logic circuit 245 detects the reset of the flag_Vth_leak signal during the leak detection period as a leakage loss fault 220. If the leakage loss fault 220 is detected over successive cycles of the power switching transistor M1, subsequent cycles can be blocked by the logic circuit 245 to protect the power switching transistor M1 from damage caused by excessive leakage currents. For example, the gate leakage threshold voltage Vth_leak can be set such that if the leakage loss is within the milliampere range, the leakage loss fault 220 is considered detected. At the end of the leakage detection period, the logic circuit 245 controls the gate driver circuit 215 to reduce the gate pull-up impedance to a value Rg4 that is less than Rg3. In some implementations, Rg4 and Rg2 are equal. Alternatively, Rg4 can be smaller than Rg2.

[0026] In response to the reset of the PWM control signal to end the on-period and begin the off-period for the power switching transistor M1, the logic circuit 245 begins the off-period for the power switching transistor, starting with period T4. During period T4, the gate driver circuit 215 discharges the gate voltage through a relatively low gate driver pull-down resistor, designated Rgdn1. Due to this relatively low pull-down resistor, the gate voltage drops rapidly and thus falls below the high threshold voltage Vth_hi, causing the comparator 225 to reset the Flag_Vth_hi signal. The logic circuit 245 responds to this reset by instructing the gate driver circuit 215 to discharge the gate voltage through a gate driver pull-down resistor, designated Rgdn2, which is larger than Rgdn1, in order to begin period T5.Additionally, logic circuit 245 initiates the timing of a pull-down delay in response to the reset of the Flag_Vth_hi signal. Upon completion of the pull-down delay, in order to end period T5 and begin period T6, logic circuit 245 again instructs the gate driver circuit 215 to discharge the gate voltage through the Rgdnl pull-down resistor, rapidly discharging the gate voltage until it is grounded to complete the turn-off period.

[0027] The person skilled in the art will now recognize that many modifications, substitutions, and variations can be made to the materials, devices, configurations, and methods of use of the devices of the present disclosure without altering their scope. In view of this, the scope of the present disclosure should not be limited to that of the specific embodiments illustrated and described herein, since these are merely examples, but should instead fully correspond to that of the claims appended herein and their functional equivalents.

Claims

[1] Integrated circuit for a switching power converter, comprising: a gate driver circuit configured to charge the gate of a GaN power switching transistor through a variable pull-up resistor comprising a first pull-up resistor and a second pull-up resistor, and to discharge the gate of the GaN power switching transistor through a variable pull-down resistor comprising a first pull-down resistor and a second pull-down resistor, wherein the first pull-up resistor is greater than the second pull-up resistor, and wherein the second pull-down resistor is greater than the first pull-down resistor; and a gate driver control circuit configured to instruct the gate driver circuit to charge the gate through the first pull-up resistor during an initial first section of a turn-on time period for the GaN power switching transistor and to charge the gate through the second pull-up resistor during a second section of the turn-on time period, wherein the gate driver control circuit is further configured to instruct the gate driver circuit to discharge the gate through the first pull-down resistor during an initial first section of a turn-off time period for the GaN power switching transistor and to discharge the gate through a second pull-down resistor during a second section of the turn-off time period. [2] Integrated circuit according to claim 1, further comprising: a gate voltage monitor configured to monitor a gate voltage of the GaN power switching transistor, wherein the gate driver control circuit is further configured to control a main turn-on delay for the GaN power switching transistor in response to a comparison of the gate voltage with a first threshold voltage by the gate voltage monitor. [3] Integrated circuit according to claim 2, wherein the gate voltage monitoring comprises: a first comparator configured to compare the gate voltage with the first threshold voltage, and wherein the gate driver control circuit is further configured to start timing the main turn-on delay in response to activation of a pulse width modulation signal and to stop timing the main turn-on delay in response to activation of an output signal from the first comparator. [4] Integrated circuit according to claim 3, wherein the gate voltage monitoring further comprises: a second comparator configured to compare the gate voltage with a second threshold voltage that is greater than the first threshold voltage, wherein the gate driver control circuit is further configured to instruct the gate driver circuit to load the gate through the second pull-up resistor in response to activation of an output signal from the second comparator. [5] Integrated circuit according to claim 4, wherein the gate voltage monitoring further comprises: a third comparator configured to compare the gate voltage with a leakage threshold voltage greater than the second threshold voltage, wherein the gate driver control circuit is further configured to start a timing of a leakage delay period in response to the activation of the output signal from the second comparator and to instruct the gate driver circuit to load the gate through a third pull-up resistor in response to the expiration of the leakage delay period and to detect a leakage loss fault in response to the deactivation of an output signal from the third comparator, while the gate driver circuit loads the gate through the third pull-up resistor. [6] Integrated circuit according to claim 5, wherein the gate driver control circuit is further configured to start a timing control of a leak detection period upon completion of the leak delay period and to instruct the gate driver circuit to load the gate through the second pull-up resistor after completion of the leak detection period. [7] Integrated circuit according to claim 4, wherein the gate driver control circuit is further configured to instruct the gate driver circuit to discharge the gate voltage through a second pull-down resistor in response to a deactivation of the output signal from the second comparator. [8] Integrated circuit according to claim 7, wherein the gate driver control circuit is further configured to initiate a timing control of a pull-down delay period in response to the deactivation of the output signal from the second comparator and to instruct the gate driver circuit to discharge the gate through the first pull-down resistor in response to the completion of the pull-down delay period. [9] Integrated circuit according to claim 1, wherein the gate driver circuit comprises a first plurality of transistors coupled between the gate of the GaN power switching transistor and a power supply node, and wherein the gate driver control circuit comprises a logic circuit configured to instruct a first number of transistors in the first plurality of transistors to turn on during the initial first section of the turn-on time period, and to instruct a second number of transistors in the first plurality of transistors to turn on during the second section of the turn-on time period, wherein the first number of transistors in the first plurality of transistors is smaller than the second number of transistors in the first plurality of transistors. [10] Integrated circuit according to claim 9, wherein the gate driver circuit further comprises a second plurality of transistors coupled between the gate of the GaN power switching transistor and ground, and wherein the logic circuit is further configured to instruct a first number of transistors in the second plurality of transistors to turn on during the initial first section of the off-time period, and to instruct a second number of transistors in the second plurality of transistors to turn on during the second section of the off-time period, wherein the first number of transistors in the second plurality of transistors is greater than the second number of transistors in the second plurality of transistors. [11] Integrated circuit according to claim 10, wherein the first plurality of transistors comprises a plurality of PMOS transistors, and wherein the second plurality of transistors comprises a plurality of NMOS transistors. [12] Integrated circuit according to claim 10, wherein each transistor in the first plurality of transistors is coupled to the power supply node by a corresponding resistor. [13] Method for driving a gate of a GaN power switching transistor in a switching power converter, comprising: Charging the gate through a first pull-up resistor during an initial section of a turn-on time period for the GaN power switching transistor, while a gate voltage of the GaN power switching transistor is less than a first threshold voltage; Charging the gate through a second pull-up resistor, which is smaller than the first pull-up resistor, during a second section of the turn-on time period, while the gate voltage is greater than the first threshold voltage; Discharging the gate through a first pull-down resistor during an initial portion of an off-time period for the GaN power switching transistor while the gate voltage is greater than a first threshold voltage; and Discharging the gate through a second pull-down resistor during a second section of the turn-off time period in response to the gate voltage falling below the first threshold voltage, where the second pull-down resistor is larger than the first pull-down resistor. [14] The method of claim 13, further comprising: Initiating a timing pull-down delay period in response to the gate voltage falling below the first threshold voltage during the turn-off period; and Switching from discharging the gate through the second pull-down resistor to discharging the gate through the first pull-down resistor in response to the expiration of the pull-down delay period. [15] The method of claim 13, further comprising: Initiation of the timing of a main turn-on delay period in response to the start of the turn-on time period; and Stopping the timing of the main turn-on delay period in response to the gate voltage rising above a second threshold voltage that is lower than the first threshold voltage. [16] The method of claim 14, further comprising: Initiation of the timing of a leakage delay period in response to the gate voltage rising above the first threshold voltage during the turn-on period; Switching from loading the gate through the second pull-up resistor to loading the gate through a third pull-up resistor to begin a leak detection period in response to the expiration of the leak delay period; and Detecting a leak fault in response to the gate voltage falling below a third threshold voltage during the leak detection period. [17] Method according to claim 16, further comprising stopping an alternating stress on the GaN power switching transistor in response to repeated detection of the leakage fault. [18] Switching power converters, comprising: an inductor; a GaN power switching transistor connected to the inductor; and An integrated circuit configured to: charge a gate of the GaN power switching transistor through a first pull-up resistor during an initial first section of a turn-on time period for the GaN power switching transistor, charge the gate through a second pull-up resistor during a second section of the turn-on time period, discharge the gate through a first pull-down resistor during an initial first section of a turn-off time period for the GaN power switching transistor, and discharge the gate through a second pull-down resistor during a second section of the turn-off time period. [19] Switching power converter according to claim 18, wherein the first pull-up resistor is larger than the second pull-up resistor, and wherein the second pull-down resistor is larger than the first pull-down resistor. [20] Switching power converter according to claim 18, wherein the inductor is a primary winding of a transformer.

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