Switching regulator and method for controlling a switching regulator

Abstract

The present document describes a switching regulator (100) configured to generate an output voltage (VOUT) based on an input voltage (VDD) using at least one power switch (101) and one inductor. The switching regulator (100) comprises a first control circuit (120, 130) configured to generate a first control signal (131) for switching off the power switch (101) depending on a level of the inductor current (104) through the inductor. Furthermore, the switching regulator (100) comprises a second control circuit (200) configured to generate a second control signal (212) for switching on the power switch (101) depending on a level of the output voltage (VOUT).

Description

Technical FieldThe present document relates to a switching regulator. In particular, the present document relates to a method for controlling a switching regulator (such as a DC-DC converter and / or a buck, boost or buck / boost converter).BackgroundOne scheme for controlling a switching regulator is a current mode controller that uses a clock signal to turn on one of the power switches of the switching regulator. The current mode control scheme may have a subharmonic problem when the duty cycle reaches a certain limit (e.g., a duty cycle ("duty cycle") that is greater than 50% when the peak control current mode is used for a buck converter). Edge compensation can be used to address this stability problem, but it reduces the control loop bandwidth and increases the response time of the controller (subject to load transient). Further, current mode control may have a clock latency problem (subject to load transient) because switching of one of the power switches is directly controlled by the clock signal.The present document is directed to the technical problem of providing a fast and stable control scheme for a switching regulator.SummaryAccording to one aspect, a switching regulator is described that is configured to generate an output voltage based on an input voltage using at least one power switch and an inductor. The switching regulator comprises a first control circuit configured to generate a first control signal for (repeatedly) turning off the power switch, wherein the first control signal is generated depending on the level of the inductor current through the inductor. Furthermore, the switching regulator comprises a second control circuit configured to generate a second control signal for (repeatedly) turning on the power switch, wherein the second control signal is generated depending on the level of the output voltage.According to another aspect, a method for controlling a switching regulator is described, wherein the switching regulator is configured to generate an output voltage based on an input voltage using at least one power switch and an inductor. The method includes generating a first control signal to turn off the power switch depending on the level of the inductor current through the inductor. The method further comprises generating a second control signal for switching on the power switch depending on the level of the output voltage.It should be noted that the methods and systems, including their preferred embodiments, as set forth herein may be used alone or in combination with the other methods and systems disclosed herein. In addition, the features set out in connection with a system can also be applied to a corresponding method. Further, all aspects of the methods and systems set forth in the present document may be combined in any combination. In particular, the features of the claims can be combined with one another in any desired manner.In the present document, the term "couple" or "coupled" refers to elements that are in electrical communication with each other, whether directly connected, e.g., via wires or in some other manner.Brief Description of the FiguresThe invention is explained by way of example below with reference to the attached drawings, in which FIG. 1 ashows an example switching regulator and / or voltage regulator; FIG. 1 b shows an example control circuit for controlling a switching regulator; FIG. 1 cshows exemplary measurement signals during the operation of a switching regulator; FIG. 2 ashows an exemplary control circuit for generating a control signal for controlling a power switch of a switching regulator; FIGS. 2 bto 2 d show exemplary measurement signals during the operation of a switching regulator; and FIG. 3 shows a flow chart of an exemplary method for controlling a switching regulator.Detailed DescriptionAs stated above, the present document is directed to controlling a (voltage) switching regulator in a stable manner such that the switching regulator has a relatively low response time subject to a load transient. In this context, FIG. 1 ashows an exemplary switching regulator 100, in particular a buck converter, comprising a high-side power switch 101 and a low-side power switch 102 arranged in series between the supply or input voltage VDDand ground. The switching node LX between the power switches 101, 102 is coupled to the output via an inductor. The output voltage VOUTis fed back as a feedback voltage 113 to the control unit 110 of the switching regulator 100. The control unit 110 is configured to control the power switches 101, 102 depending on a reference voltage VREF 112 (for the output voltage VOUT), depending on the feedback voltage 113 and depending on a clock signal 111 (for adjusting the switching frequency of the switching regulator 100).FIG. 1 b shows further details with respect to the control unit 110. In particular, FIG. 1 b illustrates how the reference voltage 112 is compared with the feedback voltage VFB 113 using an amplifier unit Gm 120 to provide a control signal 121 for controlling a sense FET (field effect transistor). The voltage provided by the sense FET may be compared to a voltage 103 indicative of the inductor current IL 104 through the inductor using a comparator unit 130 to provide a control signal peak_comp_out 131, which may be used for controlling the power switches 101, 102. The control signal peak_comp_out 131 may be referred to herein as the first control signal.As illustrated in FIG. 1 c, the control signal peak_comp_out 131 may be generated such that each time the inductor current 104 has reached a predetermined peak current 150, a control pulse 151 is generated, wherein the peak current 150 is adjusted by the Gm unit 120 in connection with the sense FET. The control signal peak_comp_out 131 may be used to trigger the turn-off of the high-side power switch 101 of the regulator 100. On the other hand, the clock signal 111, in particular the clock pulses 161 of the clock signal 111, may be used to trigger the turn-on of the high-side power switch 101. Thus, the clock signal 111 may be used to adjust the total length of a cycle period and the control signal peak_comp_out 131 may be used to adjust the duration of the duty cycle within the cycle period.FIG. 1 cshows a PWM (pulse width modulation) signal 160 for controlling the power switches 101, 102. It can be seen that a switch-on period 163 during which the high-side power switch 101 is switched on (and the low-side power switch 102 is switched off) starts with a pulse 161 of the clock signal 111 and ends with a pulse 151 of the (first) control signal peak_comp_out 131. Further, the subsequent turn-off period 162 during which the high-side power switch 101 is turned off (and the low-side power switch 102 is turned on) starts with the pulse 151 of the (first) control signal peak_comp_out 131 and ends with the subsequent pulse 161 of the clock signal 111.FIG. 1 cillustrates the load current 105 of a load at the output of the regulator 100. The load current 105 has an abrupt increase during a turn-off period 162. Due to the fact that the turn-off period 162 is terminated only by the subsequent pulse 161 of the clock signal 111 (see pointer 170), the regulator 100 responds with a relatively high latency to the increase of the load current 105.In the present document, a control scheme for controlling a switching regulator 100 is described, which comprises a circuit for generating a second control signal for adjusting the end of the turn-off period 162 and the beginning of the subsequent turn-on period 163, such that the second control signal may deviate from the clock signal 111 subject to a load transient, in particular subject to a load increase.FIG. 2 ashows an example (second) control circuit 200 for generating the second control signal toff_comp_out 212. The circuit 200 includes a capacitor 202 that is charged using one or more current sources Ibias2 203, Ibias1 205. Further, the capacitor 202 may be discharged using a reset switch 201 disposed in parallel with the capacitor 202. The reset switch 201 may be controlled in response to the clock signal 111. In particular, the reset switch 201 may be closed at each pulse 161 of the clock signal 111, thereby causing the capacitor 202 to be fully discharged.After a pulse 161 of the clock signal 111, the reset switch 201 may be opened and may be kept open (until the next pulse 161 of the clock signal 111) so that the capacitor 202 is charged (continuously) using the second current source Ibias 2 203. As a result, the capacitor voltage 207 increases with a base gradient 221, as illustrated in FIG. 2 b. The (second) control circuit 200 further comprises a first current source Ibias 1 205 coupled to the capacitor 202 via a control switch 204. The control switch 204 may be closed using the control signal 206, causing the capacitor 202 to be charged with the currents from the second current source 203 and from the first current source 205, such that the capacitor voltage 207 increases with an increased gradient 222 that is higher than the base gradient 221. The control signal 206 for controlling the control switch 204 may be generated depending on the first control signal peak_comp_out 131. In particular, a pulse 131 of the first control signal peak_comp_out 131 may trigger the control switch 204 to close, thereby increasing the (temporal) gradient 222 for increasing the capacitor voltage 207.Thus, the capacitor 202 is charged with the sum of the currents provided by the second current source 203 and by the first current source 205 during the (total) turn-off period 162 of the power switch 101 of the regulator 100. On the other hand, the capacitor 202 is charged only with the current provided by the second current source 203 during the on-period 163 of the power switch 101.The capacitor voltage 207 may be compared with a comparison voltage 211 using a comparator 210, wherein the comparison voltage 211 may depend on the deviation of the output voltage VOUTof the regulator 100 from the reference voltage Vref 112. Typically, the comparison voltage 211 falls when the output voltage VOUTof the regulator 100 falls. The second control signal toff_comp_out 212 may be provided at the output of the comparator 210. The second control signal toff_comp_out 212 may include a pulse 261 each time the capacitor voltage 207 reaches the comparison voltage 211. A pulse 261 of the second control signal toff_comp_out 212 may trigger the end of the turn-off period 162 and the beginning of the subsequent turn-on period 163. Furthermore, a pulse 261 of the second control signal toff_comp_out 212 resets and / or pulls down the capacitor voltage 207 to 0 V.As shown in FIG. 2 c, the pulses 261 of the second control signal toff_comp_out 212 may deviate from the pulses 161 of the control signal 111. In particular, a load increase may result in a voltage drop of the output voltage VOUTof the regulator 100, which results in a corresponding drop of the comparison voltage 211 (as illustrated in FIG. 2 d). As a result, the time at which the capacitor voltage 207 reaches the comparison voltage 211 is shifted forward, thereby shifting the pulse 261 of the second control signal toff_comp_out 212 and thus the beginning of the subsequent turn-on period 163 forward.Thus, the frequency of a switching regulator 100 may be controlled by using a control circuit 200 in the PWM mode (CCM (continuous conduction mode) and / or heavy load state). As a result, a fast transient response (line transient, load transient, etc.) can be achieved. Further, the control circuit 200 may be used in polyphase converters.As set forth in connection with FIGS. 1 aand 1 b, the VDD may be the input power rail and VOUT may be the output voltage at an output capacitor COUT of a regulator 100. The controller 100 may achieve a buck, boost, and / or buck / boost mode. A sense FET, e.g., a PMOS sense device, may be driven by the output 121 of the Gm unit 120. The Gm unit 120 detects the feedback signal VFB 113 (which is proportional to VOUT) and the reference voltage Vref 112. A voltage comparator 130 compares the drain voltage of the sense FET and the voltage 103 provided by the LX node.The control circuit 200 uses the clock_input 111 to control a bias current Ibias 2 203 to periodically charge the capacitor 202. Clock_input 111 has the desired switching frequency of regulator 100. The bias current Ibias 1 205 charges the capacitor 202 in response to a control signal PWM_b 206. The PWM_b signal 206 may be generated in a digital controller. A comparator 210 compares a DC voltage Vref 211 and the voltage 207 Vcap_charge across the capacitor 202 and generates the output signal toff_comp_out 212, i.e., the second control signal.It can be shown that a time error of the PWM signal 160 (which may be caused by noise etc.) in the feedback loop may be attenuated and that the switching frequency of the regulator 100 converges towards the frequency of the clock_input signal 111 after a few clock cycles.FIG. 3 shows a flow chart of an example method 400 for controlling a switching regulator 100, wherein the switching regulator 100 is configured to generate an output voltage VOUTbased on an input voltage VDDusing at least one power switch 101 and an inductor. The method 300 comprises generating 301 a first control signal 131 for turning off the power switch 101 depending on the level of the inductor current 104 through the inductor. The first control signal 131 may be generated using peak current control or valley current control of the inductor current 104.Furthermore, the method 300 comprises generating 302 a second control signal 212 for switching on the power switch 101 depending on the level of the output voltage VOUT, in particular depending on the deviation of the output voltage VOUTfrom the reference voltage Vref 112 for the output voltage VOUT. As set forth in the present document, a capacitor voltage 207 may be generated, in particular depending on the clock signal 111 (for adjusting the switching frequency of the switching regulator 100) and / or depending on the duration of the turn-off period 162 (during which the power switch 101 is turned off). The capacitor voltage 207 may be compared with a comparison voltage 211, which depends on the value of the output voltage VOUT, to generate the second control signal 212.Depending on an increase in load current 105 (and a corresponding decrease in the value of output voltage VOUT), second control signal 212 may deviate from clock signal 111, thereby allowing voltage regulator 100 to respond to the increase in load current 105 in a stable and fast manner.Thus, a switching regulator 100 configured to generate an output voltage VOUTbased on an input voltage VDDusing at least one power switch 101 and an inductor is described. The switching regulator 100 may include, for example, a buck converter, a boost converter, and / or a buck / boost converter.The switching regulator 100 comprises a first control circuit 120, 130 configured to generate a first control signal 131 for turning off the power switch 101. The first control signal 131 may be generated depending on the level of the inductor current 104 through the inductor. The first control circuit 120, 130 may be configured to generate the first control signal 131 for turning off the power switch 101 depending on a comparison of the level of the inductor current 104 with a target peak value or a target valley value for the inductor current 104. In particular, the first control signal 131 may be generated using peak current or valley current control of the inductor current 104. The first control signal 131 may comprise a sequence of pulses 151, wherein each pulse 151 of the first control signal 131 may be used to turn off the power switch 101. Thus, each turn-off period 162 of the power switch 101 may be started by a pulse 151 of the first control signal 131 and / or each turn-on period 163 of the power switch 101 may be ended by a pulse 151 of the first control signal 131.The switching regulator 100 further comprises a second control circuit 200 configured to generate a second control signal 212 for switching on the power switch 101. The second control signal 212 may be generated depending on the level of the output voltage VOUT, in particular depending on the deviation of the level of the output voltage VOUTfrom the reference voltage 112 of the switching regulator 100. The second control signal 212 may include a sequence of pulses 261, wherein each pulse 261 of the second control signal 212 may turn on the power switch 101. Thus, each turn-on period 163 of the power switch 101 may be started by a pulse 261 of the second control signal 212 and / or each turn-off period 162 of the power switch 101 may be ended by a pulse 261 of the second control signal 212.The second control circuit 200 may be configured to generate the second control signal 212 in dependence on the clock signal 111 for adjusting the switching frequency of the switching regulator 100. The second control signal 212 may be generated such that during steady state operation (with a constant load current 105) of the switching regulator 100, the second control signal 212 is aligned with the clock signal 111. During steady state operation, the pulses 261 of the second control signal 212 may correspond to the pulses 161 of the clock signal 111. In particular, during steady state operation, the pulses 261 of the second control signal 212 and the pulses 161 of the clock signal 111 may correspond to each other in a one-to-one correspondence, such that each pulse 161 of the clock signal 111 has a corresponding pulse 261 within the second control signal 212. The individual pulses 261 within the second control signal 212 may occur at the same times as their corresponding pulses 161 of the clock signal 111. As a result, particularly stable operation of the switching regulator can be achieved.The second control circuit 200 may include a capacitor 202 which is charged during a (in particular during each) turn-off period 162 of the power switch 101 to provide a capacitor voltage 207. The capacitor voltage 207 may increase (during a turn-off period 162 of the power switch 101) with a certain gradient 221, 222.Further, the second control circuit 200 may include a comparator 210 configured to compare the capacitor voltage 207 with a comparison voltage 211 depending on the level of the output voltage VOUT. The second control circuit 200 is configured to generate the comparison voltage 211 depending on the deviation of the value of the output voltage VOUTfrom the reference voltage 112. As a result of the comparison, e.g. at the output of the comparator 210, the second control signal 212 may be provided. By using a (progressively increasing) capacitor voltage 207, the second control signal 212 may be generated in a particularly robust manner.The second control circuit 200 may be configured to reset the capacitor voltage 207 in dependence on the clock signal 111 for adjusting the switching frequency of the switching regulator 100. Alternatively or additionally, the second control circuit 200 may include a reset switch 201 arranged in parallel with the capacitor 202 and controlled using the clock signal 111. The capacitor voltage 207 may be reset at each pulse 161 of the clock signal 111. By resetting the capacitor voltage 207 depending on the clock signal 111, a particularly robust and precise switching frequency can be achieved.The second control circuit 200 may include a first current source 205 configured to charge the capacitor 202 via a control switch 204 using a first current. The second control circuit 200 may be configured to close the control switch 204 such that the capacitor 202 is charged with the first current provided by the first current source 205.The control switch 204 may be controlled depending on the first control signal 131. Alternatively or additionally, the second control circuit 200 may be configured to close the control switch 204 at the beginning of a (e.g. each) turn-off period 162 of the power switch 101. Further, the second control circuit 200 may be configured to keep the control switch 204 closed during the (entire) turn-off period 162 of the power switch 101.Thus, the second control circuit 200 may be configured to generate a capacitor voltage 207 indicative of and / or depending on the duration of the turn-off period 162 of the power switch 101, thereby enabling a particularly precise control of the switching regulator 100.The second control circuit 200 may include a second current source 203 configured to continuously charge the capacitor 202 using a second current such that the capacitor voltage 207 increases with a base gradient 221 when the capacitor 202 is charged using the second current alone. On the other hand, the capacitor voltage 207 may increase with an increased gradient 222 when the control switch 204 is closed and / or when the capacitor 202 is charged using the second current provided by the second current source 203 and the first current provided by the first current source 205. The increased gradient 222 may be higher than the baseline gradient 221. By providing a second current source 203 that continuously charges the capacitor 202, the robustness of the control scheme may be further increased.It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements which, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiments set forth herein are, in principle, expressly intended for purposes of illustration only to aid the reader in understanding the principles of the proposed methods and systems. Furthermore, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.

Claims

A switching regulator configured to generate an output voltage based on an input voltage using at least one power switch and an inductor; the switching regulator comprising: - a first control circuit configured to generate a first control signal for turning off the power switch depending on a level of the inductor current through the inductor; and - a second control circuit configured to generate a second control signal for turning on the power switch depending on a level of the output voltage.The switching regulator of claim 1, wherein the second control circuit is configured to generate the second control signal in response to a clock signal for adjusting a switching frequency of the switching regulator such that during steady state operation of the switching regulator, the second control signal is aligned with the clock signal.The switching regulator of claim 1, wherein the second control circuit comprises: - a capacitor charged during a turn-off period of the power switch to provide a capacitor voltage; and - a comparator configured to compare the capacitor voltage with a comparison voltage that depends on the level of the output voltage to provide the second control signal.The switching regulator of claim 3, wherein - the second control circuit is configured to reset the capacitor voltage in dependence on a clock signal for adjusting a switching frequency of the switching regulator; and / or - the second control circuit comprises a reset switch arranged in parallel with the capacitor and controlled using the clock signal.The switching regulator of claim 3, wherein - the second control circuit comprises a first current source configured to charge the capacitor via a control switch; and - the second control circuit is configured to close the control switch such that the capacitor is charged with the first current provided by the first current source.The switching regulator of claim 5, wherein the control switch is controlled in response to the first control signal.The switching regulator of claim 5, wherein the second control circuit is configured to: - close the control switch at the beginning of a turn-off period of the power switch; and - maintain the control switch closed during the turn-off period of the power switch.The switching regulator of claim 5, wherein the second control circuit comprises a second current source configured to continuously charge the capacitor using a second current such that the capacitor voltage increases with a base gradient when the capacitor is charged using the second current alone.The switching regulator of claim 8, wherein - the capacitor voltage increases with an increased gradient when the control switch is closed and / or when the capacitor is charged using the second current provided by the second current source and the first current provided by the first current source; and - the increased gradient is higher than the base gradient.The switching regulator of claim 3, wherein the second control circuit is configured to generate the comparison voltage depending on a deviation of the value of the output voltage from a reference voltage.The switching regulator of claim 1, wherein the first control circuit is configured to generate the first control signal for turning off the power switch in dependence on a comparison of the level of the inductor current with a target peak value or a target valley value for the inductor current.The switching regulator of claim 1, wherein - the first control circuit is configured to generate a first control signal comprising a sequence of pulses; wherein each pulse of the first control signal turns off the power switch; and / or - the second control circuit is configured to generate a second control signal comprising a sequence of pulses; wherein each pulse of the second control signal turns on the power switch.The switching regulator of claim 1, wherein the switching regulator comprises a buck converter, a boost converter, and / or a buck / boost converter.A method for controlling a switching regulator configured to generate an output voltage based on an input voltage using at least one power switch and an inductor; the method comprising: - generating a first control signal for turning off the power switch depending on a level of the inductor current through the inductor; and - generating a second control signal for turning on the power switch depending on a level of the output voltage.

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