Tail current bias for measurement operations in a storage device

Abstract

A storage device comprises a storage array containing a plurality of memory cells formed at the respective intersections of a plurality of word lines and a plurality of bit lines. The storage device further comprises a side buffer circuit coupled to the storage array, the side buffer circuit comprising a measuring circuit for measuring a cell current read from a bit line of the plurality of bit lines and a tail current bias circuit coupled to the bit line, the tail current bias circuit comprising a tail current capacitor having a first terminal coupled to the bit line, the tail current capacitor serving to generate a tail current in the bit line during a signal integration period when the measuring circuit measures the cell current read from the bit line.

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