OPTIMIZATION OF CFET DEVICES BY PLACING MULTIPLE CELL HEIGHTS

Abstract

A structure comprises a standard cell consisting of a first single-height section and a second single-height section. The first single-height section includes a first VDD line, a first VSS line, and a first inlet metal line. The second single-height section adjoins the first single-height section to form an interface. The second single-height section includes a second VDD line, a second VSS line, and an outlet metal line. In a plan view of the structure, the first inlet metal line and the outlet metal line have longitudinal directions that run parallel to the interface.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over the following provisional US patent application: Application No. 63 / 638,507, filed on April 25, 2024, entitled “CFET DEVICE OPTIMIZATION BY MULTIPLE CELL HEIGHT PLACEMENT”, which is hereby incorporated by reference into the present text. BACKGROUND

[0002] Standard cells are the fundamental building blocks for the design of integrated circuits. These standard cells are designed in advance and stored in design libraries. When integrated circuits are designed, the standard cells are placed and interconnected to form the circuits. The circuits (including the standard cells) are then fabricated as fixture dies.

[0003] As integrated circuits become increasingly smaller, new problems arise, and standard cells can be redesigned to solve these problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood by referring to the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. Figures 1-7 illustrate views of intermediate stages in the formation of a complementary field-effect transistor (CFET) according to some embodiments. Fig. Figure 8 illustrates the circuit diagram of an inverter cell (INVD4 cell) which has four inverters connected in parallel, according to some embodiments. Fig. 9A and Fig. Figure 9B illustrates the layout of some structural elements on a front or back side of an INVD4 inverter cell according to some embodiments. Fig. 10A and Fig. Figure 10B illustrates the layout of some structural elements on a front or back side of an INVD4 inverter cell according to some embodiments. Fig. Figure 11 illustrates the circuit diagram of a NAND cell (ND2D4) which has four NAND cells connected in parallel, according to some embodiments. Fig. 12A and Fig. Figure 12B illustrates the layout of some structural elements on a front or back side of an ND2D4 gate according to some embodiments. Fig. 13A and Fig. Figure 13B illustrates the layout of some structural elements on a front face or of an ND2D4 gate according to some embodiments. Fig. Figure 14 illustrates a perspective view of a section of an ND2D4 gate according to some embodiments. Fig. Figure 15 illustrates a schematic top view of a standard double-height cell and four metal conduits that can be accommodated therein, according to some embodiments. Fig. Figure 16 illustrates some performance data of some standard cells according to some embodiments. Fig. Figure 17 illustrates the speed and cell spacing penalty amount of some standard double-height cells according to some embodiments. Fig. Figure 18 illustrates a device having both single-height cells and a double-height cell, according to some embodiments. Fig. Figure 19 illustrates a process flow for forming a CFET according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to limit the scope of the invention. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or facilities discussed.

[0006] Furthermore, spatially relative terms, such as "underlying," "below," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0007] An inverter (INVD4) comprising four inverters connected in parallel and a NAND cell (ND2D4) comprising four NAND cells connected in parallel are provided. According to some embodiments of the present disclosure, the inverter INVD4 and the NAND cell ND2D4 are designed and manufactured using complementary field-effect transistors (CFETs) and occupy double the height. This makes it possible to position the one or more input metal leads further away from the output metal lead, and the parasitic capacitance between them is reduced. Furthermore, it is possible to route short-length signals without having to rely on long metal leads on the back side of the circuit. The resistance and performance of the standard cells are thereby improved.

[0008] The embodiments discussed in this text are intended to provide examples to facilitate the manufacture or use of the subject matter of this disclosure. The person skilled in the art will immediately think of modifications that can be made without departing from the intended scopes of application of the various embodiments. The same reference numerals are used in the different views and illustrative embodiments to denote the same elements. Although some method embodiments may be discussed as being carried out in a specific sequence, other method embodiments may be carried out in any logical order.

[0009] Fig. Figures 1 to 7 illustrate intermediate stages in the formation of a CFET according to some embodiments of the present disclosure. The corresponding processes are also described in the Fig. The process flow shown in Figure 19 is schematically reflected.

[0010] Fig. Figure 1 illustrates an example of CFETs 10 (including FETs (transistors) 10U and 10L) according to some embodiments. Fig. Figure 1 is a three-dimensional view in which some structural elements of the CFETs have been omitted for the sake of clarity.

[0011] The CFETs feature multiple vertically stacked FETs. For example, a CFET can comprise a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type) oriented opposite the first device type. The nanostructure FETs 10U and 10L feature semiconductor nanostructures 26' (including lower semiconductor nanostructures 26'L and upper semiconductor nanostructures 26'U), with the semiconductor nanostructures 26' acting as the channel regions for the nanostructure FETs. The lower semiconductor nanostructures 26'L are for the lower nanostructure FET 10L, and the upper semiconductor nanostructures 26'U are for the upper nanostructure FET 10U.

[0012] Gate dielectrics 78 surround the respective semiconductor nanostructures 26'. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectrics 78. Source / drain regions 62 (including lower source / drain regions 62L and upper source / drain regions 62U) are arranged on opposite sides of the gate dielectrics 78 and the respective gate electrodes 80. The term "source / drain region" can refer to a source or a drain individually or collectively, depending on the context. Insulating structure elements (not shown) can be formed to selectively separate the source / drain regions 62 and / or the gate electrodes 80.

[0013] Fig. Figure 1 further illustrates reference cross-sections used in later figures. Cross-section AA' is a vertical cross-section running parallel to a longitudinal axis of the semiconductor nanostructures 26' of a CFET and in a direction of, for example, current flow between the source / drain regions 62 of the CFET. Cross-section BB' is a vertical cross-section running perpendicular to cross-section AA' and along a longitudinal axis of a gate electrode 80 of the CFET. Subsequent figures may refer to these reference cross-sections for clarification.

[0014] Fig. Figures 2 to 7 illustrate the cross-sectional views of intermediate stages in the formation of CFETs (as in Fig. 1 schematically depicted) according to some embodiments. The corresponding processes are also described in the Fig. The process flow shown in 16 is schematically reflected in 200.

[0015] In Fig. In step 2, the wafer 2, which has the substrate 20, is provided. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (for example, with a p-type or n-type dopant) or undoped. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, a III-V composite semiconductor, or the like, or combinations thereof.

[0016] A multilayer stack 22 is formed on top of the substrate 20. The respective process is designated as process 202 in the Fig. The process flow 200 shown in Figure 19 is illustrated. The multilayer stack 22 contains alternating dummy semiconductor layers 24 (including dummy semiconductor layers 24A and a dummy semiconductor layer 24B) and semiconductor layers 26 (including lower semiconductor layers 26L and upper semiconductor layers 26U). The lower semiconductor layers 26L and the upper semiconductor layers 26U serve to form a lower FET and an upper FET, respectively.

[0017] The dummy semiconductor layers 24A are formed from a first semiconductor material, and the dummy semiconductor layer 24B is formed from a second semiconductor material that differs from the first semiconductor material. The first and second semiconductor materials can be selected from the available semiconductor materials of the substrate 20. The first and second semiconductor materials exhibit high etch selectivity with respect to each other. This means that the dummy semiconductor layer 24B can be removed at a faster rate in subsequent processes than the dummy semiconductor layers 24A.

[0018] The semiconductor layers 26 (including the lower semiconductor layers 26L and the upper semiconductor layers 26U) are formed from one or more semiconductor materials. The one or more semiconductor materials can be selected from the available semiconductor materials of the substrate 20. The lower semiconductor layers 26L and the upper semiconductor layers 26U can be formed from the same semiconductor material or from different semiconductor materials.

[0019] In some embodiments, the dummy semiconductor layers 24A are formed from or comprise silicon-germanium, the semiconductor layers 26 are formed from silicon, and the dummy semiconductor layer 24B may be formed from germanium or silicon-germanium having a higher germanium atom percentage than in the semiconductor layer 24A.

[0020] In Fig. In step 3, the multilayer stack 22 and the substrate 20 are structured to form semiconductor strips 28. The respective process is described as process 204 in the section on Fig. Figure 19 illustrates the process flow 200. Each of the semiconductor strips 28 comprises a semiconductor strip 20' (the sections of the original substrate 20) and the multilayer stack 22', which is the remaining section of the multilayer stack 22. The remaining sections 22' of the multilayer stack 22 are hereby referred to as nanostructures, designated by the appropriate reference number followed by a hyphen. Accordingly, the multilayer stack 22' comprises dummy nanostructures 24'A, dummy nanostructures 24'B, lower semiconductor nanostructures 26'L, middle semiconductor nanostructures 26'M, and upper semiconductor nanostructures 26'U. The etching may be anisotropic. The dummy nanostructures 24'A and the dummy nanostructures 24'B may also be referred to collectively as dummy nanostructures 24'.The lower semiconductor nanostructures 26'L and the upper semiconductor nanostructures 26'U can also be referred to together as semiconductor nanostructures 26'.

[0021] The lower semiconductor nanostructures 26'L function as channel regions for the lower nanostructure FETs of the CFETs. The upper semiconductor nanostructures 26'U function as channel regions for the upper nanostructure FETs of the CFETs. The middle semiconductor nanostructures 26'M are the semiconductor nanostructures 26' located immediately above / below the dummy nanostructures 24'B (for example, in contact with them). The middle semiconductor nanostructures 26'M can be used for insulation and can optionally function as channel regions for the CFETs. The dummy nanostructures 24'B are subsequently replaced by insulation structures. The insulation structures and the middle semiconductor nanostructures 26'M can define the boundaries of the lower and upper nanostructure FETs.

[0022] In Fig. 4 Insulation regions 32 (shallow trench isolation regions [STI regions]) are formed above the substrate 20 and between adjacent semiconductor strips 28. The respective process is described as process 205 in the Fig. The process flow 200 shown in Figure 19 illustrates this. The insulation regions 32 may have a dielectric lining and a dielectric material over the dielectric lining. The insulation regions 32 are then recessed. Some upper sections of the semiconductor strips 28 (including the multilayer stacks 22') protrude higher than the remaining insulation regions 32 to form projecting fins 34.

[0023] The dummy dielectric layer 36 is then formed on the protruding fins 34. The respective process is described as process 206 in the Fig. The process flow 200 shown in Figure 19 is illustrated. The dummy dielectric layer 36 can, for example, be formed from or comprise silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques.

[0024] A dummy gate layer 38 is formed above the dummy dielectric layer 36. The respective process is described as process 208 in the Fig. The process flow 200 shown in Figure 19 illustrates this. The material of the dummy gate layer 38 can be conductive or non-conductive and can be selected from a group that includes amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), or the like. A mask layer 40 is formed over the planarized dummy gate layer 38, which can contain, for example, silicon nitride, silicon oxynitride, or the like.

[0025] Next, the mask layer 40 can be structured by photolithography and etching processes to form a mask, which is then used to etch and structure the dummy gate layer 38 and possibly the dummy dielectric layer 36. The resulting structure is shown in Fig. 5 shown. The remaining sections of the mask layer 40, the dummy gate layer 38 and the dummy dielectric layer 36 form dummy gate stack 42.

[0026] In Fig. Gate spacers 44 are formed over the multilayer stacks 22' and on exposed sidewalls of dummy gate stacks 42. The gate spacers 44 can be formed by conformal formation of one or more dielectric layers and subsequent anisotropic etching of the dielectric layers. Suitable dielectric materials include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which can be formed by a deposition process such as CVD, ALD, or the like. Fin spacers 45 are also formed.

[0027] Then source / drain recesses 46 are formed in the semiconductor strips 28. The respective process is described as process 210 in the Fig. The process flow 200 shown in Figure 19 illustrates this. The source / drain recesses 46 are formed by etching and can extend through the multilayer stacks 22' and into the semiconductor strips 20'. The undersides of the source / drain recesses 46 can be located on a plane above, below, or flush with the tops of the insulation regions 32. In the etching processes, the gate spacers 44 and the dummy gate stacks 42 mask some sections of the semiconductor strips 28.

[0028] In a subsequent process, dummy nanostructures 24'A are laterally recessed, and a dielectric material is filled into the respective recesses to form internal spacers 54, which are dielectric spacers. The resulting structure is in Fig. Figure 6 shows. In addition, dummy nanostructures 24'B are removed and filled with a dielectric material to form dielectric insulating layers 56.

[0029] Next, lower epitaxial source / drain regions 62L are formed in the lower sections of the source / drain recesses 46 ( Fig. 5) The respective process is designated as process 212 in the Fig. The process flow 200 shown in Figure 19 is illustrated. The lower epitaxial source / drain regions 62L are in contact with the lower semiconductor nanostructures 26'L and are not in contact with the upper semiconductor nanostructures 26'U. Internal spacers 54 electrically isolate the lower epitaxial source / drain regions 62L from the dummy nanostructures 24'A, which are replaced by substitute gates in subsequent processes.

[0030] The lower epitaxial source / drain regions 62L are epitaxially grown and have a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FETs. If the lower epitaxial source / drain regions 62L are n-type, the material can be silicon or carbon-doped silicon doped with an n-type dopant such as phosphorus, arsenic, or the like. If the lower epitaxial source / drain regions 62L are p-type, the material can be silicon or silicon-germanium doped with a p-type dopant such as boron, indium, or the like. The lower epitaxial source / drain regions 62L can be doped in situ and can be implanted with the appropriate p- or n-type dopants, if desired.

[0031] A first coaching etch stop layer (CESL) 66 and a first interlayer etch stop layer (ILD) 68 are formed. The first CESL 66 can be formed from a dielectric material exhibiting high etch selectivity with respect to the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which can be formed by any suitable deposition process, such as CVD, ALD, or the like. The first ILD 68 can be formed from a dielectric material. Suitable dielectric materials for the first ILD 68 include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, or the like.

[0032] The formation processes can include the deposition of a conformal CESL layer, the deposition of material for the ILD 68, followed by a planarization process and then a back-etching process. In some embodiments, the first ILD 68 is etched first, leaving the first CESL 66 unetched. Then, an anisotropic etching process is performed to remove the portions of the first CESL 66 that are higher than the recessed first ILD 68. After recession, the sidewalls of the upper semiconductor nanostructures 26'U are exposed.

[0033] Next, upper epitaxial source / drain regions 62U are formed in the upper sections of the source / drain recesses 46. The respective process is designated as process 214 in the Fig. The process flow 200 shown in Figure 19 illustrates this. The materials of the upper epitaxial source / drain regions 62U can be selected from the same group of suitable materials used to form the lower source / drain regions 62L, depending on the desired conductivity type of the upper epitaxial source / drain regions 62U.

[0034] The conductivity type of the upper epitaxial source / drain regions 62U can be opposite to that of the lower epitaxial source / drain regions 62L. In other words, the upper epitaxial source / drain regions 62U can be doped in the opposite way to the lower epitaxial source / drain regions 62L. The upper epitaxial source / drain regions 62U can be doped in situ with an n- or p-type dopant and / or can be implanted with an n- or p-type dopant.

[0035] Next, a second CESL 70 and a second ILD 72 are formed. The materials and formation procedures may be similar to those of the first CESL 66 and ILD 68, respectively, and are not discussed in detail here. The formation process may include depositing the layers for CESL 70 and ILD 72 and performing a planarization process to remove the excess portion of the respective layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacer 44, and the dummy gate stack 42 are coplanar (within process variations). The planarization process may remove masks 40 or leave hard masks 40 intact.

[0036] The dummy gate stacks 42 are then removed in one or more etching processes, and replacement gate stacks 90 (including gate stacks 90L and 90U) are formed in the respective recesses, as shown in Fig. 7 shown. The respective processes are designated as processes 216 and 218 in the Fig. The process flow 200 shown in Figure 19 illustrates this. The gate stacks 90L have gate spacers 78 and gate electrodes 80L. The gate stacks 90U have gate spacers 78 and gate electrodes 80U. Each of the gate dielectrics 78 can have an interface layer (such as a silicon oxide layer) and a high k-value dielectric layer above the interface layer.

[0037] Dielectric hard masks 92 are formed over the gate stacks 90U. The gate electrodes 80L and 80U contain conductive materials that can impart suitable work functions to the resulting lower FETs (lower transistors) 10L and upper FETs (upper transistors) 10U. The gate electrodes 80L and 80U can be common gates formed in the same formation process.

[0038] Fig. Figure 7 further illustrates the formation of a source / drain contact connector 81, which is connected to the upper source / drain regions 62U, according to some embodiments. Source / drain silicide layers 83 are also formed. The electrical connection to the lower source / drain regions 62L can be made via vertical interconnect connections.

[0039] The CFET 10 can be used to form standard cells, which include the INVD4 inverter and the ND2D4 NAND cells, as will be discussed in detail later. In the following examples, it is assumed that the lower transistors are p-type transistors and the upper transistors are n-type transistors. Accordingly, in the respective standard cells, such as INVD4 and ND2D4, the VSS (electrical ground) lines are formed on the front side of the transistors and the respective wafer / die, and the VDD (positive power supply) lines are formed on the back side of the transistors and the respective wafer / die.

[0040] According to alternative embodiments, the lower transistors can be n-type transistors, and the upper transistors can be p-type transistors. Accordingly, in the respective standard cells, such as INVD4 and ND2D4, the VDD lines can be formed on the front side of the transistors and the respective wafer / chip, and the VSS lines can be formed on the back side of the transistors and the respective wafer / chip.

[0041] Furthermore, the standard INVD4 and ND2D4 cells comprise CMOS transistors, each consisting of one p-transistor and one n-transistor, with the gates of the p-transistor and the n-transistor connected together. The CMOS transistors can perform the functions described in the Fig. 1 and Fig. 7 structures shown, wherein the p-transistor and the n-transistor have a gate 80 (including the gate electrodes 80L and 80U, Fig. 1 and Fig. 7) share.

[0042] Fig. Figure 8 illustrates the circuit diagram of an inverter INVD4, which has four inverters INV-1, INV-2, INV-3, and INV-4 connected in parallel. Inverter INV-1 comprises a p-type transistor (alternatively referred to as a PMOS transistor) P1 and an n-type transistor (alternatively referred to as an NMOS transistor) N1. Inverter INV-2 comprises the PMOS transistor P2 and the NMOS transistor N2. Inverter INV-3 comprises the PMOS transistor P3 and the NMOS transistor N3. Inverter INV-4 comprises the PMOS transistor P4 and the NMOS transistor N4.

[0043] Inverters INV-1, INV-2, INV-3, and INV-4 are connected in parallel to provide higher speed. The input node I is connected to the gates of all PMOS and NMOS transistors. The common drain regions of the four inverters are connected together as the output node ZN.

[0044] Fig. 9A and Fig. Figure 9B illustrates the layout of a front and a rear side of an INVD4 inverter according to some embodiments. Throughout the description, a layout may have an upper part and a lower part, separated, for example, by a boundary line that may be the middle plane of the dielectric insulating layers 56, as in Fig. Figure 7 shows that the term "front" of a layout refers to the part of the structure above the boundary line and can include top transistors (such as transistors 10U in Figure 7). Fig. 7), the respective front-side metal leads on the front of the transistor, and the portions of the vertical interconnect connection above the boundary line.

[0045] The term "backside" of a layout refers to the part of the structure that lies below the boundary line and can include bottom transistors (such as the 10L transistors in Fig. 7), the respective rear metal leads on the back of the transistor, and the parts of the vertical interconnect connection that are lower than the boundary line.

[0046] Fig. Figure 9A illustrates the front face of inverter INVD4 according to one embodiment. The cell height of inverter INVD4 is twice the height H2, which is twice the single height H1. According to some embodiments, the single height H1 is the unit cell height for integrated circuit design. The corresponding cell library and the integrated circuits designed and fabricated on wafers may also have the single height H1. Viewed from the top, a single-height cell has a VDD trace extending to a first edge of the single-height cell and a VSS trace extending to a second edge (of the single-height cell) parallel to and opposite the first edge.

[0047] The VDD and VSS lines can be located on opposite sides (front and back) of the transistors and the corresponding device die. Accordingly, a standard double-height cell comprises two VSS lines and two VDD lines, subdivided into two single-height sections, each of which has a single height H1 and includes one VDD line and one VSS line. Throughout the description, the illustrated single-height sections comprise a first single-height section SH-1 (when viewed in layout, which is also the top view) and a second single-height section SH-2.

[0048] Referring again to Fig. The INVD4 9A inverter has two VSS leads, each extending to the bottom edge of the illustrated single-height parts SH-1 and SH-2. The horizontal metal leads in Fig. 9A are located in the lower metal layer Mo. Gate stacks G1 and G2 are located beneath the lower metal layer Mo. The first single-height part SH-1 is adjacent to the second single-height part SH-2. The front face of the first single-height part SH-1 features NMOS transistors N1 and N2. The front face of the second single-height part SH-2 features NMOS transistors N3 and N4.

[0049] As in Fig. As shown in Figure 9B, the back side of the first single-height part SH-1 features the PMOS transistors P1 and P2. The back side of the first single-height part SH-2 features the PMOS transistors P3 and P4. The common gates G1 and G2 (which form the gate stack 90 in Figure 9B) are located on the back side of the first single-height part SH-2. Fig. (7 can be) extend into both parts SH-1 and SH-2 with single height and extend from the front to the back, as in the Fig. 9A and Fig. Figure 9B shows dummy gate stacks G3 located at the boundaries of standard cell INVD4.

[0050] As in Fig. As shown in Figure 9A, the drain contact connector 102 extends continuously into the single-height parts SH-1 and SH-2. The drain contact connector 102 electrically connects the drain regions of the NMOS transistors N1, N2, N3, and N4 and the PMOS transistors P1, P2, P3, and P4. Although in Fig. Not shown in Figure 7, the drain contact connector 102 penetrates the ILDs 72 and 68 and is electrically connected to the source / drain regions 62L and 62U of the NMOS transistors N1, N2, N3, and N4 and the PMOS transistors P1, P2, P3, and P4. The conductive structural element 104 can be a vertical interconnect used to connect the drain regions of the PMOS transistors P1, P2, P3, and P4 to the output metal trace ZN. Alternatively, if the drain contact connector 102 already connects the drain regions of all eight transistors, the conductive structural element 104 can also be a via connecting the drain contact connector 102 to the output metal trace ZN. The output metal trace ZN can partially overlap the VDD trace in the single-height section SH-1.

[0051] According to some embodiments, each of the single-height parts SH-1 and SH-2 is capable of accommodating two metal conductors parallel to the VSS conductor and in the lower (front) metal layer Mo. As in Fig. As shown in Figure 9A, a single, single-height metal conductor is used as the output metal conductor ZN in section SH-1, and a single, single-height metal conductor is used as the input metal conductor I in section SH-2. Accordingly, by using a double-height structure, the output metal conductor ZN and the input metal conductor I are far apart. The parasitic capacitance is reduced, and the performance of the INV2D4 inverter is improved.

[0052] In comparison, if the INV2D4 inverter is designed as a standard single-height cell, the two metal conductors that can be accommodated in the single-height structure must be used for the input metal conductor I and the output metal conductor ZN, which are located close together. The parasitic capacitance is therefore high, and the performance degrades.

[0053] Fig. Figure 10A illustrates the front panel layout of the INVD4 inverter. Fig. 9A and Fig. Figure 10A illustrates the same front-facing structures of the INVD4 inverter, except that some conductive structural elements are in Fig. 9A are illustrated, while the semiconductor nanostructures and source / drain regions in Fig. Figure 10A is shown to illustrate the structural elements more clearly.

[0054] Fig. 10A illustrates semiconductor nanostructures 26'U (see also Fig. 7) than the channels. Source regions S-1 and S-2 are the source regions of NMOS transistors N1 and N2, respectively. A common drain CD-1 is located between two gate stacks G1 and G2 and is connected to the drain contact pin 102 ( Fig. 9A) is connected, which in turn is connected to the output metal conductor ZN. It is understood that, although the common drain CD-1 is illustrated as a single piece, it may also be divided into two parts located on opposite sides of the drain contact connector 102.

[0055] Similarly illustrated Fig. 10A also includes the source regions S-3 and S-4, which are the source regions of NMOS transistors N3 and N4, respectively. A common drain CD-2 is located between two gate stacks G1 and G2 and is connected to the drain contact 102 ( Fig. 9A) connected, which in turn is connected to the output metal conductor ZN. It is understood that, although the common drain CD-2 is illustrated as a single piece, it may also be divided into two parts located on opposite sides of the drain contact connector 102. Conductive structural elements 105A ( Fig. 10A) connect the source regions of NMOS transistors N1, N2, N3 and N4 to the VSS lines, and conductive structural elements 105B ( Fig. 10B) connect the source regions of PMOS transistors P1, P2, P3 and P4 to the VDD lines.

[0056] Fig. 9B and Fig. Figure 10B illustrates the same front-facing structures of the INVD4 inverter, except that some rear-facing metal traces are in Fig. 9B are illustrated with dashed lines, while the semiconductor nanostructures and source / drain regions in Fig. 10B are shown in such a way that the structural elements are more clearly visible.

[0057] Fig. Figure 9B illustrates the metal traces on the back of the transistor and parallel to the VDD traces. Fig. 10B illustrates semiconductor nanostructures 26'L (see also Fig. 7) than the channels and the source regions S-5 and S-6, which are the source regions of PMOS transistors P1 and P2, respectively. A common drain CD-3 is located between two gate stacks G1 and G2 and is connected to the drain contact plug 102 ( Fig. 9A) is connected, which in turn is connected to the output metal conductor ZN. The common drain CD-3 can also be formed as two separate pieces.

[0058] Similarly illustrated Fig. 10B also includes the source regions S-7 and S-8, which are the source regions of PMOS transistors P3 and P4, respectively. A common drain CD-3 is located between two gate stacks G1 and G2 and is connected to the conductive structural element 102 (when it is in Fig. 9A is a vertical interconnect connection, which in turn is connected to the output metal conductor ZN. The common drain CD-4 can also be formed as two separate pieces.

[0059] Fig. Figure 11 illustrates a circuit diagram of a NAND cell (ND2D4) comprising four ND2 cells connected in parallel: ND2-1, ND2-2, ND2-3, and ND2-4. Each of the ND2 cells ND2-1, ND2-2, ND2-3, and ND2-4 has a first input A1, with all inputs A1 connected together. Each of the ND2 cells ND2-1, ND2-2, ND2-3, and ND2-4 also has a second input A2, with all inputs A2 connected together. The outputs of the ND2 cells are connected together to form the output ZN'.

[0060] Fig. 12A and Fig. Figure 13A illustrates the front faces (NMOS transistors) of the NAND cell ND2D4 according to some embodiments, with some structural elements omitted for better visibility. Fig. 12A and Fig. 13A are divided. The horizontal metal conductors in Fig. 12A are located in the lower metal layer Mo. The gate stacks G1', G2', G3', and G4' are located beneath the lower metal layer Mo. The NAND cell ND2D4 also has a double-height structure comprising two single-height parts SH-1' and SH-2', each with a height H1, so that the total height H2 equals 2 x H1. Each of the gate stacks G1', G2', G3', and G4' extends into both of the single-height parts SH-1' and SH-2'. Furthermore, each of the gate stacks G1', G2', G3', and G4' extends into the Fig. 13A and Fig. 14A shown frontal structures and in the Fig. 13B and Fig. The rear-facing structures shown in Figure 14B. Dummy gate stacks G5' are located at the boundaries of the NAND cell ND2D4.

[0061] Fig. 13A illustrates semiconductor nanostructures 26'U (see also Fig. 7) as the channels, and source / drain regions. In each of the first single-height parts SH-1' and SH-2', each of the gate stacks G1', G2', G3', and G4' forms an NMOS transistor N1' or N2' with the corresponding source / drain regions SD1' located on opposite sides of the respective gate stacks G1', G2', G3', and G4'. Accordingly, four NMOS transistors N1' and four NMOS transistors N2' are formed and are evenly distributed between the single-height parts SH-1' and SH-2'.

[0062] Fig. Figure 12A illustrates the input metal conductors A1 and A2 in the metal layer Mo, which is the bottom metal layer on the front face of the transistors. According to some embodiments, both input metal conductors A1 and A2 are formed in the single-height part SH-1'. The output metal conductor ZN', on the other hand, is formed in the single-height part SH-2'. The source / drain contact plug 102', which extends into both single-height parts SH-1' and SH-2', is used to electrically connect the common source / drain regions of transistors N1' and P1' to the output metal conductor ZN'. The source / drain contact plug 102' further connects the common source / drain regions of transistors N2' and P2' ( Fig. 11) electrically with the output metal conductor ZN'.

[0063] Fig. 12B and Fig. Figure 13B illustrates the back sides (PMOS transistors) of the NAND cell ND2D4 according to some embodiments, with some structural elements omitted for better visibility. Fig. 12B and Fig. 13B are divided. As in Fig. As shown in Figure 12B, the rear metal conduits 104' and 106' are formed in parts SH-1' and SH-2' respectively with single height.

[0064] Fig. 13B illustrates semiconductor nanostructures 26'L (see also Fig. 7) as the channels, and source / drain regions SD2'. In each of the single-height parts SH-1' and SH-2', each of the gate stacks G1', G2', G3', and G4' forms a PMOS P1' or P2' with the corresponding source / drain regions SD2' located on opposite sides of the respective gate stacks G1', G2', G3', and G4'. Accordingly, four PMOS transistors P1' and four PMOS transistors P2' are formed and are evenly distributed across the single-height parts SH-1' and SH-2'.

[0065] Fig. Figure 12B illustrates the metal trace 104' in the single-height section SH-1'. The metal trace 104' is located on the back side of the transistors and may be in the same metal layer as the VDD traces located beneath the PMOS transistors P1' and P2'. The metal trace 104' electrically connects the drain regions of four PMOS transistors P1' and P2' (see Figure 12B). Fig. 13B) and is connected to the vertical interconnect 108'. The vertical interconnect 108' is used to connect the rear structural elements to the front, as also in Fig. 13B is shown.

[0066] The vertical interconnect connection 108' can be connected to the front-facing source / drain contact connector 102' ( Fig. 12A) is connected, which in turn is connected to the output metal conductor ZN'. The connection paths are indicated by arrows 111, as shown in Fig. 12A shown, illustrated.

[0067] Fig. Figure 12B also illustrates the metal trace 106' in the single-height section SH-2'. The metal trace 106' is located on the back side of the transistors and may be in the same metal layer as the VDD traces. The metal trace 106' electrically connects the drain regions of four PMOS transistors P1' and P2' (see Figure 12B). Fig. 13B) and is connected to the vertical interconnect 110'. The vertical interconnect 110' is used to connect the rear structural elements to the front, as also in Fig. 13B is shown. The vertical interconnect connection 110 can be connected to the front-facing source / drain contact plug 102' ( Fig. 12A) is connected, which in turn is connected to the output metal conductor ZN', as shown by arrows 111, as in Fig. 12A shown.

[0068] Fig. Figure 14 illustrates a schematic perspective view of a portion of the NAND cell ND2D4 according to some embodiments, wherein the illustrated portion comprises the right-hand parts of the NAND cell ND2D4, this right-hand part being the front, as shown in Fig. 12A shown, and the reverse side, as in Fig. shown in Figure 12B. The far right drain region 124 and the source region 126 (see also Fig. 13A) are illustrated, while the source / drain region and the gate between them are not shown. The two metal conductors (2Mo) in the Mo metal layer are shown schematically, and no further metal conductor can be accommodated in a single-height section.

[0069] Signal path 120, which runs from drain region 124 to source region 126 and then to output metal trace ZN', is illustrated. Signal path 120 connects the rightmost drain region 124 and the source / drain regions and channels on its left side to the output metal trace ZN'. It can be seen that the entire signal path 120 is located on the front of the cell and does not extend to the back of the transistors. Consequently, the signal path is short, and the number of components in signal path 120 is not significant. The resistance of signal path 120 is therefore low, and the power handling of the NAND cell ND2D4 is high. This advantageous feature results from the use of a double-height design, which allows space to place the output metal trace ZN' in a separate, single-height section from at least one or both input metal traces A1 and A2.

[0070] In comparison, if the NAND cell ND2D4 is designed as a single-height cell, all eight PMOS transistors must be placed in a single row, and all eight NMOS transistors must also be placed in a single row. The row length is therefore considerable. Since the input metal traces A1 and A2 already consume the two allowed metal traces, the output metal trace ZN' must be placed at one end of the long row. The signal may need to be routed to one end of the long row, across the back of the die, and then to the opposite end and the output metal trace ZN'. The long signal traces and the increased number of components result in an increase in the resistance of the signal path and a degradation in the cell's performance.

[0071] Fig. Figure 15 schematically illustrates a block view of a standard cell with a double-height design, allowing four metal conduits in the standard double-height cell (and in the lower metal layer Mo). This increases routing flexibility.

[0072] Fig. Figure 16 illustrates a table showing some INVD4 inverters, ND2D4 NAND cells, and NR2D4 NOR gates (each having four NOR gates connected in parallel), according to some embodiments. The single-height design of these standard cells is used as a reference, and the cell current Icell, the capacity Ccell, and the speed of the double-height design are compared with those of the single-height design. The in Fig. Table 16 illustrates that each double-height design requires one more cell spacing (CPP, also called gate spacing, which is the distance between adjacent gate stacks) than the corresponding single-height design. This penalty in chip area results in improved cell currents (ICell), reduced capacity (Ccell), and improved speed. For example, the speed of the NAND cell ND2D4 can be improved by 16 percent compared to the single-cell design.

[0073] Fig. Figure 17 illustrates the speed improvement of standard cells and the cell spacing penalty of some standard cells according to certain embodiments. The X-axis illustrates some exemplary types of standard cells. The left Y-axis represents the speed improvement of double-height cells compared to the respective single-height cells and corresponds to the illustrated vertical bars. For example, it can be seen that for inverters INVD2, IVDD4, INVD6, and INVD8, which have two, four, six, and eight inverters connected in parallel, respectively, the speed improvement is 5%, 7%, 5%, and 7%. The speed improvement of NAND cells ND2D2, ND2D4, ND2D6, and ND2D8 is 6%, 16%, 12%, and 16%, respectively. The last digit of these cells indicates how many cells of the same type are connected in parallel. The speed improvement of the NOR gates NR2D2, NR2D4, NR2D6 and NR2D8 is 5%, 11%, 12% and 17% respectively.

[0074] Line 130 illustrates the penalty amount for the cell spacing area of ​​the corresponding standard cells as a percentage, shown by the right y-axis. Line 130 also illustrates the increase in the percentage calculated based on the required number of CPPs in the respective single-height design.

[0075] The double-height cells discussed throughout this description are stored in a cell library and are also formed on physical wafers / dies. Furthermore, a device die can contain both standard single-height cells and standard double-height cells. For example, [illustrates...] Fig.18. A device die 150 (which can be formed on a silicon substrate) comprising a circuit 152. The circuit 152 includes a standard double-height cell 140 and two single-height cells 142 and 144, which may be adjacent to the standard double-height cell 140 and may be in the same row as it. The single-height cells 142 and 144 together occupy two rows, while the standard double-height cell 140 alone occupies two rows. The single-height cells 142 and 144 may be inverters (INV), INVD2, ND2D2, NR2, NR2D2, or the like, which have less identical cells connected in parallel. The double-height cell 140 can be INVD4, INVD6, INVD8, ND2D4, ND2D6, ND2D8, NR2D4, NR2D6, NR2D8 or the like, which have more identical cells connected in parallel.

[0076] The embodiments of the present disclosure are characterized by several advantageous features. By forming double-height cells for some standard cells, which have several identical devices / circuits connected in parallel, the parasitic capacitance between the input and output of the double-height cells can be reduced, and the performance of the devices can be improved.

[0077] According to some embodiments of the present disclosure, a structure comprises a standard cell comprising a first single-height part comprising a first VDD line, a first VSS line, a first inlet metal line; and a second single-height part adjoining the first single-height part to form an interface, wherein the second single-height part comprises: a second VDD line, a second VSS line; and an outlet metal line, wherein, in a plan view of the structure, the first inlet metal line and the outlet metal line have longitudinal directions parallel to the interface.In one embodiment, the standard cell comprises a first transistor of a first conductivity type; and a second transistor of a second conductivity type opposite to the first conductivity type, wherein the second transistor overlaps the first transistor and wherein a first of the first VSS line and the first VDD line is higher than the second transistor.

[0078] In one embodiment, a second VSS line and a second VDD line are located lower than the first transistor. In another embodiment, the structure further comprises a vertical interconnect connecting the first transistor to the output metal line. In another embodiment, the standard cell comprises four inverters connected in parallel. In yet another embodiment, the structure further comprises a drain contact connector extending continuously into both the first single-height and second single-height sections, the drain contact connector electrically connecting common drain regions of transistors in the four inverters to the output metal line.

[0079] In one embodiment, the drain contact connector, viewed from above, has a longitudinal direction perpendicular to the interface. In another embodiment, the drain contact connector, viewed from above, is located in the center of the standard cell. In another embodiment, the standard cell occupies three gate spacings, where a gate spacing is the distance between two adjacent gate stacks of transistors in the standard cell. In another embodiment, the standard cell comprises four NAND cells connected in parallel.

[0080] In one embodiment, the structure further comprises a second input metal conductor in the first single-height part and parallel to the first input metal conductor. In another embodiment, the structure further comprises a source / drain connector extending continuously into both the first single-height part and the second single-height part, the source / drain connector connecting common drain regions of transistors in the four NAND cells to the output metal conductor. In one embodiment, in a top view of the structure, the source / drain connector has a longitudinal direction perpendicular to the interface.

[0081] In one embodiment, the standard cell comprises a first transistor and a second transistor of a first conductivity type; and a third transistor and a fourth transistor of a second conductivity type opposite to the first conductivity type, wherein the third transistor and the fourth transistor overlap the first transistor and the second transistor, respectively; and wherein the structure further comprises: a first vertical interconnect connecting the first transistor to the output metal conductor, wherein the first vertical interconnect is located in the first single-height portion; and a second vertical interconnect connecting the second transistor to the output metal conductor, wherein the second vertical interconnect is located in the second single-height portion.In one embodiment, the standard cell occupies five gate spacings, where a gate spacing is a distance between two adjacent gate stacks of transistors in the standard cell.

[0082] According to some embodiments of the present disclosure, a structure comprises an inverter cell comprising a first single-height part, comprising a first VSS line at a first edge of the first single-height part; an input metal line; and a second single-height part, comprising a first VDD line at a first edge of the second single-height part, wherein the first edge of the first single-height part is adjacent to the first edge of the second single-height part; an output metal line, wherein, in a top view of the inverter cell, the input metal line is spaced apart from the output metal line by the first VSS line.

[0083] In one embodiment, in a top view, the input metal conductor is further spaced from the output metal conductor by the first VDD conductor. In another embodiment, in a cross-sectional view of the structure, the first VSS conductor and the first VDD conductor are located on opposite sides of the transistors of the inverter cell.

[0084] According to some embodiments of the present disclosure, a structure comprises an inverter cell comprising four inverters, wherein the inverter cell comprises: a first edge and a second edge parallel to each other; a first VDD line extending to the first edge; a first VSS line extending to the second edge; a second VDD line extending to a centerline of the inverter cell, the centerline being midway between the first edge and the second edge; an input metal line electrically coupled to inputs of the four inverters, wherein, in a top view of the inverter cell, the input metal line runs parallel to and between the second VDD line and the first VSS line;and an output metal conductor electrically coupled to outputs of the four inverters, wherein, in the top view of the inverter cell, the output metal conductor runs parallel to and partially overlaps the first VDD conductor.

[0085] In one embodiment, the structure further comprises a contact plug having a first longitudinal direction perpendicular to a second longitudinal direction of the first VDD line, wherein the contact plug lies on a plane lower than the first VSS line and higher than the first VDD line, and wherein a first end of the contact plug overlaps a first section of the first VDD line and a second end of the contact plug overlaps a second section of the first VSS line.

[0086] The above outlines features of various embodiments so that the person skilled in the art can better understand the aspects of the present disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as in the embodiments presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to the present invention without departing from the essence and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 638,507

[0001]

Claims

[1] Structure, comprehensive: a standard cell, comprising: a first part with simple height, comprising: a first VDD line; a first VSS line; a first input metal conduit; and a second part of single height adjacent to the first part of single height to form a boundary surface, the second part of single height comprising: a second VDD line; a second VSS line; and an output metal conduit, wherein, in a top view of the structure, the first input metal conduit and the output metal conduit have longitudinal directions that run parallel to the interface. [2] Structure according to claim 1, wherein the standard cell comprises: a first transistor of a first conductivity type; and a second transistor of a second conductivity type opposite to the first conductivity type, wherein the second transistor overlaps the first transistor and wherein a first of the first VSS line and the first VDD line is higher than the second transistor. [3] Structure according to claim 2, wherein a second of the first VSS line and the first VDD line is located lower than the first transistor. [4] Structure according to claim 2 or 3, further comprising a vertical interconnect link connecting the first transistor to the output metal conductor. [5] Structure according to any one of claims 1 to 4, wherein the standard cell comprises four inverters connected in parallel. [6] Structure according to claim 5, further comprising a drain contact connector extending continuously into both the first single-height part and the second single-height part, wherein the drain contact connector electrically connects common drain regions of transistors in the four inverters to the output metal conductor. [7] Structure according to claim 6, wherein, in the top view of the structure, the drain contact plug has a longitudinal direction that is perpendicular to the interface. [8] Structure according to claim 6, wherein, in the top view of the structure, the drain contact plug is located in the center of the standard cell. [9] Structure according to any one of claims 5 to 8, wherein the standard cell occupies three gate spacings, and wherein a gate spacing is a distance between two adjacent gate stacks of transistors in the standard cell. [10] Structure according to any one of claims 1 to 9, wherein the standard cell comprises four NAND cells connected in parallel. [11] Structure according to claim 10, which further comprises a second inlet metal conduit in the first part with a single height and parallel to the first inlet metal conduit. [12] Structure according to claim 10, further comprising a source / drain contact connector extending continuously into both the first single-height part and the second single-height part, wherein the source / drain contact connector connects common drain regions of transistors in the four NAND cells to the output metal lead. [13] Structure according to claim 12, wherein, in the top view of the structure, the source / drain contact connector has a longitudinal direction that is perpendicular to the interface. [14] Structure according to any one of claims 10 to 13, wherein the standard cell comprises: a first transistor and a second transistor of a first conductivity type; and a third transistor and a fourth transistor of a second conductivity type opposite to the first conductivity type, wherein the third transistor and the fourth transistor overlap the first transistor and the second transistor respectively, and wherein the structure further comprises: a first vertical interconnect link connecting the first transistor to the output metal conductor, wherein the first vertical interconnect link is located in the first single-height portion; and a second vertical interconnect connection that connects the second transistor to the output metal conductor, the second vertical interconnect being located in the second single-height part. [15] Structure according to any one of claims 10 to 14, wherein the standard cell occupies five gate spacings, and wherein a gate spacing is a distance between two adjacent gate stacks of transistors in the standard cell. [16] Structure, comprehensive: an inverter cell, comprising: a first part with simple height, comprising: a first VSS line at a first edge of the first part with a single height; an input metal conduit; and a second part with simple height, comprising: a first VDD line at a first edge of the second single-height part, wherein the first edge of the first single-height part borders the first edge of the second single-height part; and an output metal conductor, wherein, in a top view of the inverter cell, the input metal conductor is spaced from the output metal conductor by the first VSS conductor. [17] Structure according to claim 16, wherein, in the top view, the inlet metal conduit is further spaced apart from the outlet metal conduit by the first VDD conduit. [18] Structure according to claim 16 or 17, wherein, in a cross-sectional view of the structure, the first VSS line and the first VDD line are located on opposite sides of transistors of the inverter cell. [19] Structure, comprehensive: an inverter cell comprising four inverters, wherein the inverter cell comprises: a first edge and a second edge that run parallel to each other; a first VDD line extending to the first edge; a first VSS line extending to the second edge; a second VDD line extending to a centerline of the inverter cell, the centerline being midway between the first edge and the second edge; an input metal conductor electrically coupled to the inputs of the four inverters, wherein, in a top view of the inverter cell, the input metal conductor runs parallel to and between the second VDD conductor and the first VSS conductor; and an output metal conductor that is electrically coupled to the outputs of the four inverters, wherein, in the top view of the inverter cell, the output metal conductor runs parallel to the first VDD conductor and partially overlaps it. [20] Structure according to claim 16, further comprising a contact connector having a first longitudinal direction perpendicular to a second longitudinal direction of the first VDD line, wherein the contact connector lies on a plane lower than the first VSS line and higher than the first VDD line, and wherein a first end of the contact connector overlaps a first section of the first VDD line and a second end of the contact connector is overlapped by a second section of the first VSS line.

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